2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_atomic_uapi.h>
19 #include <drm/drm_crtc.h>
20 #include <drm/drm_flip_work.h>
21 #include <drm/drm_gem_framebuffer_helper.h>
22 #include <drm/drm_plane_helper.h>
23 #include <drm/drm_probe_helper.h>
24 #ifdef CONFIG_DRM_ANALOGIX_DP
25 #include <drm/bridge/analogix_dp.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32 #include <linux/iopoll.h>
34 #include <linux/of_device.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/component.h>
37 #include <linux/overflow.h>
39 #include <linux/reset.h>
40 #include <linux/delay.h>
42 #include "rockchip_drm_drv.h"
43 #include "rockchip_drm_gem.h"
44 #include "rockchip_drm_fb.h"
45 #include "rockchip_drm_psr.h"
46 #include "rockchip_drm_vop.h"
47 #include "rockchip_rgb.h"
49 #define VOP_WIN_SET(vop, win, name, v) \
50 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
51 #define VOP_SCL_SET(vop, win, name, v) \
52 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
53 #define VOP_SCL_SET_EXT(vop, win, name, v) \
54 vop_reg_set(vop, &win->phy->scl->ext->name, \
55 win->base, ~0, v, #name)
57 #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \
59 if (win_yuv2yuv && win_yuv2yuv->name.mask) \
60 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \
63 #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \
65 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \
66 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \
69 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
70 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
72 #define VOP_REG_SET(vop, group, name, v) \
73 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
75 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
77 int i, reg = 0, mask = 0; \
78 for (i = 0; i < vop->data->intr->nintrs; i++) { \
79 if (vop->data->intr->intrs[i] & type) { \
84 VOP_INTR_SET_MASK(vop, name, mask, reg); \
86 #define VOP_INTR_GET_TYPE(vop, name, type) \
87 vop_get_intr_type(vop, &vop->data->intr->name, type)
89 #define VOP_WIN_GET(vop, win, name) \
90 vop_read_reg(vop, win->offset, win->phy->name)
92 #define VOP_WIN_HAS_REG(win, name) \
93 (!!(win->phy->name.mask))
95 #define VOP_WIN_GET_YRGBADDR(vop, win) \
96 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
98 #define VOP_WIN_TO_INDEX(vop_win) \
99 ((vop_win) - (vop_win)->vop->win)
101 #define to_vop(x) container_of(x, struct vop, crtc)
102 #define to_vop_win(x) container_of(x, struct vop_win, base)
105 * The coefficients of the following matrix are all fixed points.
106 * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets.
107 * They are all represented in two's complement.
109 static const uint32_t bt601_yuv2rgb[] = {
111 0x4A8, 0x1E6F, 0x1CBF,
113 0x321168, 0x0877CF, 0x2EB127
117 VOP_PENDING_FB_UNREF,
121 struct drm_plane base;
122 const struct vop_win_data *data;
123 const struct vop_win_yuv2yuv_data *yuv2yuv_data;
129 struct drm_crtc crtc;
131 struct drm_device *drm_dev;
134 struct completion dsp_hold_completion;
136 /* protected by dev->event_lock */
137 struct drm_pending_vblank_event *event;
139 struct drm_flip_work fb_unref_work;
140 unsigned long pending;
142 struct completion line_flag_completion;
144 const struct vop_data *data;
149 /* physical map length of vop register */
152 /* one time only one process allowed to config the register */
154 /* lock vop irq reg */
156 /* protects crtc enable/disable */
157 struct mutex vop_lock;
165 /* vop share memory frequency */
169 struct reset_control *dclk_rst;
171 /* optional internal rgb encoder */
172 struct rockchip_rgb *rgb;
174 struct vop_win win[];
177 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
179 writel(v, vop->regs + offset);
180 vop->regsbak[offset >> 2] = v;
183 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
185 return readl(vop->regs + offset);
188 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
189 const struct vop_reg *reg)
191 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
194 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
195 uint32_t _offset, uint32_t _mask, uint32_t v,
196 const char *reg_name)
198 int offset, mask, shift;
200 if (!reg || !reg->mask) {
201 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name);
205 offset = reg->offset + _offset;
206 mask = reg->mask & _mask;
209 if (reg->write_mask) {
210 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
212 uint32_t cached_val = vop->regsbak[offset >> 2];
214 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
215 vop->regsbak[offset >> 2] = v;
219 writel_relaxed(v, vop->regs + offset);
221 writel(v, vop->regs + offset);
224 static inline uint32_t vop_get_intr_type(struct vop *vop,
225 const struct vop_reg *reg, int type)
228 uint32_t regs = vop_read_reg(vop, 0, reg);
230 for (i = 0; i < vop->data->intr->nintrs; i++) {
231 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
232 ret |= vop->data->intr->intrs[i];
238 static inline void vop_cfg_done(struct vop *vop)
240 VOP_REG_SET(vop, common, cfg_done, 1);
243 static bool has_rb_swapped(uint32_t format)
246 case DRM_FORMAT_XBGR8888:
247 case DRM_FORMAT_ABGR8888:
248 case DRM_FORMAT_BGR888:
249 case DRM_FORMAT_BGR565:
256 static enum vop_data_format vop_convert_format(uint32_t format)
259 case DRM_FORMAT_XRGB8888:
260 case DRM_FORMAT_ARGB8888:
261 case DRM_FORMAT_XBGR8888:
262 case DRM_FORMAT_ABGR8888:
263 return VOP_FMT_ARGB8888;
264 case DRM_FORMAT_RGB888:
265 case DRM_FORMAT_BGR888:
266 return VOP_FMT_RGB888;
267 case DRM_FORMAT_RGB565:
268 case DRM_FORMAT_BGR565:
269 return VOP_FMT_RGB565;
270 case DRM_FORMAT_NV12:
271 return VOP_FMT_YUV420SP;
272 case DRM_FORMAT_NV16:
273 return VOP_FMT_YUV422SP;
274 case DRM_FORMAT_NV24:
275 return VOP_FMT_YUV444SP;
277 DRM_ERROR("unsupported format[%08x]\n", format);
282 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
283 uint32_t dst, bool is_horizontal,
284 int vsu_mode, int *vskiplines)
286 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
292 if (mode == SCALE_UP)
293 val = GET_SCL_FT_BIC(src, dst);
294 else if (mode == SCALE_DOWN)
295 val = GET_SCL_FT_BILI_DN(src, dst);
297 if (mode == SCALE_UP) {
298 if (vsu_mode == SCALE_UP_BIL)
299 val = GET_SCL_FT_BILI_UP(src, dst);
301 val = GET_SCL_FT_BIC(src, dst);
302 } else if (mode == SCALE_DOWN) {
304 *vskiplines = scl_get_vskiplines(src, dst);
305 val = scl_get_bili_dn_vskip(src, dst,
308 val = GET_SCL_FT_BILI_DN(src, dst);
316 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
317 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
318 uint32_t dst_h, uint32_t pixel_format)
320 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
321 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
322 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
323 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
324 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
325 const struct drm_format_info *info;
327 uint16_t cbcr_src_w = src_w / hsub;
328 uint16_t cbcr_src_h = src_h / vsub;
334 info = drm_format_info(pixel_format);
340 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
344 if (!win->phy->scl->ext) {
345 VOP_SCL_SET(vop, win, scale_yrgb_x,
346 scl_cal_scale2(src_w, dst_w));
347 VOP_SCL_SET(vop, win, scale_yrgb_y,
348 scl_cal_scale2(src_h, dst_h));
350 VOP_SCL_SET(vop, win, scale_cbcr_x,
351 scl_cal_scale2(cbcr_src_w, dst_w));
352 VOP_SCL_SET(vop, win, scale_cbcr_y,
353 scl_cal_scale2(cbcr_src_h, dst_h));
358 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
359 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
362 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
363 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
364 if (cbcr_hor_scl_mode == SCALE_DOWN)
365 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
367 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
369 if (yrgb_hor_scl_mode == SCALE_DOWN)
370 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
372 lb_mode = scl_vop_cal_lb_mode(src_w, false);
375 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
376 if (lb_mode == LB_RGB_3840X2) {
377 if (yrgb_ver_scl_mode != SCALE_NONE) {
378 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
381 if (cbcr_ver_scl_mode != SCALE_NONE) {
382 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
385 vsu_mode = SCALE_UP_BIL;
386 } else if (lb_mode == LB_RGB_2560X4) {
387 vsu_mode = SCALE_UP_BIL;
389 vsu_mode = SCALE_UP_BIC;
392 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
394 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
395 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
396 false, vsu_mode, &vskiplines);
397 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
399 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
400 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
402 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
403 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
404 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
405 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
406 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
408 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
409 dst_w, true, 0, NULL);
410 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
411 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
412 dst_h, false, vsu_mode, &vskiplines);
413 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
415 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
416 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
417 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
418 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
419 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
420 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
421 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
425 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
429 if (WARN_ON(!vop->is_enabled))
432 spin_lock_irqsave(&vop->irq_lock, flags);
434 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
435 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
437 spin_unlock_irqrestore(&vop->irq_lock, flags);
440 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
444 if (WARN_ON(!vop->is_enabled))
447 spin_lock_irqsave(&vop->irq_lock, flags);
449 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
451 spin_unlock_irqrestore(&vop->irq_lock, flags);
455 * (1) each frame starts at the start of the Vsync pulse which is signaled by
456 * the "FRAME_SYNC" interrupt.
457 * (2) the active data region of each frame ends at dsp_vact_end
458 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
459 * to get "LINE_FLAG" interrupt at the end of the active on screen data.
461 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
463 * LINE_FLAG -------------------------------+
467 * | Vsync | Vbp | Vactive | Vfp |
471 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END
472 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END
473 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END
474 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END
476 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
478 uint32_t line_flag_irq;
481 spin_lock_irqsave(&vop->irq_lock, flags);
483 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
485 spin_unlock_irqrestore(&vop->irq_lock, flags);
487 return !!line_flag_irq;
490 static void vop_line_flag_irq_enable(struct vop *vop)
494 if (WARN_ON(!vop->is_enabled))
497 spin_lock_irqsave(&vop->irq_lock, flags);
499 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
500 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
502 spin_unlock_irqrestore(&vop->irq_lock, flags);
505 static void vop_line_flag_irq_disable(struct vop *vop)
509 if (WARN_ON(!vop->is_enabled))
512 spin_lock_irqsave(&vop->irq_lock, flags);
514 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
516 spin_unlock_irqrestore(&vop->irq_lock, flags);
519 static int vop_core_clks_enable(struct vop *vop)
523 ret = clk_enable(vop->hclk);
527 ret = clk_enable(vop->aclk);
529 goto err_disable_hclk;
534 clk_disable(vop->hclk);
538 static void vop_core_clks_disable(struct vop *vop)
540 clk_disable(vop->aclk);
541 clk_disable(vop->hclk);
544 static void vop_win_disable(struct vop *vop, const struct vop_win_data *win)
546 if (win->phy->scl && win->phy->scl->ext) {
547 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
548 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
549 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
550 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
553 VOP_WIN_SET(vop, win, enable, 0);
556 static int vop_enable(struct drm_crtc *crtc)
558 struct vop *vop = to_vop(crtc);
561 ret = pm_runtime_get_sync(vop->dev);
563 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
567 ret = vop_core_clks_enable(vop);
568 if (WARN_ON(ret < 0))
569 goto err_put_pm_runtime;
571 ret = clk_enable(vop->dclk);
572 if (WARN_ON(ret < 0))
573 goto err_disable_core;
576 * Slave iommu shares power, irq and clock with vop. It was associated
577 * automatically with this master device via common driver code.
578 * Now that we have enabled the clock we attach it to the shared drm
581 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
583 DRM_DEV_ERROR(vop->dev,
584 "failed to attach dma mapping, %d\n", ret);
585 goto err_disable_dclk;
588 spin_lock(&vop->reg_lock);
589 for (i = 0; i < vop->len; i += 4)
590 writel_relaxed(vop->regsbak[i / 4], vop->regs + i);
593 * We need to make sure that all windows are disabled before we
594 * enable the crtc. Otherwise we might try to scan from a destroyed
597 for (i = 0; i < vop->data->win_size; i++) {
598 struct vop_win *vop_win = &vop->win[i];
599 const struct vop_win_data *win = vop_win->data;
601 vop_win_disable(vop, win);
603 spin_unlock(&vop->reg_lock);
608 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
610 vop->is_enabled = true;
612 spin_lock(&vop->reg_lock);
614 VOP_REG_SET(vop, common, standby, 1);
616 spin_unlock(&vop->reg_lock);
618 drm_crtc_vblank_on(crtc);
623 clk_disable(vop->dclk);
625 vop_core_clks_disable(vop);
627 pm_runtime_put_sync(vop->dev);
631 static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
632 struct drm_crtc_state *old_state)
634 struct vop *vop = to_vop(crtc);
638 mutex_lock(&vop->vop_lock);
639 drm_crtc_vblank_off(crtc);
642 * Vop standby will take effect at end of current frame,
643 * if dsp hold valid irq happen, it means standby complete.
645 * we must wait standby complete when we want to disable aclk,
646 * if not, memory bus maybe dead.
648 reinit_completion(&vop->dsp_hold_completion);
649 vop_dsp_hold_valid_irq_enable(vop);
651 spin_lock(&vop->reg_lock);
653 VOP_REG_SET(vop, common, standby, 1);
655 spin_unlock(&vop->reg_lock);
657 wait_for_completion(&vop->dsp_hold_completion);
659 vop_dsp_hold_valid_irq_disable(vop);
661 vop->is_enabled = false;
664 * vop standby complete, so iommu detach is safe.
666 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
668 clk_disable(vop->dclk);
669 vop_core_clks_disable(vop);
670 pm_runtime_put(vop->dev);
671 mutex_unlock(&vop->vop_lock);
673 if (crtc->state->event && !crtc->state->active) {
674 spin_lock_irq(&crtc->dev->event_lock);
675 drm_crtc_send_vblank_event(crtc, crtc->state->event);
676 spin_unlock_irq(&crtc->dev->event_lock);
678 crtc->state->event = NULL;
682 static void vop_plane_destroy(struct drm_plane *plane)
684 drm_plane_cleanup(plane);
687 static int vop_plane_atomic_check(struct drm_plane *plane,
688 struct drm_plane_state *state)
690 struct drm_crtc *crtc = state->crtc;
691 struct drm_crtc_state *crtc_state;
692 struct drm_framebuffer *fb = state->fb;
693 struct vop_win *vop_win = to_vop_win(plane);
694 const struct vop_win_data *win = vop_win->data;
696 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
697 DRM_PLANE_HELPER_NO_SCALING;
698 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
699 DRM_PLANE_HELPER_NO_SCALING;
704 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
705 if (WARN_ON(!crtc_state))
708 ret = drm_atomic_helper_check_plane_state(state, crtc_state,
709 min_scale, max_scale,
717 ret = vop_convert_format(fb->format->format);
722 * Src.x1 can be odd when do clip, but yuv plane start point
723 * need align with 2 pixel.
725 if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) {
726 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n");
730 if (fb->format->is_yuv && state->rotation & DRM_MODE_REFLECT_Y) {
731 DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n");
738 static void vop_plane_atomic_disable(struct drm_plane *plane,
739 struct drm_plane_state *old_state)
741 struct vop_win *vop_win = to_vop_win(plane);
742 const struct vop_win_data *win = vop_win->data;
743 struct vop *vop = to_vop(old_state->crtc);
745 if (!old_state->crtc)
748 spin_lock(&vop->reg_lock);
750 vop_win_disable(vop, win);
752 spin_unlock(&vop->reg_lock);
755 static void vop_plane_atomic_update(struct drm_plane *plane,
756 struct drm_plane_state *old_state)
758 struct drm_plane_state *state = plane->state;
759 struct drm_crtc *crtc = state->crtc;
760 struct vop_win *vop_win = to_vop_win(plane);
761 const struct vop_win_data *win = vop_win->data;
762 const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data;
763 struct vop *vop = to_vop(state->crtc);
764 struct drm_framebuffer *fb = state->fb;
765 unsigned int actual_w, actual_h;
766 unsigned int dsp_stx, dsp_sty;
767 uint32_t act_info, dsp_info, dsp_st;
768 struct drm_rect *src = &state->src;
769 struct drm_rect *dest = &state->dst;
770 struct drm_gem_object *obj, *uv_obj;
771 struct rockchip_gem_object *rk_obj, *rk_uv_obj;
772 unsigned long offset;
776 int win_index = VOP_WIN_TO_INDEX(vop_win);
778 int is_yuv = fb->format->is_yuv;
782 * can't update plane when vop is disabled.
787 if (WARN_ON(!vop->is_enabled))
790 if (!state->visible) {
791 vop_plane_atomic_disable(plane, old_state);
796 rk_obj = to_rockchip_obj(obj);
798 actual_w = drm_rect_width(src) >> 16;
799 actual_h = drm_rect_height(src) >> 16;
800 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
802 dsp_info = (drm_rect_height(dest) - 1) << 16;
803 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
805 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
806 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
807 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
809 offset = (src->x1 >> 16) * fb->format->cpp[0];
810 offset += (src->y1 >> 16) * fb->pitches[0];
811 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
814 * For y-mirroring we need to move address
815 * to the beginning of the last line.
817 if (state->rotation & DRM_MODE_REFLECT_Y)
818 dma_addr += (actual_h - 1) * fb->pitches[0];
820 format = vop_convert_format(fb->format->format);
822 spin_lock(&vop->reg_lock);
824 VOP_WIN_SET(vop, win, format, format);
825 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
826 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
827 VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
828 VOP_WIN_SET(vop, win, y_mir_en,
829 (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0);
830 VOP_WIN_SET(vop, win, x_mir_en,
831 (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
834 int hsub = drm_format_horz_chroma_subsampling(fb->format->format);
835 int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
836 int bpp = fb->format->cpp[1];
839 rk_uv_obj = to_rockchip_obj(uv_obj);
841 offset = (src->x1 >> 16) * bpp / hsub;
842 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
844 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
845 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
846 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
848 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
849 VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop,
857 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
858 drm_rect_width(dest), drm_rect_height(dest),
861 VOP_WIN_SET(vop, win, act_info, act_info);
862 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
863 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
865 rb_swap = has_rb_swapped(fb->format->format);
866 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
869 * Blending win0 with the background color doesn't seem to work
870 * correctly. We only get the background color, no matter the contents
871 * of the win0 framebuffer. However, blending pre-multiplied color
872 * with the default opaque black default background color is a no-op,
873 * so we can just disable blending to get the correct result.
875 if (fb->format->has_alpha && win_index > 0) {
876 VOP_WIN_SET(vop, win, dst_alpha_ctl,
877 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
878 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
879 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
880 SRC_BLEND_M0(ALPHA_PER_PIX) |
881 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
882 SRC_FACTOR_M0(ALPHA_ONE);
883 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
885 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
888 VOP_WIN_SET(vop, win, enable, 1);
889 spin_unlock(&vop->reg_lock);
892 static int vop_plane_atomic_async_check(struct drm_plane *plane,
893 struct drm_plane_state *state)
895 struct vop_win *vop_win = to_vop_win(plane);
896 const struct vop_win_data *win = vop_win->data;
897 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
898 DRM_PLANE_HELPER_NO_SCALING;
899 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
900 DRM_PLANE_HELPER_NO_SCALING;
901 struct drm_crtc_state *crtc_state;
903 if (plane != state->crtc->cursor)
909 if (!plane->state->fb)
913 crtc_state = drm_atomic_get_existing_crtc_state(state->state,
915 else /* Special case for asynchronous cursor updates. */
916 crtc_state = plane->crtc->state;
918 return drm_atomic_helper_check_plane_state(plane->state, crtc_state,
919 min_scale, max_scale,
923 static void vop_plane_atomic_async_update(struct drm_plane *plane,
924 struct drm_plane_state *new_state)
926 struct vop *vop = to_vop(plane->state->crtc);
927 struct drm_framebuffer *old_fb = plane->state->fb;
929 plane->state->crtc_x = new_state->crtc_x;
930 plane->state->crtc_y = new_state->crtc_y;
931 plane->state->crtc_h = new_state->crtc_h;
932 plane->state->crtc_w = new_state->crtc_w;
933 plane->state->src_x = new_state->src_x;
934 plane->state->src_y = new_state->src_y;
935 plane->state->src_h = new_state->src_h;
936 plane->state->src_w = new_state->src_w;
937 swap(plane->state->fb, new_state->fb);
939 if (vop->is_enabled) {
940 rockchip_drm_psr_inhibit_get_state(new_state->state);
941 vop_plane_atomic_update(plane, plane->state);
942 spin_lock(&vop->reg_lock);
944 spin_unlock(&vop->reg_lock);
945 rockchip_drm_psr_inhibit_put_state(new_state->state);
948 * A scanout can still be occurring, so we can't drop the
949 * reference to the old framebuffer. To solve this we get a
950 * reference to old_fb and set a worker to release it later.
951 * FIXME: if we perform 500 async_update calls before the
952 * vblank, then we can have 500 different framebuffers waiting
955 if (old_fb && plane->state->fb != old_fb) {
956 drm_framebuffer_get(old_fb);
957 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0);
958 drm_flip_work_queue(&vop->fb_unref_work, old_fb);
959 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
964 static const struct drm_plane_helper_funcs plane_helper_funcs = {
965 .atomic_check = vop_plane_atomic_check,
966 .atomic_update = vop_plane_atomic_update,
967 .atomic_disable = vop_plane_atomic_disable,
968 .atomic_async_check = vop_plane_atomic_async_check,
969 .atomic_async_update = vop_plane_atomic_async_update,
970 .prepare_fb = drm_gem_fb_prepare_fb,
973 static const struct drm_plane_funcs vop_plane_funcs = {
974 .update_plane = drm_atomic_helper_update_plane,
975 .disable_plane = drm_atomic_helper_disable_plane,
976 .destroy = vop_plane_destroy,
977 .reset = drm_atomic_helper_plane_reset,
978 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
979 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
982 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
984 struct vop *vop = to_vop(crtc);
987 if (WARN_ON(!vop->is_enabled))
990 spin_lock_irqsave(&vop->irq_lock, flags);
992 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
993 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
995 spin_unlock_irqrestore(&vop->irq_lock, flags);
1000 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1002 struct vop *vop = to_vop(crtc);
1003 unsigned long flags;
1005 if (WARN_ON(!vop->is_enabled))
1008 spin_lock_irqsave(&vop->irq_lock, flags);
1010 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1012 spin_unlock_irqrestore(&vop->irq_lock, flags);
1015 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1016 const struct drm_display_mode *mode,
1017 struct drm_display_mode *adjusted_mode)
1019 struct vop *vop = to_vop(crtc);
1021 adjusted_mode->clock =
1022 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1027 static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
1028 struct drm_crtc_state *old_state)
1030 struct vop *vop = to_vop(crtc);
1031 const struct vop_data *vop_data = vop->data;
1032 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1033 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1034 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1035 u16 hdisplay = adjusted_mode->hdisplay;
1036 u16 htotal = adjusted_mode->htotal;
1037 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1038 u16 hact_end = hact_st + hdisplay;
1039 u16 vdisplay = adjusted_mode->vdisplay;
1040 u16 vtotal = adjusted_mode->vtotal;
1041 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1042 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1043 u16 vact_end = vact_st + vdisplay;
1044 uint32_t pin_pol, val;
1045 int dither_bpc = s->output_bpc ? s->output_bpc : 10;
1048 mutex_lock(&vop->vop_lock);
1050 WARN_ON(vop->event);
1052 ret = vop_enable(crtc);
1054 mutex_unlock(&vop->vop_lock);
1055 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
1059 pin_pol = BIT(DCLK_INVERT);
1060 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
1061 BIT(HSYNC_POSITIVE) : 0;
1062 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
1063 BIT(VSYNC_POSITIVE) : 0;
1064 VOP_REG_SET(vop, output, pin_pol, pin_pol);
1065 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0);
1067 switch (s->output_type) {
1068 case DRM_MODE_CONNECTOR_LVDS:
1069 VOP_REG_SET(vop, output, rgb_en, 1);
1070 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);
1072 case DRM_MODE_CONNECTOR_eDP:
1073 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);
1074 VOP_REG_SET(vop, output, edp_en, 1);
1076 case DRM_MODE_CONNECTOR_HDMIA:
1077 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);
1078 VOP_REG_SET(vop, output, hdmi_en, 1);
1080 case DRM_MODE_CONNECTOR_DSI:
1081 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);
1082 VOP_REG_SET(vop, output, mipi_en, 1);
1083 VOP_REG_SET(vop, output, mipi_dual_channel_en,
1084 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL));
1086 case DRM_MODE_CONNECTOR_DisplayPort:
1087 pin_pol &= ~BIT(DCLK_INVERT);
1088 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);
1089 VOP_REG_SET(vop, output, dp_en, 1);
1092 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
1097 * if vop is not support RGB10 output, need force RGB10 to RGB888.
1099 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1100 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
1101 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1103 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8)
1104 VOP_REG_SET(vop, common, pre_dither_down, 1);
1106 VOP_REG_SET(vop, common, pre_dither_down, 0);
1108 if (dither_bpc == 6) {
1109 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO);
1110 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666);
1111 VOP_REG_SET(vop, common, dither_down_en, 1);
1113 VOP_REG_SET(vop, common, dither_down_en, 0);
1116 VOP_REG_SET(vop, common, out_mode, s->output_mode);
1118 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
1119 val = hact_st << 16;
1121 VOP_REG_SET(vop, modeset, hact_st_end, val);
1122 VOP_REG_SET(vop, modeset, hpost_st_end, val);
1124 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len);
1125 val = vact_st << 16;
1127 VOP_REG_SET(vop, modeset, vact_st_end, val);
1128 VOP_REG_SET(vop, modeset, vpost_st_end, val);
1130 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
1132 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1134 VOP_REG_SET(vop, common, standby, 0);
1135 mutex_unlock(&vop->vop_lock);
1138 static bool vop_fs_irq_is_pending(struct vop *vop)
1140 return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
1143 static void vop_wait_for_irq_handler(struct vop *vop)
1149 * Spin until frame start interrupt status bit goes low, which means
1150 * that interrupt handler was invoked and cleared it. The timeout of
1151 * 10 msecs is really too long, but it is just a safety measure if
1152 * something goes really wrong. The wait will only happen in the very
1153 * unlikely case of a vblank happening exactly at the same time and
1154 * shouldn't exceed microseconds range.
1156 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1157 !pending, 0, 10 * 1000);
1159 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1161 synchronize_irq(vop->irq);
1164 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1165 struct drm_crtc_state *old_crtc_state)
1167 struct drm_atomic_state *old_state = old_crtc_state->state;
1168 struct drm_plane_state *old_plane_state, *new_plane_state;
1169 struct vop *vop = to_vop(crtc);
1170 struct drm_plane *plane;
1173 if (WARN_ON(!vop->is_enabled))
1176 spin_lock(&vop->reg_lock);
1180 spin_unlock(&vop->reg_lock);
1183 * There is a (rather unlikely) possiblity that a vblank interrupt
1184 * fired before we set the cfg_done bit. To avoid spuriously
1185 * signalling flip completion we need to wait for it to finish.
1187 vop_wait_for_irq_handler(vop);
1189 spin_lock_irq(&crtc->dev->event_lock);
1190 if (crtc->state->event) {
1191 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1192 WARN_ON(vop->event);
1194 vop->event = crtc->state->event;
1195 crtc->state->event = NULL;
1197 spin_unlock_irq(&crtc->dev->event_lock);
1199 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state,
1200 new_plane_state, i) {
1201 if (!old_plane_state->fb)
1204 if (old_plane_state->fb == new_plane_state->fb)
1207 drm_framebuffer_get(old_plane_state->fb);
1208 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1209 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1210 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1214 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1215 .mode_fixup = vop_crtc_mode_fixup,
1216 .atomic_flush = vop_crtc_atomic_flush,
1217 .atomic_enable = vop_crtc_atomic_enable,
1218 .atomic_disable = vop_crtc_atomic_disable,
1221 static void vop_crtc_destroy(struct drm_crtc *crtc)
1223 drm_crtc_cleanup(crtc);
1226 static void vop_crtc_reset(struct drm_crtc *crtc)
1229 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1232 crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1234 crtc->state->crtc = crtc;
1237 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1239 struct rockchip_crtc_state *rockchip_state;
1241 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1242 if (!rockchip_state)
1245 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1246 return &rockchip_state->base;
1249 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1250 struct drm_crtc_state *state)
1252 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1254 __drm_atomic_helper_crtc_destroy_state(&s->base);
1258 #ifdef CONFIG_DRM_ANALOGIX_DP
1259 static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1261 struct drm_connector *connector;
1262 struct drm_connector_list_iter conn_iter;
1264 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
1265 drm_for_each_connector_iter(connector, &conn_iter) {
1266 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1267 drm_connector_list_iter_end(&conn_iter);
1271 drm_connector_list_iter_end(&conn_iter);
1276 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1277 const char *source_name)
1279 struct vop *vop = to_vop(crtc);
1280 struct drm_connector *connector;
1283 connector = vop_get_edp_connector(vop);
1287 if (source_name && strcmp(source_name, "auto") == 0)
1288 ret = analogix_dp_start_crc(connector);
1289 else if (!source_name)
1290 ret = analogix_dp_stop_crc(connector);
1298 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1301 if (source_name && strcmp(source_name, "auto") != 0)
1309 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1310 const char *source_name)
1316 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1323 static const struct drm_crtc_funcs vop_crtc_funcs = {
1324 .set_config = drm_atomic_helper_set_config,
1325 .page_flip = drm_atomic_helper_page_flip,
1326 .destroy = vop_crtc_destroy,
1327 .reset = vop_crtc_reset,
1328 .atomic_duplicate_state = vop_crtc_duplicate_state,
1329 .atomic_destroy_state = vop_crtc_destroy_state,
1330 .enable_vblank = vop_crtc_enable_vblank,
1331 .disable_vblank = vop_crtc_disable_vblank,
1332 .set_crc_source = vop_crtc_set_crc_source,
1333 .verify_crc_source = vop_crtc_verify_crc_source,
1336 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1338 struct vop *vop = container_of(work, struct vop, fb_unref_work);
1339 struct drm_framebuffer *fb = val;
1341 drm_crtc_vblank_put(&vop->crtc);
1342 drm_framebuffer_put(fb);
1345 static void vop_handle_vblank(struct vop *vop)
1347 struct drm_device *drm = vop->drm_dev;
1348 struct drm_crtc *crtc = &vop->crtc;
1350 spin_lock(&drm->event_lock);
1352 drm_crtc_send_vblank_event(crtc, vop->event);
1353 drm_crtc_vblank_put(crtc);
1356 spin_unlock(&drm->event_lock);
1358 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1359 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1362 static irqreturn_t vop_isr(int irq, void *data)
1364 struct vop *vop = data;
1365 struct drm_crtc *crtc = &vop->crtc;
1366 uint32_t active_irqs;
1370 * The irq is shared with the iommu. If the runtime-pm state of the
1371 * vop-device is disabled the irq has to be targeted at the iommu.
1373 if (!pm_runtime_get_if_in_use(vop->dev))
1376 if (vop_core_clks_enable(vop)) {
1377 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n");
1382 * interrupt register has interrupt status, enable and clear bits, we
1383 * must hold irq_lock to avoid a race with enable/disable_vblank().
1385 spin_lock(&vop->irq_lock);
1387 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1388 /* Clear all active interrupt sources */
1390 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1392 spin_unlock(&vop->irq_lock);
1394 /* This is expected for vop iommu irqs, since the irq is shared */
1398 if (active_irqs & DSP_HOLD_VALID_INTR) {
1399 complete(&vop->dsp_hold_completion);
1400 active_irqs &= ~DSP_HOLD_VALID_INTR;
1404 if (active_irqs & LINE_FLAG_INTR) {
1405 complete(&vop->line_flag_completion);
1406 active_irqs &= ~LINE_FLAG_INTR;
1410 if (active_irqs & FS_INTR) {
1411 drm_crtc_handle_vblank(crtc);
1412 vop_handle_vblank(vop);
1413 active_irqs &= ~FS_INTR;
1417 /* Unhandled irqs are spurious. */
1419 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1423 vop_core_clks_disable(vop);
1425 pm_runtime_put(vop->dev);
1429 static void vop_plane_add_properties(struct drm_plane *plane,
1430 const struct vop_win_data *win_data)
1432 unsigned int flags = 0;
1434 flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0;
1435 flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0;
1437 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
1438 DRM_MODE_ROTATE_0 | flags);
1441 static int vop_create_crtc(struct vop *vop)
1443 const struct vop_data *vop_data = vop->data;
1444 struct device *dev = vop->dev;
1445 struct drm_device *drm_dev = vop->drm_dev;
1446 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1447 struct drm_crtc *crtc = &vop->crtc;
1448 struct device_node *port;
1453 * Create drm_plane for primary and cursor planes first, since we need
1454 * to pass them to drm_crtc_init_with_planes, which sets the
1455 * "possible_crtcs" to the newly initialized crtc.
1457 for (i = 0; i < vop_data->win_size; i++) {
1458 struct vop_win *vop_win = &vop->win[i];
1459 const struct vop_win_data *win_data = vop_win->data;
1461 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1462 win_data->type != DRM_PLANE_TYPE_CURSOR)
1465 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1466 0, &vop_plane_funcs,
1467 win_data->phy->data_formats,
1468 win_data->phy->nformats,
1469 NULL, win_data->type, NULL);
1471 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1473 goto err_cleanup_planes;
1476 plane = &vop_win->base;
1477 drm_plane_helper_add(plane, &plane_helper_funcs);
1478 vop_plane_add_properties(plane, win_data);
1479 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1481 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1485 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1486 &vop_crtc_funcs, NULL);
1488 goto err_cleanup_planes;
1490 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1493 * Create drm_planes for overlay windows with possible_crtcs restricted
1494 * to the newly created crtc.
1496 for (i = 0; i < vop_data->win_size; i++) {
1497 struct vop_win *vop_win = &vop->win[i];
1498 const struct vop_win_data *win_data = vop_win->data;
1499 unsigned long possible_crtcs = drm_crtc_mask(crtc);
1501 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1504 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1507 win_data->phy->data_formats,
1508 win_data->phy->nformats,
1509 NULL, win_data->type, NULL);
1511 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1513 goto err_cleanup_crtc;
1515 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1516 vop_plane_add_properties(&vop_win->base, win_data);
1519 port = of_get_child_by_name(dev->of_node, "port");
1521 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n",
1524 goto err_cleanup_crtc;
1527 drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1528 vop_fb_unref_worker);
1530 init_completion(&vop->dsp_hold_completion);
1531 init_completion(&vop->line_flag_completion);
1537 drm_crtc_cleanup(crtc);
1539 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1541 drm_plane_cleanup(plane);
1545 static void vop_destroy_crtc(struct vop *vop)
1547 struct drm_crtc *crtc = &vop->crtc;
1548 struct drm_device *drm_dev = vop->drm_dev;
1549 struct drm_plane *plane, *tmp;
1551 of_node_put(crtc->port);
1554 * We need to cleanup the planes now. Why?
1556 * The planes are "&vop->win[i].base". That means the memory is
1557 * all part of the big "struct vop" chunk of memory. That memory
1558 * was devm allocated and associated with this component. We need to
1559 * free it ourselves before vop_unbind() finishes.
1561 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1563 vop_plane_destroy(plane);
1566 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1567 * references the CRTC.
1569 drm_crtc_cleanup(crtc);
1570 drm_flip_work_cleanup(&vop->fb_unref_work);
1573 static int vop_initial(struct vop *vop)
1575 const struct vop_data *vop_data = vop->data;
1576 struct reset_control *ahb_rst;
1579 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1580 if (IS_ERR(vop->hclk)) {
1581 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n");
1582 return PTR_ERR(vop->hclk);
1584 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1585 if (IS_ERR(vop->aclk)) {
1586 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n");
1587 return PTR_ERR(vop->aclk);
1589 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1590 if (IS_ERR(vop->dclk)) {
1591 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n");
1592 return PTR_ERR(vop->dclk);
1595 ret = pm_runtime_get_sync(vop->dev);
1597 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
1601 ret = clk_prepare(vop->dclk);
1603 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n");
1604 goto err_put_pm_runtime;
1607 /* Enable both the hclk and aclk to setup the vop */
1608 ret = clk_prepare_enable(vop->hclk);
1610 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n");
1611 goto err_unprepare_dclk;
1614 ret = clk_prepare_enable(vop->aclk);
1616 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n");
1617 goto err_disable_hclk;
1621 * do hclk_reset, reset all vop registers.
1623 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1624 if (IS_ERR(ahb_rst)) {
1625 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n");
1626 ret = PTR_ERR(ahb_rst);
1627 goto err_disable_aclk;
1629 reset_control_assert(ahb_rst);
1630 usleep_range(10, 20);
1631 reset_control_deassert(ahb_rst);
1633 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1);
1634 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0);
1636 for (i = 0; i < vop->len; i += sizeof(u32))
1637 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i);
1639 VOP_REG_SET(vop, misc, global_regdone_en, 1);
1640 VOP_REG_SET(vop, common, dsp_blank, 0);
1642 for (i = 0; i < vop_data->win_size; i++) {
1643 const struct vop_win_data *win = &vop_data->win[i];
1644 int channel = i * 2 + 1;
1646 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
1647 vop_win_disable(vop, win);
1648 VOP_WIN_SET(vop, win, gate, 1);
1654 * do dclk_reset, let all config take affect.
1656 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1657 if (IS_ERR(vop->dclk_rst)) {
1658 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n");
1659 ret = PTR_ERR(vop->dclk_rst);
1660 goto err_disable_aclk;
1662 reset_control_assert(vop->dclk_rst);
1663 usleep_range(10, 20);
1664 reset_control_deassert(vop->dclk_rst);
1666 clk_disable(vop->hclk);
1667 clk_disable(vop->aclk);
1669 vop->is_enabled = false;
1671 pm_runtime_put_sync(vop->dev);
1676 clk_disable_unprepare(vop->aclk);
1678 clk_disable_unprepare(vop->hclk);
1680 clk_unprepare(vop->dclk);
1682 pm_runtime_put_sync(vop->dev);
1687 * Initialize the vop->win array elements.
1689 static void vop_win_init(struct vop *vop)
1691 const struct vop_data *vop_data = vop->data;
1694 for (i = 0; i < vop_data->win_size; i++) {
1695 struct vop_win *vop_win = &vop->win[i];
1696 const struct vop_win_data *win_data = &vop_data->win[i];
1698 vop_win->data = win_data;
1701 if (vop_data->win_yuv2yuv)
1702 vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i];
1707 * rockchip_drm_wait_vact_end
1708 * @crtc: CRTC to enable line flag
1709 * @mstimeout: millisecond for timeout
1711 * Wait for vact_end line flag irq or timeout.
1714 * Zero on success, negative errno on failure.
1716 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
1718 struct vop *vop = to_vop(crtc);
1719 unsigned long jiffies_left;
1722 if (!crtc || !vop->is_enabled)
1725 mutex_lock(&vop->vop_lock);
1726 if (mstimeout <= 0) {
1731 if (vop_line_flag_irq_is_enabled(vop)) {
1736 reinit_completion(&vop->line_flag_completion);
1737 vop_line_flag_irq_enable(vop);
1739 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
1740 msecs_to_jiffies(mstimeout));
1741 vop_line_flag_irq_disable(vop);
1743 if (jiffies_left == 0) {
1744 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n");
1750 mutex_unlock(&vop->vop_lock);
1753 EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
1755 static int vop_bind(struct device *dev, struct device *master, void *data)
1757 struct platform_device *pdev = to_platform_device(dev);
1758 const struct vop_data *vop_data;
1759 struct drm_device *drm_dev = data;
1761 struct resource *res;
1764 vop_data = of_device_get_match_data(dev);
1768 /* Allocate vop struct and its vop_win array */
1769 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size),
1775 vop->data = vop_data;
1776 vop->drm_dev = drm_dev;
1777 dev_set_drvdata(dev, vop);
1781 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1782 vop->len = resource_size(res);
1783 vop->regs = devm_ioremap_resource(dev, res);
1784 if (IS_ERR(vop->regs))
1785 return PTR_ERR(vop->regs);
1787 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1791 irq = platform_get_irq(pdev, 0);
1793 DRM_DEV_ERROR(dev, "cannot find irq for vop\n");
1796 vop->irq = (unsigned int)irq;
1798 spin_lock_init(&vop->reg_lock);
1799 spin_lock_init(&vop->irq_lock);
1800 mutex_init(&vop->vop_lock);
1802 ret = vop_create_crtc(vop);
1806 pm_runtime_enable(&pdev->dev);
1808 ret = vop_initial(vop);
1810 DRM_DEV_ERROR(&pdev->dev,
1811 "cannot initial vop dev - err %d\n", ret);
1812 goto err_disable_pm_runtime;
1815 ret = devm_request_irq(dev, vop->irq, vop_isr,
1816 IRQF_SHARED, dev_name(dev), vop);
1818 goto err_disable_pm_runtime;
1820 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) {
1821 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev);
1822 if (IS_ERR(vop->rgb)) {
1823 ret = PTR_ERR(vop->rgb);
1824 goto err_disable_pm_runtime;
1830 err_disable_pm_runtime:
1831 pm_runtime_disable(&pdev->dev);
1832 vop_destroy_crtc(vop);
1836 static void vop_unbind(struct device *dev, struct device *master, void *data)
1838 struct vop *vop = dev_get_drvdata(dev);
1841 rockchip_rgb_fini(vop->rgb);
1843 pm_runtime_disable(dev);
1844 vop_destroy_crtc(vop);
1846 clk_unprepare(vop->aclk);
1847 clk_unprepare(vop->hclk);
1848 clk_unprepare(vop->dclk);
1851 const struct component_ops vop_component_ops = {
1853 .unbind = vop_unbind,
1855 EXPORT_SYMBOL_GPL(vop_component_ops);