drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_flip_work.h>
  21 #include <drm/drm_plane_helper.h>
  22 #ifdef CONFIG_DRM_ANALOGIX_DP
  23 #include <drm/bridge/analogix_dp.h>
  24 #endif
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/clk.h>
  30 #include <linux/iopoll.h>
  31 #include <linux/of.h>
  32 #include <linux/of_device.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/component.h>
  35
  36 #include <linux/reset.h>
  37 #include <linux/delay.h>
  38
  39 #include "rockchip_drm_drv.h"
  40 #include "rockchip_drm_gem.h"
  41 #include "rockchip_drm_fb.h"
  42 #include "rockchip_drm_psr.h"
  43 #include "rockchip_drm_vop.h"
  44
  45 #define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
  46                 vop_mask_write(x, off, mask, shift, v, write_mask, true)
  47
  48 #define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
  49                 vop_mask_write(x, off, mask, shift, v, write_mask, false)
  50
  51 #define REG_SET(x, base, reg, v, mode) \
  52                 __REG_SET_##mode(x, base + reg.offset, \
  53                                  reg.mask, reg.shift, v, reg.write_mask)
  54 #define REG_SET_MASK(x, base, reg, mask, v, mode) \
  55                 __REG_SET_##mode(x, base + reg.offset, \
  56                                  mask, reg.shift, v, reg.write_mask)
  57
  58 #define VOP_WIN_SET(x, win, name, v) \
  59                 REG_SET(x, win->base, win->phy->name, v, RELAXED)
  60 #define VOP_SCL_SET(x, win, name, v) \
  61                 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
  62 #define VOP_SCL_SET_EXT(x, win, name, v) \
  63                 REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
  64 #define VOP_CTRL_SET(x, name, v) \
  65                 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
  66
  67 #define VOP_INTR_GET(vop, name) \
  68                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  69
  70 #define VOP_INTR_SET(vop, name, mask, v) \
  71                 REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
  72 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  73         do { \
  74                 int i, reg = 0, mask = 0; \
  75                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  76                         if (vop->data->intr->intrs[i] & type) { \
  77                                 reg |= (v) << i; \
  78                                 mask |= 1 << i; \
  79                         } \
  80                 } \
  81                 VOP_INTR_SET(vop, name, mask, reg); \
  82         } while (0)
  83 #define VOP_INTR_GET_TYPE(vop, name, type) \
  84                 vop_get_intr_type(vop, &vop->data->intr->name, type)
  85
  86 #define VOP_WIN_GET(x, win, name) \
  87                 vop_read_reg(x, win->base, &win->phy->name)
  88
  89 #define VOP_WIN_GET_YRGBADDR(vop, win) \
  90                 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
  91
  92 #define to_vop(x) container_of(x, struct vop, crtc)
  93 #define to_vop_win(x) container_of(x, struct vop_win, base)
  94
  95 enum vop_pending {
  96         VOP_PENDING_FB_UNREF,
  97 };
  98
  99 struct vop_win {
 100         struct drm_plane base;
 101         const struct vop_win_data *data;
 102         struct vop *vop;
 103 };
 104
 105 struct vop {
 106         struct drm_crtc crtc;
 107         struct device *dev;
 108         struct drm_device *drm_dev;
 109         bool is_enabled;
 110
 111         /* mutex vsync_ work */
 112         struct mutex vsync_mutex;
 113         bool vsync_work_pending;
 114         struct completion dsp_hold_completion;
 115
 116         /* protected by dev->event_lock */
 117         struct drm_pending_vblank_event *event;
 118
 119         struct drm_flip_work fb_unref_work;
 120         unsigned long pending;
 121
 122         struct completion line_flag_completion;
 123
 124         const struct vop_data *data;
 125
 126         uint32_t *regsbak;
 127         void __iomem *regs;
 128
 129         /* physical map length of vop register */
 130         uint32_t len;
 131
 132         /* one time only one process allowed to config the register */
 133         spinlock_t reg_lock;
 134         /* lock vop irq reg */
 135         spinlock_t irq_lock;
 136
 137         unsigned int irq;
 138
 139         /* vop AHP clk */
 140         struct clk *hclk;
 141         /* vop dclk */
 142         struct clk *dclk;
 143         /* vop share memory frequency */
 144         struct clk *aclk;
 145
 146         /* vop dclk reset */
 147         struct reset_control *dclk_rst;
 148
 149         struct vop_win win[];
 150 };
 151
 152 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 153 {
 154         writel(v, vop->regs + offset);
 155         vop->regsbak[offset >> 2] = v;
 156 }
 157
 158 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 159 {
 160         return readl(vop->regs + offset);
 161 }
 162
 163 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 164                                     const struct vop_reg *reg)
 165 {
 166         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 167 }
 168
 169 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 170                                   uint32_t mask, uint32_t shift, uint32_t v,
 171                                   bool write_mask, bool relaxed)
 172 {
 173         if (!mask)
 174                 return;
 175
 176         if (write_mask) {
 177                 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
 178         } else {
 179                 uint32_t cached_val = vop->regsbak[offset >> 2];
 180
 181                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 182                 vop->regsbak[offset >> 2] = v;
 183         }
 184
 185         if (relaxed)
 186                 writel_relaxed(v, vop->regs + offset);
 187         else
 188                 writel(v, vop->regs + offset);
 189 }
 190
 191 static inline uint32_t vop_get_intr_type(struct vop *vop,
 192                                          const struct vop_reg *reg, int type)
 193 {
 194         uint32_t i, ret = 0;
 195         uint32_t regs = vop_read_reg(vop, 0, reg);
 196
 197         for (i = 0; i < vop->data->intr->nintrs; i++) {
 198                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 199                         ret |= vop->data->intr->intrs[i];
 200         }
 201
 202         return ret;
 203 }
 204
 205 static inline void vop_cfg_done(struct vop *vop)
 206 {
 207         VOP_CTRL_SET(vop, cfg_done, 1);
 208 }
 209
 210 static bool has_rb_swapped(uint32_t format)
 211 {
 212         switch (format) {
 213         case DRM_FORMAT_XBGR8888:
 214         case DRM_FORMAT_ABGR8888:
 215         case DRM_FORMAT_BGR888:
 216         case DRM_FORMAT_BGR565:
 217                 return true;
 218         default:
 219                 return false;
 220         }
 221 }
 222
 223 static enum vop_data_format vop_convert_format(uint32_t format)
 224 {
 225         switch (format) {
 226         case DRM_FORMAT_XRGB8888:
 227         case DRM_FORMAT_ARGB8888:
 228         case DRM_FORMAT_XBGR8888:
 229         case DRM_FORMAT_ABGR8888:
 230                 return VOP_FMT_ARGB8888;
 231         case DRM_FORMAT_RGB888:
 232         case DRM_FORMAT_BGR888:
 233                 return VOP_FMT_RGB888;
 234         case DRM_FORMAT_RGB565:
 235         case DRM_FORMAT_BGR565:
 236                 return VOP_FMT_RGB565;
 237         case DRM_FORMAT_NV12:
 238                 return VOP_FMT_YUV420SP;
 239         case DRM_FORMAT_NV16:
 240                 return VOP_FMT_YUV422SP;
 241         case DRM_FORMAT_NV24:
 242                 return VOP_FMT_YUV444SP;
 243         default:
 244                 DRM_ERROR("unsupported format[%08x]\n", format);
 245                 return -EINVAL;
 246         }
 247 }
 248
 249 static bool is_yuv_support(uint32_t format)
 250 {
 251         switch (format) {
 252         case DRM_FORMAT_NV12:
 253         case DRM_FORMAT_NV16:
 254         case DRM_FORMAT_NV24:
 255                 return true;
 256         default:
 257                 return false;
 258         }
 259 }
 260
 261 static bool is_alpha_support(uint32_t format)
 262 {
 263         switch (format) {
 264         case DRM_FORMAT_ARGB8888:
 265         case DRM_FORMAT_ABGR8888:
 266                 return true;
 267         default:
 268                 return false;
 269         }
 270 }
 271
 272 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 273                                   uint32_t dst, bool is_horizontal,
 274                                   int vsu_mode, int *vskiplines)
 275 {
 276         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 277
 278         if (is_horizontal) {
 279                 if (mode == SCALE_UP)
 280                         val = GET_SCL_FT_BIC(src, dst);
 281                 else if (mode == SCALE_DOWN)
 282                         val = GET_SCL_FT_BILI_DN(src, dst);
 283         } else {
 284                 if (mode == SCALE_UP) {
 285                         if (vsu_mode == SCALE_UP_BIL)
 286                                 val = GET_SCL_FT_BILI_UP(src, dst);
 287                         else
 288                                 val = GET_SCL_FT_BIC(src, dst);
 289                 } else if (mode == SCALE_DOWN) {
 290                         if (vskiplines) {
 291                                 *vskiplines = scl_get_vskiplines(src, dst);
 292                                 val = scl_get_bili_dn_vskip(src, dst,
 293                                                             *vskiplines);
 294                         } else {
 295                                 val = GET_SCL_FT_BILI_DN(src, dst);
 296                         }
 297                 }
 298         }
 299
 300         return val;
 301 }
 302
 303 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
 304                              uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 305                              uint32_t dst_h, uint32_t pixel_format)
 306 {
 307         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 308         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 309         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 310         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 311         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 312         bool is_yuv = is_yuv_support(pixel_format);
 313         uint16_t cbcr_src_w = src_w / hsub;
 314         uint16_t cbcr_src_h = src_h / vsub;
 315         uint16_t vsu_mode;
 316         uint16_t lb_mode;
 317         uint32_t val;
 318         int vskiplines = 0;
 319
 320         if (dst_w > 3840) {
 321                 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
 322                 return;
 323         }
 324
 325         if (!win->phy->scl->ext) {
 326                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 327                             scl_cal_scale2(src_w, dst_w));
 328                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 329                             scl_cal_scale2(src_h, dst_h));
 330                 if (is_yuv) {
 331                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 332                                     scl_cal_scale2(cbcr_src_w, dst_w));
 333                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 334                                     scl_cal_scale2(cbcr_src_h, dst_h));
 335                 }
 336                 return;
 337         }
 338
 339         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 340         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 341
 342         if (is_yuv) {
 343                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 344                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 345                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 346                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 347                 else
 348                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 349         } else {
 350                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 351                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 352                 else
 353                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 354         }
 355
 356         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 357         if (lb_mode == LB_RGB_3840X2) {
 358                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 359                         DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
 360                         return;
 361                 }
 362                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 363                         DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
 364                         return;
 365                 }
 366                 vsu_mode = SCALE_UP_BIL;
 367         } else if (lb_mode == LB_RGB_2560X4) {
 368                 vsu_mode = SCALE_UP_BIL;
 369         } else {
 370                 vsu_mode = SCALE_UP_BIC;
 371         }
 372
 373         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 374                                 true, 0, NULL);
 375         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 376         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 377                                 false, vsu_mode, &vskiplines);
 378         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 379
 380         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 381         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 382
 383         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 384         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 385         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 386         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 387         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 388         if (is_yuv) {
 389                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 390                                         dst_w, true, 0, NULL);
 391                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 392                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 393                                         dst_h, false, vsu_mode, &vskiplines);
 394                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 395
 396                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 397                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 398                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 399                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 400                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 401                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 402                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 403         }
 404 }
 405
 406 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 407 {
 408         unsigned long flags;
 409
 410         if (WARN_ON(!vop->is_enabled))
 411                 return;
 412
 413         spin_lock_irqsave(&vop->irq_lock, flags);
 414
 415         VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
 416         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 417
 418         spin_unlock_irqrestore(&vop->irq_lock, flags);
 419 }
 420
 421 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 422 {
 423         unsigned long flags;
 424
 425         if (WARN_ON(!vop->is_enabled))
 426                 return;
 427
 428         spin_lock_irqsave(&vop->irq_lock, flags);
 429
 430         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 431
 432         spin_unlock_irqrestore(&vop->irq_lock, flags);
 433 }
 434
 435 /*
 436  * (1) each frame starts at the start of the Vsync pulse which is signaled by
 437  *     the "FRAME_SYNC" interrupt.
 438  * (2) the active data region of each frame ends at dsp_vact_end
 439  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
 440  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
 441  *
 442  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
 443  * Interrupts
 444  * LINE_FLAG -------------------------------+
 445  * FRAME_SYNC ----+                         |
 446  *                |                         |
 447  *                v                         v
 448  *                | Vsync | Vbp |  Vactive  | Vfp |
 449  *                        ^     ^           ^     ^
 450  *                        |     |           |     |
 451  *                        |     |           |     |
 452  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
 453  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
 454  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
 455  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
 456  */
 457 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
 458 {
 459         uint32_t line_flag_irq;
 460         unsigned long flags;
 461
 462         spin_lock_irqsave(&vop->irq_lock, flags);
 463
 464         line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
 465
 466         spin_unlock_irqrestore(&vop->irq_lock, flags);
 467
 468         return !!line_flag_irq;
 469 }
 470
 471 static void vop_line_flag_irq_enable(struct vop *vop)
 472 {
 473         unsigned long flags;
 474
 475         if (WARN_ON(!vop->is_enabled))
 476                 return;
 477
 478         spin_lock_irqsave(&vop->irq_lock, flags);
 479
 480         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
 481         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 482
 483         spin_unlock_irqrestore(&vop->irq_lock, flags);
 484 }
 485
 486 static void vop_line_flag_irq_disable(struct vop *vop)
 487 {
 488         unsigned long flags;
 489
 490         if (WARN_ON(!vop->is_enabled))
 491                 return;
 492
 493         spin_lock_irqsave(&vop->irq_lock, flags);
 494
 495         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
 496
 497         spin_unlock_irqrestore(&vop->irq_lock, flags);
 498 }
 499
 500 static int vop_enable(struct drm_crtc *crtc)
 501 {
 502         struct vop *vop = to_vop(crtc);
 503         int ret;
 504
 505         ret = pm_runtime_get_sync(vop->dev);
 506         if (ret < 0) {
 507                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 508                 return ret;
 509         }
 510
 511         ret = clk_enable(vop->hclk);
 512         if (WARN_ON(ret < 0))
 513                 goto err_put_pm_runtime;
 514
 515         ret = clk_enable(vop->dclk);
 516         if (WARN_ON(ret < 0))
 517                 goto err_disable_hclk;
 518
 519         ret = clk_enable(vop->aclk);
 520         if (WARN_ON(ret < 0))
 521                 goto err_disable_dclk;
 522
 523         /*
 524          * Slave iommu shares power, irq and clock with vop.  It was associated
 525          * automatically with this master device via common driver code.
 526          * Now that we have enabled the clock we attach it to the shared drm
 527          * mapping.
 528          */
 529         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 530         if (ret) {
 531                 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
 532                 goto err_disable_aclk;
 533         }
 534
 535         memcpy(vop->regs, vop->regsbak, vop->len);
 536         vop_cfg_done(vop);
 537
 538         /*
 539          * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 540          */
 541         vop->is_enabled = true;
 542
 543         spin_lock(&vop->reg_lock);
 544
 545         VOP_CTRL_SET(vop, standby, 0);
 546
 547         spin_unlock(&vop->reg_lock);
 548
 549         enable_irq(vop->irq);
 550
 551         drm_crtc_vblank_on(crtc);
 552
 553         return 0;
 554
 555 err_disable_aclk:
 556         clk_disable(vop->aclk);
 557 err_disable_dclk:
 558         clk_disable(vop->dclk);
 559 err_disable_hclk:
 560         clk_disable(vop->hclk);
 561 err_put_pm_runtime:
 562         pm_runtime_put_sync(vop->dev);
 563         return ret;
 564 }
 565
 566 static void vop_crtc_disable(struct drm_crtc *crtc)
 567 {
 568         struct vop *vop = to_vop(crtc);
 569         int i;
 570
 571         WARN_ON(vop->event);
 572
 573         rockchip_drm_psr_deactivate(&vop->crtc);
 574
 575         /*
 576          * We need to make sure that all windows are disabled before we
 577          * disable that crtc. Otherwise we might try to scan from a destroyed
 578          * buffer later.
 579          */
 580         for (i = 0; i < vop->data->win_size; i++) {
 581                 struct vop_win *vop_win = &vop->win[i];
 582                 const struct vop_win_data *win = vop_win->data;
 583
 584                 spin_lock(&vop->reg_lock);
 585                 VOP_WIN_SET(vop, win, enable, 0);
 586                 spin_unlock(&vop->reg_lock);
 587         }
 588
 589         vop_cfg_done(vop);
 590
 591         drm_crtc_vblank_off(crtc);
 592
 593         /*
 594          * Vop standby will take effect at end of current frame,
 595          * if dsp hold valid irq happen, it means standby complete.
 596          *
 597          * we must wait standby complete when we want to disable aclk,
 598          * if not, memory bus maybe dead.
 599          */
 600         reinit_completion(&vop->dsp_hold_completion);
 601         vop_dsp_hold_valid_irq_enable(vop);
 602
 603         spin_lock(&vop->reg_lock);
 604
 605         VOP_CTRL_SET(vop, standby, 1);
 606
 607         spin_unlock(&vop->reg_lock);
 608
 609         wait_for_completion(&vop->dsp_hold_completion);
 610
 611         vop_dsp_hold_valid_irq_disable(vop);
 612
 613         disable_irq(vop->irq);
 614
 615         vop->is_enabled = false;
 616
 617         /*
 618          * vop standby complete, so iommu detach is safe.
 619          */
 620         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 621
 622         clk_disable(vop->dclk);
 623         clk_disable(vop->aclk);
 624         clk_disable(vop->hclk);
 625         pm_runtime_put(vop->dev);
 626
 627         if (crtc->state->event && !crtc->state->active) {
 628                 spin_lock_irq(&crtc->dev->event_lock);
 629                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 630                 spin_unlock_irq(&crtc->dev->event_lock);
 631
 632                 crtc->state->event = NULL;
 633         }
 634 }
 635
 636 static void vop_plane_destroy(struct drm_plane *plane)
 637 {
 638         drm_plane_cleanup(plane);
 639 }
 640
 641 static int vop_plane_atomic_check(struct drm_plane *plane,
 642                            struct drm_plane_state *state)
 643 {
 644         struct drm_crtc *crtc = state->crtc;
 645         struct drm_crtc_state *crtc_state;
 646         struct drm_framebuffer *fb = state->fb;
 647         struct vop_win *vop_win = to_vop_win(plane);
 648         const struct vop_win_data *win = vop_win->data;
 649         int ret;
 650         struct drm_rect clip;
 651         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 652                                         DRM_PLANE_HELPER_NO_SCALING;
 653         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 654                                         DRM_PLANE_HELPER_NO_SCALING;
 655
 656         if (!crtc || !fb)
 657                 return 0;
 658
 659         crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
 660         if (WARN_ON(!crtc_state))
 661                 return -EINVAL;
 662
 663         clip.x1 = 0;
 664         clip.y1 = 0;
 665         clip.x2 = crtc_state->adjusted_mode.hdisplay;
 666         clip.y2 = crtc_state->adjusted_mode.vdisplay;
 667
 668         ret = drm_plane_helper_check_state(state, &clip,
 669                                            min_scale, max_scale,
 670                                            true, true);
 671         if (ret)
 672                 return ret;
 673
 674         if (!state->visible)
 675                 return 0;
 676
 677         ret = vop_convert_format(fb->format->format);
 678         if (ret < 0)
 679                 return ret;
 680
 681         /*
 682          * Src.x1 can be odd when do clip, but yuv plane start point
 683          * need align with 2 pixel.
 684          */
 685         if (is_yuv_support(fb->format->format) && ((state->src.x1 >> 16) % 2))
 686                 return -EINVAL;
 687
 688         return 0;
 689 }
 690
 691 static void vop_plane_atomic_disable(struct drm_plane *plane,
 692                                      struct drm_plane_state *old_state)
 693 {
 694         struct vop_win *vop_win = to_vop_win(plane);
 695         const struct vop_win_data *win = vop_win->data;
 696         struct vop *vop = to_vop(old_state->crtc);
 697
 698         if (!old_state->crtc)
 699                 return;
 700
 701         spin_lock(&vop->reg_lock);
 702
 703         VOP_WIN_SET(vop, win, enable, 0);
 704
 705         spin_unlock(&vop->reg_lock);
 706 }
 707
 708 static void vop_plane_atomic_update(struct drm_plane *plane,
 709                 struct drm_plane_state *old_state)
 710 {
 711         struct drm_plane_state *state = plane->state;
 712         struct drm_crtc *crtc = state->crtc;
 713         struct vop_win *vop_win = to_vop_win(plane);
 714         const struct vop_win_data *win = vop_win->data;
 715         struct vop *vop = to_vop(state->crtc);
 716         struct drm_framebuffer *fb = state->fb;
 717         unsigned int actual_w, actual_h;
 718         unsigned int dsp_stx, dsp_sty;
 719         uint32_t act_info, dsp_info, dsp_st;
 720         struct drm_rect *src = &state->src;
 721         struct drm_rect *dest = &state->dst;
 722         struct drm_gem_object *obj, *uv_obj;
 723         struct rockchip_gem_object *rk_obj, *rk_uv_obj;
 724         unsigned long offset;
 725         dma_addr_t dma_addr;
 726         uint32_t val;
 727         bool rb_swap;
 728         int format;
 729
 730         /*
 731          * can't update plane when vop is disabled.
 732          */
 733         if (WARN_ON(!crtc))
 734                 return;
 735
 736         if (WARN_ON(!vop->is_enabled))
 737                 return;
 738
 739         if (!state->visible) {
 740                 vop_plane_atomic_disable(plane, old_state);
 741                 return;
 742         }
 743
 744         obj = rockchip_fb_get_gem_obj(fb, 0);
 745         rk_obj = to_rockchip_obj(obj);
 746
 747         actual_w = drm_rect_width(src) >> 16;
 748         actual_h = drm_rect_height(src) >> 16;
 749         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 750
 751         dsp_info = (drm_rect_height(dest) - 1) << 16;
 752         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 753
 754         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 755         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 756         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 757
 758         offset = (src->x1 >> 16) * fb->format->cpp[0];
 759         offset += (src->y1 >> 16) * fb->pitches[0];
 760         dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
 761
 762         format = vop_convert_format(fb->format->format);
 763
 764         spin_lock(&vop->reg_lock);
 765
 766         VOP_WIN_SET(vop, win, format, format);
 767         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
 768         VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
 769         if (is_yuv_support(fb->format->format)) {
 770                 int hsub = drm_format_horz_chroma_subsampling(fb->format->format);
 771                 int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
 772                 int bpp = fb->format->cpp[1];
 773
 774                 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
 775                 rk_uv_obj = to_rockchip_obj(uv_obj);
 776
 777                 offset = (src->x1 >> 16) * bpp / hsub;
 778                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 779
 780                 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 781                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
 782                 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
 783         }
 784
 785         if (win->phy->scl)
 786                 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 787                                     drm_rect_width(dest), drm_rect_height(dest),
 788                                     fb->format->format);
 789
 790         VOP_WIN_SET(vop, win, act_info, act_info);
 791         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 792         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 793
 794         rb_swap = has_rb_swapped(fb->format->format);
 795         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 796
 797         if (is_alpha_support(fb->format->format)) {
 798                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 799                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 800                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 801                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 802                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 803                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 804                         SRC_FACTOR_M0(ALPHA_ONE);
 805                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 806         } else {
 807                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 808         }
 809
 810         VOP_WIN_SET(vop, win, enable, 1);
 811         spin_unlock(&vop->reg_lock);
 812 }
 813
 814 static const struct drm_plane_helper_funcs plane_helper_funcs = {
 815         .atomic_check = vop_plane_atomic_check,
 816         .atomic_update = vop_plane_atomic_update,
 817         .atomic_disable = vop_plane_atomic_disable,
 818 };
 819
 820 static const struct drm_plane_funcs vop_plane_funcs = {
 821         .update_plane   = drm_atomic_helper_update_plane,
 822         .disable_plane  = drm_atomic_helper_disable_plane,
 823         .destroy = vop_plane_destroy,
 824         .reset = drm_atomic_helper_plane_reset,
 825         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 826         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
 827 };
 828
 829 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
 830 {
 831         struct vop *vop = to_vop(crtc);
 832         unsigned long flags;
 833
 834         if (WARN_ON(!vop->is_enabled))
 835                 return -EPERM;
 836
 837         spin_lock_irqsave(&vop->irq_lock, flags);
 838
 839         VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
 840         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
 841
 842         spin_unlock_irqrestore(&vop->irq_lock, flags);
 843
 844         return 0;
 845 }
 846
 847 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
 848 {
 849         struct vop *vop = to_vop(crtc);
 850         unsigned long flags;
 851
 852         if (WARN_ON(!vop->is_enabled))
 853                 return;
 854
 855         spin_lock_irqsave(&vop->irq_lock, flags);
 856
 857         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
 858
 859         spin_unlock_irqrestore(&vop->irq_lock, flags);
 860 }
 861
 862 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
 863                                 const struct drm_display_mode *mode,
 864                                 struct drm_display_mode *adjusted_mode)
 865 {
 866         struct vop *vop = to_vop(crtc);
 867
 868         adjusted_mode->clock =
 869                 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
 870
 871         return true;
 872 }
 873
 874 static void vop_crtc_enable(struct drm_crtc *crtc)
 875 {
 876         struct vop *vop = to_vop(crtc);
 877         const struct vop_data *vop_data = vop->data;
 878         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
 879         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
 880         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
 881         u16 hdisplay = adjusted_mode->hdisplay;
 882         u16 htotal = adjusted_mode->htotal;
 883         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
 884         u16 hact_end = hact_st + hdisplay;
 885         u16 vdisplay = adjusted_mode->vdisplay;
 886         u16 vtotal = adjusted_mode->vtotal;
 887         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
 888         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
 889         u16 vact_end = vact_st + vdisplay;
 890         uint32_t pin_pol, val;
 891         int ret;
 892
 893         WARN_ON(vop->event);
 894
 895         ret = vop_enable(crtc);
 896         if (ret) {
 897                 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
 898                 return;
 899         }
 900
 901         /*
 902          * If dclk rate is zero, mean that scanout is stop,
 903          * we don't need wait any more.
 904          */
 905         if (clk_get_rate(vop->dclk)) {
 906                 /*
 907                  * Rk3288 vop timing register is immediately, when configure
 908                  * display timing on display time, may cause tearing.
 909                  *
 910                  * Vop standby will take effect at end of current frame,
 911                  * if dsp hold valid irq happen, it means standby complete.
 912                  *
 913                  * mode set:
 914                  *    standby and wait complete --> |----
 915                  *                                  | display time
 916                  *                                  |----
 917                  *                                  |---> dsp hold irq
 918                  *     configure display timing --> |
 919                  *         standby exit             |
 920                  *                                  | new frame start.
 921                  */
 922
 923                 reinit_completion(&vop->dsp_hold_completion);
 924                 vop_dsp_hold_valid_irq_enable(vop);
 925
 926                 spin_lock(&vop->reg_lock);
 927
 928                 VOP_CTRL_SET(vop, standby, 1);
 929
 930                 spin_unlock(&vop->reg_lock);
 931
 932                 wait_for_completion(&vop->dsp_hold_completion);
 933
 934                 vop_dsp_hold_valid_irq_disable(vop);
 935         }
 936
 937         pin_pol = BIT(DCLK_INVERT);
 938         pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
 939                    BIT(HSYNC_POSITIVE) : 0;
 940         pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
 941                    BIT(VSYNC_POSITIVE) : 0;
 942         VOP_CTRL_SET(vop, pin_pol, pin_pol);
 943
 944         switch (s->output_type) {
 945         case DRM_MODE_CONNECTOR_LVDS:
 946                 VOP_CTRL_SET(vop, rgb_en, 1);
 947                 VOP_CTRL_SET(vop, rgb_pin_pol, pin_pol);
 948                 break;
 949         case DRM_MODE_CONNECTOR_eDP:
 950                 VOP_CTRL_SET(vop, edp_pin_pol, pin_pol);
 951                 VOP_CTRL_SET(vop, edp_en, 1);
 952                 break;
 953         case DRM_MODE_CONNECTOR_HDMIA:
 954                 VOP_CTRL_SET(vop, hdmi_pin_pol, pin_pol);
 955                 VOP_CTRL_SET(vop, hdmi_en, 1);
 956                 break;
 957         case DRM_MODE_CONNECTOR_DSI:
 958                 VOP_CTRL_SET(vop, mipi_pin_pol, pin_pol);
 959                 VOP_CTRL_SET(vop, mipi_en, 1);
 960                 break;
 961         case DRM_MODE_CONNECTOR_DisplayPort:
 962                 pin_pol &= ~BIT(DCLK_INVERT);
 963                 VOP_CTRL_SET(vop, dp_pin_pol, pin_pol);
 964                 VOP_CTRL_SET(vop, dp_en, 1);
 965                 break;
 966         default:
 967                 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
 968                               s->output_type);
 969         }
 970
 971         /*
 972          * if vop is not support RGB10 output, need force RGB10 to RGB888.
 973          */
 974         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
 975             !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
 976                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
 977         VOP_CTRL_SET(vop, out_mode, s->output_mode);
 978
 979         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
 980         val = hact_st << 16;
 981         val |= hact_end;
 982         VOP_CTRL_SET(vop, hact_st_end, val);
 983         VOP_CTRL_SET(vop, hpost_st_end, val);
 984
 985         VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
 986         val = vact_st << 16;
 987         val |= vact_end;
 988         VOP_CTRL_SET(vop, vact_st_end, val);
 989         VOP_CTRL_SET(vop, vpost_st_end, val);
 990
 991         VOP_CTRL_SET(vop, line_flag_num[0], vact_end);
 992
 993         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
 994
 995         VOP_CTRL_SET(vop, standby, 0);
 996
 997         rockchip_drm_psr_activate(&vop->crtc);
 998 }
 999
1000 static bool vop_fs_irq_is_pending(struct vop *vop)
1001 {
1002         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
1003 }
1004
1005 static void vop_wait_for_irq_handler(struct vop *vop)
1006 {
1007         bool pending;
1008         int ret;
1009
1010         /*
1011          * Spin until frame start interrupt status bit goes low, which means
1012          * that interrupt handler was invoked and cleared it. The timeout of
1013          * 10 msecs is really too long, but it is just a safety measure if
1014          * something goes really wrong. The wait will only happen in the very
1015          * unlikely case of a vblank happening exactly at the same time and
1016          * shouldn't exceed microseconds range.
1017          */
1018         ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1019                                         !pending, 0, 10 * 1000);
1020         if (ret)
1021                 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1022
1023         synchronize_irq(vop->irq);
1024 }
1025
1026 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1027                                   struct drm_crtc_state *old_crtc_state)
1028 {
1029         struct drm_atomic_state *old_state = old_crtc_state->state;
1030         struct drm_plane_state *old_plane_state;
1031         struct vop *vop = to_vop(crtc);
1032         struct drm_plane *plane;
1033         int i;
1034
1035         if (WARN_ON(!vop->is_enabled))
1036                 return;
1037
1038         spin_lock(&vop->reg_lock);
1039
1040         vop_cfg_done(vop);
1041
1042         spin_unlock(&vop->reg_lock);
1043
1044         /*
1045          * There is a (rather unlikely) possiblity that a vblank interrupt
1046          * fired before we set the cfg_done bit. To avoid spuriously
1047          * signalling flip completion we need to wait for it to finish.
1048          */
1049         vop_wait_for_irq_handler(vop);
1050
1051         spin_lock_irq(&crtc->dev->event_lock);
1052         if (crtc->state->event) {
1053                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1054                 WARN_ON(vop->event);
1055
1056                 vop->event = crtc->state->event;
1057                 crtc->state->event = NULL;
1058         }
1059         spin_unlock_irq(&crtc->dev->event_lock);
1060
1061         for_each_plane_in_state(old_state, plane, old_plane_state, i) {
1062                 if (!old_plane_state->fb)
1063                         continue;
1064
1065                 if (old_plane_state->fb == plane->state->fb)
1066                         continue;
1067
1068                 drm_framebuffer_reference(old_plane_state->fb);
1069                 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1070                 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1071                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1072         }
1073 }
1074
1075 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1076                                   struct drm_crtc_state *old_crtc_state)
1077 {
1078         rockchip_drm_psr_flush(crtc);
1079 }
1080
1081 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1082         .enable = vop_crtc_enable,
1083         .disable = vop_crtc_disable,
1084         .mode_fixup = vop_crtc_mode_fixup,
1085         .atomic_flush = vop_crtc_atomic_flush,
1086         .atomic_begin = vop_crtc_atomic_begin,
1087 };
1088
1089 static void vop_crtc_destroy(struct drm_crtc *crtc)
1090 {
1091         drm_crtc_cleanup(crtc);
1092 }
1093
1094 static void vop_crtc_reset(struct drm_crtc *crtc)
1095 {
1096         if (crtc->state)
1097                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1098         kfree(crtc->state);
1099
1100         crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1101         if (crtc->state)
1102                 crtc->state->crtc = crtc;
1103 }
1104
1105 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1106 {
1107         struct rockchip_crtc_state *rockchip_state;
1108
1109         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1110         if (!rockchip_state)
1111                 return NULL;
1112
1113         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1114         return &rockchip_state->base;
1115 }
1116
1117 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1118                                    struct drm_crtc_state *state)
1119 {
1120         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1121
1122         __drm_atomic_helper_crtc_destroy_state(&s->base);
1123         kfree(s);
1124 }
1125
1126 #ifdef CONFIG_DRM_ANALOGIX_DP
1127 static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1128 {
1129         struct drm_connector *connector;
1130         struct drm_connector_list_iter conn_iter;
1131
1132         drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
1133         drm_for_each_connector_iter(connector, &conn_iter) {
1134                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1135                         drm_connector_list_iter_end(&conn_iter);
1136                         return connector;
1137                 }
1138         }
1139         drm_connector_list_iter_end(&conn_iter);
1140
1141         return NULL;
1142 }
1143
1144 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1145                                    const char *source_name, size_t *values_cnt)
1146 {
1147         struct vop *vop = to_vop(crtc);
1148         struct drm_connector *connector;
1149         int ret;
1150
1151         connector = vop_get_edp_connector(vop);
1152         if (!connector)
1153                 return -EINVAL;
1154
1155         *values_cnt = 3;
1156
1157         if (source_name && strcmp(source_name, "auto") == 0)
1158                 ret = analogix_dp_start_crc(connector);
1159         else if (!source_name)
1160                 ret = analogix_dp_stop_crc(connector);
1161         else
1162                 ret = -EINVAL;
1163
1164         return ret;
1165 }
1166 #else
1167 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1168                                    const char *source_name, size_t *values_cnt)
1169 {
1170         return -ENODEV;
1171 }
1172 #endif
1173
1174 static const struct drm_crtc_funcs vop_crtc_funcs = {
1175         .set_config = drm_atomic_helper_set_config,
1176         .page_flip = drm_atomic_helper_page_flip,
1177         .destroy = vop_crtc_destroy,
1178         .reset = vop_crtc_reset,
1179         .atomic_duplicate_state = vop_crtc_duplicate_state,
1180         .atomic_destroy_state = vop_crtc_destroy_state,
1181         .enable_vblank = vop_crtc_enable_vblank,
1182         .disable_vblank = vop_crtc_disable_vblank,
1183         .set_crc_source = vop_crtc_set_crc_source,
1184 };
1185
1186 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1187 {
1188         struct vop *vop = container_of(work, struct vop, fb_unref_work);
1189         struct drm_framebuffer *fb = val;
1190
1191         drm_crtc_vblank_put(&vop->crtc);
1192         drm_framebuffer_unreference(fb);
1193 }
1194
1195 static void vop_handle_vblank(struct vop *vop)
1196 {
1197         struct drm_device *drm = vop->drm_dev;
1198         struct drm_crtc *crtc = &vop->crtc;
1199         unsigned long flags;
1200
1201         spin_lock_irqsave(&drm->event_lock, flags);
1202         if (vop->event) {
1203                 drm_crtc_send_vblank_event(crtc, vop->event);
1204                 drm_crtc_vblank_put(crtc);
1205                 vop->event = NULL;
1206         }
1207         spin_unlock_irqrestore(&drm->event_lock, flags);
1208
1209         if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1210                 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1211 }
1212
1213 static irqreturn_t vop_isr(int irq, void *data)
1214 {
1215         struct vop *vop = data;
1216         struct drm_crtc *crtc = &vop->crtc;
1217         uint32_t active_irqs;
1218         unsigned long flags;
1219         int ret = IRQ_NONE;
1220
1221         /*
1222          * interrupt register has interrupt status, enable and clear bits, we
1223          * must hold irq_lock to avoid a race with enable/disable_vblank().
1224         */
1225         spin_lock_irqsave(&vop->irq_lock, flags);
1226
1227         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1228         /* Clear all active interrupt sources */
1229         if (active_irqs)
1230                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1231
1232         spin_unlock_irqrestore(&vop->irq_lock, flags);
1233
1234         /* This is expected for vop iommu irqs, since the irq is shared */
1235         if (!active_irqs)
1236                 return IRQ_NONE;
1237
1238         if (active_irqs & DSP_HOLD_VALID_INTR) {
1239                 complete(&vop->dsp_hold_completion);
1240                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1241                 ret = IRQ_HANDLED;
1242         }
1243
1244         if (active_irqs & LINE_FLAG_INTR) {
1245                 complete(&vop->line_flag_completion);
1246                 active_irqs &= ~LINE_FLAG_INTR;
1247                 ret = IRQ_HANDLED;
1248         }
1249
1250         if (active_irqs & FS_INTR) {
1251                 drm_crtc_handle_vblank(crtc);
1252                 vop_handle_vblank(vop);
1253                 active_irqs &= ~FS_INTR;
1254                 ret = IRQ_HANDLED;
1255         }
1256
1257         /* Unhandled irqs are spurious. */
1258         if (active_irqs)
1259                 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1260                               active_irqs);
1261
1262         return ret;
1263 }
1264
1265 static int vop_create_crtc(struct vop *vop)
1266 {
1267         const struct vop_data *vop_data = vop->data;
1268         struct device *dev = vop->dev;
1269         struct drm_device *drm_dev = vop->drm_dev;
1270         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1271         struct drm_crtc *crtc = &vop->crtc;
1272         struct device_node *port;
1273         int ret;
1274         int i;
1275
1276         /*
1277          * Create drm_plane for primary and cursor planes first, since we need
1278          * to pass them to drm_crtc_init_with_planes, which sets the
1279          * "possible_crtcs" to the newly initialized crtc.
1280          */
1281         for (i = 0; i < vop_data->win_size; i++) {
1282                 struct vop_win *vop_win = &vop->win[i];
1283                 const struct vop_win_data *win_data = vop_win->data;
1284
1285                 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1286                     win_data->type != DRM_PLANE_TYPE_CURSOR)
1287                         continue;
1288
1289                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1290                                                0, &vop_plane_funcs,
1291                                                win_data->phy->data_formats,
1292                                                win_data->phy->nformats,
1293                                                win_data->type, NULL);
1294                 if (ret) {
1295                         DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1296                                       ret);
1297                         goto err_cleanup_planes;
1298                 }
1299
1300                 plane = &vop_win->base;
1301                 drm_plane_helper_add(plane, &plane_helper_funcs);
1302                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1303                         primary = plane;
1304                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1305                         cursor = plane;
1306         }
1307
1308         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1309                                         &vop_crtc_funcs, NULL);
1310         if (ret)
1311                 goto err_cleanup_planes;
1312
1313         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1314
1315         /*
1316          * Create drm_planes for overlay windows with possible_crtcs restricted
1317          * to the newly created crtc.
1318          */
1319         for (i = 0; i < vop_data->win_size; i++) {
1320                 struct vop_win *vop_win = &vop->win[i];
1321                 const struct vop_win_data *win_data = vop_win->data;
1322                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1323
1324                 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1325                         continue;
1326
1327                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1328                                                possible_crtcs,
1329                                                &vop_plane_funcs,
1330                                                win_data->phy->data_formats,
1331                                                win_data->phy->nformats,
1332                                                win_data->type, NULL);
1333                 if (ret) {
1334                         DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1335                                       ret);
1336                         goto err_cleanup_crtc;
1337                 }
1338                 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1339         }
1340
1341         port = of_get_child_by_name(dev->of_node, "port");
1342         if (!port) {
1343                 DRM_DEV_ERROR(vop->dev, "no port node found in %s\n",
1344                               dev->of_node->full_name);
1345                 ret = -ENOENT;
1346                 goto err_cleanup_crtc;
1347         }
1348
1349         drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1350                            vop_fb_unref_worker);
1351
1352         init_completion(&vop->dsp_hold_completion);
1353         init_completion(&vop->line_flag_completion);
1354         crtc->port = port;
1355
1356         return 0;
1357
1358 err_cleanup_crtc:
1359         drm_crtc_cleanup(crtc);
1360 err_cleanup_planes:
1361         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1362                                  head)
1363                 drm_plane_cleanup(plane);
1364         return ret;
1365 }
1366
1367 static void vop_destroy_crtc(struct vop *vop)
1368 {
1369         struct drm_crtc *crtc = &vop->crtc;
1370         struct drm_device *drm_dev = vop->drm_dev;
1371         struct drm_plane *plane, *tmp;
1372
1373         of_node_put(crtc->port);
1374
1375         /*
1376          * We need to cleanup the planes now.  Why?
1377          *
1378          * The planes are "&vop->win[i].base".  That means the memory is
1379          * all part of the big "struct vop" chunk of memory.  That memory
1380          * was devm allocated and associated with this component.  We need to
1381          * free it ourselves before vop_unbind() finishes.
1382          */
1383         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1384                                  head)
1385                 vop_plane_destroy(plane);
1386
1387         /*
1388          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1389          * references the CRTC.
1390          */
1391         drm_crtc_cleanup(crtc);
1392         drm_flip_work_cleanup(&vop->fb_unref_work);
1393 }
1394
1395 static int vop_initial(struct vop *vop)
1396 {
1397         const struct vop_data *vop_data = vop->data;
1398         const struct vop_reg_data *init_table = vop_data->init_table;
1399         struct reset_control *ahb_rst;
1400         int i, ret;
1401
1402         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1403         if (IS_ERR(vop->hclk)) {
1404                 dev_err(vop->dev, "failed to get hclk source\n");
1405                 return PTR_ERR(vop->hclk);
1406         }
1407         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1408         if (IS_ERR(vop->aclk)) {
1409                 dev_err(vop->dev, "failed to get aclk source\n");
1410                 return PTR_ERR(vop->aclk);
1411         }
1412         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1413         if (IS_ERR(vop->dclk)) {
1414                 dev_err(vop->dev, "failed to get dclk source\n");
1415                 return PTR_ERR(vop->dclk);
1416         }
1417
1418         ret = pm_runtime_get_sync(vop->dev);
1419         if (ret < 0) {
1420                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
1421                 return ret;
1422         }
1423
1424         ret = clk_prepare(vop->dclk);
1425         if (ret < 0) {
1426                 dev_err(vop->dev, "failed to prepare dclk\n");
1427                 goto err_put_pm_runtime;
1428         }
1429
1430         /* Enable both the hclk and aclk to setup the vop */
1431         ret = clk_prepare_enable(vop->hclk);
1432         if (ret < 0) {
1433                 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1434                 goto err_unprepare_dclk;
1435         }
1436
1437         ret = clk_prepare_enable(vop->aclk);
1438         if (ret < 0) {
1439                 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1440                 goto err_disable_hclk;
1441         }
1442
1443         /*
1444          * do hclk_reset, reset all vop registers.
1445          */
1446         ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1447         if (IS_ERR(ahb_rst)) {
1448                 dev_err(vop->dev, "failed to get ahb reset\n");
1449                 ret = PTR_ERR(ahb_rst);
1450                 goto err_disable_aclk;
1451         }
1452         reset_control_assert(ahb_rst);
1453         usleep_range(10, 20);
1454         reset_control_deassert(ahb_rst);
1455
1456         memcpy(vop->regsbak, vop->regs, vop->len);
1457
1458         for (i = 0; i < vop_data->table_size; i++)
1459                 vop_writel(vop, init_table[i].offset, init_table[i].value);
1460
1461         for (i = 0; i < vop_data->win_size; i++) {
1462                 const struct vop_win_data *win = &vop_data->win[i];
1463
1464                 VOP_WIN_SET(vop, win, enable, 0);
1465         }
1466
1467         vop_cfg_done(vop);
1468
1469         /*
1470          * do dclk_reset, let all config take affect.
1471          */
1472         vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1473         if (IS_ERR(vop->dclk_rst)) {
1474                 dev_err(vop->dev, "failed to get dclk reset\n");
1475                 ret = PTR_ERR(vop->dclk_rst);
1476                 goto err_disable_aclk;
1477         }
1478         reset_control_assert(vop->dclk_rst);
1479         usleep_range(10, 20);
1480         reset_control_deassert(vop->dclk_rst);
1481
1482         clk_disable(vop->hclk);
1483         clk_disable(vop->aclk);
1484
1485         vop->is_enabled = false;
1486
1487         pm_runtime_put_sync(vop->dev);
1488
1489         return 0;
1490
1491 err_disable_aclk:
1492         clk_disable_unprepare(vop->aclk);
1493 err_disable_hclk:
1494         clk_disable_unprepare(vop->hclk);
1495 err_unprepare_dclk:
1496         clk_unprepare(vop->dclk);
1497 err_put_pm_runtime:
1498         pm_runtime_put_sync(vop->dev);
1499         return ret;
1500 }
1501
1502 /*
1503  * Initialize the vop->win array elements.
1504  */
1505 static void vop_win_init(struct vop *vop)
1506 {
1507         const struct vop_data *vop_data = vop->data;
1508         unsigned int i;
1509
1510         for (i = 0; i < vop_data->win_size; i++) {
1511                 struct vop_win *vop_win = &vop->win[i];
1512                 const struct vop_win_data *win_data = &vop_data->win[i];
1513
1514                 vop_win->data = win_data;
1515                 vop_win->vop = vop;
1516         }
1517 }
1518
1519 /**
1520  * rockchip_drm_wait_vact_end
1521  * @crtc: CRTC to enable line flag
1522  * @mstimeout: millisecond for timeout
1523  *
1524  * Wait for vact_end line flag irq or timeout.
1525  *
1526  * Returns:
1527  * Zero on success, negative errno on failure.
1528  */
1529 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
1530 {
1531         struct vop *vop = to_vop(crtc);
1532         unsigned long jiffies_left;
1533
1534         if (!crtc || !vop->is_enabled)
1535                 return -ENODEV;
1536
1537         if (mstimeout <= 0)
1538                 return -EINVAL;
1539
1540         if (vop_line_flag_irq_is_enabled(vop))
1541                 return -EBUSY;
1542
1543         reinit_completion(&vop->line_flag_completion);
1544         vop_line_flag_irq_enable(vop);
1545
1546         jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
1547                                                    msecs_to_jiffies(mstimeout));
1548         vop_line_flag_irq_disable(vop);
1549
1550         if (jiffies_left == 0) {
1551                 dev_err(vop->dev, "Timeout waiting for IRQ\n");
1552                 return -ETIMEDOUT;
1553         }
1554
1555         return 0;
1556 }
1557 EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
1558
1559 static int vop_bind(struct device *dev, struct device *master, void *data)
1560 {
1561         struct platform_device *pdev = to_platform_device(dev);
1562         const struct vop_data *vop_data;
1563         struct drm_device *drm_dev = data;
1564         struct vop *vop;
1565         struct resource *res;
1566         size_t alloc_size;
1567         int ret, irq;
1568
1569         vop_data = of_device_get_match_data(dev);
1570         if (!vop_data)
1571                 return -ENODEV;
1572
1573         /* Allocate vop struct and its vop_win array */
1574         alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1575         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1576         if (!vop)
1577                 return -ENOMEM;
1578
1579         vop->dev = dev;
1580         vop->data = vop_data;
1581         vop->drm_dev = drm_dev;
1582         dev_set_drvdata(dev, vop);
1583
1584         vop_win_init(vop);
1585
1586         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1587         vop->len = resource_size(res);
1588         vop->regs = devm_ioremap_resource(dev, res);
1589         if (IS_ERR(vop->regs))
1590                 return PTR_ERR(vop->regs);
1591
1592         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1593         if (!vop->regsbak)
1594                 return -ENOMEM;
1595
1596         irq = platform_get_irq(pdev, 0);
1597         if (irq < 0) {
1598                 dev_err(dev, "cannot find irq for vop\n");
1599                 return irq;
1600         }
1601         vop->irq = (unsigned int)irq;
1602
1603         spin_lock_init(&vop->reg_lock);
1604         spin_lock_init(&vop->irq_lock);
1605
1606         mutex_init(&vop->vsync_mutex);
1607
1608         ret = devm_request_irq(dev, vop->irq, vop_isr,
1609                                IRQF_SHARED, dev_name(dev), vop);
1610         if (ret)
1611                 return ret;
1612
1613         /* IRQ is initially disabled; it gets enabled in power_on */
1614         disable_irq(vop->irq);
1615
1616         ret = vop_create_crtc(vop);
1617         if (ret)
1618                 goto err_enable_irq;
1619
1620         pm_runtime_enable(&pdev->dev);
1621
1622         ret = vop_initial(vop);
1623         if (ret < 0) {
1624                 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1625                 goto err_disable_pm_runtime;
1626         }
1627
1628         return 0;
1629
1630 err_disable_pm_runtime:
1631         pm_runtime_disable(&pdev->dev);
1632         vop_destroy_crtc(vop);
1633 err_enable_irq:
1634         enable_irq(vop->irq); /* To balance out the disable_irq above */
1635         return ret;
1636 }
1637
1638 static void vop_unbind(struct device *dev, struct device *master, void *data)
1639 {
1640         struct vop *vop = dev_get_drvdata(dev);
1641
1642         pm_runtime_disable(dev);
1643         vop_destroy_crtc(vop);
1644
1645         clk_unprepare(vop->aclk);
1646         clk_unprepare(vop->hclk);
1647         clk_unprepare(vop->dclk);
1648 }
1649
1650 const struct component_ops vop_component_ops = {
1651         .bind = vop_bind,
1652         .unbind = vop_unbind,
1653 };
1654 EXPORT_SYMBOL_GPL(vop_component_ops);