Merge remote-tracking branch 'drm/drm-next' into drm-misc-next
[sfrench/cifs-2.6.git] / drivers / gpu / drm / rockchip / dw_hdmi-rockchip.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4  */
5
6 #include <linux/clk.h>
7 #include <linux/mfd/syscon.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/phy/phy.h>
11 #include <linux/regmap.h>
12
13 #include <drm/drm_of.h>
14 #include <drm/drmP.h>
15 #include <drm/drm_edid.h>
16 #include <drm/drm_probe_helper.h>
17 #include <drm/bridge/dw_hdmi.h>
18
19 #include "rockchip_drm_drv.h"
20 #include "rockchip_drm_vop.h"
21
22 #define RK3228_GRF_SOC_CON2             0x0408
23 #define RK3228_HDMI_SDAIN_MSK           BIT(14)
24 #define RK3228_HDMI_SCLIN_MSK           BIT(13)
25 #define RK3228_GRF_SOC_CON6             0x0418
26 #define RK3228_HDMI_HPD_VSEL            BIT(6)
27 #define RK3228_HDMI_SDA_VSEL            BIT(5)
28 #define RK3228_HDMI_SCL_VSEL            BIT(4)
29
30 #define RK3288_GRF_SOC_CON6             0x025C
31 #define RK3288_HDMI_LCDC_SEL            BIT(4)
32 #define RK3328_GRF_SOC_CON2             0x0408
33
34 #define RK3328_HDMI_SDAIN_MSK           BIT(11)
35 #define RK3328_HDMI_SCLIN_MSK           BIT(10)
36 #define RK3328_HDMI_HPD_IOE             BIT(2)
37 #define RK3328_GRF_SOC_CON3             0x040c
38 /* need to be unset if hdmi or i2c should control voltage */
39 #define RK3328_HDMI_SDA5V_GRF           BIT(15)
40 #define RK3328_HDMI_SCL5V_GRF           BIT(14)
41 #define RK3328_HDMI_HPD5V_GRF           BIT(13)
42 #define RK3328_HDMI_CEC5V_GRF           BIT(12)
43 #define RK3328_GRF_SOC_CON4             0x0410
44 #define RK3328_HDMI_HPD_SARADC          BIT(13)
45 #define RK3328_HDMI_CEC_5V              BIT(11)
46 #define RK3328_HDMI_SDA_5V              BIT(10)
47 #define RK3328_HDMI_SCL_5V              BIT(9)
48 #define RK3328_HDMI_HPD_5V              BIT(8)
49
50 #define RK3399_GRF_SOC_CON20            0x6250
51 #define RK3399_HDMI_LCDC_SEL            BIT(6)
52
53 #define HIWORD_UPDATE(val, mask)        (val | (mask) << 16)
54
55 /**
56  * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
57  * @lcdsel_grf_reg: grf register offset of lcdc select
58  * @lcdsel_big: reg value of selecting vop big for HDMI
59  * @lcdsel_lit: reg value of selecting vop little for HDMI
60  */
61 struct rockchip_hdmi_chip_data {
62         int     lcdsel_grf_reg;
63         u32     lcdsel_big;
64         u32     lcdsel_lit;
65 };
66
67 struct rockchip_hdmi {
68         struct device *dev;
69         struct regmap *regmap;
70         struct drm_encoder encoder;
71         const struct rockchip_hdmi_chip_data *chip_data;
72         struct clk *vpll_clk;
73         struct clk *grf_clk;
74         struct dw_hdmi *hdmi;
75         struct phy *phy;
76 };
77
78 #define to_rockchip_hdmi(x)     container_of(x, struct rockchip_hdmi, x)
79
80 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
81         {
82                 27000000, {
83                         { 0x00b3, 0x0000},
84                         { 0x2153, 0x0000},
85                         { 0x40f3, 0x0000}
86                 },
87         }, {
88                 36000000, {
89                         { 0x00b3, 0x0000},
90                         { 0x2153, 0x0000},
91                         { 0x40f3, 0x0000}
92                 },
93         }, {
94                 40000000, {
95                         { 0x00b3, 0x0000},
96                         { 0x2153, 0x0000},
97                         { 0x40f3, 0x0000}
98                 },
99         }, {
100                 54000000, {
101                         { 0x0072, 0x0001},
102                         { 0x2142, 0x0001},
103                         { 0x40a2, 0x0001},
104                 },
105         }, {
106                 65000000, {
107                         { 0x0072, 0x0001},
108                         { 0x2142, 0x0001},
109                         { 0x40a2, 0x0001},
110                 },
111         }, {
112                 66000000, {
113                         { 0x013e, 0x0003},
114                         { 0x217e, 0x0002},
115                         { 0x4061, 0x0002}
116                 },
117         }, {
118                 74250000, {
119                         { 0x0072, 0x0001},
120                         { 0x2145, 0x0002},
121                         { 0x4061, 0x0002}
122                 },
123         }, {
124                 83500000, {
125                         { 0x0072, 0x0001},
126                 },
127         }, {
128                 108000000, {
129                         { 0x0051, 0x0002},
130                         { 0x2145, 0x0002},
131                         { 0x4061, 0x0002}
132                 },
133         }, {
134                 106500000, {
135                         { 0x0051, 0x0002},
136                         { 0x2145, 0x0002},
137                         { 0x4061, 0x0002}
138                 },
139         }, {
140                 146250000, {
141                         { 0x0051, 0x0002},
142                         { 0x2145, 0x0002},
143                         { 0x4061, 0x0002}
144                 },
145         }, {
146                 148500000, {
147                         { 0x0051, 0x0003},
148                         { 0x214c, 0x0003},
149                         { 0x4064, 0x0003}
150                 },
151         }, {
152                 ~0UL, {
153                         { 0x00a0, 0x000a },
154                         { 0x2001, 0x000f },
155                         { 0x4002, 0x000f },
156                 },
157         }
158 };
159
160 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
161         /*      pixelclk    bpp8    bpp10   bpp12 */
162         {
163                 40000000,  { 0x0018, 0x0018, 0x0018 },
164         }, {
165                 65000000,  { 0x0028, 0x0028, 0x0028 },
166         }, {
167                 66000000,  { 0x0038, 0x0038, 0x0038 },
168         }, {
169                 74250000,  { 0x0028, 0x0038, 0x0038 },
170         }, {
171                 83500000,  { 0x0028, 0x0038, 0x0038 },
172         }, {
173                 146250000, { 0x0038, 0x0038, 0x0038 },
174         }, {
175                 148500000, { 0x0000, 0x0038, 0x0038 },
176         }, {
177                 ~0UL,      { 0x0000, 0x0000, 0x0000},
178         }
179 };
180
181 static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
182         /*pixelclk   symbol   term   vlev*/
183         { 74250000,  0x8009, 0x0004, 0x0272},
184         { 148500000, 0x802b, 0x0004, 0x028d},
185         { 297000000, 0x8039, 0x0005, 0x028d},
186         { ~0UL,      0x0000, 0x0000, 0x0000}
187 };
188
189 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
190 {
191         struct device_node *np = hdmi->dev->of_node;
192
193         hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
194         if (IS_ERR(hdmi->regmap)) {
195                 DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,grf\n");
196                 return PTR_ERR(hdmi->regmap);
197         }
198
199         hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
200         if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
201                 hdmi->vpll_clk = NULL;
202         } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
203                 return -EPROBE_DEFER;
204         } else if (IS_ERR(hdmi->vpll_clk)) {
205                 DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n");
206                 return PTR_ERR(hdmi->vpll_clk);
207         }
208
209         hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
210         if (PTR_ERR(hdmi->grf_clk) == -ENOENT) {
211                 hdmi->grf_clk = NULL;
212         } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) {
213                 return -EPROBE_DEFER;
214         } else if (IS_ERR(hdmi->grf_clk)) {
215                 DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n");
216                 return PTR_ERR(hdmi->grf_clk);
217         }
218
219         return 0;
220 }
221
222 static enum drm_mode_status
223 dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
224                             const struct drm_display_mode *mode)
225 {
226         const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
227         int pclk = mode->clock * 1000;
228         bool valid = false;
229         int i;
230
231         for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
232                 if (pclk == mpll_cfg[i].mpixelclock) {
233                         valid = true;
234                         break;
235                 }
236         }
237
238         return (valid) ? MODE_OK : MODE_BAD;
239 }
240
241 static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
242         .destroy = drm_encoder_cleanup,
243 };
244
245 static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
246 {
247 }
248
249 static bool
250 dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
251                                     const struct drm_display_mode *mode,
252                                     struct drm_display_mode *adj_mode)
253 {
254         return true;
255 }
256
257 static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
258                                               struct drm_display_mode *mode,
259                                               struct drm_display_mode *adj_mode)
260 {
261         struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
262
263         clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000);
264 }
265
266 static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
267 {
268         struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
269         u32 val;
270         int ret;
271
272         if (hdmi->chip_data->lcdsel_grf_reg < 0)
273                 return;
274
275         ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
276         if (ret)
277                 val = hdmi->chip_data->lcdsel_lit;
278         else
279                 val = hdmi->chip_data->lcdsel_big;
280
281         ret = clk_prepare_enable(hdmi->grf_clk);
282         if (ret < 0) {
283                 DRM_DEV_ERROR(hdmi->dev, "failed to enable grfclk %d\n", ret);
284                 return;
285         }
286
287         ret = regmap_write(hdmi->regmap, hdmi->chip_data->lcdsel_grf_reg, val);
288         if (ret != 0)
289                 DRM_DEV_ERROR(hdmi->dev, "Could not write to GRF: %d\n", ret);
290
291         clk_disable_unprepare(hdmi->grf_clk);
292         DRM_DEV_DEBUG(hdmi->dev, "vop %s output to hdmi\n",
293                       ret ? "LIT" : "BIG");
294 }
295
296 static int
297 dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
298                                       struct drm_crtc_state *crtc_state,
299                                       struct drm_connector_state *conn_state)
300 {
301         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
302
303         s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
304         s->output_type = DRM_MODE_CONNECTOR_HDMIA;
305
306         return 0;
307 }
308
309 static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
310         .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
311         .mode_set   = dw_hdmi_rockchip_encoder_mode_set,
312         .enable     = dw_hdmi_rockchip_encoder_enable,
313         .disable    = dw_hdmi_rockchip_encoder_disable,
314         .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
315 };
316
317 static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data,
318                              struct drm_display_mode *mode)
319 {
320         struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
321
322         return phy_power_on(hdmi->phy);
323 }
324
325 static void dw_hdmi_rockchip_genphy_disable(struct dw_hdmi *dw_hdmi, void *data)
326 {
327         struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
328
329         phy_power_off(hdmi->phy);
330 }
331
332 static void dw_hdmi_rk3228_setup_hpd(struct dw_hdmi *dw_hdmi, void *data)
333 {
334         struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
335
336         dw_hdmi_phy_setup_hpd(dw_hdmi, data);
337
338         regmap_write(hdmi->regmap,
339                 RK3228_GRF_SOC_CON6,
340                 HIWORD_UPDATE(RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL |
341                               RK3228_HDMI_SCL_VSEL,
342                               RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL |
343                               RK3228_HDMI_SCL_VSEL));
344
345         regmap_write(hdmi->regmap,
346                 RK3228_GRF_SOC_CON2,
347                 HIWORD_UPDATE(RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK,
348                               RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK));
349 }
350
351 static enum drm_connector_status
352 dw_hdmi_rk3328_read_hpd(struct dw_hdmi *dw_hdmi, void *data)
353 {
354         struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
355         enum drm_connector_status status;
356
357         status = dw_hdmi_phy_read_hpd(dw_hdmi, data);
358
359         if (status == connector_status_connected)
360                 regmap_write(hdmi->regmap,
361                         RK3328_GRF_SOC_CON4,
362                         HIWORD_UPDATE(RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V,
363                                       RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V));
364         else
365                 regmap_write(hdmi->regmap,
366                         RK3328_GRF_SOC_CON4,
367                         HIWORD_UPDATE(0, RK3328_HDMI_SDA_5V |
368                                          RK3328_HDMI_SCL_5V));
369         return status;
370 }
371
372 static void dw_hdmi_rk3328_setup_hpd(struct dw_hdmi *dw_hdmi, void *data)
373 {
374         struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
375
376         dw_hdmi_phy_setup_hpd(dw_hdmi, data);
377
378         /* Enable and map pins to 3V grf-controlled io-voltage */
379         regmap_write(hdmi->regmap,
380                 RK3328_GRF_SOC_CON4,
381                 HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V |
382                                  RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V |
383                                  RK3328_HDMI_HPD_5V));
384         regmap_write(hdmi->regmap,
385                 RK3328_GRF_SOC_CON3,
386                 HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF |
387                                  RK3328_HDMI_HPD5V_GRF |
388                                  RK3328_HDMI_CEC5V_GRF));
389         regmap_write(hdmi->regmap,
390                 RK3328_GRF_SOC_CON2,
391                 HIWORD_UPDATE(RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK,
392                               RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK |
393                               RK3328_HDMI_HPD_IOE));
394 }
395
396 static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = {
397         .init           = dw_hdmi_rockchip_genphy_init,
398         .disable        = dw_hdmi_rockchip_genphy_disable,
399         .read_hpd       = dw_hdmi_phy_read_hpd,
400         .update_hpd     = dw_hdmi_phy_update_hpd,
401         .setup_hpd      = dw_hdmi_rk3228_setup_hpd,
402 };
403
404 static struct rockchip_hdmi_chip_data rk3228_chip_data = {
405         .lcdsel_grf_reg = -1,
406 };
407
408 static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
409         .mode_valid = dw_hdmi_rockchip_mode_valid,
410         .mpll_cfg = rockchip_mpll_cfg,
411         .cur_ctr = rockchip_cur_ctr,
412         .phy_config = rockchip_phy_config,
413         .phy_data = &rk3228_chip_data,
414         .phy_ops = &rk3228_hdmi_phy_ops,
415         .phy_name = "inno_dw_hdmi_phy2",
416         .phy_force_vendor = true,
417 };
418
419 static struct rockchip_hdmi_chip_data rk3288_chip_data = {
420         .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
421         .lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),
422         .lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SEL, RK3288_HDMI_LCDC_SEL),
423 };
424
425 static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
426         .mode_valid = dw_hdmi_rockchip_mode_valid,
427         .mpll_cfg   = rockchip_mpll_cfg,
428         .cur_ctr    = rockchip_cur_ctr,
429         .phy_config = rockchip_phy_config,
430         .phy_data = &rk3288_chip_data,
431 };
432
433 static const struct dw_hdmi_phy_ops rk3328_hdmi_phy_ops = {
434         .init           = dw_hdmi_rockchip_genphy_init,
435         .disable        = dw_hdmi_rockchip_genphy_disable,
436         .read_hpd       = dw_hdmi_rk3328_read_hpd,
437         .update_hpd     = dw_hdmi_phy_update_hpd,
438         .setup_hpd      = dw_hdmi_rk3328_setup_hpd,
439 };
440
441 static struct rockchip_hdmi_chip_data rk3328_chip_data = {
442         .lcdsel_grf_reg = -1,
443 };
444
445 static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
446         .mode_valid = dw_hdmi_rockchip_mode_valid,
447         .mpll_cfg = rockchip_mpll_cfg,
448         .cur_ctr = rockchip_cur_ctr,
449         .phy_config = rockchip_phy_config,
450         .phy_data = &rk3328_chip_data,
451         .phy_ops = &rk3328_hdmi_phy_ops,
452         .phy_name = "inno_dw_hdmi_phy2",
453         .phy_force_vendor = true,
454 };
455
456 static struct rockchip_hdmi_chip_data rk3399_chip_data = {
457         .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
458         .lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL),
459         .lcdsel_lit = HIWORD_UPDATE(RK3399_HDMI_LCDC_SEL, RK3399_HDMI_LCDC_SEL),
460 };
461
462 static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
463         .mode_valid = dw_hdmi_rockchip_mode_valid,
464         .mpll_cfg   = rockchip_mpll_cfg,
465         .cur_ctr    = rockchip_cur_ctr,
466         .phy_config = rockchip_phy_config,
467         .phy_data = &rk3399_chip_data,
468 };
469
470 static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
471         { .compatible = "rockchip,rk3228-dw-hdmi",
472           .data = &rk3228_hdmi_drv_data
473         },
474         { .compatible = "rockchip,rk3288-dw-hdmi",
475           .data = &rk3288_hdmi_drv_data
476         },
477         { .compatible = "rockchip,rk3328-dw-hdmi",
478           .data = &rk3328_hdmi_drv_data
479         },
480         { .compatible = "rockchip,rk3399-dw-hdmi",
481           .data = &rk3399_hdmi_drv_data
482         },
483         {},
484 };
485 MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
486
487 static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
488                                  void *data)
489 {
490         struct platform_device *pdev = to_platform_device(dev);
491         struct dw_hdmi_plat_data *plat_data;
492         const struct of_device_id *match;
493         struct drm_device *drm = data;
494         struct drm_encoder *encoder;
495         struct rockchip_hdmi *hdmi;
496         int ret;
497
498         if (!pdev->dev.of_node)
499                 return -ENODEV;
500
501         hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
502         if (!hdmi)
503                 return -ENOMEM;
504
505         match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
506         plat_data = devm_kmemdup(&pdev->dev, match->data,
507                                              sizeof(*plat_data), GFP_KERNEL);
508         if (!plat_data)
509                 return -ENOMEM;
510
511         hdmi->dev = &pdev->dev;
512         hdmi->chip_data = plat_data->phy_data;
513         plat_data->phy_data = hdmi;
514         encoder = &hdmi->encoder;
515
516         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
517         /*
518          * If we failed to find the CRTC(s) which this encoder is
519          * supposed to be connected to, it's because the CRTC has
520          * not been registered yet.  Defer probing, and hope that
521          * the required CRTC is added later.
522          */
523         if (encoder->possible_crtcs == 0)
524                 return -EPROBE_DEFER;
525
526         ret = rockchip_hdmi_parse_dt(hdmi);
527         if (ret) {
528                 DRM_DEV_ERROR(hdmi->dev, "Unable to parse OF data\n");
529                 return ret;
530         }
531
532         ret = clk_prepare_enable(hdmi->vpll_clk);
533         if (ret) {
534                 DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
535                               ret);
536                 return ret;
537         }
538
539         hdmi->phy = devm_phy_optional_get(dev, "hdmi");
540         if (IS_ERR(hdmi->phy)) {
541                 ret = PTR_ERR(hdmi->phy);
542                 if (ret != -EPROBE_DEFER)
543                         DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n");
544                 return ret;
545         }
546
547         drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
548         drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
549                          DRM_MODE_ENCODER_TMDS, NULL);
550
551         platform_set_drvdata(pdev, hdmi);
552
553         hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
554
555         /*
556          * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
557          * which would have called the encoder cleanup.  Do it manually.
558          */
559         if (IS_ERR(hdmi->hdmi)) {
560                 ret = PTR_ERR(hdmi->hdmi);
561                 drm_encoder_cleanup(encoder);
562                 clk_disable_unprepare(hdmi->vpll_clk);
563         }
564
565         return ret;
566 }
567
568 static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
569                                     void *data)
570 {
571         struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
572
573         dw_hdmi_unbind(hdmi->hdmi);
574         clk_disable_unprepare(hdmi->vpll_clk);
575 }
576
577 static const struct component_ops dw_hdmi_rockchip_ops = {
578         .bind   = dw_hdmi_rockchip_bind,
579         .unbind = dw_hdmi_rockchip_unbind,
580 };
581
582 static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
583 {
584         return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
585 }
586
587 static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
588 {
589         component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
590
591         return 0;
592 }
593
594 static int __maybe_unused dw_hdmi_rockchip_resume(struct device *dev)
595 {
596         struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
597
598         dw_hdmi_resume(hdmi->hdmi);
599
600         return 0;
601 }
602
603 static const struct dev_pm_ops dw_hdmi_rockchip_pm = {
604         SET_SYSTEM_SLEEP_PM_OPS(NULL, dw_hdmi_rockchip_resume)
605 };
606
607 struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
608         .probe  = dw_hdmi_rockchip_probe,
609         .remove = dw_hdmi_rockchip_remove,
610         .driver = {
611                 .name = "dwhdmi-rockchip",
612                 .pm = &dw_hdmi_rockchip_pm,
613                 .of_match_table = dw_hdmi_rockchip_dt_ids,
614         },
615 };