drivers/gpu/drm/rockchip/dw-mipi-dsi.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/math64.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/regmap.h>
  17 #include <linux/reset.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_crtc.h>
  21 #include <drm/drm_crtc_helper.h>
  22 #include <drm/drm_mipi_dsi.h>
  23 #include <drm/drm_of.h>
  24 #include <drm/drm_panel.h>
  25 #include <drm/drmP.h>
  26 #include <video/mipi_display.h>
  27
  28 #include "rockchip_drm_drv.h"
  29 #include "rockchip_drm_vop.h"
  30
  31 #define DRIVER_NAME    "dw-mipi-dsi"
  32
  33 #define RK3288_GRF_SOC_CON6             0x025c
  34 #define RK3288_DSI0_SEL_VOP_LIT         BIT(6)
  35 #define RK3288_DSI1_SEL_VOP_LIT         BIT(9)
  36
  37 #define RK3399_GRF_SOC_CON20            0x6250
  38 #define RK3399_DSI0_SEL_VOP_LIT         BIT(0)
  39 #define RK3399_DSI1_SEL_VOP_LIT         BIT(4)
  40
  41 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
  42 #define RK3399_GRF_SOC_CON22            0x6258
  43 #define RK3399_GRF_DSI_MODE             0xffff0000
  44
  45 #define DSI_VERSION                     0x00
  46 #define DSI_PWR_UP                      0x04
  47 #define RESET                           0
  48 #define POWERUP                         BIT(0)
  49
  50 #define DSI_CLKMGR_CFG                  0x08
  51 #define TO_CLK_DIVIDSION(div)           (((div) & 0xff) << 8)
  52 #define TX_ESC_CLK_DIVIDSION(div)       (((div) & 0xff) << 0)
  53
  54 #define DSI_DPI_VCID                    0x0c
  55 #define DPI_VID(vid)                    (((vid) & 0x3) << 0)
  56
  57 #define DSI_DPI_COLOR_CODING            0x10
  58 #define EN18_LOOSELY                    BIT(8)
  59 #define DPI_COLOR_CODING_16BIT_1        0x0
  60 #define DPI_COLOR_CODING_16BIT_2        0x1
  61 #define DPI_COLOR_CODING_16BIT_3        0x2
  62 #define DPI_COLOR_CODING_18BIT_1        0x3
  63 #define DPI_COLOR_CODING_18BIT_2        0x4
  64 #define DPI_COLOR_CODING_24BIT          0x5
  65
  66 #define DSI_DPI_CFG_POL                 0x14
  67 #define COLORM_ACTIVE_LOW               BIT(4)
  68 #define SHUTD_ACTIVE_LOW                BIT(3)
  69 #define HSYNC_ACTIVE_LOW                BIT(2)
  70 #define VSYNC_ACTIVE_LOW                BIT(1)
  71 #define DATAEN_ACTIVE_LOW               BIT(0)
  72
  73 #define DSI_DPI_LP_CMD_TIM              0x18
  74 #define OUTVACT_LPCMD_TIME(p)           (((p) & 0xff) << 16)
  75 #define INVACT_LPCMD_TIME(p)            ((p) & 0xff)
  76
  77 #define DSI_DBI_CFG                     0x20
  78 #define DSI_DBI_CMDSIZE                 0x28
  79
  80 #define DSI_PCKHDL_CFG                  0x2c
  81 #define EN_CRC_RX                       BIT(4)
  82 #define EN_ECC_RX                       BIT(3)
  83 #define EN_BTA                          BIT(2)
  84 #define EN_EOTP_RX                      BIT(1)
  85 #define EN_EOTP_TX                      BIT(0)
  86
  87 #define DSI_MODE_CFG                    0x34
  88 #define ENABLE_VIDEO_MODE               0
  89 #define ENABLE_CMD_MODE                 BIT(0)
  90
  91 #define DSI_VID_MODE_CFG                0x38
  92 #define FRAME_BTA_ACK                   BIT(14)
  93 #define ENABLE_LOW_POWER                (0x3f << 8)
  94 #define ENABLE_LOW_POWER_MASK           (0x3f << 8)
  95 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES     0x0
  96 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS     0x1
  97 #define VID_MODE_TYPE_BURST                     0x2
  98 #define VID_MODE_TYPE_MASK                      0x3
  99
 100 #define DSI_VID_PKT_SIZE                0x3c
 101 #define VID_PKT_SIZE(p)                 (((p) & 0x3fff) << 0)
 102 #define VID_PKT_MAX_SIZE                0x3fff
 103
 104 #define DSI_VID_HSA_TIME                0x48
 105 #define DSI_VID_HBP_TIME                0x4c
 106 #define DSI_VID_HLINE_TIME              0x50
 107 #define DSI_VID_VSA_LINES               0x54
 108 #define DSI_VID_VBP_LINES               0x58
 109 #define DSI_VID_VFP_LINES               0x5c
 110 #define DSI_VID_VACTIVE_LINES           0x60
 111 #define DSI_CMD_MODE_CFG                0x68
 112 #define MAX_RD_PKT_SIZE_LP              BIT(24)
 113 #define DCS_LW_TX_LP                    BIT(19)
 114 #define DCS_SR_0P_TX_LP                 BIT(18)
 115 #define DCS_SW_1P_TX_LP                 BIT(17)
 116 #define DCS_SW_0P_TX_LP                 BIT(16)
 117 #define GEN_LW_TX_LP                    BIT(14)
 118 #define GEN_SR_2P_TX_LP                 BIT(13)
 119 #define GEN_SR_1P_TX_LP                 BIT(12)
 120 #define GEN_SR_0P_TX_LP                 BIT(11)
 121 #define GEN_SW_2P_TX_LP                 BIT(10)
 122 #define GEN_SW_1P_TX_LP                 BIT(9)
 123 #define GEN_SW_0P_TX_LP                 BIT(8)
 124 #define EN_ACK_RQST                     BIT(1)
 125 #define EN_TEAR_FX                      BIT(0)
 126
 127 #define CMD_MODE_ALL_LP                 (MAX_RD_PKT_SIZE_LP | \
 128                                          DCS_LW_TX_LP | \
 129                                          DCS_SR_0P_TX_LP | \
 130                                          DCS_SW_1P_TX_LP | \
 131                                          DCS_SW_0P_TX_LP | \
 132                                          GEN_LW_TX_LP | \
 133                                          GEN_SR_2P_TX_LP | \
 134                                          GEN_SR_1P_TX_LP | \
 135                                          GEN_SR_0P_TX_LP | \
 136                                          GEN_SW_2P_TX_LP | \
 137                                          GEN_SW_1P_TX_LP | \
 138                                          GEN_SW_0P_TX_LP)
 139
 140 #define DSI_GEN_HDR                     0x6c
 141 #define GEN_HDATA(data)                 (((data) & 0xffff) << 8)
 142 #define GEN_HDATA_MASK                  (0xffff << 8)
 143 #define GEN_HTYPE(type)                 (((type) & 0xff) << 0)
 144 #define GEN_HTYPE_MASK                  0xff
 145
 146 #define DSI_GEN_PLD_DATA                0x70
 147
 148 #define DSI_CMD_PKT_STATUS              0x74
 149 #define GEN_CMD_EMPTY                   BIT(0)
 150 #define GEN_CMD_FULL                    BIT(1)
 151 #define GEN_PLD_W_EMPTY                 BIT(2)
 152 #define GEN_PLD_W_FULL                  BIT(3)
 153 #define GEN_PLD_R_EMPTY                 BIT(4)
 154 #define GEN_PLD_R_FULL                  BIT(5)
 155 #define GEN_RD_CMD_BUSY                 BIT(6)
 156
 157 #define DSI_TO_CNT_CFG                  0x78
 158 #define HSTX_TO_CNT(p)                  (((p) & 0xffff) << 16)
 159 #define LPRX_TO_CNT(p)                  ((p) & 0xffff)
 160
 161 #define DSI_BTA_TO_CNT                  0x8c
 162 #define DSI_LPCLK_CTRL                  0x94
 163 #define AUTO_CLKLANE_CTRL               BIT(1)
 164 #define PHY_TXREQUESTCLKHS              BIT(0)
 165
 166 #define DSI_PHY_TMR_LPCLK_CFG           0x98
 167 #define PHY_CLKHS2LP_TIME(lbcc)         (((lbcc) & 0x3ff) << 16)
 168 #define PHY_CLKLP2HS_TIME(lbcc)         ((lbcc) & 0x3ff)
 169
 170 #define DSI_PHY_TMR_CFG                 0x9c
 171 #define PHY_HS2LP_TIME(lbcc)            (((lbcc) & 0xff) << 24)
 172 #define PHY_LP2HS_TIME(lbcc)            (((lbcc) & 0xff) << 16)
 173 #define MAX_RD_TIME(lbcc)               ((lbcc) & 0x7fff)
 174
 175 #define DSI_PHY_RSTZ                    0xa0
 176 #define PHY_DISFORCEPLL                 0
 177 #define PHY_ENFORCEPLL                  BIT(3)
 178 #define PHY_DISABLECLK                  0
 179 #define PHY_ENABLECLK                   BIT(2)
 180 #define PHY_RSTZ                        0
 181 #define PHY_UNRSTZ                      BIT(1)
 182 #define PHY_SHUTDOWNZ                   0
 183 #define PHY_UNSHUTDOWNZ                 BIT(0)
 184
 185 #define DSI_PHY_IF_CFG                  0xa4
 186 #define N_LANES(n)                      ((((n) - 1) & 0x3) << 0)
 187 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
 188
 189 #define DSI_PHY_STATUS                  0xb0
 190 #define LOCK                            BIT(0)
 191 #define STOP_STATE_CLK_LANE             BIT(2)
 192
 193 #define DSI_PHY_TST_CTRL0               0xb4
 194 #define PHY_TESTCLK                     BIT(1)
 195 #define PHY_UNTESTCLK                   0
 196 #define PHY_TESTCLR                     BIT(0)
 197 #define PHY_UNTESTCLR                   0
 198
 199 #define DSI_PHY_TST_CTRL1               0xb8
 200 #define PHY_TESTEN                      BIT(16)
 201 #define PHY_UNTESTEN                    0
 202 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
 203 #define PHY_TESTDIN(n)                  (((n) & 0xff) << 0)
 204
 205 #define DSI_INT_ST0                     0xbc
 206 #define DSI_INT_ST1                     0xc0
 207 #define DSI_INT_MSK0                    0xc4
 208 #define DSI_INT_MSK1                    0xc8
 209
 210 #define PHY_STATUS_TIMEOUT_US           10000
 211 #define CMD_PKT_STATUS_TIMEOUT_US       20000
 212
 213 #define BYPASS_VCO_RANGE        BIT(7)
 214 #define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
 215 #define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
 216 #define VCO_IN_CAP_CON_LOW      (0x1 << 1)
 217 #define VCO_IN_CAP_CON_HIGH     (0x2 << 1)
 218 #define REF_BIAS_CUR_SEL        BIT(0)
 219
 220 #define CP_CURRENT_3MA          BIT(3)
 221 #define CP_PROGRAM_EN           BIT(7)
 222 #define LPF_PROGRAM_EN          BIT(6)
 223 #define LPF_RESISTORS_20_KOHM   0
 224
 225 #define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
 226
 227 #define INPUT_DIVIDER(val)      (((val) - 1) & 0x7f)
 228 #define LOW_PROGRAM_EN          0
 229 #define HIGH_PROGRAM_EN         BIT(7)
 230 #define LOOP_DIV_LOW_SEL(val)   (((val) - 1) & 0x1f)
 231 #define LOOP_DIV_HIGH_SEL(val)  ((((val) - 1) >> 5) & 0x1f)
 232 #define PLL_LOOP_DIV_EN         BIT(5)
 233 #define PLL_INPUT_DIV_EN        BIT(4)
 234
 235 #define POWER_CONTROL           BIT(6)
 236 #define INTERNAL_REG_CURRENT    BIT(3)
 237 #define BIAS_BLOCK_ON           BIT(2)
 238 #define BANDGAP_ON              BIT(0)
 239
 240 #define TER_RESISTOR_HIGH       BIT(7)
 241 #define TER_RESISTOR_LOW        0
 242 #define LEVEL_SHIFTERS_ON       BIT(6)
 243 #define TER_CAL_DONE            BIT(5)
 244 #define SETRD_MAX               (0x7 << 2)
 245 #define POWER_MANAGE            BIT(1)
 246 #define TER_RESISTORS_ON        BIT(0)
 247
 248 #define BIASEXTR_SEL(val)       ((val) & 0x7)
 249 #define BANDGAP_SEL(val)        ((val) & 0x7)
 250 #define TLP_PROGRAM_EN          BIT(7)
 251 #define THS_PRE_PROGRAM_EN      BIT(7)
 252 #define THS_ZERO_PROGRAM_EN     BIT(6)
 253
 254 #define DW_MIPI_NEEDS_PHY_CFG_CLK       BIT(0)
 255 #define DW_MIPI_NEEDS_GRF_CLK           BIT(1)
 256
 257 enum {
 258         BANDGAP_97_07,
 259         BANDGAP_98_05,
 260         BANDGAP_99_02,
 261         BANDGAP_100_00,
 262         BANDGAP_93_17,
 263         BANDGAP_94_15,
 264         BANDGAP_95_12,
 265         BANDGAP_96_10,
 266 };
 267
 268 enum {
 269         BIASEXTR_87_1,
 270         BIASEXTR_91_5,
 271         BIASEXTR_95_9,
 272         BIASEXTR_100,
 273         BIASEXTR_105_94,
 274         BIASEXTR_111_88,
 275         BIASEXTR_118_8,
 276         BIASEXTR_127_7,
 277 };
 278
 279 struct dw_mipi_dsi_plat_data {
 280         u32 dsi0_en_bit;
 281         u32 dsi1_en_bit;
 282         u32 grf_switch_reg;
 283         u32 grf_dsi0_mode;
 284         u32 grf_dsi0_mode_reg;
 285         unsigned int flags;
 286         unsigned int max_data_lanes;
 287 };
 288
 289 struct dw_mipi_dsi {
 290         struct drm_encoder encoder;
 291         struct drm_connector connector;
 292         struct mipi_dsi_host dsi_host;
 293         struct drm_panel *panel;
 294         struct device *dev;
 295         struct regmap *grf_regmap;
 296         void __iomem *base;
 297
 298         struct clk *grf_clk;
 299         struct clk *pllref_clk;
 300         struct clk *pclk;
 301         struct clk *phy_cfg_clk;
 302
 303         int dpms_mode;
 304         unsigned int lane_mbps; /* per lane */
 305         u32 channel;
 306         u32 lanes;
 307         u32 format;
 308         u16 input_div;
 309         u16 feedback_div;
 310         unsigned long mode_flags;
 311
 312         const struct dw_mipi_dsi_plat_data *pdata;
 313 };
 314
 315 enum dw_mipi_dsi_mode {
 316         DW_MIPI_DSI_CMD_MODE,
 317         DW_MIPI_DSI_VID_MODE,
 318 };
 319
 320 struct dphy_pll_testdin_map {
 321         unsigned int max_mbps;
 322         u8 testdin;
 323 };
 324
 325 /* The table is based on 27MHz DPHY pll reference clock. */
 326 static const struct dphy_pll_testdin_map dptdin_map[] = {
 327         {  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
 328         { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
 329         { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
 330         { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
 331         { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
 332         { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
 333         { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
 334         {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
 335         {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
 336         {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
 337 };
 338
 339 static int max_mbps_to_testdin(unsigned int max_mbps)
 340 {
 341         int i;
 342
 343         for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
 344                 if (dptdin_map[i].max_mbps > max_mbps)
 345                         return dptdin_map[i].testdin;
 346
 347         return -EINVAL;
 348 }
 349
 350 /*
 351  * The controller should generate 2 frames before
 352  * preparing the peripheral.
 353  */
 354 static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode *mode)
 355 {
 356         int refresh, two_frames;
 357
 358         refresh = drm_mode_vrefresh(mode);
 359         two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
 360         msleep(two_frames);
 361 }
 362
 363 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
 364 {
 365         return container_of(host, struct dw_mipi_dsi, dsi_host);
 366 }
 367
 368 static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
 369 {
 370         return container_of(con, struct dw_mipi_dsi, connector);
 371 }
 372
 373 static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
 374 {
 375         return container_of(encoder, struct dw_mipi_dsi, encoder);
 376 }
 377
 378 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
 379 {
 380         writel(val, dsi->base + reg);
 381 }
 382
 383 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
 384 {
 385         return readl(dsi->base + reg);
 386 }
 387
 388 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
 389                                   u8 test_data)
 390 {
 391         /*
 392          * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
 393          * is latched internally as the current test code. Test data is
 394          * programmed internally by rising edge on TESTCLK.
 395          */
 396         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 397
 398         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
 399                                           PHY_TESTDIN(test_code));
 400
 401         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
 402
 403         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
 404                                           PHY_TESTDIN(test_data));
 405
 406         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 407 }
 408
 409 /**
 410  * ns2bc - Nanoseconds to byte clock cycles
 411  */
 412 static inline unsigned int ns2bc(struct dw_mipi_dsi *dsi, int ns)
 413 {
 414         return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);
 415 }
 416
 417 /**
 418  * ns2ui - Nanoseconds to UI time periods
 419  */
 420 static inline unsigned int ns2ui(struct dw_mipi_dsi *dsi, int ns)
 421 {
 422         return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);
 423 }
 424
 425 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 426 {
 427         int ret, testdin, vco, val;
 428
 429         vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
 430
 431         testdin = max_mbps_to_testdin(dsi->lane_mbps);
 432         if (testdin < 0) {
 433                 DRM_DEV_ERROR(dsi->dev,
 434                               "failed to get testdin for %dmbps lane clock\n",
 435                               dsi->lane_mbps);
 436                 return testdin;
 437         }
 438
 439         /* Start by clearing PHY state */
 440         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
 441         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
 442         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
 443
 444         ret = clk_prepare_enable(dsi->phy_cfg_clk);
 445         if (ret) {
 446                 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");
 447                 return ret;
 448         }
 449
 450         dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
 451                                          VCO_RANGE_CON_SEL(vco) |
 452                                          VCO_IN_CAP_CON_LOW |
 453                                          REF_BIAS_CUR_SEL);
 454
 455         dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
 456         dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
 457                                          LPF_RESISTORS_20_KOHM);
 458
 459         dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
 460
 461         dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
 462         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
 463                                          LOW_PROGRAM_EN);
 464         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 465                                          HIGH_PROGRAM_EN);
 466         dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 467
 468         dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
 469                                          BIASEXTR_SEL(BIASEXTR_127_7));
 470         dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
 471                                          BANDGAP_SEL(BANDGAP_96_10));
 472
 473         dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
 474                                          BIAS_BLOCK_ON | BANDGAP_ON);
 475
 476         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
 477                                          SETRD_MAX | TER_RESISTORS_ON);
 478         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
 479                                          SETRD_MAX | POWER_MANAGE |
 480                                          TER_RESISTORS_ON);
 481
 482         dw_mipi_dsi_phy_write(dsi, 0x60, TLP_PROGRAM_EN | ns2bc(dsi, 500));
 483         dw_mipi_dsi_phy_write(dsi, 0x61, THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
 484         dw_mipi_dsi_phy_write(dsi, 0x62, THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
 485         dw_mipi_dsi_phy_write(dsi, 0x63, THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
 486         dw_mipi_dsi_phy_write(dsi, 0x64, BIT(5) | ns2bc(dsi, 100));
 487         dw_mipi_dsi_phy_write(dsi, 0x65, BIT(5) | (ns2bc(dsi, 60) + 7));
 488
 489         dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | ns2bc(dsi, 500));
 490         dw_mipi_dsi_phy_write(dsi, 0x71,
 491                               THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 5));
 492         dw_mipi_dsi_phy_write(dsi, 0x72,
 493                               THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
 494         dw_mipi_dsi_phy_write(dsi, 0x73,
 495                               THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
 496         dw_mipi_dsi_phy_write(dsi, 0x74, BIT(5) | ns2bc(dsi, 100));
 497
 498         dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 499                                      PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 500
 501         ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
 502                                  val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
 503         if (ret < 0) {
 504                 DRM_DEV_ERROR(dsi->dev, "failed to wait for phy lock state\n");
 505                 goto phy_init_end;
 506         }
 507
 508         ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
 509                                  val, val & STOP_STATE_CLK_LANE, 1000,
 510                                  PHY_STATUS_TIMEOUT_US);
 511         if (ret < 0)
 512                 DRM_DEV_ERROR(dsi->dev,
 513                               "failed to wait for phy clk lane stop state\n");
 514
 515 phy_init_end:
 516         clk_disable_unprepare(dsi->phy_cfg_clk);
 517
 518         return ret;
 519 }
 520
 521 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
 522                                     struct drm_display_mode *mode)
 523 {
 524         unsigned int i, pre;
 525         unsigned long mpclk, pllref, tmp;
 526         unsigned int m = 1, n = 1, target_mbps = 1000;
 527         unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps;
 528         int bpp;
 529
 530         bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 531         if (bpp < 0) {
 532                 DRM_DEV_ERROR(dsi->dev,
 533                               "failed to get bpp for pixel format %d\n",
 534                               dsi->format);
 535                 return bpp;
 536         }
 537
 538         mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
 539         if (mpclk) {
 540                 /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
 541                 tmp = mpclk * (bpp / dsi->lanes) * 10 / 8;
 542                 if (tmp < max_mbps)
 543                         target_mbps = tmp;
 544                 else
 545                         DRM_DEV_ERROR(dsi->dev,
 546                                       "DPHY clock frequency is out of range\n");
 547         }
 548
 549         pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
 550         tmp = pllref;
 551
 552         /*
 553          * The limits on the PLL divisor are:
 554          *
 555          *      5MHz <= (pllref / n) <= 40MHz
 556          *
 557          * we walk over these values in descreasing order so that if we hit
 558          * an exact match for target_mbps it is more likely that "m" will be
 559          * even.
 560          *
 561          * TODO: ensure that "m" is even after this loop.
 562          */
 563         for (i = pllref / 5; i > (pllref / 40); i--) {
 564                 pre = pllref / i;
 565                 if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
 566                         tmp = target_mbps % pre;
 567                         n = i;
 568                         m = target_mbps / pre;
 569                 }
 570                 if (tmp == 0)
 571                         break;
 572         }
 573
 574         dsi->lane_mbps = pllref / n * m;
 575         dsi->input_div = n;
 576         dsi->feedback_div = m;
 577
 578         return 0;
 579 }
 580
 581 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 582                                    struct mipi_dsi_device *device)
 583 {
 584         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 585
 586         if (device->lanes > dsi->pdata->max_data_lanes) {
 587                 DRM_DEV_ERROR(dsi->dev,
 588                               "the number of data lanes(%u) is too many\n",
 589                               device->lanes);
 590                 return -EINVAL;
 591         }
 592
 593         dsi->lanes = device->lanes;
 594         dsi->channel = device->channel;
 595         dsi->format = device->format;
 596         dsi->mode_flags = device->mode_flags;
 597         dsi->panel = of_drm_find_panel(device->dev.of_node);
 598         if (dsi->panel)
 599                 return drm_panel_attach(dsi->panel, &dsi->connector);
 600
 601         return -EINVAL;
 602 }
 603
 604 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 605                                    struct mipi_dsi_device *device)
 606 {
 607         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 608
 609         drm_panel_detach(dsi->panel);
 610
 611         return 0;
 612 }
 613
 614 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
 615                                    const struct mipi_dsi_msg *msg)
 616 {
 617         bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
 618         u32 val = 0;
 619
 620         if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
 621                 val |= EN_ACK_RQST;
 622         if (lpm)
 623                 val |= CMD_MODE_ALL_LP;
 624
 625         dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
 626         dsi_write(dsi, DSI_CMD_MODE_CFG, val);
 627 }
 628
 629 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
 630 {
 631         int ret;
 632         u32 val, mask;
 633
 634         ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 635                                  val, !(val & GEN_CMD_FULL), 1000,
 636                                  CMD_PKT_STATUS_TIMEOUT_US);
 637         if (ret < 0) {
 638                 DRM_DEV_ERROR(dsi->dev,
 639                               "failed to get available command FIFO\n");
 640                 return ret;
 641         }
 642
 643         dsi_write(dsi, DSI_GEN_HDR, hdr_val);
 644
 645         mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
 646         ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 647                                  val, (val & mask) == mask,
 648                                  1000, CMD_PKT_STATUS_TIMEOUT_US);
 649         if (ret < 0) {
 650                 DRM_DEV_ERROR(dsi->dev, "failed to write command FIFO\n");
 651                 return ret;
 652         }
 653
 654         return 0;
 655 }
 656
 657 static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi,
 658                                        const struct mipi_dsi_msg *msg)
 659 {
 660         const u8 *tx_buf = msg->tx_buf;
 661         u16 data = 0;
 662         u32 val;
 663
 664         if (msg->tx_len > 0)
 665                 data |= tx_buf[0];
 666         if (msg->tx_len > 1)
 667                 data |= tx_buf[1] << 8;
 668
 669         if (msg->tx_len > 2) {
 670                 DRM_DEV_ERROR(dsi->dev,
 671                               "too long tx buf length %zu for short write\n",
 672                               msg->tx_len);
 673                 return -EINVAL;
 674         }
 675
 676         val = GEN_HDATA(data) | GEN_HTYPE(msg->type);
 677         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
 678 }
 679
 680 static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
 681                                       const struct mipi_dsi_msg *msg)
 682 {
 683         const u8 *tx_buf = msg->tx_buf;
 684         int len = msg->tx_len, pld_data_bytes = sizeof(u32), ret;
 685         u32 hdr_val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
 686         u32 remainder;
 687         u32 val;
 688
 689         if (msg->tx_len < 3) {
 690                 DRM_DEV_ERROR(dsi->dev,
 691                               "wrong tx buf length %zu for long write\n",
 692                               msg->tx_len);
 693                 return -EINVAL;
 694         }
 695
 696         while (DIV_ROUND_UP(len, pld_data_bytes)) {
 697                 if (len < pld_data_bytes) {
 698                         remainder = 0;
 699                         memcpy(&remainder, tx_buf, len);
 700                         dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
 701                         len = 0;
 702                 } else {
 703                         memcpy(&remainder, tx_buf, pld_data_bytes);
 704                         dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
 705                         tx_buf += pld_data_bytes;
 706                         len -= pld_data_bytes;
 707                 }
 708
 709                 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 710                                          val, !(val & GEN_PLD_W_FULL), 1000,
 711                                          CMD_PKT_STATUS_TIMEOUT_US);
 712                 if (ret < 0) {
 713                         DRM_DEV_ERROR(dsi->dev,
 714                                       "failed to get available write payload FIFO\n");
 715                         return ret;
 716                 }
 717         }
 718
 719         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, hdr_val);
 720 }
 721
 722 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
 723                                          const struct mipi_dsi_msg *msg)
 724 {
 725         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 726         int ret;
 727
 728         dw_mipi_message_config(dsi, msg);
 729
 730         switch (msg->type) {
 731         case MIPI_DSI_DCS_SHORT_WRITE:
 732         case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 733         case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
 734                 ret = dw_mipi_dsi_dcs_short_write(dsi, msg);
 735                 break;
 736         case MIPI_DSI_DCS_LONG_WRITE:
 737                 ret = dw_mipi_dsi_dcs_long_write(dsi, msg);
 738                 break;
 739         default:
 740                 DRM_DEV_ERROR(dsi->dev, "unsupported message type 0x%02x\n",
 741                               msg->type);
 742                 ret = -EINVAL;
 743         }
 744
 745         return ret;
 746 }
 747
 748 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 749         .attach = dw_mipi_dsi_host_attach,
 750         .detach = dw_mipi_dsi_host_detach,
 751         .transfer = dw_mipi_dsi_host_transfer,
 752 };
 753
 754 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 755 {
 756         u32 val;
 757
 758         val = ENABLE_LOW_POWER;
 759
 760         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 761                 val |= VID_MODE_TYPE_BURST;
 762         else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 763                 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
 764         else
 765                 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
 766
 767         dsi_write(dsi, DSI_VID_MODE_CFG, val);
 768 }
 769
 770 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 771                                  enum dw_mipi_dsi_mode mode)
 772 {
 773         if (mode == DW_MIPI_DSI_CMD_MODE) {
 774                 dsi_write(dsi, DSI_PWR_UP, RESET);
 775                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 776                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 777         } else {
 778                 dsi_write(dsi, DSI_PWR_UP, RESET);
 779                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 780                 dw_mipi_dsi_video_mode_config(dsi);
 781                 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 782                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 783         }
 784 }
 785
 786 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
 787 {
 788         dsi_write(dsi, DSI_PWR_UP, RESET);
 789         dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
 790 }
 791
 792 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 793 {
 794         /*
 795          * The maximum permitted escape clock is 20MHz and it is derived from
 796          * lanebyteclk, which is running at "lane_mbps / 8".  Thus we want:
 797          *
 798          *     (lane_mbps >> 3) / esc_clk_division < 20
 799          * which is:
 800          *     (lane_mbps >> 3) / 20 > esc_clk_division
 801          */
 802         u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
 803
 804         dsi_write(dsi, DSI_PWR_UP, RESET);
 805         dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 806                   | PHY_RSTZ | PHY_SHUTDOWNZ);
 807         dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
 808                   TX_ESC_CLK_DIVIDSION(esc_clk_division));
 809 }
 810
 811 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 812                                    struct drm_display_mode *mode)
 813 {
 814         u32 val = 0, color = 0;
 815
 816         switch (dsi->format) {
 817         case MIPI_DSI_FMT_RGB888:
 818                 color = DPI_COLOR_CODING_24BIT;
 819                 break;
 820         case MIPI_DSI_FMT_RGB666:
 821                 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
 822                 break;
 823         case MIPI_DSI_FMT_RGB666_PACKED:
 824                 color = DPI_COLOR_CODING_18BIT_1;
 825                 break;
 826         case MIPI_DSI_FMT_RGB565:
 827                 color = DPI_COLOR_CODING_16BIT_1;
 828                 break;
 829         }
 830
 831         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 832                 val |= VSYNC_ACTIVE_LOW;
 833         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 834                 val |= HSYNC_ACTIVE_LOW;
 835
 836         dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
 837         dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
 838         dsi_write(dsi, DSI_DPI_CFG_POL, val);
 839         dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
 840                   | INVACT_LPCMD_TIME(4));
 841 }
 842
 843 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 844 {
 845         dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
 846 }
 847
 848 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 849                                             struct drm_display_mode *mode)
 850 {
 851         dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
 852 }
 853
 854 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 855 {
 856         dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
 857         dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
 858         dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 859 }
 860
 861 /* Get lane byte clock cycles. */
 862 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
 863                                            struct drm_display_mode *mode,
 864                                            u32 hcomponent)
 865 {
 866         u32 frac, lbcc;
 867
 868         lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
 869
 870         frac = lbcc % mode->clock;
 871         lbcc = lbcc / mode->clock;
 872         if (frac)
 873                 lbcc++;
 874
 875         return lbcc;
 876 }
 877
 878 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
 879                                           struct drm_display_mode *mode)
 880 {
 881         u32 htotal, hsa, hbp, lbcc;
 882
 883         htotal = mode->htotal;
 884         hsa = mode->hsync_end - mode->hsync_start;
 885         hbp = mode->htotal - mode->hsync_end;
 886
 887         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
 888         dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
 889
 890         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
 891         dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
 892
 893         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
 894         dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
 895 }
 896
 897 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
 898                                                struct drm_display_mode *mode)
 899 {
 900         u32 vactive, vsa, vfp, vbp;
 901
 902         vactive = mode->vdisplay;
 903         vsa = mode->vsync_end - mode->vsync_start;
 904         vfp = mode->vsync_start - mode->vdisplay;
 905         vbp = mode->vtotal - mode->vsync_end;
 906
 907         dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 908         dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
 909         dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
 910         dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
 911 }
 912
 913 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 914 {
 915         dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)
 916                   | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
 917
 918         dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
 919                   | PHY_CLKLP2HS_TIME(0x40));
 920 }
 921
 922 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 923 {
 924         dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
 925                   N_LANES(dsi->lanes));
 926 }
 927
 928 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 929 {
 930         dsi_read(dsi, DSI_INT_ST0);
 931         dsi_read(dsi, DSI_INT_ST1);
 932         dsi_write(dsi, DSI_INT_MSK0, 0);
 933         dsi_write(dsi, DSI_INT_MSK1, 0);
 934 }
 935
 936 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
 937 {
 938         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 939
 940         if (dsi->dpms_mode != DRM_MODE_DPMS_ON)
 941                 return;
 942
 943         if (clk_prepare_enable(dsi->pclk)) {
 944                 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk\n");
 945                 return;
 946         }
 947
 948         drm_panel_disable(dsi->panel);
 949
 950         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
 951         drm_panel_unprepare(dsi->panel);
 952
 953         dw_mipi_dsi_disable(dsi);
 954         pm_runtime_put(dsi->dev);
 955         clk_disable_unprepare(dsi->pclk);
 956         dsi->dpms_mode = DRM_MODE_DPMS_OFF;
 957 }
 958
 959 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 960 {
 961         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 962         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 963         const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
 964         int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
 965         u32 val;
 966         int ret;
 967
 968         ret = dw_mipi_dsi_get_lane_bps(dsi, mode);
 969         if (ret < 0)
 970                 return;
 971
 972         if (dsi->dpms_mode == DRM_MODE_DPMS_ON)
 973                 return;
 974
 975         if (clk_prepare_enable(dsi->pclk)) {
 976                 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk\n");
 977                 return;
 978         }
 979
 980         pm_runtime_get_sync(dsi->dev);
 981         dw_mipi_dsi_init(dsi);
 982         dw_mipi_dsi_dpi_config(dsi, mode);
 983         dw_mipi_dsi_packet_handler_config(dsi);
 984         dw_mipi_dsi_video_mode_config(dsi);
 985         dw_mipi_dsi_video_packet_config(dsi, mode);
 986         dw_mipi_dsi_command_mode_config(dsi);
 987         dw_mipi_dsi_line_timer_config(dsi, mode);
 988         dw_mipi_dsi_vertical_timing_config(dsi, mode);
 989         dw_mipi_dsi_dphy_timing_config(dsi);
 990         dw_mipi_dsi_dphy_interface_config(dsi);
 991         dw_mipi_dsi_clear_err(dsi);
 992
 993         /*
 994          * For the RK3399, the clk of grf must be enabled before writing grf
 995          * register. And for RK3288 or other soc, this grf_clk must be NULL,
 996          * the clk_prepare_enable return true directly.
 997          */
 998         ret = clk_prepare_enable(dsi->grf_clk);
 999         if (ret) {
1000                 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
1001                 return;
1002         }
1003
1004         if (pdata->grf_dsi0_mode_reg)
1005                 regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
1006                              pdata->grf_dsi0_mode);
1007
1008         dw_mipi_dsi_phy_init(dsi);
1009         dw_mipi_dsi_wait_for_two_frames(mode);
1010
1011         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
1012         if (drm_panel_prepare(dsi->panel))
1013                 DRM_DEV_ERROR(dsi->dev, "failed to prepare panel\n");
1014
1015         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
1016         drm_panel_enable(dsi->panel);
1017
1018         clk_disable_unprepare(dsi->pclk);
1019
1020         if (mux)
1021                 val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
1022         else
1023                 val = pdata->dsi0_en_bit << 16;
1024
1025         regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
1026         DRM_DEV_DEBUG(dsi->dev,
1027                       "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
1028         dsi->dpms_mode = DRM_MODE_DPMS_ON;
1029
1030         clk_disable_unprepare(dsi->grf_clk);
1031 }
1032
1033 static int
1034 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
1035                                  struct drm_crtc_state *crtc_state,
1036                                  struct drm_connector_state *conn_state)
1037 {
1038         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1039         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
1040
1041         switch (dsi->format) {
1042         case MIPI_DSI_FMT_RGB888:
1043                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1044                 break;
1045         case MIPI_DSI_FMT_RGB666:
1046                 s->output_mode = ROCKCHIP_OUT_MODE_P666;
1047                 break;
1048         case MIPI_DSI_FMT_RGB565:
1049                 s->output_mode = ROCKCHIP_OUT_MODE_P565;
1050                 break;
1051         default:
1052                 WARN_ON(1);
1053                 return -EINVAL;
1054         }
1055
1056         s->output_type = DRM_MODE_CONNECTOR_DSI;
1057
1058         return 0;
1059 }
1060
1061 static const struct drm_encoder_helper_funcs
1062 dw_mipi_dsi_encoder_helper_funcs = {
1063         .enable = dw_mipi_dsi_encoder_enable,
1064         .disable = dw_mipi_dsi_encoder_disable,
1065         .atomic_check = dw_mipi_dsi_encoder_atomic_check,
1066 };
1067
1068 static const struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
1069         .destroy = drm_encoder_cleanup,
1070 };
1071
1072 static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
1073 {
1074         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1075
1076         return drm_panel_get_modes(dsi->panel);
1077 }
1078
1079 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
1080         .get_modes = dw_mipi_dsi_connector_get_modes,
1081 };
1082
1083 static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
1084 {
1085         drm_connector_unregister(connector);
1086         drm_connector_cleanup(connector);
1087 }
1088
1089 static const struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
1090         .fill_modes = drm_helper_probe_single_connector_modes,
1091         .destroy = dw_mipi_dsi_drm_connector_destroy,
1092         .reset = drm_atomic_helper_connector_reset,
1093         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1094         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1095 };
1096
1097 static int dw_mipi_dsi_register(struct drm_device *drm,
1098                                 struct dw_mipi_dsi *dsi)
1099 {
1100         struct drm_encoder *encoder = &dsi->encoder;
1101         struct drm_connector *connector = &dsi->connector;
1102         struct device *dev = dsi->dev;
1103         int ret;
1104
1105         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
1106                                                              dev->of_node);
1107         /*
1108          * If we failed to find the CRTC(s) which this encoder is
1109          * supposed to be connected to, it's because the CRTC has
1110          * not been registered yet.  Defer probing, and hope that
1111          * the required CRTC is added later.
1112          */
1113         if (encoder->possible_crtcs == 0)
1114                 return -EPROBE_DEFER;
1115
1116         drm_encoder_helper_add(&dsi->encoder,
1117                                &dw_mipi_dsi_encoder_helper_funcs);
1118         ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
1119                                DRM_MODE_ENCODER_DSI, NULL);
1120         if (ret) {
1121                 DRM_DEV_ERROR(dev, "Failed to initialize encoder with drm\n");
1122                 return ret;
1123         }
1124
1125         drm_connector_helper_add(connector,
1126                                  &dw_mipi_dsi_connector_helper_funcs);
1127
1128         drm_connector_init(drm, &dsi->connector,
1129                            &dw_mipi_dsi_atomic_connector_funcs,
1130                            DRM_MODE_CONNECTOR_DSI);
1131
1132         drm_mode_connector_attach_encoder(connector, encoder);
1133
1134         return 0;
1135 }
1136
1137 static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi)
1138 {
1139         struct device_node *np = dsi->dev->of_node;
1140
1141         dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1142         if (IS_ERR(dsi->grf_regmap)) {
1143                 DRM_DEV_ERROR(dsi->dev, "Unable to get rockchip,grf\n");
1144                 return PTR_ERR(dsi->grf_regmap);
1145         }
1146
1147         return 0;
1148 }
1149
1150 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
1151         .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
1152         .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
1153         .grf_switch_reg = RK3288_GRF_SOC_CON6,
1154         .max_data_lanes = 4,
1155 };
1156
1157 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
1158         .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
1159         .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
1160         .grf_switch_reg = RK3399_GRF_SOC_CON20,
1161         .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
1162         .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
1163         .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1164         .max_data_lanes = 4,
1165 };
1166
1167 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
1168         {
1169          .compatible = "rockchip,rk3288-mipi-dsi",
1170          .data = &rk3288_mipi_dsi_drv_data,
1171         }, {
1172          .compatible = "rockchip,rk3399-mipi-dsi",
1173          .data = &rk3399_mipi_dsi_drv_data,
1174         },
1175         { /* sentinel */ }
1176 };
1177 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
1178
1179 static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
1180                             void *data)
1181 {
1182         const struct of_device_id *of_id =
1183                         of_match_device(dw_mipi_dsi_dt_ids, dev);
1184         const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
1185         struct platform_device *pdev = to_platform_device(dev);
1186         struct reset_control *apb_rst;
1187         struct drm_device *drm = data;
1188         struct dw_mipi_dsi *dsi;
1189         struct resource *res;
1190         int ret;
1191
1192         dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1193         if (!dsi)
1194                 return -ENOMEM;
1195
1196         dsi->dev = dev;
1197         dsi->pdata = pdata;
1198         dsi->dpms_mode = DRM_MODE_DPMS_OFF;
1199
1200         ret = rockchip_mipi_parse_dt(dsi);
1201         if (ret)
1202                 return ret;
1203
1204         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1205         if (!res)
1206                 return -ENODEV;
1207
1208         dsi->base = devm_ioremap_resource(dev, res);
1209         if (IS_ERR(dsi->base))
1210                 return PTR_ERR(dsi->base);
1211
1212         dsi->pllref_clk = devm_clk_get(dev, "ref");
1213         if (IS_ERR(dsi->pllref_clk)) {
1214                 ret = PTR_ERR(dsi->pllref_clk);
1215                 DRM_DEV_ERROR(dev,
1216                               "Unable to get pll reference clock: %d\n", ret);
1217                 return ret;
1218         }
1219
1220         dsi->pclk = devm_clk_get(dev, "pclk");
1221         if (IS_ERR(dsi->pclk)) {
1222                 ret = PTR_ERR(dsi->pclk);
1223                 DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret);
1224                 return ret;
1225         }
1226
1227         /*
1228          * Note that the reset was not defined in the initial device tree, so
1229          * we have to be prepared for it not being found.
1230          */
1231         apb_rst = devm_reset_control_get(dev, "apb");
1232         if (IS_ERR(apb_rst)) {
1233                 ret = PTR_ERR(apb_rst);
1234                 if (ret == -ENOENT) {
1235                         apb_rst = NULL;
1236                 } else {
1237                         DRM_DEV_ERROR(dev,
1238                                       "Unable to get reset control: %d\n", ret);
1239                         return ret;
1240                 }
1241         }
1242
1243         if (apb_rst) {
1244                 ret = clk_prepare_enable(dsi->pclk);
1245                 if (ret) {
1246                         DRM_DEV_ERROR(dev, "Failed to enable pclk\n");
1247                         return ret;
1248                 }
1249
1250                 reset_control_assert(apb_rst);
1251                 usleep_range(10, 20);
1252                 reset_control_deassert(apb_rst);
1253
1254                 clk_disable_unprepare(dsi->pclk);
1255         }
1256
1257         if (pdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
1258                 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1259                 if (IS_ERR(dsi->phy_cfg_clk)) {
1260                         ret = PTR_ERR(dsi->phy_cfg_clk);
1261                         DRM_DEV_ERROR(dev,
1262                                       "Unable to get phy_cfg_clk: %d\n", ret);
1263                         return ret;
1264                 }
1265         }
1266
1267         if (pdata->flags & DW_MIPI_NEEDS_GRF_CLK) {
1268                 dsi->grf_clk = devm_clk_get(dev, "grf");
1269                 if (IS_ERR(dsi->grf_clk)) {
1270                         ret = PTR_ERR(dsi->grf_clk);
1271                         DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret);
1272                         return ret;
1273                 }
1274         }
1275
1276         ret = clk_prepare_enable(dsi->pllref_clk);
1277         if (ret) {
1278                 DRM_DEV_ERROR(dev, "Failed to enable pllref_clk\n");
1279                 return ret;
1280         }
1281
1282         ret = dw_mipi_dsi_register(drm, dsi);
1283         if (ret) {
1284                 DRM_DEV_ERROR(dev, "Failed to register mipi_dsi: %d\n", ret);
1285                 goto err_pllref;
1286         }
1287
1288         dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1289         dsi->dsi_host.dev = dev;
1290         ret = mipi_dsi_host_register(&dsi->dsi_host);
1291         if (ret) {
1292                 DRM_DEV_ERROR(dev, "Failed to register MIPI host: %d\n", ret);
1293                 goto err_cleanup;
1294         }
1295
1296         if (!dsi->panel) {
1297                 ret = -EPROBE_DEFER;
1298                 goto err_mipi_dsi_host;
1299         }
1300
1301         dev_set_drvdata(dev, dsi);
1302         pm_runtime_enable(dev);
1303         return 0;
1304
1305 err_mipi_dsi_host:
1306         mipi_dsi_host_unregister(&dsi->dsi_host);
1307 err_cleanup:
1308         drm_encoder_cleanup(&dsi->encoder);
1309         drm_connector_cleanup(&dsi->connector);
1310 err_pllref:
1311         clk_disable_unprepare(dsi->pllref_clk);
1312         return ret;
1313 }
1314
1315 static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
1316                                void *data)
1317 {
1318         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1319
1320         mipi_dsi_host_unregister(&dsi->dsi_host);
1321         pm_runtime_disable(dev);
1322         clk_disable_unprepare(dsi->pllref_clk);
1323 }
1324
1325 static const struct component_ops dw_mipi_dsi_ops = {
1326         .bind   = dw_mipi_dsi_bind,
1327         .unbind = dw_mipi_dsi_unbind,
1328 };
1329
1330 static int dw_mipi_dsi_probe(struct platform_device *pdev)
1331 {
1332         return component_add(&pdev->dev, &dw_mipi_dsi_ops);
1333 }
1334
1335 static int dw_mipi_dsi_remove(struct platform_device *pdev)
1336 {
1337         component_del(&pdev->dev, &dw_mipi_dsi_ops);
1338         return 0;
1339 }
1340
1341 struct platform_driver dw_mipi_dsi_driver = {
1342         .probe          = dw_mipi_dsi_probe,
1343         .remove         = dw_mipi_dsi_remove,
1344         .driver         = {
1345                 .of_match_table = dw_mipi_dsi_dt_ids,
1346                 .name   = DRIVER_NAME,
1347         },
1348 };