1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Rockchip SoC DP (Display Port) interface driver.
5 * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
6 * Author: Andy Yan <andy.yan@rock-chips.com>
7 * Yakir Yang <ykk@rock-chips.com>
8 * Jeff Chen <jeff.chen@rock-chips.com>
11 #include <linux/component.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/of_device.h>
14 #include <linux/of_graph.h>
15 #include <linux/regmap.h>
16 #include <linux/reset.h>
17 #include <linux/clk.h>
20 #include <drm/drm_dp_helper.h>
21 #include <drm/drm_of.h>
22 #include <drm/drm_panel.h>
23 #include <drm/drm_probe_helper.h>
25 #include <video/of_videomode.h>
26 #include <video/videomode.h>
28 #include <drm/bridge/analogix_dp.h>
30 #include "rockchip_drm_drv.h"
31 #include "rockchip_drm_psr.h"
32 #include "rockchip_drm_vop.h"
34 #define RK3288_GRF_SOC_CON6 0x25c
35 #define RK3288_EDP_LCDC_SEL BIT(5)
36 #define RK3399_GRF_SOC_CON20 0x6250
37 #define RK3399_EDP_LCDC_SEL BIT(5)
39 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
41 #define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100
43 #define to_dp(nm) container_of(nm, struct rockchip_dp_device, nm)
46 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
47 * @lcdsel_grf_reg: grf register offset of lcdc select
48 * @lcdsel_big: reg value of selecting vop big for eDP
49 * @lcdsel_lit: reg value of selecting vop little for eDP
50 * @chip_type: specific chip type
52 struct rockchip_dp_chip_data {
59 struct rockchip_dp_device {
60 struct drm_device *drm_dev;
62 struct drm_encoder encoder;
63 struct drm_display_mode mode;
68 struct reset_control *rst;
70 const struct rockchip_dp_chip_data *data;
72 struct analogix_dp_device *adp;
73 struct analogix_dp_plat_data plat_data;
76 static int analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled)
78 struct rockchip_dp_device *dp = to_dp(encoder);
81 if (!analogix_dp_psr_enabled(dp->adp))
84 DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");
86 ret = rockchip_drm_wait_vact_end(dp->encoder.crtc,
87 PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
89 DRM_DEV_ERROR(dp->dev, "line flag interrupt did not arrive\n");
94 return analogix_dp_enable_psr(dp->adp);
96 return analogix_dp_disable_psr(dp->adp);
99 static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
101 reset_control_assert(dp->rst);
102 usleep_range(10, 20);
103 reset_control_deassert(dp->rst);
108 static int rockchip_dp_poweron_start(struct analogix_dp_plat_data *plat_data)
110 struct rockchip_dp_device *dp = to_dp(plat_data);
113 ret = clk_prepare_enable(dp->pclk);
115 DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
119 ret = rockchip_dp_pre_init(dp);
121 DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret);
122 clk_disable_unprepare(dp->pclk);
129 static int rockchip_dp_poweron_end(struct analogix_dp_plat_data *plat_data)
131 struct rockchip_dp_device *dp = to_dp(plat_data);
133 return rockchip_drm_psr_inhibit_put(&dp->encoder);
136 static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
138 struct rockchip_dp_device *dp = to_dp(plat_data);
141 ret = rockchip_drm_psr_inhibit_get(&dp->encoder);
145 clk_disable_unprepare(dp->pclk);
150 static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
151 struct drm_connector *connector)
153 struct drm_display_info *di = &connector->display_info;
154 /* VOP couldn't output YUV video format for eDP rightly */
155 u32 mask = DRM_COLOR_FORMAT_YCRCB444 | DRM_COLOR_FORMAT_YCRCB422;
157 if ((di->color_formats & mask)) {
158 DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n");
159 di->color_formats &= ~mask;
160 di->color_formats |= DRM_COLOR_FORMAT_RGB444;
168 rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
169 const struct drm_display_mode *mode,
170 struct drm_display_mode *adjusted_mode)
176 static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
177 struct drm_display_mode *mode,
178 struct drm_display_mode *adjusted)
183 static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)
185 struct rockchip_dp_device *dp = to_dp(encoder);
189 ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
194 val = dp->data->lcdsel_lit;
196 val = dp->data->lcdsel_big;
198 DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
200 ret = clk_prepare_enable(dp->grfclk);
202 DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret);
206 ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
208 DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);
210 clk_disable_unprepare(dp->grfclk);
213 static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
219 rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
220 struct drm_crtc_state *crtc_state,
221 struct drm_connector_state *conn_state)
223 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
224 struct drm_display_info *di = &conn_state->connector->display_info;
227 * The hardware IC designed that VOP must output the RGB10 video
228 * format to eDP controller, and if eDP panel only support RGB8,
229 * then eDP controller should cut down the video data, not via VOP
230 * controller, that's why we need to hardcode the VOP output mode
234 s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
235 s->output_type = DRM_MODE_CONNECTOR_eDP;
236 s->output_bpc = di->bpc;
241 static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
242 .mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
243 .mode_set = rockchip_dp_drm_encoder_mode_set,
244 .enable = rockchip_dp_drm_encoder_enable,
245 .disable = rockchip_dp_drm_encoder_nop,
246 .atomic_check = rockchip_dp_drm_encoder_atomic_check,
249 static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
250 .destroy = drm_encoder_cleanup,
253 static int rockchip_dp_of_probe(struct rockchip_dp_device *dp)
255 struct device *dev = dp->dev;
256 struct device_node *np = dev->of_node;
258 dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
259 if (IS_ERR(dp->grf)) {
260 DRM_DEV_ERROR(dev, "failed to get rockchip,grf property\n");
261 return PTR_ERR(dp->grf);
264 dp->grfclk = devm_clk_get(dev, "grf");
265 if (PTR_ERR(dp->grfclk) == -ENOENT) {
267 } else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
268 return -EPROBE_DEFER;
269 } else if (IS_ERR(dp->grfclk)) {
270 DRM_DEV_ERROR(dev, "failed to get grf clock\n");
271 return PTR_ERR(dp->grfclk);
274 dp->pclk = devm_clk_get(dev, "pclk");
275 if (IS_ERR(dp->pclk)) {
276 DRM_DEV_ERROR(dev, "failed to get pclk property\n");
277 return PTR_ERR(dp->pclk);
280 dp->rst = devm_reset_control_get(dev, "dp");
281 if (IS_ERR(dp->rst)) {
282 DRM_DEV_ERROR(dev, "failed to get dp reset control\n");
283 return PTR_ERR(dp->rst);
289 static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
291 struct drm_encoder *encoder = &dp->encoder;
292 struct drm_device *drm_dev = dp->drm_dev;
293 struct device *dev = dp->dev;
296 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
298 DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
300 ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
301 DRM_MODE_ENCODER_TMDS, NULL);
303 DRM_ERROR("failed to initialize encoder with drm\n");
307 drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
312 static int rockchip_dp_bind(struct device *dev, struct device *master,
315 struct rockchip_dp_device *dp = dev_get_drvdata(dev);
316 const struct rockchip_dp_chip_data *dp_data;
317 struct drm_device *drm_dev = data;
320 dp_data = of_device_get_match_data(dev);
325 dp->drm_dev = drm_dev;
327 ret = rockchip_dp_drm_create_encoder(dp);
329 DRM_ERROR("failed to create drm encoder\n");
333 dp->plat_data.encoder = &dp->encoder;
335 dp->plat_data.dev_type = dp->data->chip_type;
336 dp->plat_data.power_on_start = rockchip_dp_poweron_start;
337 dp->plat_data.power_on_end = rockchip_dp_poweron_end;
338 dp->plat_data.power_off = rockchip_dp_powerdown;
339 dp->plat_data.get_modes = rockchip_dp_get_modes;
341 ret = rockchip_drm_psr_register(&dp->encoder, analogix_dp_psr_set);
343 goto err_cleanup_encoder;
345 dp->adp = analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
346 if (IS_ERR(dp->adp)) {
347 ret = PTR_ERR(dp->adp);
353 rockchip_drm_psr_unregister(&dp->encoder);
355 dp->encoder.funcs->destroy(&dp->encoder);
359 static void rockchip_dp_unbind(struct device *dev, struct device *master,
362 struct rockchip_dp_device *dp = dev_get_drvdata(dev);
364 analogix_dp_unbind(dp->adp);
365 rockchip_drm_psr_unregister(&dp->encoder);
366 dp->encoder.funcs->destroy(&dp->encoder);
368 dp->adp = ERR_PTR(-ENODEV);
371 static const struct component_ops rockchip_dp_component_ops = {
372 .bind = rockchip_dp_bind,
373 .unbind = rockchip_dp_unbind,
376 static int rockchip_dp_probe(struct platform_device *pdev)
378 struct device *dev = &pdev->dev;
379 struct drm_panel *panel = NULL;
380 struct rockchip_dp_device *dp;
383 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
387 dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
392 dp->adp = ERR_PTR(-ENODEV);
393 dp->plat_data.panel = panel;
395 ret = rockchip_dp_of_probe(dp);
399 platform_set_drvdata(pdev, dp);
401 return component_add(dev, &rockchip_dp_component_ops);
404 static int rockchip_dp_remove(struct platform_device *pdev)
406 component_del(&pdev->dev, &rockchip_dp_component_ops);
411 #ifdef CONFIG_PM_SLEEP
412 static int rockchip_dp_suspend(struct device *dev)
414 struct rockchip_dp_device *dp = dev_get_drvdata(dev);
419 return analogix_dp_suspend(dp->adp);
422 static int rockchip_dp_resume(struct device *dev)
424 struct rockchip_dp_device *dp = dev_get_drvdata(dev);
429 return analogix_dp_resume(dp->adp);
433 static const struct dev_pm_ops rockchip_dp_pm_ops = {
434 #ifdef CONFIG_PM_SLEEP
435 .suspend_late = rockchip_dp_suspend,
436 .resume_early = rockchip_dp_resume,
440 static const struct rockchip_dp_chip_data rk3399_edp = {
441 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
442 .lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
443 .lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
444 .chip_type = RK3399_EDP,
447 static const struct rockchip_dp_chip_data rk3288_dp = {
448 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
449 .lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
450 .lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
451 .chip_type = RK3288_DP,
454 static const struct of_device_id rockchip_dp_dt_ids[] = {
455 {.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp },
456 {.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp },
459 MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
461 struct platform_driver rockchip_dp_driver = {
462 .probe = rockchip_dp_probe,
463 .remove = rockchip_dp_remove,
465 .name = "rockchip-dp",
466 .pm = &rockchip_dp_pm_ops,
467 .of_match_table = of_match_ptr(rockchip_dp_dt_ids),