drivers/gpu/drm/radeon/si_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "drmP.h"
  25 #include "radeon.h"
  26 #include "radeon_asic.h"
  27 #include "sid.h"
  28 #include "r600_dpm.h"
  29 #include "si_dpm.h"
  30 #include "atom.h"
  31 #include <linux/math64.h>
  32 #include <linux/seq_file.h>
  33
  34 #define MC_CG_ARB_FREQ_F0           0x0a
  35 #define MC_CG_ARB_FREQ_F1           0x0b
  36 #define MC_CG_ARB_FREQ_F2           0x0c
  37 #define MC_CG_ARB_FREQ_F3           0x0d
  38
  39 #define SMC_RAM_END                 0x20000
  40
  41 #define SCLK_MIN_DEEPSLEEP_FREQ     1350
  42
  43 static const struct si_cac_config_reg cac_weights_tahiti[] =
  44 {
  45         { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
  46         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  47         { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
  48         { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
  49         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  50         { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  51         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  52         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  53         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  54         { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
  55         { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  56         { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
  57         { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
  58         { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
  59         { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
  60         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  61         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  62         { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
  63         { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  64         { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
  65         { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
  66         { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
  67         { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  68         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  69         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  70         { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  71         { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  72         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  73         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  74         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  75         { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
  76         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  77         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  78         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  79         { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
  80         { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  81         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  82         { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
  83         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  84         { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
  85         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  86         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  87         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  88         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  89         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  90         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  91         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  92         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  93         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  94         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  95         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  96         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  97         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  98         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  99         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 100         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 101         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 102         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 103         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 104         { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
 105         { 0xFFFFFFFF }
 106 };
 107
 108 static const struct si_cac_config_reg lcac_tahiti[] =
 109 {
 110         { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 111         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 112         { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 113         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 114         { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 115         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 116         { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 117         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 118         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 119         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 120         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 121         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 122         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 123         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 124         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 125         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 126         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 127         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 128         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 129         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 130         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 131         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 132         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 133         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 134         { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 135         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 136         { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 137         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 138         { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 139         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 140         { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 141         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 142         { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 143         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 144         { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 145         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 146         { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 147         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 148         { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 149         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 150         { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 151         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 152         { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 153         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 154         { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 155         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 156         { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 157         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 158         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 159         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 160         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 161         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 162         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 163         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 164         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 165         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 166         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 167         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 168         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 169         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 170         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 171         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 172         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 173         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 174         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 175         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 176         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 177         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 178         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 179         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 180         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 181         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 182         { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
 183         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 184         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 185         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 186         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 187         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 188         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 189         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 190         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 191         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 192         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 193         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 194         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 195         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 196         { 0xFFFFFFFF }
 197
 198 };
 199
 200 static const struct si_cac_config_reg cac_override_tahiti[] =
 201 {
 202         { 0xFFFFFFFF }
 203 };
 204
 205 static const struct si_powertune_data powertune_data_tahiti =
 206 {
 207         ((1 << 16) | 27027),
 208         6,
 209         0,
 210         4,
 211         95,
 212         {
 213                 0UL,
 214                 0UL,
 215                 4521550UL,
 216                 309631529UL,
 217                 -1270850L,
 218                 4513710L,
 219                 40
 220         },
 221         595000000UL,
 222         12,
 223         {
 224                 0,
 225                 0,
 226                 0,
 227                 0,
 228                 0,
 229                 0,
 230                 0,
 231                 0
 232         },
 233         true
 234 };
 235
 236 static const struct si_dte_data dte_data_tahiti =
 237 {
 238         { 1159409, 0, 0, 0, 0 },
 239         { 777, 0, 0, 0, 0 },
 240         2,
 241         54000,
 242         127000,
 243         25,
 244         2,
 245         10,
 246         13,
 247         { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
 248         { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
 249         { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
 250         85,
 251         false
 252 };
 253
 254 static const struct si_dte_data dte_data_tahiti_le =
 255 {
 256         { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
 257         { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
 258         0x5,
 259         0xAFC8,
 260         0x64,
 261         0x32,
 262         1,
 263         0,
 264         0x10,
 265         { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
 266         { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
 267         { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
 268         85,
 269         true
 270 };
 271
 272 static const struct si_dte_data dte_data_tahiti_pro =
 273 {
 274         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 275         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 276         5,
 277         45000,
 278         100,
 279         0xA,
 280         1,
 281         0,
 282         0x10,
 283         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 284         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 285         { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 286         90,
 287         true
 288 };
 289
 290 static const struct si_dte_data dte_data_new_zealand =
 291 {
 292         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
 293         { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
 294         0x5,
 295         0xAFC8,
 296         0x69,
 297         0x32,
 298         1,
 299         0,
 300         0x10,
 301         { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
 302         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 303         { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
 304         85,
 305         true
 306 };
 307
 308 static const struct si_dte_data dte_data_aruba_pro =
 309 {
 310         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 311         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 312         5,
 313         45000,
 314         100,
 315         0xA,
 316         1,
 317         0,
 318         0x10,
 319         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 320         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 321         { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 322         90,
 323         true
 324 };
 325
 326 static const struct si_dte_data dte_data_malta =
 327 {
 328         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 329         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 330         5,
 331         45000,
 332         100,
 333         0xA,
 334         1,
 335         0,
 336         0x10,
 337         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 338         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 339         { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 340         90,
 341         true
 342 };
 343
 344 struct si_cac_config_reg cac_weights_pitcairn[] =
 345 {
 346         { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
 347         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 348         { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 349         { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
 350         { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
 351         { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 352         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 353         { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
 354         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 355         { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
 356         { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
 357         { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
 358         { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
 359         { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
 360         { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 361         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 362         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 363         { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
 364         { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
 365         { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
 366         { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
 367         { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
 368         { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
 369         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 370         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 371         { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
 372         { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
 373         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 374         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 375         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 376         { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
 377         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 378         { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
 379         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 380         { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
 381         { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
 382         { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
 383         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 384         { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
 385         { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 386         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 387         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 388         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 389         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 390         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 391         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 392         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 393         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 394         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 395         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 396         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 397         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 398         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 399         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 400         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 401         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 402         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 403         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 404         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 405         { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
 406         { 0xFFFFFFFF }
 407 };
 408
 409 static const struct si_cac_config_reg lcac_pitcairn[] =
 410 {
 411         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 412         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 413         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 414         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 415         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 416         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 417         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 418         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 419         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 420         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 421         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 422         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 423         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 424         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 425         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 426         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 427         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 428         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 429         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 430         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 431         { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 432         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 433         { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 434         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 435         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 436         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 437         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 438         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 439         { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 440         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 441         { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 442         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 443         { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 444         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 445         { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 446         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 447         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 448         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 449         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 450         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 451         { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 452         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 453         { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 454         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 455         { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 456         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 457         { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 458         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 459         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 460         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 461         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 462         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 463         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 464         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 465         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 466         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 467         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 468         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 469         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 470         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 471         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 472         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 473         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 474         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 475         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 476         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 477         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 478         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 479         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 480         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 481         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 482         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 483         { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 484         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 485         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 486         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 487         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 488         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 489         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 490         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 491         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 492         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 493         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 494         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 495         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 496         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 497         { 0xFFFFFFFF }
 498 };
 499
 500 static const struct si_cac_config_reg cac_override_pitcairn[] =
 501 {
 502         { 0xFFFFFFFF }
 503 };
 504
 505 static const struct si_powertune_data powertune_data_pitcairn =
 506 {
 507         ((1 << 16) | 27027),
 508         5,
 509         0,
 510         6,
 511         100,
 512         {
 513                 51600000UL,
 514                 1800000UL,
 515                 7194395UL,
 516                 309631529UL,
 517                 -1270850L,
 518                 4513710L,
 519                 100
 520         },
 521         117830498UL,
 522         12,
 523         {
 524                 0,
 525                 0,
 526                 0,
 527                 0,
 528                 0,
 529                 0,
 530                 0,
 531                 0
 532         },
 533         true
 534 };
 535
 536 static const struct si_dte_data dte_data_pitcairn =
 537 {
 538         { 0, 0, 0, 0, 0 },
 539         { 0, 0, 0, 0, 0 },
 540         0,
 541         0,
 542         0,
 543         0,
 544         0,
 545         0,
 546         0,
 547         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 548         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 549         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 550         0,
 551         false
 552 };
 553
 554 static const struct si_dte_data dte_data_curacao_xt =
 555 {
 556         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 557         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 558         5,
 559         45000,
 560         100,
 561         0xA,
 562         1,
 563         0,
 564         0x10,
 565         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 566         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 567         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 568         90,
 569         true
 570 };
 571
 572 static const struct si_dte_data dte_data_curacao_pro =
 573 {
 574         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 575         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 576         5,
 577         45000,
 578         100,
 579         0xA,
 580         1,
 581         0,
 582         0x10,
 583         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 584         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 585         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 586         90,
 587         true
 588 };
 589
 590 static const struct si_dte_data dte_data_neptune_xt =
 591 {
 592         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 593         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 594         5,
 595         45000,
 596         100,
 597         0xA,
 598         1,
 599         0,
 600         0x10,
 601         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 602         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 603         { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 604         90,
 605         true
 606 };
 607
 608 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
 609 {
 610         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 611         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 612         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 613         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 614         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 615         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 616         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 617         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 618         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 619         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 620         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 621         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 622         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 623         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 624         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 625         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 626         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 627         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 628         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 629         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 630         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 631         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 632         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 633         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 634         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 635         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 636         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 637         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 638         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 639         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 640         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 641         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 642         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 643         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 644         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 645         { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
 646         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 647         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 648         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 649         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 650         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 651         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 652         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 653         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 654         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 655         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 656         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 657         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 658         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 659         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 660         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 661         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 662         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 663         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 664         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 665         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 666         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 667         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 668         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 669         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 670         { 0xFFFFFFFF }
 671 };
 672
 673 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
 674 {
 675         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 676         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 677         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 678         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 679         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 680         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 681         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 682         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 683         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 684         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 685         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 686         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 687         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 688         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 689         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 690         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 691         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 692         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 693         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 694         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 695         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 696         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 697         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 698         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 699         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 700         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 701         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 702         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 703         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 704         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 705         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 706         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 707         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 708         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 709         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 710         { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
 711         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 712         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 713         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 714         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 715         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 716         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 717         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 718         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 719         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 720         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 721         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 722         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 723         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 724         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 725         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 726         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 727         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 728         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 729         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 730         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 731         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 732         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 733         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 734         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 735         { 0xFFFFFFFF }
 736 };
 737
 738 static const struct si_cac_config_reg cac_weights_heathrow[] =
 739 {
 740         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 741         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 742         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 743         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 744         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 745         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 746         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 747         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 748         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 749         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 750         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 751         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 752         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 753         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 754         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 755         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 756         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 757         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 758         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 759         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 760         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 761         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 762         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 763         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 764         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 765         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 766         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 767         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 768         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 769         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 770         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 771         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 772         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 773         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 774         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 775         { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
 776         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 777         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 778         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 779         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 780         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 781         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 782         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 783         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 784         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 785         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 786         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 787         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 788         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 789         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 790         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 791         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 792         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 793         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 794         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 795         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 796         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 797         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 798         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 799         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 800         { 0xFFFFFFFF }
 801 };
 802
 803 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
 804 {
 805         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 806         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 807         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 808         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 809         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 810         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 811         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 812         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 813         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 814         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 815         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 816         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 817         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 818         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 819         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 820         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 821         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 822         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 823         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 824         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 825         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 826         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 827         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 828         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 829         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 830         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 831         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 832         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 833         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 834         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 835         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 836         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 837         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 838         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 839         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 840         { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
 841         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 842         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 843         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 844         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 845         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 846         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 847         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 848         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 849         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 850         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 851         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 852         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 853         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 854         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 855         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 856         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 857         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 858         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 859         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 860         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 861         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 862         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 863         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 864         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 865         { 0xFFFFFFFF }
 866 };
 867
 868 static const struct si_cac_config_reg cac_weights_cape_verde[] =
 869 {
 870         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 871         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 872         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 873         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 874         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 875         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 876         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 877         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 878         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 879         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 880         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 881         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 882         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 883         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 884         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 885         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 886         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 887         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 888         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 889         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 890         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 891         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 892         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 893         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 894         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 895         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 896         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 897         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 898         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 899         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 900         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 901         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 902         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 903         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 904         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 905         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
 906         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 907         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 908         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 909         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 910         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 911         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 912         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 913         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 914         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 915         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 916         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 917         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 918         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 919         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 920         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 921         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 922         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 923         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 924         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 925         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 926         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 927         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 928         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 929         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 930         { 0xFFFFFFFF }
 931 };
 932
 933 static const struct si_cac_config_reg lcac_cape_verde[] =
 934 {
 935         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 936         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 937         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 938         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 939         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 940         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 941         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 942         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 943         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 944         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 945         { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 946         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 947         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 948         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 949         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 950         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 951         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 952         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 953         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 954         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 955         { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 956         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 957         { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 958         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 959         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 960         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 961         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 962         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 963         { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 964         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 965         { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 966         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 967         { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 968         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 969         { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 970         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 971         { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 972         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 973         { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 974         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 975         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 976         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 977         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 978         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 979         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 980         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 981         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 982         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 983         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 984         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 985         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 986         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 987         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 988         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 989         { 0xFFFFFFFF }
 990 };
 991
 992 static const struct si_cac_config_reg cac_override_cape_verde[] =
 993 {
 994         { 0xFFFFFFFF }
 995 };
 996
 997 static const struct si_powertune_data powertune_data_cape_verde =
 998 {
 999         ((1 << 16) | 0x6993),
1000         5,
1001         0,
1002         7,
1003         105,
1004         {
1005                 0UL,
1006                 0UL,
1007                 7194395UL,
1008                 309631529UL,
1009                 -1270850L,
1010                 4513710L,
1011                 100
1012         },
1013         117830498UL,
1014         12,
1015         {
1016                 0,
1017                 0,
1018                 0,
1019                 0,
1020                 0,
1021                 0,
1022                 0,
1023                 0
1024         },
1025         true
1026 };
1027
1028 static const struct si_dte_data dte_data_cape_verde =
1029 {
1030         { 0, 0, 0, 0, 0 },
1031         { 0, 0, 0, 0, 0 },
1032         0,
1033         0,
1034         0,
1035         0,
1036         0,
1037         0,
1038         0,
1039         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1042         0,
1043         false
1044 };
1045
1046 static const struct si_dte_data dte_data_venus_xtx =
1047 {
1048         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1049         { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1050         5,
1051         55000,
1052         0x69,
1053         0xA,
1054         1,
1055         0,
1056         0x3,
1057         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059         { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1060         90,
1061         true
1062 };
1063
1064 static const struct si_dte_data dte_data_venus_xt =
1065 {
1066         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1067         { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1068         5,
1069         55000,
1070         0x69,
1071         0xA,
1072         1,
1073         0,
1074         0x3,
1075         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077         { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1078         90,
1079         true
1080 };
1081
1082 static const struct si_dte_data dte_data_venus_pro =
1083 {
1084         {  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1085         { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1086         5,
1087         55000,
1088         0x69,
1089         0xA,
1090         1,
1091         0,
1092         0x3,
1093         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095         { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1096         90,
1097         true
1098 };
1099
1100 struct si_cac_config_reg cac_weights_oland[] =
1101 {
1102         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1103         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1104         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1105         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1106         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1107         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1108         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1109         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1110         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1111         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1112         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1113         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1114         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1115         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1116         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1117         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1118         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1119         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1120         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1121         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1122         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1123         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1124         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1125         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1126         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1127         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1128         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1129         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1130         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1131         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1132         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1133         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1134         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1135         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1136         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1137         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1138         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1139         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1140         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1141         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1142         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1143         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1145         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1146         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1147         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1148         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1149         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1150         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1151         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1152         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1153         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1154         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1155         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1156         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1157         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1158         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1159         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1160         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1161         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1162         { 0xFFFFFFFF }
1163 };
1164
1165 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1166 {
1167         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1168         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1169         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1170         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1171         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1172         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1173         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1174         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1175         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1176         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1177         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1178         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1179         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1180         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1181         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1182         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1183         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1184         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1185         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1186         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1187         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1188         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1189         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1190         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1191         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1192         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1193         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1194         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1195         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1196         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1197         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1198         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1199         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1200         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1201         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1202         { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1203         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1204         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1205         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1206         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1207         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1208         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1210         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1211         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1212         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1213         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1214         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1215         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1216         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1217         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1218         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1219         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1220         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1222         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1223         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1224         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1225         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1226         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1227         { 0xFFFFFFFF }
1228 };
1229
1230 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1231 {
1232         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1233         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1234         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1235         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1236         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1237         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1238         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1239         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1240         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1241         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1242         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1243         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1244         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1245         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1246         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1247         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1248         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1249         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1250         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1251         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1252         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1253         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1254         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1255         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1256         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1257         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1258         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1259         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1260         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1261         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1262         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1263         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1264         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1265         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1266         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1267         { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1268         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1269         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1270         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1271         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1272         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1273         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1275         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1276         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1277         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1278         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1279         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1280         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1281         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1282         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1283         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1284         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1285         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1286         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1287         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1288         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1289         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1290         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1291         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1292         { 0xFFFFFFFF }
1293 };
1294
1295 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1296 {
1297         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1298         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1299         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1300         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1301         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1302         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1303         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1304         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1305         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1306         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1307         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1308         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1309         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1310         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1311         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1312         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1313         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1314         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1315         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1316         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1317         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1318         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1319         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1320         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1321         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1322         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1323         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1324         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1325         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1326         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1327         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1328         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1329         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1330         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1331         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1332         { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1333         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1334         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1335         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1336         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1337         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1338         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1340         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1341         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1342         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1343         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1344         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1345         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1346         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1347         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1348         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1349         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1350         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1351         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1352         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1353         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1354         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1355         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1356         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1357         { 0xFFFFFFFF }
1358 };
1359
1360 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1361 {
1362         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1363         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1364         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1365         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1366         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1367         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1368         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1369         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1370         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1371         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1372         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1373         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1374         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1375         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1376         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1377         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1378         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1379         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1380         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1381         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1382         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1383         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1384         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1385         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1386         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1387         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1388         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1389         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1390         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1391         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1392         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1393         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1394         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1395         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1396         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1397         { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1398         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1399         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1400         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1401         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1402         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1403         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1405         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1406         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1407         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1408         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1409         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1410         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1411         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1412         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1413         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1414         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1415         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1416         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1417         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1418         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1419         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1420         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1421         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1422         { 0xFFFFFFFF }
1423 };
1424
1425 static const struct si_cac_config_reg lcac_oland[] =
1426 {
1427         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1428         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1429         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1430         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1431         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1432         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1434         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1435         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1436         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1437         { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1438         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1439         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1440         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1441         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1442         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1443         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1444         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1445         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1446         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1447         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1448         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1449         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1450         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1451         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1452         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1453         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1454         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1455         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1456         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1457         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1458         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1459         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1460         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1461         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1462         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1463         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1464         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1465         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1466         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1467         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1468         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1469         { 0xFFFFFFFF }
1470 };
1471
1472 static const struct si_cac_config_reg lcac_mars_pro[] =
1473 {
1474         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1475         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1476         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1477         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1478         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1479         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1480         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1481         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1483         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1484         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1485         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1486         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1487         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1488         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1489         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1490         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1491         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1492         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1493         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1494         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1495         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1496         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1497         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1499         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1500         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1501         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1502         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1503         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1504         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1505         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1506         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1507         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1508         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1509         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1510         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1511         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1512         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1513         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1514         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1515         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1516         { 0xFFFFFFFF }
1517 };
1518
1519 static const struct si_cac_config_reg cac_override_oland[] =
1520 {
1521         { 0xFFFFFFFF }
1522 };
1523
1524 static const struct si_powertune_data powertune_data_oland =
1525 {
1526         ((1 << 16) | 0x6993),
1527         5,
1528         0,
1529         7,
1530         105,
1531         {
1532                 0UL,
1533                 0UL,
1534                 7194395UL,
1535                 309631529UL,
1536                 -1270850L,
1537                 4513710L,
1538                 100
1539         },
1540         117830498UL,
1541         12,
1542         {
1543                 0,
1544                 0,
1545                 0,
1546                 0,
1547                 0,
1548                 0,
1549                 0,
1550                 0
1551         },
1552         true
1553 };
1554
1555 static const struct si_powertune_data powertune_data_mars_pro =
1556 {
1557         ((1 << 16) | 0x6993),
1558         5,
1559         0,
1560         7,
1561         105,
1562         {
1563                 0UL,
1564                 0UL,
1565                 7194395UL,
1566                 309631529UL,
1567                 -1270850L,
1568                 4513710L,
1569                 100
1570         },
1571         117830498UL,
1572         12,
1573         {
1574                 0,
1575                 0,
1576                 0,
1577                 0,
1578                 0,
1579                 0,
1580                 0,
1581                 0
1582         },
1583         true
1584 };
1585
1586 static const struct si_dte_data dte_data_oland =
1587 {
1588         { 0, 0, 0, 0, 0 },
1589         { 0, 0, 0, 0, 0 },
1590         0,
1591         0,
1592         0,
1593         0,
1594         0,
1595         0,
1596         0,
1597         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1600         0,
1601         false
1602 };
1603
1604 static const struct si_dte_data dte_data_mars_pro =
1605 {
1606         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1607         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1608         5,
1609         55000,
1610         105,
1611         0xA,
1612         1,
1613         0,
1614         0x10,
1615         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1616         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1617         { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1618         90,
1619         true
1620 };
1621
1622 static const struct si_dte_data dte_data_sun_xt =
1623 {
1624         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1625         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1626         5,
1627         55000,
1628         105,
1629         0xA,
1630         1,
1631         0,
1632         0x10,
1633         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1634         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1635         { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1636         90,
1637         true
1638 };
1639
1640
1641 static const struct si_cac_config_reg cac_weights_hainan[] =
1642 {
1643         { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1644         { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1645         { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1646         { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1647         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1648         { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1649         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1650         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1651         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1652         { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1653         { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1654         { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1655         { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1656         { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1657         { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1658         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1659         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1660         { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1661         { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1662         { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1663         { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1664         { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1665         { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1666         { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1667         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1668         { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1669         { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1670         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1671         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1672         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1673         { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1674         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1675         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1677         { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1678         { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1679         { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1680         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1681         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1682         { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1683         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1684         { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1685         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1686         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1687         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1688         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1689         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1690         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1691         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1692         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1693         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1694         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1695         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1696         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1697         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1698         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1699         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1700         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1701         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1702         { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1703         { 0xFFFFFFFF }
1704 };
1705
1706 static const struct si_powertune_data powertune_data_hainan =
1707 {
1708         ((1 << 16) | 0x6993),
1709         5,
1710         0,
1711         9,
1712         105,
1713         {
1714                 0UL,
1715                 0UL,
1716                 7194395UL,
1717                 309631529UL,
1718                 -1270850L,
1719                 4513710L,
1720                 100
1721         },
1722         117830498UL,
1723         12,
1724         {
1725                 0,
1726                 0,
1727                 0,
1728                 0,
1729                 0,
1730                 0,
1731                 0,
1732                 0
1733         },
1734         true
1735 };
1736
1737 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1738 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1739 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1740 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1741
1742 extern int si_mc_load_microcode(struct radeon_device *rdev);
1743 extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable);
1744
1745 static int si_populate_voltage_value(struct radeon_device *rdev,
1746                                      const struct atom_voltage_table *table,
1747                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1748 static int si_get_std_voltage_value(struct radeon_device *rdev,
1749                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1750                                     u16 *std_voltage);
1751 static int si_write_smc_soft_register(struct radeon_device *rdev,
1752                                       u16 reg_offset, u32 value);
1753 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1754                                          struct rv7xx_pl *pl,
1755                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1756 static int si_calculate_sclk_params(struct radeon_device *rdev,
1757                                     u32 engine_clock,
1758                                     SISLANDS_SMC_SCLK_VALUE *sclk);
1759
1760 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
1761 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);
1762
1763 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1764 {
1765         struct si_power_info *pi = rdev->pm.dpm.priv;
1766
1767         return pi;
1768 }
1769
1770 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1771                                                      u16 v, s32 t, u32 ileakage, u32 *leakage)
1772 {
1773         s64 kt, kv, leakage_w, i_leakage, vddc;
1774         s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1775         s64 tmp;
1776
1777         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1778         vddc = div64_s64(drm_int2fixp(v), 1000);
1779         temperature = div64_s64(drm_int2fixp(t), 1000);
1780
1781         t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1782         t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1783         av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1784         bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1785         t_ref = drm_int2fixp(coeff->t_ref);
1786
1787         tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1788         kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1789         kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1790         kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1791
1792         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1793
1794         *leakage = drm_fixp2int(leakage_w * 1000);
1795 }
1796
1797 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1798                                              const struct ni_leakage_coeffients *coeff,
1799                                              u16 v,
1800                                              s32 t,
1801                                              u32 i_leakage,
1802                                              u32 *leakage)
1803 {
1804         si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1805 }
1806
1807 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1808                                                const u32 fixed_kt, u16 v,
1809                                                u32 ileakage, u32 *leakage)
1810 {
1811         s64 kt, kv, leakage_w, i_leakage, vddc;
1812
1813         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1814         vddc = div64_s64(drm_int2fixp(v), 1000);
1815
1816         kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1817         kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1818                           drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1819
1820         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1821
1822         *leakage = drm_fixp2int(leakage_w * 1000);
1823 }
1824
1825 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1826                                        const struct ni_leakage_coeffients *coeff,
1827                                        const u32 fixed_kt,
1828                                        u16 v,
1829                                        u32 i_leakage,
1830                                        u32 *leakage)
1831 {
1832         si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1833 }
1834
1835
1836 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1837                                    struct si_dte_data *dte_data)
1838 {
1839         u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1840         u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1841         u32 k = dte_data->k;
1842         u32 t_max = dte_data->max_t;
1843         u32 t_split[5] = { 10, 15, 20, 25, 30 };
1844         u32 t_0 = dte_data->t0;
1845         u32 i;
1846
1847         if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1848                 dte_data->tdep_count = 3;
1849
1850                 for (i = 0; i < k; i++) {
1851                         dte_data->r[i] =
1852                                 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1853                                 (p_limit2  * (u32)100);
1854                 }
1855
1856                 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1857
1858                 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1859                         dte_data->tdep_r[i] = dte_data->r[4];
1860                 }
1861         } else {
1862                 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1863         }
1864 }
1865
1866 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1867 {
1868         struct ni_power_info *ni_pi = ni_get_pi(rdev);
1869         struct si_power_info *si_pi = si_get_pi(rdev);
1870         bool update_dte_from_pl2 = false;
1871
1872         if (rdev->family == CHIP_TAHITI) {
1873                 si_pi->cac_weights = cac_weights_tahiti;
1874                 si_pi->lcac_config = lcac_tahiti;
1875                 si_pi->cac_override = cac_override_tahiti;
1876                 si_pi->powertune_data = &powertune_data_tahiti;
1877                 si_pi->dte_data = dte_data_tahiti;
1878
1879                 switch (rdev->pdev->device) {
1880                 case 0x6798:
1881                         si_pi->dte_data.enable_dte_by_default = true;
1882                         break;
1883                 case 0x6799:
1884                         si_pi->dte_data = dte_data_new_zealand;
1885                         break;
1886                 case 0x6790:
1887                 case 0x6791:
1888                 case 0x6792:
1889                 case 0x679E:
1890                         si_pi->dte_data = dte_data_aruba_pro;
1891                         update_dte_from_pl2 = true;
1892                         break;
1893                 case 0x679B:
1894                         si_pi->dte_data = dte_data_malta;
1895                         update_dte_from_pl2 = true;
1896                         break;
1897                 case 0x679A:
1898                         si_pi->dte_data = dte_data_tahiti_pro;
1899                         update_dte_from_pl2 = true;
1900                         break;
1901                 default:
1902                         if (si_pi->dte_data.enable_dte_by_default == true)
1903                                 DRM_ERROR("DTE is not enabled!\n");
1904                         break;
1905                 }
1906         } else if (rdev->family == CHIP_PITCAIRN) {
1907                 switch (rdev->pdev->device) {
1908                 case 0x6810:
1909                 case 0x6818:
1910                         si_pi->cac_weights = cac_weights_pitcairn;
1911                         si_pi->lcac_config = lcac_pitcairn;
1912                         si_pi->cac_override = cac_override_pitcairn;
1913                         si_pi->powertune_data = &powertune_data_pitcairn;
1914                         si_pi->dte_data = dte_data_curacao_xt;
1915                         update_dte_from_pl2 = true;
1916                         break;
1917                 case 0x6819:
1918                 case 0x6811:
1919                         si_pi->cac_weights = cac_weights_pitcairn;
1920                         si_pi->lcac_config = lcac_pitcairn;
1921                         si_pi->cac_override = cac_override_pitcairn;
1922                         si_pi->powertune_data = &powertune_data_pitcairn;
1923                         si_pi->dte_data = dte_data_curacao_pro;
1924                         update_dte_from_pl2 = true;
1925                         break;
1926                 case 0x6800:
1927                 case 0x6806:
1928                         si_pi->cac_weights = cac_weights_pitcairn;
1929                         si_pi->lcac_config = lcac_pitcairn;
1930                         si_pi->cac_override = cac_override_pitcairn;
1931                         si_pi->powertune_data = &powertune_data_pitcairn;
1932                         si_pi->dte_data = dte_data_neptune_xt;
1933                         update_dte_from_pl2 = true;
1934                         break;
1935                 default:
1936                         si_pi->cac_weights = cac_weights_pitcairn;
1937                         si_pi->lcac_config = lcac_pitcairn;
1938                         si_pi->cac_override = cac_override_pitcairn;
1939                         si_pi->powertune_data = &powertune_data_pitcairn;
1940                         si_pi->dte_data = dte_data_pitcairn;
1941                         break;
1942                 }
1943         } else if (rdev->family == CHIP_VERDE) {
1944                 si_pi->lcac_config = lcac_cape_verde;
1945                 si_pi->cac_override = cac_override_cape_verde;
1946                 si_pi->powertune_data = &powertune_data_cape_verde;
1947
1948                 switch (rdev->pdev->device) {
1949                 case 0x683B:
1950                 case 0x683F:
1951                 case 0x6829:
1952                 case 0x6835:
1953                         si_pi->cac_weights = cac_weights_cape_verde_pro;
1954                         si_pi->dte_data = dte_data_cape_verde;
1955                         break;
1956                 case 0x682C:
1957                         si_pi->cac_weights = cac_weights_cape_verde_pro;
1958                         si_pi->dte_data = dte_data_sun_xt;
1959                         break;
1960                 case 0x6825:
1961                 case 0x6827:
1962                         si_pi->cac_weights = cac_weights_heathrow;
1963                         si_pi->dte_data = dte_data_cape_verde;
1964                         break;
1965                 case 0x6824:
1966                 case 0x682D:
1967                         si_pi->cac_weights = cac_weights_chelsea_xt;
1968                         si_pi->dte_data = dte_data_cape_verde;
1969                         break;
1970                 case 0x682F:
1971                         si_pi->cac_weights = cac_weights_chelsea_pro;
1972                         si_pi->dte_data = dte_data_cape_verde;
1973                         break;
1974                 case 0x6820:
1975                         si_pi->cac_weights = cac_weights_heathrow;
1976                         si_pi->dte_data = dte_data_venus_xtx;
1977                         break;
1978                 case 0x6821:
1979                         si_pi->cac_weights = cac_weights_heathrow;
1980                         si_pi->dte_data = dte_data_venus_xt;
1981                         break;
1982                 case 0x6823:
1983                 case 0x682B:
1984                 case 0x6822:
1985                 case 0x682A:
1986                         si_pi->cac_weights = cac_weights_chelsea_pro;
1987                         si_pi->dte_data = dte_data_venus_pro;
1988                         break;
1989                 default:
1990                         si_pi->cac_weights = cac_weights_cape_verde;
1991                         si_pi->dte_data = dte_data_cape_verde;
1992                         break;
1993                 }
1994         } else if (rdev->family == CHIP_OLAND) {
1995                 switch (rdev->pdev->device) {
1996                 case 0x6601:
1997                 case 0x6621:
1998                 case 0x6603:
1999                 case 0x6605:
2000                         si_pi->cac_weights = cac_weights_mars_pro;
2001                         si_pi->lcac_config = lcac_mars_pro;
2002                         si_pi->cac_override = cac_override_oland;
2003                         si_pi->powertune_data = &powertune_data_mars_pro;
2004                         si_pi->dte_data = dte_data_mars_pro;
2005                         update_dte_from_pl2 = true;
2006                         break;
2007                 case 0x6600:
2008                 case 0x6606:
2009                 case 0x6620:
2010                 case 0x6604:
2011                         si_pi->cac_weights = cac_weights_mars_xt;
2012                         si_pi->lcac_config = lcac_mars_pro;
2013                         si_pi->cac_override = cac_override_oland;
2014                         si_pi->powertune_data = &powertune_data_mars_pro;
2015                         si_pi->dte_data = dte_data_mars_pro;
2016                         update_dte_from_pl2 = true;
2017                         break;
2018                 case 0x6611:
2019                 case 0x6613:
2020                 case 0x6608:
2021                         si_pi->cac_weights = cac_weights_oland_pro;
2022                         si_pi->lcac_config = lcac_mars_pro;
2023                         si_pi->cac_override = cac_override_oland;
2024                         si_pi->powertune_data = &powertune_data_mars_pro;
2025                         si_pi->dte_data = dte_data_mars_pro;
2026                         update_dte_from_pl2 = true;
2027                         break;
2028                 case 0x6610:
2029                         si_pi->cac_weights = cac_weights_oland_xt;
2030                         si_pi->lcac_config = lcac_mars_pro;
2031                         si_pi->cac_override = cac_override_oland;
2032                         si_pi->powertune_data = &powertune_data_mars_pro;
2033                         si_pi->dte_data = dte_data_mars_pro;
2034                         update_dte_from_pl2 = true;
2035                         break;
2036                 default:
2037                         si_pi->cac_weights = cac_weights_oland;
2038                         si_pi->lcac_config = lcac_oland;
2039                         si_pi->cac_override = cac_override_oland;
2040                         si_pi->powertune_data = &powertune_data_oland;
2041                         si_pi->dte_data = dte_data_oland;
2042                         break;
2043                 }
2044         } else if (rdev->family == CHIP_HAINAN) {
2045                 si_pi->cac_weights = cac_weights_hainan;
2046                 si_pi->lcac_config = lcac_oland;
2047                 si_pi->cac_override = cac_override_oland;
2048                 si_pi->powertune_data = &powertune_data_hainan;
2049                 si_pi->dte_data = dte_data_sun_xt;
2050                 update_dte_from_pl2 = true;
2051         } else {
2052                 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2053                 return;
2054         }
2055
2056         ni_pi->enable_power_containment = false;
2057         ni_pi->enable_cac = false;
2058         ni_pi->enable_sq_ramping = false;
2059         si_pi->enable_dte = false;
2060
2061         if (si_pi->powertune_data->enable_powertune_by_default) {
2062                 ni_pi->enable_power_containment= true;
2063                 ni_pi->enable_cac = true;
2064                 if (si_pi->dte_data.enable_dte_by_default) {
2065                         si_pi->enable_dte = true;
2066                         if (update_dte_from_pl2)
2067                                 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2068
2069                 }
2070                 ni_pi->enable_sq_ramping = true;
2071         }
2072
2073         ni_pi->driver_calculate_cac_leakage = true;
2074         ni_pi->cac_configuration_required = true;
2075
2076         if (ni_pi->cac_configuration_required) {
2077                 ni_pi->support_cac_long_term_average = true;
2078                 si_pi->dyn_powertune_data.l2_lta_window_size =
2079                         si_pi->powertune_data->l2_lta_window_size_default;
2080                 si_pi->dyn_powertune_data.lts_truncate =
2081                         si_pi->powertune_data->lts_truncate_default;
2082         } else {
2083                 ni_pi->support_cac_long_term_average = false;
2084                 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2085                 si_pi->dyn_powertune_data.lts_truncate = 0;
2086         }
2087
2088         si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2089 }
2090
2091 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2092 {
2093         return 1;
2094 }
2095
2096 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2097 {
2098         u32 xclk;
2099         u32 wintime;
2100         u32 cac_window;
2101         u32 cac_window_size;
2102
2103         xclk = radeon_get_xclk(rdev);
2104
2105         if (xclk == 0)
2106                 return 0;
2107
2108         cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2109         cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2110
2111         wintime = (cac_window_size * 100) / xclk;
2112
2113         return wintime;
2114 }
2115
2116 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2117 {
2118         return power_in_watts;
2119 }
2120
2121 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2122                                             bool adjust_polarity,
2123                                             u32 tdp_adjustment,
2124                                             u32 *tdp_limit,
2125                                             u32 *near_tdp_limit)
2126 {
2127         u32 adjustment_delta, max_tdp_limit;
2128
2129         if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2130                 return -EINVAL;
2131
2132         max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2133
2134         if (adjust_polarity) {
2135                 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2136                 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2137         } else {
2138                 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2139                 adjustment_delta  = rdev->pm.dpm.tdp_limit - *tdp_limit;
2140                 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2141                         *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2142                 else
2143                         *near_tdp_limit = 0;
2144         }
2145
2146         if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2147                 return -EINVAL;
2148         if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2149                 return -EINVAL;
2150
2151         return 0;
2152 }
2153
2154 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2155                                       struct radeon_ps *radeon_state)
2156 {
2157         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2158         struct si_power_info *si_pi = si_get_pi(rdev);
2159
2160         if (ni_pi->enable_power_containment) {
2161                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2162                 PP_SIslands_PAPMParameters *papm_parm;
2163                 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2164                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2165                 u32 tdp_limit;
2166                 u32 near_tdp_limit;
2167                 int ret;
2168
2169                 if (scaling_factor == 0)
2170                         return -EINVAL;
2171
2172                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2173
2174                 ret = si_calculate_adjusted_tdp_limits(rdev,
2175                                                        false, /* ??? */
2176                                                        rdev->pm.dpm.tdp_adjustment,
2177                                                        &tdp_limit,
2178                                                        &near_tdp_limit);
2179                 if (ret)
2180                         return ret;
2181
2182                 smc_table->dpm2Params.TDPLimit =
2183                         cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2184                 smc_table->dpm2Params.NearTDPLimit =
2185                         cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2186                 smc_table->dpm2Params.SafePowerLimit =
2187                         cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2188
2189                 ret = si_copy_bytes_to_smc(rdev,
2190                                            (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2191                                                  offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2192                                            (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2193                                            sizeof(u32) * 3,
2194                                            si_pi->sram_end);
2195                 if (ret)
2196                         return ret;
2197
2198                 if (si_pi->enable_ppm) {
2199                         papm_parm = &si_pi->papm_parm;
2200                         memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2201                         papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2202                         papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2203                         papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2204                         papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2205                         papm_parm->PlatformPowerLimit = 0xffffffff;
2206                         papm_parm->NearTDPLimitPAPM = 0xffffffff;
2207
2208                         ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2209                                                    (u8 *)papm_parm,
2210                                                    sizeof(PP_SIslands_PAPMParameters),
2211                                                    si_pi->sram_end);
2212                         if (ret)
2213                                 return ret;
2214                 }
2215         }
2216         return 0;
2217 }
2218
2219 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2220                                         struct radeon_ps *radeon_state)
2221 {
2222         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2223         struct si_power_info *si_pi = si_get_pi(rdev);
2224
2225         if (ni_pi->enable_power_containment) {
2226                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2227                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2228                 int ret;
2229
2230                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2231
2232                 smc_table->dpm2Params.NearTDPLimit =
2233                         cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2234                 smc_table->dpm2Params.SafePowerLimit =
2235                         cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2236
2237                 ret = si_copy_bytes_to_smc(rdev,
2238                                            (si_pi->state_table_start +
2239                                             offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2240                                             offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2241                                            (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2242                                            sizeof(u32) * 2,
2243                                            si_pi->sram_end);
2244                 if (ret)
2245                         return ret;
2246         }
2247
2248         return 0;
2249 }
2250
2251 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2252                                                const u16 prev_std_vddc,
2253                                                const u16 curr_std_vddc)
2254 {
2255         u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2256         u64 prev_vddc = (u64)prev_std_vddc;
2257         u64 curr_vddc = (u64)curr_std_vddc;
2258         u64 pwr_efficiency_ratio, n, d;
2259
2260         if ((prev_vddc == 0) || (curr_vddc == 0))
2261                 return 0;
2262
2263         n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2264         d = prev_vddc * prev_vddc;
2265         pwr_efficiency_ratio = div64_u64(n, d);
2266
2267         if (pwr_efficiency_ratio > (u64)0xFFFF)
2268                 return 0;
2269
2270         return (u16)pwr_efficiency_ratio;
2271 }
2272
2273 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2274                                             struct radeon_ps *radeon_state)
2275 {
2276         struct si_power_info *si_pi = si_get_pi(rdev);
2277
2278         if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2279             radeon_state->vclk && radeon_state->dclk)
2280                 return true;
2281
2282         return false;
2283 }
2284
2285 static int si_populate_power_containment_values(struct radeon_device *rdev,
2286                                                 struct radeon_ps *radeon_state,
2287                                                 SISLANDS_SMC_SWSTATE *smc_state)
2288 {
2289         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2290         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2291         struct ni_ps *state = ni_get_ps(radeon_state);
2292         SISLANDS_SMC_VOLTAGE_VALUE vddc;
2293         u32 prev_sclk;
2294         u32 max_sclk;
2295         u32 min_sclk;
2296         u16 prev_std_vddc;
2297         u16 curr_std_vddc;
2298         int i;
2299         u16 pwr_efficiency_ratio;
2300         u8 max_ps_percent;
2301         bool disable_uvd_power_tune;
2302         int ret;
2303
2304         if (ni_pi->enable_power_containment == false)
2305                 return 0;
2306
2307         if (state->performance_level_count == 0)
2308                 return -EINVAL;
2309
2310         if (smc_state->levelCount != state->performance_level_count)
2311                 return -EINVAL;
2312
2313         disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2314
2315         smc_state->levels[0].dpm2.MaxPS = 0;
2316         smc_state->levels[0].dpm2.NearTDPDec = 0;
2317         smc_state->levels[0].dpm2.AboveSafeInc = 0;
2318         smc_state->levels[0].dpm2.BelowSafeInc = 0;
2319         smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2320
2321         for (i = 1; i < state->performance_level_count; i++) {
2322                 prev_sclk = state->performance_levels[i-1].sclk;
2323                 max_sclk  = state->performance_levels[i].sclk;
2324                 if (i == 1)
2325                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2326                 else
2327                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2328
2329                 if (prev_sclk > max_sclk)
2330                         return -EINVAL;
2331
2332                 if ((max_ps_percent == 0) ||
2333                     (prev_sclk == max_sclk) ||
2334                     disable_uvd_power_tune) {
2335                         min_sclk = max_sclk;
2336                 } else if (i == 1) {
2337                         min_sclk = prev_sclk;
2338                 } else {
2339                         min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2340                 }
2341
2342                 if (min_sclk < state->performance_levels[0].sclk)
2343                         min_sclk = state->performance_levels[0].sclk;
2344
2345                 if (min_sclk == 0)
2346                         return -EINVAL;
2347
2348                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2349                                                 state->performance_levels[i-1].vddc, &vddc);
2350                 if (ret)
2351                         return ret;
2352
2353                 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2354                 if (ret)
2355                         return ret;
2356
2357                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2358                                                 state->performance_levels[i].vddc, &vddc);
2359                 if (ret)
2360                         return ret;
2361
2362                 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2363                 if (ret)
2364                         return ret;
2365
2366                 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2367                                                                            prev_std_vddc, curr_std_vddc);
2368
2369                 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2370                 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2371                 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2372                 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2373                 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2374         }
2375
2376         return 0;
2377 }
2378
2379 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2380                                          struct radeon_ps *radeon_state,
2381                                          SISLANDS_SMC_SWSTATE *smc_state)
2382 {
2383         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2384         struct ni_ps *state = ni_get_ps(radeon_state);
2385         u32 sq_power_throttle, sq_power_throttle2;
2386         bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2387         int i;
2388
2389         if (state->performance_level_count == 0)
2390                 return -EINVAL;
2391
2392         if (smc_state->levelCount != state->performance_level_count)
2393                 return -EINVAL;
2394
2395         if (rdev->pm.dpm.sq_ramping_threshold == 0)
2396                 return -EINVAL;
2397
2398         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2399                 enable_sq_ramping = false;
2400
2401         if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2402                 enable_sq_ramping = false;
2403
2404         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2405                 enable_sq_ramping = false;
2406
2407         if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2408                 enable_sq_ramping = false;
2409
2410         if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2411                 enable_sq_ramping = false;
2412
2413         for (i = 0; i < state->performance_level_count; i++) {
2414                 sq_power_throttle = 0;
2415                 sq_power_throttle2 = 0;
2416
2417                 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2418                     enable_sq_ramping) {
2419                         sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2420                         sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2421                         sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2422                         sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2423                         sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2424                 } else {
2425                         sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2426                         sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2427                 }
2428
2429                 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2430                 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2431         }
2432
2433         return 0;
2434 }
2435
2436 static int si_enable_power_containment(struct radeon_device *rdev,
2437                                        struct radeon_ps *radeon_new_state,
2438                                        bool enable)
2439 {
2440         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2441         PPSMC_Result smc_result;
2442         int ret = 0;
2443
2444         if (ni_pi->enable_power_containment) {
2445                 if (enable) {
2446                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2447                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2448                                 if (smc_result != PPSMC_Result_OK) {
2449                                         ret = -EINVAL;
2450                                         ni_pi->pc_enabled = false;
2451                                 } else {
2452                                         ni_pi->pc_enabled = true;
2453                                 }
2454                         }
2455                 } else {
2456                         smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2457                         if (smc_result != PPSMC_Result_OK)
2458                                 ret = -EINVAL;
2459                         ni_pi->pc_enabled = false;
2460                 }
2461         }
2462
2463         return ret;
2464 }
2465
2466 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2467 {
2468         struct si_power_info *si_pi = si_get_pi(rdev);
2469         int ret = 0;
2470         struct si_dte_data *dte_data = &si_pi->dte_data;
2471         Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2472         u32 table_size;
2473         u8 tdep_count;
2474         u32 i;
2475
2476         if (dte_data == NULL)
2477                 si_pi->enable_dte = false;
2478
2479         if (si_pi->enable_dte == false)
2480                 return 0;
2481
2482         if (dte_data->k <= 0)
2483                 return -EINVAL;
2484
2485         dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2486         if (dte_tables == NULL) {
2487                 si_pi->enable_dte = false;
2488                 return -ENOMEM;
2489         }
2490
2491         table_size = dte_data->k;
2492
2493         if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2494                 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2495
2496         tdep_count = dte_data->tdep_count;
2497         if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2498                 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2499
2500         dte_tables->K = cpu_to_be32(table_size);
2501         dte_tables->T0 = cpu_to_be32(dte_data->t0);
2502         dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2503         dte_tables->WindowSize = dte_data->window_size;
2504         dte_tables->temp_select = dte_data->temp_select;
2505         dte_tables->DTE_mode = dte_data->dte_mode;
2506         dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2507
2508         if (tdep_count > 0)
2509                 table_size--;
2510
2511         for (i = 0; i < table_size; i++) {
2512                 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2513                 dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2514         }
2515
2516         dte_tables->Tdep_count = tdep_count;
2517
2518         for (i = 0; i < (u32)tdep_count; i++) {
2519                 dte_tables->T_limits[i] = dte_data->t_limits[i];
2520                 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2521                 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2522         }
2523
2524         ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2525                                    sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2526         kfree(dte_tables);
2527
2528         return ret;
2529 }
2530
2531 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2532                                           u16 *max, u16 *min)
2533 {
2534         struct si_power_info *si_pi = si_get_pi(rdev);
2535         struct radeon_cac_leakage_table *table =
2536                 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2537         u32 i;
2538         u32 v0_loadline;
2539
2540
2541         if (table == NULL)
2542                 return -EINVAL;
2543
2544         *max = 0;
2545         *min = 0xFFFF;
2546
2547         for (i = 0; i < table->count; i++) {
2548                 if (table->entries[i].vddc > *max)
2549                         *max = table->entries[i].vddc;
2550                 if (table->entries[i].vddc < *min)
2551                         *min = table->entries[i].vddc;
2552         }
2553
2554         if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2555                 return -EINVAL;
2556
2557         v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2558
2559         if (v0_loadline > 0xFFFFUL)
2560                 return -EINVAL;
2561
2562         *min = (u16)v0_loadline;
2563
2564         if ((*min > *max) || (*max == 0) || (*min == 0))
2565                 return -EINVAL;
2566
2567         return 0;
2568 }
2569
2570 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2571 {
2572         return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2573                 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2574 }
2575
2576 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2577                                      PP_SIslands_CacConfig *cac_tables,
2578                                      u16 vddc_max, u16 vddc_min, u16 vddc_step,
2579                                      u16 t0, u16 t_step)
2580 {
2581         struct si_power_info *si_pi = si_get_pi(rdev);
2582         u32 leakage;
2583         unsigned int i, j;
2584         s32 t;
2585         u32 smc_leakage;
2586         u32 scaling_factor;
2587         u16 voltage;
2588
2589         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2590
2591         for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2592                 t = (1000 * (i * t_step + t0));
2593
2594                 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2595                         voltage = vddc_max - (vddc_step * j);
2596
2597                         si_calculate_leakage_for_v_and_t(rdev,
2598                                                          &si_pi->powertune_data->leakage_coefficients,
2599                                                          voltage,
2600                                                          t,
2601                                                          si_pi->dyn_powertune_data.cac_leakage,
2602                                                          &leakage);
2603
2604                         smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2605
2606                         if (smc_leakage > 0xFFFF)
2607                                 smc_leakage = 0xFFFF;
2608
2609                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2610                                 cpu_to_be16((u16)smc_leakage);
2611                 }
2612         }
2613         return 0;
2614 }
2615
2616 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2617                                             PP_SIslands_CacConfig *cac_tables,
2618                                             u16 vddc_max, u16 vddc_min, u16 vddc_step)
2619 {
2620         struct si_power_info *si_pi = si_get_pi(rdev);
2621         u32 leakage;
2622         unsigned int i, j;
2623         u32 smc_leakage;
2624         u32 scaling_factor;
2625         u16 voltage;
2626
2627         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2628
2629         for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2630                 voltage = vddc_max - (vddc_step * j);
2631
2632                 si_calculate_leakage_for_v(rdev,
2633                                            &si_pi->powertune_data->leakage_coefficients,
2634                                            si_pi->powertune_data->fixed_kt,
2635                                            voltage,
2636                                            si_pi->dyn_powertune_data.cac_leakage,
2637                                            &leakage);
2638
2639                 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2640
2641                 if (smc_leakage > 0xFFFF)
2642                         smc_leakage = 0xFFFF;
2643
2644                 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2645                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2646                                 cpu_to_be16((u16)smc_leakage);
2647         }
2648         return 0;
2649 }
2650
2651 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2652 {
2653         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2654         struct si_power_info *si_pi = si_get_pi(rdev);
2655         PP_SIslands_CacConfig *cac_tables = NULL;
2656         u16 vddc_max, vddc_min, vddc_step;
2657         u16 t0, t_step;
2658         u32 load_line_slope, reg;
2659         int ret = 0;
2660         u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2661
2662         if (ni_pi->enable_cac == false)
2663                 return 0;
2664
2665         cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2666         if (!cac_tables)
2667                 return -ENOMEM;
2668
2669         reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2670         reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2671         WREG32(CG_CAC_CTRL, reg);
2672
2673         si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2674         si_pi->dyn_powertune_data.dc_pwr_value =
2675                 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2676         si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2677         si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2678
2679         si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2680
2681         ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2682         if (ret)
2683                 goto done_free;
2684
2685         vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2686         vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2687         t_step = 4;
2688         t0 = 60;
2689
2690         if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2691                 ret = si_init_dte_leakage_table(rdev, cac_tables,
2692                                                 vddc_max, vddc_min, vddc_step,
2693                                                 t0, t_step);
2694         else
2695                 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2696                                                        vddc_max, vddc_min, vddc_step);
2697         if (ret)
2698                 goto done_free;
2699
2700         load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2701
2702         cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2703         cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2704         cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2705         cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2706         cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2707         cac_tables->R_LL = cpu_to_be32(load_line_slope);
2708         cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2709         cac_tables->calculation_repeats = cpu_to_be32(2);
2710         cac_tables->dc_cac = cpu_to_be32(0);
2711         cac_tables->log2_PG_LKG_SCALE = 12;
2712         cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2713         cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2714         cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2715
2716         ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2717                                    sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2718
2719         if (ret)
2720                 goto done_free;
2721
2722         ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2723
2724 done_free:
2725         if (ret) {
2726                 ni_pi->enable_cac = false;
2727                 ni_pi->enable_power_containment = false;
2728         }
2729
2730         kfree(cac_tables);
2731
2732         return 0;
2733 }
2734
2735 static int si_program_cac_config_registers(struct radeon_device *rdev,
2736                                            const struct si_cac_config_reg *cac_config_regs)
2737 {
2738         const struct si_cac_config_reg *config_regs = cac_config_regs;
2739         u32 data = 0, offset;
2740
2741         if (!config_regs)
2742                 return -EINVAL;
2743
2744         while (config_regs->offset != 0xFFFFFFFF) {
2745                 switch (config_regs->type) {
2746                 case SISLANDS_CACCONFIG_CGIND:
2747                         offset = SMC_CG_IND_START + config_regs->offset;
2748                         if (offset < SMC_CG_IND_END)
2749                                 data = RREG32_SMC(offset);
2750                         break;
2751                 default:
2752                         data = RREG32(config_regs->offset << 2);
2753                         break;
2754                 }
2755
2756                 data &= ~config_regs->mask;
2757                 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2758
2759                 switch (config_regs->type) {
2760                 case SISLANDS_CACCONFIG_CGIND:
2761                         offset = SMC_CG_IND_START + config_regs->offset;
2762                         if (offset < SMC_CG_IND_END)
2763                                 WREG32_SMC(offset, data);
2764                         break;
2765                 default:
2766                         WREG32(config_regs->offset << 2, data);
2767                         break;
2768                 }
2769                 config_regs++;
2770         }
2771         return 0;
2772 }
2773
2774 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2775 {
2776         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2777         struct si_power_info *si_pi = si_get_pi(rdev);
2778         int ret;
2779
2780         if ((ni_pi->enable_cac == false) ||
2781             (ni_pi->cac_configuration_required == false))
2782                 return 0;
2783
2784         ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2785         if (ret)
2786                 return ret;
2787         ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2788         if (ret)
2789                 return ret;
2790         ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2791         if (ret)
2792                 return ret;
2793
2794         return 0;
2795 }
2796
2797 static int si_enable_smc_cac(struct radeon_device *rdev,
2798                              struct radeon_ps *radeon_new_state,
2799                              bool enable)
2800 {
2801         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2802         struct si_power_info *si_pi = si_get_pi(rdev);
2803         PPSMC_Result smc_result;
2804         int ret = 0;
2805
2806         if (ni_pi->enable_cac) {
2807                 if (enable) {
2808                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2809                                 if (ni_pi->support_cac_long_term_average) {
2810                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2811                                         if (smc_result != PPSMC_Result_OK)
2812                                                 ni_pi->support_cac_long_term_average = false;
2813                                 }
2814
2815                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2816                                 if (smc_result != PPSMC_Result_OK) {
2817                                         ret = -EINVAL;
2818                                         ni_pi->cac_enabled = false;
2819                                 } else {
2820                                         ni_pi->cac_enabled = true;
2821                                 }
2822
2823                                 if (si_pi->enable_dte) {
2824                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2825                                         if (smc_result != PPSMC_Result_OK)
2826                                                 ret = -EINVAL;
2827                                 }
2828                         }
2829                 } else if (ni_pi->cac_enabled) {
2830                         if (si_pi->enable_dte)
2831                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2832
2833                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2834
2835                         ni_pi->cac_enabled = false;
2836
2837                         if (ni_pi->support_cac_long_term_average)
2838                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2839                 }
2840         }
2841         return ret;
2842 }
2843
2844 static int si_init_smc_spll_table(struct radeon_device *rdev)
2845 {
2846         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2847         struct si_power_info *si_pi = si_get_pi(rdev);
2848         SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2849         SISLANDS_SMC_SCLK_VALUE sclk_params;
2850         u32 fb_div, p_div;
2851         u32 clk_s, clk_v;
2852         u32 sclk = 0;
2853         int ret = 0;
2854         u32 tmp;
2855         int i;
2856
2857         if (si_pi->spll_table_start == 0)
2858                 return -EINVAL;
2859
2860         spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2861         if (spll_table == NULL)
2862                 return -ENOMEM;
2863
2864         for (i = 0; i < 256; i++) {
2865                 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2866                 if (ret)
2867                         break;
2868
2869                 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2870                 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2871                 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2872                 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2873
2874                 fb_div &= ~0x00001FFF;
2875                 fb_div >>= 1;
2876                 clk_v >>= 6;
2877
2878                 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2879                         ret = -EINVAL;
2880                 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2881                         ret = -EINVAL;
2882                 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2883                         ret = -EINVAL;
2884                 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2885                         ret = -EINVAL;
2886
2887                 if (ret)
2888                         break;
2889
2890                 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2891                         ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2892                 spll_table->freq[i] = cpu_to_be32(tmp);
2893
2894                 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2895                         ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2896                 spll_table->ss[i] = cpu_to_be32(tmp);
2897
2898                 sclk += 512;
2899         }
2900
2901
2902         if (!ret)
2903                 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2904                                            (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2905                                            si_pi->sram_end);
2906
2907         if (ret)
2908                 ni_pi->enable_power_containment = false;
2909
2910         kfree(spll_table);
2911
2912         return ret;
2913 }
2914
2915 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev,
2916                                                    u16 vce_voltage)
2917 {
2918         u16 highest_leakage = 0;
2919         struct si_power_info *si_pi = si_get_pi(rdev);
2920         int i;
2921
2922         for (i = 0; i < si_pi->leakage_voltage.count; i++){
2923                 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
2924                         highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
2925         }
2926
2927         if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
2928                 return highest_leakage;
2929
2930         return vce_voltage;
2931 }
2932
2933 static int si_get_vce_clock_voltage(struct radeon_device *rdev,
2934                                     u32 evclk, u32 ecclk, u16 *voltage)
2935 {
2936         u32 i;
2937         int ret = -EINVAL;
2938         struct radeon_vce_clock_voltage_dependency_table *table =
2939                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2940
2941         if (((evclk == 0) && (ecclk == 0)) ||
2942             (table && (table->count == 0))) {
2943                 *voltage = 0;
2944                 return 0;
2945         }
2946
2947         for (i = 0; i < table->count; i++) {
2948                 if ((evclk <= table->entries[i].evclk) &&
2949                     (ecclk <= table->entries[i].ecclk)) {
2950                         *voltage = table->entries[i].v;
2951                         ret = 0;
2952                         break;
2953                 }
2954         }
2955
2956         /* if no match return the highest voltage */
2957         if (ret)
2958                 *voltage = table->entries[table->count - 1].v;
2959
2960         *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage);
2961
2962         return ret;
2963 }
2964
2965 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2966                                         struct radeon_ps *rps)
2967 {
2968         struct ni_ps *ps = ni_get_ps(rps);
2969         struct radeon_clock_and_voltage_limits *max_limits;
2970         bool disable_mclk_switching = false;
2971         bool disable_sclk_switching = false;
2972         u32 mclk, sclk;
2973         u16 vddc, vddci, min_vce_voltage = 0;
2974         u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2975         u32 max_sclk = 0, max_mclk = 0;
2976         int i;
2977
2978         if (rdev->family == CHIP_HAINAN) {
2979                 if ((rdev->pdev->revision == 0x81) ||
2980                     (rdev->pdev->revision == 0x83) ||
2981                     (rdev->pdev->revision == 0xC3) ||
2982                     (rdev->pdev->device == 0x6664) ||
2983                     (rdev->pdev->device == 0x6665) ||
2984                     (rdev->pdev->device == 0x6667)) {
2985                         max_sclk = 75000;
2986                 }
2987         } else if (rdev->family == CHIP_OLAND) {
2988                 if ((rdev->pdev->revision == 0xC7) ||
2989                     (rdev->pdev->revision == 0x80) ||
2990                     (rdev->pdev->revision == 0x81) ||
2991                     (rdev->pdev->revision == 0x83) ||
2992                     (rdev->pdev->revision == 0x87) ||
2993                     (rdev->pdev->device == 0x6604) ||
2994                     (rdev->pdev->device == 0x6605)) {
2995                         max_sclk = 75000;
2996                 }
2997         }
2998
2999         if (rps->vce_active) {
3000                 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
3001                 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
3002                 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk,
3003                                          &min_vce_voltage);
3004         } else {
3005                 rps->evclk = 0;
3006                 rps->ecclk = 0;
3007         }
3008
3009         if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
3010             ni_dpm_vblank_too_short(rdev))
3011                 disable_mclk_switching = true;
3012
3013         if (rps->vclk || rps->dclk) {
3014                 disable_mclk_switching = true;
3015                 disable_sclk_switching = true;
3016         }
3017
3018         if (rdev->pm.dpm.ac_power)
3019                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3020         else
3021                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3022
3023         for (i = ps->performance_level_count - 2; i >= 0; i--) {
3024                 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3025                         ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3026         }
3027         if (rdev->pm.dpm.ac_power == false) {
3028                 for (i = 0; i < ps->performance_level_count; i++) {
3029                         if (ps->performance_levels[i].mclk > max_limits->mclk)
3030                                 ps->performance_levels[i].mclk = max_limits->mclk;
3031                         if (ps->performance_levels[i].sclk > max_limits->sclk)
3032                                 ps->performance_levels[i].sclk = max_limits->sclk;
3033                         if (ps->performance_levels[i].vddc > max_limits->vddc)
3034                                 ps->performance_levels[i].vddc = max_limits->vddc;
3035                         if (ps->performance_levels[i].vddci > max_limits->vddci)
3036                                 ps->performance_levels[i].vddci = max_limits->vddci;
3037                 }
3038         }
3039
3040         /* limit clocks to max supported clocks based on voltage dependency tables */
3041         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3042                                                         &max_sclk_vddc);
3043         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3044                                                         &max_mclk_vddci);
3045         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3046                                                         &max_mclk_vddc);
3047
3048         for (i = 0; i < ps->performance_level_count; i++) {
3049                 if (max_sclk_vddc) {
3050                         if (ps->performance_levels[i].sclk > max_sclk_vddc)
3051                                 ps->performance_levels[i].sclk = max_sclk_vddc;
3052                 }
3053                 if (max_mclk_vddci) {
3054                         if (ps->performance_levels[i].mclk > max_mclk_vddci)
3055                                 ps->performance_levels[i].mclk = max_mclk_vddci;
3056                 }
3057                 if (max_mclk_vddc) {
3058                         if (ps->performance_levels[i].mclk > max_mclk_vddc)
3059                                 ps->performance_levels[i].mclk = max_mclk_vddc;
3060                 }
3061                 if (max_mclk) {
3062                         if (ps->performance_levels[i].mclk > max_mclk)
3063                                 ps->performance_levels[i].mclk = max_mclk;
3064                 }
3065                 if (max_sclk) {
3066                         if (ps->performance_levels[i].sclk > max_sclk)
3067                                 ps->performance_levels[i].sclk = max_sclk;
3068                 }
3069         }
3070
3071         /* XXX validate the min clocks required for display */
3072
3073         if (disable_mclk_switching) {
3074                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
3075                 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3076         } else {
3077                 mclk = ps->performance_levels[0].mclk;
3078                 vddci = ps->performance_levels[0].vddci;
3079         }
3080
3081         if (disable_sclk_switching) {
3082                 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3083                 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3084         } else {
3085                 sclk = ps->performance_levels[0].sclk;
3086                 vddc = ps->performance_levels[0].vddc;
3087         }
3088
3089         if (rps->vce_active) {
3090                 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
3091                         sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
3092                 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
3093                         mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
3094         }
3095
3096         /* adjusted low state */
3097         ps->performance_levels[0].sclk = sclk;
3098         ps->performance_levels[0].mclk = mclk;
3099         ps->performance_levels[0].vddc = vddc;
3100         ps->performance_levels[0].vddci = vddci;
3101
3102         if (disable_sclk_switching) {
3103                 sclk = ps->performance_levels[0].sclk;
3104                 for (i = 1; i < ps->performance_level_count; i++) {
3105                         if (sclk < ps->performance_levels[i].sclk)
3106                                 sclk = ps->performance_levels[i].sclk;
3107                 }
3108                 for (i = 0; i < ps->performance_level_count; i++) {
3109                         ps->performance_levels[i].sclk = sclk;
3110                         ps->performance_levels[i].vddc = vddc;
3111                 }
3112         } else {
3113                 for (i = 1; i < ps->performance_level_count; i++) {
3114                         if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3115                                 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3116                         if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3117                                 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3118                 }
3119         }
3120
3121         if (disable_mclk_switching) {
3122                 mclk = ps->performance_levels[0].mclk;
3123                 for (i = 1; i < ps->performance_level_count; i++) {
3124                         if (mclk < ps->performance_levels[i].mclk)
3125                                 mclk = ps->performance_levels[i].mclk;
3126                 }
3127                 for (i = 0; i < ps->performance_level_count; i++) {
3128                         ps->performance_levels[i].mclk = mclk;
3129                         ps->performance_levels[i].vddci = vddci;
3130                 }
3131         } else {
3132                 for (i = 1; i < ps->performance_level_count; i++) {
3133                         if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3134                                 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3135                         if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3136                                 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3137                 }
3138         }
3139
3140         for (i = 0; i < ps->performance_level_count; i++)
3141                 btc_adjust_clock_combinations(rdev, max_limits,
3142                                               &ps->performance_levels[i]);
3143
3144         for (i = 0; i < ps->performance_level_count; i++) {
3145                 if (ps->performance_levels[i].vddc < min_vce_voltage)
3146                         ps->performance_levels[i].vddc = min_vce_voltage;
3147                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3148                                                    ps->performance_levels[i].sclk,
3149                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3150                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3151                                                    ps->performance_levels[i].mclk,
3152                                                    max_limits->vddci, &ps->performance_levels[i].vddci);
3153                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3154                                                    ps->performance_levels[i].mclk,
3155                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3156                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3157                                                    rdev->clock.current_dispclk,
3158                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3159         }
3160
3161         for (i = 0; i < ps->performance_level_count; i++) {
3162                 btc_apply_voltage_delta_rules(rdev,
3163                                               max_limits->vddc, max_limits->vddci,
3164                                               &ps->performance_levels[i].vddc,
3165                                               &ps->performance_levels[i].vddci);
3166         }
3167
3168         ps->dc_compatible = true;
3169         for (i = 0; i < ps->performance_level_count; i++) {
3170                 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3171                         ps->dc_compatible = false;
3172         }
3173 }
3174
3175 #if 0
3176 static int si_read_smc_soft_register(struct radeon_device *rdev,
3177                                      u16 reg_offset, u32 *value)
3178 {
3179         struct si_power_info *si_pi = si_get_pi(rdev);
3180
3181         return si_read_smc_sram_dword(rdev,
3182                                       si_pi->soft_regs_start + reg_offset, value,
3183                                       si_pi->sram_end);
3184 }
3185 #endif
3186
3187 static int si_write_smc_soft_register(struct radeon_device *rdev,
3188                                       u16 reg_offset, u32 value)
3189 {
3190         struct si_power_info *si_pi = si_get_pi(rdev);
3191
3192         return si_write_smc_sram_dword(rdev,
3193                                        si_pi->soft_regs_start + reg_offset,
3194                                        value, si_pi->sram_end);
3195 }
3196
3197 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3198 {
3199         bool ret = false;
3200         u32 tmp, width, row, column, bank, density;
3201         bool is_memory_gddr5, is_special;
3202
3203         tmp = RREG32(MC_SEQ_MISC0);
3204         is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3205         is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3206                 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3207
3208         WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3209         width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3210
3211         tmp = RREG32(MC_ARB_RAMCFG);
3212         row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3213         column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3214         bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3215
3216         density = (1 << (row + column - 20 + bank)) * width;
3217
3218         if ((rdev->pdev->device == 0x6819) &&
3219             is_memory_gddr5 && is_special && (density == 0x400))
3220                 ret = true;
3221
3222         return ret;
3223 }
3224
3225 static void si_get_leakage_vddc(struct radeon_device *rdev)
3226 {
3227         struct si_power_info *si_pi = si_get_pi(rdev);
3228         u16 vddc, count = 0;
3229         int i, ret;
3230
3231         for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3232                 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3233
3234                 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3235                         si_pi->leakage_voltage.entries[count].voltage = vddc;
3236                         si_pi->leakage_voltage.entries[count].leakage_index =
3237                                 SISLANDS_LEAKAGE_INDEX0 + i;
3238                         count++;
3239                 }
3240         }
3241         si_pi->leakage_voltage.count = count;
3242 }
3243
3244 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3245                                                      u32 index, u16 *leakage_voltage)
3246 {
3247         struct si_power_info *si_pi = si_get_pi(rdev);
3248         int i;
3249
3250         if (leakage_voltage == NULL)
3251                 return -EINVAL;
3252
3253         if ((index & 0xff00) != 0xff00)
3254                 return -EINVAL;
3255
3256         if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3257                 return -EINVAL;
3258
3259         if (index < SISLANDS_LEAKAGE_INDEX0)
3260                 return -EINVAL;
3261
3262         for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3263                 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3264                         *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3265                         return 0;
3266                 }
3267         }
3268         return -EAGAIN;
3269 }
3270
3271 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3272 {
3273         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3274         bool want_thermal_protection;
3275         enum radeon_dpm_event_src dpm_event_src;
3276
3277         switch (sources) {
3278         case 0:
3279         default:
3280                 want_thermal_protection = false;
3281                 break;
3282         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3283                 want_thermal_protection = true;
3284                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3285                 break;
3286         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3287                 want_thermal_protection = true;
3288                 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3289                 break;
3290         case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3291               (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3292                 want_thermal_protection = true;
3293                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3294                 break;
3295         }
3296
3297         if (want_thermal_protection) {
3298                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3299                 if (pi->thermal_protection)
3300                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3301         } else {
3302                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3303         }
3304 }
3305
3306 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3307                                            enum radeon_dpm_auto_throttle_src source,
3308                                            bool enable)
3309 {
3310         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3311
3312         if (enable) {
3313                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3314                         pi->active_auto_throttle_sources |= 1 << source;
3315                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3316                 }
3317         } else {
3318                 if (pi->active_auto_throttle_sources & (1 << source)) {
3319                         pi->active_auto_throttle_sources &= ~(1 << source);
3320                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3321                 }
3322         }
3323 }
3324
3325 static void si_start_dpm(struct radeon_device *rdev)
3326 {
3327         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3328 }
3329
3330 static void si_stop_dpm(struct radeon_device *rdev)
3331 {
3332         WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3333 }
3334
3335 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3336 {
3337         if (enable)
3338                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3339         else
3340                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3341
3342 }
3343
3344 #if 0
3345 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3346                                                u32 thermal_level)
3347 {
3348         PPSMC_Result ret;
3349
3350         if (thermal_level == 0) {
3351                 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3352                 if (ret == PPSMC_Result_OK)
3353                         return 0;
3354                 else
3355                         return -EINVAL;
3356         }
3357         return 0;
3358 }
3359
3360 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3361 {
3362         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3363 }
3364 #endif
3365
3366 #if 0
3367 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3368 {
3369         if (ac_power)
3370                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3371                         0 : -EINVAL;
3372
3373         return 0;
3374 }
3375 #endif
3376
3377 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3378                                                       PPSMC_Msg msg, u32 parameter)
3379 {
3380         WREG32(SMC_SCRATCH0, parameter);
3381         return si_send_msg_to_smc(rdev, msg);
3382 }
3383
3384 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3385 {
3386         if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3387                 return -EINVAL;
3388
3389         return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3390                 0 : -EINVAL;
3391 }
3392
3393 int si_dpm_force_performance_level(struct radeon_device *rdev,
3394                                    enum radeon_dpm_forced_level level)
3395 {
3396         struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3397         struct ni_ps *ps = ni_get_ps(rps);
3398         u32 levels = ps->performance_level_count;
3399
3400         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3401                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3402                         return -EINVAL;
3403
3404                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3405                         return -EINVAL;
3406         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3407                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3408                         return -EINVAL;
3409
3410                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3411                         return -EINVAL;
3412         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3413                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3414                         return -EINVAL;
3415
3416                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3417                         return -EINVAL;
3418         }
3419
3420         rdev->pm.dpm.forced_level = level;
3421
3422         return 0;
3423 }
3424
3425 #if 0
3426 static int si_set_boot_state(struct radeon_device *rdev)
3427 {
3428         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3429                 0 : -EINVAL;
3430 }
3431 #endif
3432
3433 static int si_set_sw_state(struct radeon_device *rdev)
3434 {
3435         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3436                 0 : -EINVAL;
3437 }
3438
3439 static int si_halt_smc(struct radeon_device *rdev)
3440 {
3441         if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3442                 return -EINVAL;
3443
3444         return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3445                 0 : -EINVAL;
3446 }
3447
3448 static int si_resume_smc(struct radeon_device *rdev)
3449 {
3450         if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3451                 return -EINVAL;
3452
3453         return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3454                 0 : -EINVAL;
3455 }
3456
3457 static void si_dpm_start_smc(struct radeon_device *rdev)
3458 {
3459         si_program_jump_on_start(rdev);
3460         si_start_smc(rdev);
3461         si_start_smc_clock(rdev);
3462 }
3463
3464 static void si_dpm_stop_smc(struct radeon_device *rdev)
3465 {
3466         si_reset_smc(rdev);
3467         si_stop_smc_clock(rdev);
3468 }
3469
3470 static int si_process_firmware_header(struct radeon_device *rdev)
3471 {
3472         struct si_power_info *si_pi = si_get_pi(rdev);
3473         u32 tmp;
3474         int ret;
3475
3476         ret = si_read_smc_sram_dword(rdev,
3477                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3478                                      SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3479                                      &tmp, si_pi->sram_end);
3480         if (ret)
3481                 return ret;
3482
3483         si_pi->state_table_start = tmp;
3484
3485         ret = si_read_smc_sram_dword(rdev,
3486                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3487                                      SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3488                                      &tmp, si_pi->sram_end);
3489         if (ret)
3490                 return ret;
3491
3492         si_pi->soft_regs_start = tmp;
3493
3494         ret = si_read_smc_sram_dword(rdev,
3495                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3496                                      SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3497                                      &tmp, si_pi->sram_end);
3498         if (ret)
3499                 return ret;
3500
3501         si_pi->mc_reg_table_start = tmp;
3502
3503         ret = si_read_smc_sram_dword(rdev,
3504                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3505                                      SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3506                                      &tmp, si_pi->sram_end);
3507         if (ret)
3508                 return ret;
3509
3510         si_pi->fan_table_start = tmp;
3511
3512         ret = si_read_smc_sram_dword(rdev,
3513                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3514                                      SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3515                                      &tmp, si_pi->sram_end);
3516         if (ret)
3517                 return ret;
3518
3519         si_pi->arb_table_start = tmp;
3520
3521         ret = si_read_smc_sram_dword(rdev,
3522                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3523                                      SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3524                                      &tmp, si_pi->sram_end);
3525         if (ret)
3526                 return ret;
3527
3528         si_pi->cac_table_start = tmp;
3529
3530         ret = si_read_smc_sram_dword(rdev,
3531                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3532                                      SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3533                                      &tmp, si_pi->sram_end);
3534         if (ret)
3535                 return ret;
3536
3537         si_pi->dte_table_start = tmp;
3538
3539         ret = si_read_smc_sram_dword(rdev,
3540                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3541                                      SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3542                                      &tmp, si_pi->sram_end);
3543         if (ret)
3544                 return ret;
3545
3546         si_pi->spll_table_start = tmp;
3547
3548         ret = si_read_smc_sram_dword(rdev,
3549                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3550                                      SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3551                                      &tmp, si_pi->sram_end);
3552         if (ret)
3553                 return ret;
3554
3555         si_pi->papm_cfg_table_start = tmp;
3556
3557         return ret;
3558 }
3559
3560 static void si_read_clock_registers(struct radeon_device *rdev)
3561 {
3562         struct si_power_info *si_pi = si_get_pi(rdev);
3563
3564         si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3565         si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3566         si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3567         si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3568         si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3569         si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3570         si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3571         si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3572         si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3573         si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3574         si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3575         si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3576         si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3577         si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3578         si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3579 }
3580
3581 static void si_enable_thermal_protection(struct radeon_device *rdev,
3582                                           bool enable)
3583 {
3584         if (enable)
3585                 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3586         else
3587                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3588 }
3589
3590 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3591 {
3592         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3593 }
3594
3595 #if 0
3596 static int si_enter_ulp_state(struct radeon_device *rdev)
3597 {
3598         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3599
3600         udelay(25000);
3601
3602         return 0;
3603 }
3604
3605 static int si_exit_ulp_state(struct radeon_device *rdev)
3606 {
3607         int i;
3608
3609         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3610
3611         udelay(7000);
3612
3613         for (i = 0; i < rdev->usec_timeout; i++) {
3614                 if (RREG32(SMC_RESP_0) == 1)
3615                         break;
3616                 udelay(1000);
3617         }
3618
3619         return 0;
3620 }
3621 #endif
3622
3623 static int si_notify_smc_display_change(struct radeon_device *rdev,
3624                                      bool has_display)
3625 {
3626         PPSMC_Msg msg = has_display ?
3627                 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3628
3629         return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3630                 0 : -EINVAL;
3631 }
3632
3633 static void si_program_response_times(struct radeon_device *rdev)
3634 {
3635         u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3636         u32 vddc_dly, acpi_dly, vbi_dly;
3637         u32 reference_clock;
3638
3639         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3640
3641         voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3642         backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3643
3644         if (voltage_response_time == 0)
3645                 voltage_response_time = 1000;
3646
3647         acpi_delay_time = 15000;
3648         vbi_time_out = 100000;
3649
3650         reference_clock = radeon_get_xclk(rdev);
3651
3652         vddc_dly = (voltage_response_time  * reference_clock) / 100;
3653         acpi_dly = (acpi_delay_time * reference_clock) / 100;
3654         vbi_dly  = (vbi_time_out * reference_clock) / 100;
3655
3656         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
3657         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
3658         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3659         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3660 }
3661
3662 static void si_program_ds_registers(struct radeon_device *rdev)
3663 {
3664         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3665         u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3666
3667         if (eg_pi->sclk_deep_sleep) {
3668                 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3669                 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3670                          ~AUTOSCALE_ON_SS_CLEAR);
3671         }
3672 }
3673
3674 static void si_program_display_gap(struct radeon_device *rdev)
3675 {
3676         u32 tmp, pipe;
3677         int i;
3678
3679         tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3680         if (rdev->pm.dpm.new_active_crtc_count > 0)
3681                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3682         else
3683                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3684
3685         if (rdev->pm.dpm.new_active_crtc_count > 1)
3686                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3687         else
3688                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3689
3690         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3691
3692         tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3693         pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3694
3695         if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3696             (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3697                 /* find the first active crtc */
3698                 for (i = 0; i < rdev->num_crtc; i++) {
3699                         if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3700                                 break;
3701                 }
3702                 if (i == rdev->num_crtc)
3703                         pipe = 0;
3704                 else
3705                         pipe = i;
3706
3707                 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3708                 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3709                 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3710         }
3711
3712         /* Setting this to false forces the performance state to low if the crtcs are disabled.
3713          * This can be a problem on PowerXpress systems or if you want to use the card
3714          * for offscreen rendering or compute if there are no crtcs enabled.
3715          */
3716         si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3717 }
3718
3719 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3720 {
3721         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3722
3723         if (enable) {
3724                 if (pi->sclk_ss)
3725                         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3726         } else {
3727                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3728                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3729         }
3730 }
3731
3732 static void si_setup_bsp(struct radeon_device *rdev)
3733 {
3734         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3735         u32 xclk = radeon_get_xclk(rdev);
3736
3737         r600_calculate_u_and_p(pi->asi,
3738                                xclk,
3739                                16,
3740                                &pi->bsp,
3741                                &pi->bsu);
3742
3743         r600_calculate_u_and_p(pi->pasi,
3744                                xclk,
3745                                16,
3746                                &pi->pbsp,
3747                                &pi->pbsu);
3748
3749
3750         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3751         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3752
3753         WREG32(CG_BSP, pi->dsp);
3754 }
3755
3756 static void si_program_git(struct radeon_device *rdev)
3757 {
3758         WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3759 }
3760
3761 static void si_program_tp(struct radeon_device *rdev)
3762 {
3763         int i;
3764         enum r600_td td = R600_TD_DFLT;
3765
3766         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3767                 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3768
3769         if (td == R600_TD_AUTO)
3770                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3771         else
3772                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3773
3774         if (td == R600_TD_UP)
3775                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3776
3777         if (td == R600_TD_DOWN)
3778                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3779 }
3780
3781 static void si_program_tpp(struct radeon_device *rdev)
3782 {
3783         WREG32(CG_TPC, R600_TPC_DFLT);
3784 }
3785
3786 static void si_program_sstp(struct radeon_device *rdev)
3787 {
3788         WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3789 }
3790
3791 static void si_enable_display_gap(struct radeon_device *rdev)
3792 {
3793         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3794
3795         tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3796         tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3797                 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3798
3799         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3800         tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3801                 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3802         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3803 }
3804
3805 static void si_program_vc(struct radeon_device *rdev)
3806 {
3807         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3808
3809         WREG32(CG_FTV, pi->vrc);
3810 }
3811
3812 static void si_clear_vc(struct radeon_device *rdev)
3813 {
3814         WREG32(CG_FTV, 0);
3815 }
3816
3817 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3818 {
3819         u8 mc_para_index;
3820
3821         if (memory_clock < 10000)
3822                 mc_para_index = 0;
3823         else if (memory_clock >= 80000)
3824                 mc_para_index = 0x0f;
3825         else
3826                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3827         return mc_para_index;
3828 }
3829
3830 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3831 {
3832         u8 mc_para_index;
3833
3834         if (strobe_mode) {
3835                 if (memory_clock < 12500)
3836                         mc_para_index = 0x00;
3837                 else if (memory_clock > 47500)
3838                         mc_para_index = 0x0f;
3839                 else
3840                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
3841         } else {
3842                 if (memory_clock < 65000)
3843                         mc_para_index = 0x00;
3844                 else if (memory_clock > 135000)
3845                         mc_para_index = 0x0f;
3846                 else
3847                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
3848         }
3849         return mc_para_index;
3850 }
3851
3852 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3853 {
3854         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3855         bool strobe_mode = false;
3856         u8 result = 0;
3857
3858         if (mclk <= pi->mclk_strobe_mode_threshold)
3859                 strobe_mode = true;
3860
3861         if (pi->mem_gddr5)
3862                 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3863         else
3864                 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3865
3866         if (strobe_mode)
3867                 result |= SISLANDS_SMC_STROBE_ENABLE;
3868
3869         return result;
3870 }
3871
3872 static int si_upload_firmware(struct radeon_device *rdev)
3873 {
3874         struct si_power_info *si_pi = si_get_pi(rdev);
3875         int ret;
3876
3877         si_reset_smc(rdev);
3878         si_stop_smc_clock(rdev);
3879
3880         ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3881
3882         return ret;
3883 }
3884
3885 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3886                                               const struct atom_voltage_table *table,
3887                                               const struct radeon_phase_shedding_limits_table *limits)
3888 {
3889         u32 data, num_bits, num_levels;
3890
3891         if ((table == NULL) || (limits == NULL))
3892                 return false;
3893
3894         data = table->mask_low;
3895
3896         num_bits = hweight32(data);
3897
3898         if (num_bits == 0)
3899                 return false;
3900
3901         num_levels = (1 << num_bits);
3902
3903         if (table->count != num_levels)
3904                 return false;
3905
3906         if (limits->count != (num_levels - 1))
3907                 return false;
3908
3909         return true;
3910 }
3911
3912 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3913                                               u32 max_voltage_steps,
3914                                               struct atom_voltage_table *voltage_table)
3915 {
3916         unsigned int i, diff;
3917
3918         if (voltage_table->count <= max_voltage_steps)
3919                 return;
3920
3921         diff = voltage_table->count - max_voltage_steps;
3922
3923         for (i= 0; i < max_voltage_steps; i++)
3924                 voltage_table->entries[i] = voltage_table->entries[i + diff];
3925
3926         voltage_table->count = max_voltage_steps;
3927 }
3928
3929 static int si_get_svi2_voltage_table(struct radeon_device *rdev,
3930                                      struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
3931                                      struct atom_voltage_table *voltage_table)
3932 {
3933         u32 i;
3934
3935         if (voltage_dependency_table == NULL)
3936                 return -EINVAL;
3937
3938         voltage_table->mask_low = 0;
3939         voltage_table->phase_delay = 0;
3940
3941         voltage_table->count = voltage_dependency_table->count;
3942         for (i = 0; i < voltage_table->count; i++) {
3943                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
3944                 voltage_table->entries[i].smio_low = 0;
3945         }
3946
3947         return 0;
3948 }
3949
3950 static int si_construct_voltage_tables(struct radeon_device *rdev)
3951 {
3952         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3953         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3954         struct si_power_info *si_pi = si_get_pi(rdev);
3955         int ret;
3956
3957         if (pi->voltage_control) {
3958                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3959                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3960                 if (ret)
3961                         return ret;
3962
3963                 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3964                         si_trim_voltage_table_to_fit_state_table(rdev,
3965                                                                  SISLANDS_MAX_NO_VREG_STEPS,
3966                                                                  &eg_pi->vddc_voltage_table);
3967         } else if (si_pi->voltage_control_svi2) {
3968                 ret = si_get_svi2_voltage_table(rdev,
3969                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3970                                                 &eg_pi->vddc_voltage_table);
3971                 if (ret)
3972                         return ret;
3973         } else {
3974                 return -EINVAL;
3975         }
3976
3977         if (eg_pi->vddci_control) {
3978                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3979                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3980                 if (ret)
3981                         return ret;
3982
3983                 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3984                         si_trim_voltage_table_to_fit_state_table(rdev,
3985                                                                  SISLANDS_MAX_NO_VREG_STEPS,
3986                                                                  &eg_pi->vddci_voltage_table);
3987         }
3988         if (si_pi->vddci_control_svi2) {
3989                 ret = si_get_svi2_voltage_table(rdev,
3990                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3991                                                 &eg_pi->vddci_voltage_table);
3992                 if (ret)
3993                         return ret;
3994         }
3995
3996         if (pi->mvdd_control) {
3997                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
3998                                                     VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
3999
4000                 if (ret) {
4001                         pi->mvdd_control = false;
4002                         return ret;
4003                 }
4004
4005                 if (si_pi->mvdd_voltage_table.count == 0) {
4006                         pi->mvdd_control = false;
4007                         return -EINVAL;
4008                 }
4009
4010                 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4011                         si_trim_voltage_table_to_fit_state_table(rdev,
4012                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4013                                                                  &si_pi->mvdd_voltage_table);
4014         }
4015
4016         if (si_pi->vddc_phase_shed_control) {
4017                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
4018                                                     VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4019                 if (ret)
4020                         si_pi->vddc_phase_shed_control = false;
4021
4022                 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4023                     (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4024                         si_pi->vddc_phase_shed_control = false;
4025         }
4026
4027         return 0;
4028 }
4029
4030 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
4031                                           const struct atom_voltage_table *voltage_table,
4032                                           SISLANDS_SMC_STATETABLE *table)
4033 {
4034         unsigned int i;
4035
4036         for (i = 0; i < voltage_table->count; i++)
4037                 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4038 }
4039
4040 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
4041                                           SISLANDS_SMC_STATETABLE *table)
4042 {
4043         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4044         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4045         struct si_power_info *si_pi = si_get_pi(rdev);
4046         u8 i;
4047
4048         if (si_pi->voltage_control_svi2) {
4049                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4050                         si_pi->svc_gpio_id);
4051                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4052                         si_pi->svd_gpio_id);
4053                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4054                                            2);
4055         } else {
4056                 if (eg_pi->vddc_voltage_table.count) {
4057                         si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
4058                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4059                                 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4060
4061                         for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4062                                 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4063                                         table->maxVDDCIndexInPPTable = i;
4064                                         break;
4065                                 }
4066                         }
4067                 }
4068
4069                 if (eg_pi->vddci_voltage_table.count) {
4070                         si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
4071
4072                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4073                                 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4074                 }
4075
4076
4077                 if (si_pi->mvdd_voltage_table.count) {
4078                         si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
4079
4080                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4081                                 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4082                 }
4083
4084                 if (si_pi->vddc_phase_shed_control) {
4085                         if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
4086                                                               &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4087                                 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
4088
4089                                 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4090                                         cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4091
4092                                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4093                                                            (u32)si_pi->vddc_phase_shed_table.phase_delay);
4094                         } else {
4095                                 si_pi->vddc_phase_shed_control = false;
4096                         }
4097                 }
4098         }
4099
4100         return 0;
4101 }
4102
4103 static int si_populate_voltage_value(struct radeon_device *rdev,
4104                                      const struct atom_voltage_table *table,
4105                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4106 {
4107         unsigned int i;
4108
4109         for (i = 0; i < table->count; i++) {
4110                 if (value <= table->entries[i].value) {
4111                         voltage->index = (u8)i;
4112                         voltage->value = cpu_to_be16(table->entries[i].value);
4113                         break;
4114                 }
4115         }
4116
4117         if (i >= table->count)
4118                 return -EINVAL;
4119
4120         return 0;
4121 }
4122
4123 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4124                                   SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4125 {
4126         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4127         struct si_power_info *si_pi = si_get_pi(rdev);
4128
4129         if (pi->mvdd_control) {
4130                 if (mclk <= pi->mvdd_split_frequency)
4131                         voltage->index = 0;
4132                 else
4133                         voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4134
4135                 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4136         }
4137         return 0;
4138 }
4139
4140 static int si_get_std_voltage_value(struct radeon_device *rdev,
4141                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4142                                     u16 *std_voltage)
4143 {
4144         u16 v_index;
4145         bool voltage_found = false;
4146         *std_voltage = be16_to_cpu(voltage->value);
4147
4148         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4149                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4150                         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4151                                 return -EINVAL;
4152
4153                         for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4154                                 if (be16_to_cpu(voltage->value) ==
4155                                     (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4156                                         voltage_found = true;
4157                                         if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4158                                                 *std_voltage =
4159                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4160                                         else
4161                                                 *std_voltage =
4162                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4163                                         break;
4164                                 }
4165                         }
4166
4167                         if (!voltage_found) {
4168                                 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4169                                         if (be16_to_cpu(voltage->value) <=
4170                                             (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4171                                                 voltage_found = true;
4172                                                 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4173                                                         *std_voltage =
4174                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4175                                                 else
4176                                                         *std_voltage =
4177                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4178                                                 break;
4179                                         }
4180                                 }
4181                         }
4182                 } else {
4183                         if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4184                                 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4185                 }
4186         }
4187
4188         return 0;
4189 }
4190
4191 static int si_populate_std_voltage_value(struct radeon_device *rdev,
4192                                          u16 value, u8 index,
4193                                          SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4194 {
4195         voltage->index = index;
4196         voltage->value = cpu_to_be16(value);
4197
4198         return 0;
4199 }
4200
4201 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4202                                             const struct radeon_phase_shedding_limits_table *limits,
4203                                             u16 voltage, u32 sclk, u32 mclk,
4204                                             SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4205 {
4206         unsigned int i;
4207
4208         for (i = 0; i < limits->count; i++) {
4209                 if ((voltage <= limits->entries[i].voltage) &&
4210                     (sclk <= limits->entries[i].sclk) &&
4211                     (mclk <= limits->entries[i].mclk))
4212                         break;
4213         }
4214
4215         smc_voltage->phase_settings = (u8)i;
4216
4217         return 0;
4218 }
4219
4220 static int si_init_arb_table_index(struct radeon_device *rdev)
4221 {
4222         struct si_power_info *si_pi = si_get_pi(rdev);
4223         u32 tmp;
4224         int ret;
4225
4226         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4227         if (ret)
4228                 return ret;
4229
4230         tmp &= 0x00FFFFFF;
4231         tmp |= MC_CG_ARB_FREQ_F1 << 24;
4232
4233         return si_write_smc_sram_dword(rdev, si_pi->arb_table_start,  tmp, si_pi->sram_end);
4234 }
4235
4236 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4237 {
4238         return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4239 }
4240
4241 static int si_reset_to_default(struct radeon_device *rdev)
4242 {
4243         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4244                 0 : -EINVAL;
4245 }
4246
4247 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4248 {
4249         struct si_power_info *si_pi = si_get_pi(rdev);
4250         u32 tmp;
4251         int ret;
4252
4253         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4254                                      &tmp, si_pi->sram_end);
4255         if (ret)
4256                 return ret;
4257
4258         tmp = (tmp >> 24) & 0xff;
4259
4260         if (tmp == MC_CG_ARB_FREQ_F0)
4261                 return 0;
4262
4263         return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4264 }
4265
4266 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4267                                             u32 engine_clock)
4268 {
4269         u32 dram_rows;
4270         u32 dram_refresh_rate;
4271         u32 mc_arb_rfsh_rate;
4272         u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4273
4274         if (tmp >= 4)
4275                 dram_rows = 16384;
4276         else
4277                 dram_rows = 1 << (tmp + 10);
4278
4279         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4280         mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4281
4282         return mc_arb_rfsh_rate;
4283 }
4284
4285 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4286                                                 struct rv7xx_pl *pl,
4287                                                 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4288 {
4289         u32 dram_timing;
4290         u32 dram_timing2;
4291         u32 burst_time;
4292
4293         arb_regs->mc_arb_rfsh_rate =
4294                 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4295
4296         radeon_atom_set_engine_dram_timings(rdev,
4297                                             pl->sclk,
4298                                             pl->mclk);
4299
4300         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4301         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4302         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4303
4304         arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4305         arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4306         arb_regs->mc_arb_burst_time = (u8)burst_time;
4307
4308         return 0;
4309 }
4310
4311 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4312                                                   struct radeon_ps *radeon_state,
4313                                                   unsigned int first_arb_set)
4314 {
4315         struct si_power_info *si_pi = si_get_pi(rdev);
4316         struct ni_ps *state = ni_get_ps(radeon_state);
4317         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4318         int i, ret = 0;
4319
4320         for (i = 0; i < state->performance_level_count; i++) {
4321                 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4322                 if (ret)
4323                         break;
4324                 ret = si_copy_bytes_to_smc(rdev,
4325                                            si_pi->arb_table_start +
4326                                            offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4327                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4328                                            (u8 *)&arb_regs,
4329                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4330                                            si_pi->sram_end);
4331                 if (ret)
4332                         break;
4333         }
4334
4335         return ret;
4336 }
4337
4338 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4339                                                struct radeon_ps *radeon_new_state)
4340 {
4341         return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4342                                                       SISLANDS_DRIVER_STATE_ARB_INDEX);
4343 }
4344
4345 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4346                                           struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4347 {
4348         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4349         struct si_power_info *si_pi = si_get_pi(rdev);
4350
4351         if (pi->mvdd_control)
4352                 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4353                                                  si_pi->mvdd_bootup_value, voltage);
4354
4355         return 0;
4356 }
4357
4358 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4359                                          struct radeon_ps *radeon_initial_state,
4360                                          SISLANDS_SMC_STATETABLE *table)
4361 {
4362         struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4363         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4364         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4365         struct si_power_info *si_pi = si_get_pi(rdev);
4366         u32 reg;
4367         int ret;
4368
4369         table->initialState.levels[0].mclk.vDLL_CNTL =
4370                 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4371         table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4372                 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4373         table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4374                 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4375         table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4376                 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4377         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4378                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4379         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4380                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4381         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4382                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4383         table->initialState.levels[0].mclk.vMPLL_SS =
4384                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4385         table->initialState.levels[0].mclk.vMPLL_SS2 =
4386                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4387
4388         table->initialState.levels[0].mclk.mclk_value =
4389                 cpu_to_be32(initial_state->performance_levels[0].mclk);
4390
4391         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4392                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4393         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4394                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4395         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4396                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4397         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4398                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4399         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4400                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4401         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4402                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4403
4404         table->initialState.levels[0].sclk.sclk_value =
4405                 cpu_to_be32(initial_state->performance_levels[0].sclk);
4406
4407         table->initialState.levels[0].arbRefreshState =
4408                 SISLANDS_INITIAL_STATE_ARB_INDEX;
4409
4410         table->initialState.levels[0].ACIndex = 0;
4411
4412         ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4413                                         initial_state->performance_levels[0].vddc,
4414                                         &table->initialState.levels[0].vddc);
4415
4416         if (!ret) {
4417                 u16 std_vddc;
4418
4419                 ret = si_get_std_voltage_value(rdev,
4420                                                &table->initialState.levels[0].vddc,
4421                                                &std_vddc);
4422                 if (!ret)
4423                         si_populate_std_voltage_value(rdev, std_vddc,
4424                                                       table->initialState.levels[0].vddc.index,
4425                                                       &table->initialState.levels[0].std_vddc);
4426         }
4427
4428         if (eg_pi->vddci_control)
4429                 si_populate_voltage_value(rdev,
4430                                           &eg_pi->vddci_voltage_table,
4431                                           initial_state->performance_levels[0].vddci,
4432                                           &table->initialState.levels[0].vddci);
4433
4434         if (si_pi->vddc_phase_shed_control)
4435                 si_populate_phase_shedding_value(rdev,
4436                                                  &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4437                                                  initial_state->performance_levels[0].vddc,
4438                                                  initial_state->performance_levels[0].sclk,
4439                                                  initial_state->performance_levels[0].mclk,
4440                                                  &table->initialState.levels[0].vddc);
4441
4442         si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4443
4444         reg = CG_R(0xffff) | CG_L(0);
4445         table->initialState.levels[0].aT = cpu_to_be32(reg);
4446
4447         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4448
4449         table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4450
4451         if (pi->mem_gddr5) {
4452                 table->initialState.levels[0].strobeMode =
4453                         si_get_strobe_mode_settings(rdev,
4454                                                     initial_state->performance_levels[0].mclk);
4455
4456                 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4457                         table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4458                 else
4459                         table->initialState.levels[0].mcFlags =  0;
4460         }
4461
4462         table->initialState.levelCount = 1;
4463
4464         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4465
4466         table->initialState.levels[0].dpm2.MaxPS = 0;
4467         table->initialState.levels[0].dpm2.NearTDPDec = 0;
4468         table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4469         table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4470         table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4471
4472         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4473         table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4474
4475         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4476         table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4477
4478         return 0;
4479 }
4480
4481 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4482                                       SISLANDS_SMC_STATETABLE *table)
4483 {
4484         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4485         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4486         struct si_power_info *si_pi = si_get_pi(rdev);
4487         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4488         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4489         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4490         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4491         u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4492         u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4493         u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4494         u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4495         u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4496         u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4497         u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4498         u32 reg;
4499         int ret;
4500
4501         table->ACPIState = table->initialState;
4502
4503         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4504
4505         if (pi->acpi_vddc) {
4506                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4507                                                 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4508                 if (!ret) {
4509                         u16 std_vddc;
4510
4511                         ret = si_get_std_voltage_value(rdev,
4512                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4513                         if (!ret)
4514                                 si_populate_std_voltage_value(rdev, std_vddc,
4515                                                               table->ACPIState.levels[0].vddc.index,
4516                                                               &table->ACPIState.levels[0].std_vddc);
4517                 }
4518                 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4519
4520                 if (si_pi->vddc_phase_shed_control) {
4521                         si_populate_phase_shedding_value(rdev,
4522                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4523                                                          pi->acpi_vddc,
4524                                                          0,
4525                                                          0,
4526                                                          &table->ACPIState.levels[0].vddc);
4527                 }
4528         } else {
4529                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4530                                                 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4531                 if (!ret) {
4532                         u16 std_vddc;
4533
4534                         ret = si_get_std_voltage_value(rdev,
4535                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4536
4537                         if (!ret)
4538                                 si_populate_std_voltage_value(rdev, std_vddc,
4539                                                               table->ACPIState.levels[0].vddc.index,
4540                                                               &table->ACPIState.levels[0].std_vddc);
4541                 }
4542                 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4543                                                                                     si_pi->sys_pcie_mask,
4544                                                                                     si_pi->boot_pcie_gen,
4545                                                                                     RADEON_PCIE_GEN1);
4546
4547                 if (si_pi->vddc_phase_shed_control)
4548                         si_populate_phase_shedding_value(rdev,
4549                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4550                                                          pi->min_vddc_in_table,
4551                                                          0,
4552                                                          0,
4553                                                          &table->ACPIState.levels[0].vddc);
4554         }
4555
4556         if (pi->acpi_vddc) {
4557                 if (eg_pi->acpi_vddci)
4558                         si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4559                                                   eg_pi->acpi_vddci,
4560                                                   &table->ACPIState.levels[0].vddci);
4561         }
4562
4563         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4564         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4565
4566         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4567
4568         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4569         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4570
4571         table->ACPIState.levels[0].mclk.vDLL_CNTL =
4572                 cpu_to_be32(dll_cntl);
4573         table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4574                 cpu_to_be32(mclk_pwrmgt_cntl);
4575         table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4576                 cpu_to_be32(mpll_ad_func_cntl);
4577         table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4578                 cpu_to_be32(mpll_dq_func_cntl);
4579         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4580                 cpu_to_be32(mpll_func_cntl);
4581         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4582                 cpu_to_be32(mpll_func_cntl_1);
4583         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4584                 cpu_to_be32(mpll_func_cntl_2);
4585         table->ACPIState.levels[0].mclk.vMPLL_SS =
4586                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4587         table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4588                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4589
4590         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4591                 cpu_to_be32(spll_func_cntl);
4592         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4593                 cpu_to_be32(spll_func_cntl_2);
4594         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4595                 cpu_to_be32(spll_func_cntl_3);
4596         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4597                 cpu_to_be32(spll_func_cntl_4);
4598
4599         table->ACPIState.levels[0].mclk.mclk_value = 0;
4600         table->ACPIState.levels[0].sclk.sclk_value = 0;
4601
4602         si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4603
4604         if (eg_pi->dynamic_ac_timing)
4605                 table->ACPIState.levels[0].ACIndex = 0;
4606
4607         table->ACPIState.levels[0].dpm2.MaxPS = 0;
4608         table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4609         table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4610         table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4611         table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4612
4613         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4614         table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4615
4616         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4617         table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4618
4619         return 0;
4620 }
4621
4622 static int si_populate_ulv_state(struct radeon_device *rdev,
4623                                  SISLANDS_SMC_SWSTATE *state)
4624 {
4625         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4626         struct si_power_info *si_pi = si_get_pi(rdev);
4627         struct si_ulv_param *ulv = &si_pi->ulv;
4628         u32 sclk_in_sr = 1350; /* ??? */
4629         int ret;
4630
4631         ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4632                                             &state->levels[0]);
4633         if (!ret) {
4634                 if (eg_pi->sclk_deep_sleep) {
4635                         if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4636                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4637                         else
4638                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4639                 }
4640                 if (ulv->one_pcie_lane_in_ulv)
4641                         state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4642                 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4643                 state->levels[0].ACIndex = 1;
4644                 state->levels[0].std_vddc = state->levels[0].vddc;
4645                 state->levelCount = 1;
4646
4647                 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4648         }
4649
4650         return ret;
4651 }
4652
4653 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4654 {
4655         struct si_power_info *si_pi = si_get_pi(rdev);
4656         struct si_ulv_param *ulv = &si_pi->ulv;
4657         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4658         int ret;
4659
4660         ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4661                                                    &arb_regs);
4662         if (ret)
4663                 return ret;
4664
4665         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4666                                    ulv->volt_change_delay);
4667
4668         ret = si_copy_bytes_to_smc(rdev,
4669                                    si_pi->arb_table_start +
4670                                    offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4671                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4672                                    (u8 *)&arb_regs,
4673                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4674                                    si_pi->sram_end);
4675
4676         return ret;
4677 }
4678
4679 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4680 {
4681         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4682
4683         pi->mvdd_split_frequency = 30000;
4684 }
4685
4686 static int si_init_smc_table(struct radeon_device *rdev)
4687 {
4688         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4689         struct si_power_info *si_pi = si_get_pi(rdev);
4690         struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4691         const struct si_ulv_param *ulv = &si_pi->ulv;
4692         SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
4693         int ret;
4694         u32 lane_width;
4695         u32 vr_hot_gpio;
4696
4697         si_populate_smc_voltage_tables(rdev, table);
4698
4699         switch (rdev->pm.int_thermal_type) {
4700         case THERMAL_TYPE_SI:
4701         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4702                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4703                 break;
4704         case THERMAL_TYPE_NONE:
4705                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4706                 break;
4707         default:
4708                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4709                 break;
4710         }
4711
4712         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4713                 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4714
4715         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4716                 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4717                         table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4718         }
4719
4720         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4721                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4722
4723         if (pi->mem_gddr5)
4724                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4725
4726         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4727                 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4728
4729         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4730                 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4731                 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4732                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4733                                            vr_hot_gpio);
4734         }
4735
4736         ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4737         if (ret)
4738                 return ret;
4739
4740         ret = si_populate_smc_acpi_state(rdev, table);
4741         if (ret)
4742                 return ret;
4743
4744         table->driverState = table->initialState;
4745
4746         ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4747                                                      SISLANDS_INITIAL_STATE_ARB_INDEX);
4748         if (ret)
4749                 return ret;
4750
4751         if (ulv->supported && ulv->pl.vddc) {
4752                 ret = si_populate_ulv_state(rdev, &table->ULVState);
4753                 if (ret)
4754                         return ret;
4755
4756                 ret = si_program_ulv_memory_timing_parameters(rdev);
4757                 if (ret)
4758                         return ret;
4759
4760                 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4761                 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4762
4763                 lane_width = radeon_get_pcie_lanes(rdev);
4764                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4765         } else {
4766                 table->ULVState = table->initialState;
4767         }
4768
4769         return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4770                                     (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4771                                     si_pi->sram_end);
4772 }
4773
4774 static int si_calculate_sclk_params(struct radeon_device *rdev,
4775                                     u32 engine_clock,
4776                                     SISLANDS_SMC_SCLK_VALUE *sclk)
4777 {
4778         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4779         struct si_power_info *si_pi = si_get_pi(rdev);
4780         struct atom_clock_dividers dividers;
4781         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4782         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4783         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4784         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4785         u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4786         u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4787         u64 tmp;
4788         u32 reference_clock = rdev->clock.spll.reference_freq;
4789         u32 reference_divider;
4790         u32 fbdiv;
4791         int ret;
4792
4793         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4794                                              engine_clock, false, &dividers);
4795         if (ret)
4796                 return ret;
4797
4798         reference_divider = 1 + dividers.ref_div;
4799
4800         tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4801         do_div(tmp, reference_clock);
4802         fbdiv = (u32) tmp;
4803
4804         spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4805         spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4806         spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4807
4808         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4809         spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4810
4811         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4812         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4813         spll_func_cntl_3 |= SPLL_DITHEN;
4814
4815         if (pi->sclk_ss) {
4816                 struct radeon_atom_ss ss;
4817                 u32 vco_freq = engine_clock * dividers.post_div;
4818
4819                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4820                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4821                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4822                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4823
4824                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
4825                         cg_spll_spread_spectrum |= CLK_S(clk_s);
4826                         cg_spll_spread_spectrum |= SSEN;
4827
4828                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4829                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4830                 }
4831         }
4832
4833         sclk->sclk_value = engine_clock;
4834         sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4835         sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4836         sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4837         sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4838         sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4839         sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4840
4841         return 0;
4842 }
4843
4844 static int si_populate_sclk_value(struct radeon_device *rdev,
4845                                   u32 engine_clock,
4846                                   SISLANDS_SMC_SCLK_VALUE *sclk)
4847 {
4848         SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4849         int ret;
4850
4851         ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4852         if (!ret) {
4853                 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4854                 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4855                 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4856                 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4857                 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4858                 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4859                 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4860         }
4861
4862         return ret;
4863 }
4864
4865 static int si_populate_mclk_value(struct radeon_device *rdev,
4866                                   u32 engine_clock,
4867                                   u32 memory_clock,
4868                                   SISLANDS_SMC_MCLK_VALUE *mclk,
4869                                   bool strobe_mode,
4870                                   bool dll_state_on)
4871 {
4872         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4873         struct si_power_info *si_pi = si_get_pi(rdev);
4874         u32  dll_cntl = si_pi->clock_registers.dll_cntl;
4875         u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4876         u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4877         u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4878         u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4879         u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4880         u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4881         u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4882         u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4883         struct atom_mpll_param mpll_param;
4884         int ret;
4885
4886         ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4887         if (ret)
4888                 return ret;
4889
4890         mpll_func_cntl &= ~BWCTRL_MASK;
4891         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4892
4893         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4894         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4895                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4896
4897         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4898         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4899
4900         if (pi->mem_gddr5) {
4901                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4902                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4903                         YCLK_POST_DIV(mpll_param.post_div);
4904         }
4905
4906         if (pi->mclk_ss) {
4907                 struct radeon_atom_ss ss;
4908                 u32 freq_nom;
4909                 u32 tmp;
4910                 u32 reference_clock = rdev->clock.mpll.reference_freq;
4911
4912                 if (pi->mem_gddr5)
4913                         freq_nom = memory_clock * 4;
4914                 else
4915                         freq_nom = memory_clock * 2;
4916
4917                 tmp = freq_nom / reference_clock;
4918                 tmp = tmp * tmp;
4919                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4920                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4921                         u32 clks = reference_clock * 5 / ss.rate;
4922                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4923
4924                         mpll_ss1 &= ~CLKV_MASK;
4925                         mpll_ss1 |= CLKV(clkv);
4926
4927                         mpll_ss2 &= ~CLKS_MASK;
4928                         mpll_ss2 |= CLKS(clks);
4929                 }
4930         }
4931
4932         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4933         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4934
4935         if (dll_state_on)
4936                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4937         else
4938                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4939
4940         mclk->mclk_value = cpu_to_be32(memory_clock);
4941         mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4942         mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4943         mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4944         mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4945         mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4946         mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4947         mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4948         mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4949         mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4950
4951         return 0;
4952 }
4953
4954 static void si_populate_smc_sp(struct radeon_device *rdev,
4955                                struct radeon_ps *radeon_state,
4956                                SISLANDS_SMC_SWSTATE *smc_state)
4957 {
4958         struct ni_ps *ps = ni_get_ps(radeon_state);
4959         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4960         int i;
4961
4962         for (i = 0; i < ps->performance_level_count - 1; i++)
4963                 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4964
4965         smc_state->levels[ps->performance_level_count - 1].bSP =
4966                 cpu_to_be32(pi->psp);
4967 }
4968
4969 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4970                                          struct rv7xx_pl *pl,
4971                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4972 {
4973         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4974         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4975         struct si_power_info *si_pi = si_get_pi(rdev);
4976         int ret;
4977         bool dll_state_on;
4978         u16 std_vddc;
4979         bool gmc_pg = false;
4980
4981         if (eg_pi->pcie_performance_request &&
4982             (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
4983                 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
4984         else
4985                 level->gen2PCIE = (u8)pl->pcie_gen;
4986
4987         ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4988         if (ret)
4989                 return ret;
4990
4991         level->mcFlags =  0;
4992
4993         if (pi->mclk_stutter_mode_threshold &&
4994             (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
4995             !eg_pi->uvd_enabled &&
4996             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
4997             (rdev->pm.dpm.new_active_crtc_count <= 2)) {
4998                 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
4999
5000                 if (gmc_pg)
5001                         level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5002         }
5003
5004         if (pi->mem_gddr5) {
5005                 if (pl->mclk > pi->mclk_edc_enable_threshold)
5006                         level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5007
5008                 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5009                         level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5010
5011                 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
5012
5013                 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5014                         if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5015                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5016                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5017                         else
5018                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5019                 } else {
5020                         dll_state_on = false;
5021                 }
5022         } else {
5023                 level->strobeMode = si_get_strobe_mode_settings(rdev,
5024                                                                 pl->mclk);
5025
5026                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5027         }
5028
5029         ret = si_populate_mclk_value(rdev,
5030                                      pl->sclk,
5031                                      pl->mclk,
5032                                      &level->mclk,
5033                                      (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5034         if (ret)
5035                 return ret;
5036
5037         ret = si_populate_voltage_value(rdev,
5038                                         &eg_pi->vddc_voltage_table,
5039                                         pl->vddc, &level->vddc);
5040         if (ret)
5041                 return ret;
5042
5043
5044         ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
5045         if (ret)
5046                 return ret;
5047
5048         ret = si_populate_std_voltage_value(rdev, std_vddc,
5049                                             level->vddc.index, &level->std_vddc);
5050         if (ret)
5051                 return ret;
5052
5053         if (eg_pi->vddci_control) {
5054                 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
5055                                                 pl->vddci, &level->vddci);
5056                 if (ret)
5057                         return ret;
5058         }
5059
5060         if (si_pi->vddc_phase_shed_control) {
5061                 ret = si_populate_phase_shedding_value(rdev,
5062                                                        &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
5063                                                        pl->vddc,
5064                                                        pl->sclk,
5065                                                        pl->mclk,
5066                                                        &level->vddc);
5067                 if (ret)
5068                         return ret;
5069         }
5070
5071         level->MaxPoweredUpCU = si_pi->max_cu;
5072
5073         ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5074
5075         return ret;
5076 }
5077
5078 static int si_populate_smc_t(struct radeon_device *rdev,
5079                              struct radeon_ps *radeon_state,
5080                              SISLANDS_SMC_SWSTATE *smc_state)
5081 {
5082         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5083         struct ni_ps *state = ni_get_ps(radeon_state);
5084         u32 a_t;
5085         u32 t_l, t_h;
5086         u32 high_bsp;
5087         int i, ret;
5088
5089         if (state->performance_level_count >= 9)
5090                 return -EINVAL;
5091
5092         if (state->performance_level_count < 2) {
5093                 a_t = CG_R(0xffff) | CG_L(0);
5094                 smc_state->levels[0].aT = cpu_to_be32(a_t);
5095                 return 0;
5096         }
5097
5098         smc_state->levels[0].aT = cpu_to_be32(0);
5099
5100         for (i = 0; i <= state->performance_level_count - 2; i++) {
5101                 ret = r600_calculate_at(
5102                         (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5103                         100 * R600_AH_DFLT,
5104                         state->performance_levels[i + 1].sclk,
5105                         state->performance_levels[i].sclk,
5106                         &t_l,
5107                         &t_h);
5108
5109                 if (ret) {
5110                         t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5111                         t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5112                 }
5113
5114                 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5115                 a_t |= CG_R(t_l * pi->bsp / 20000);
5116                 smc_state->levels[i].aT = cpu_to_be32(a_t);
5117
5118                 high_bsp = (i == state->performance_level_count - 2) ?
5119                         pi->pbsp : pi->bsp;
5120                 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5121                 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5122         }
5123
5124         return 0;
5125 }
5126
5127 static int si_disable_ulv(struct radeon_device *rdev)
5128 {
5129         struct si_power_info *si_pi = si_get_pi(rdev);
5130         struct si_ulv_param *ulv = &si_pi->ulv;
5131
5132         if (ulv->supported)
5133                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5134                         0 : -EINVAL;
5135
5136         return 0;
5137 }
5138
5139 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5140                                        struct radeon_ps *radeon_state)
5141 {
5142         const struct si_power_info *si_pi = si_get_pi(rdev);
5143         const struct si_ulv_param *ulv = &si_pi->ulv;
5144         const struct ni_ps *state = ni_get_ps(radeon_state);
5145         int i;
5146
5147         if (state->performance_levels[0].mclk != ulv->pl.mclk)
5148                 return false;
5149
5150         /* XXX validate against display requirements! */
5151
5152         for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5153                 if (rdev->clock.current_dispclk <=
5154                     rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5155                         if (ulv->pl.vddc <
5156                             rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5157                                 return false;
5158                 }
5159         }
5160
5161         if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5162                 return false;
5163
5164         return true;
5165 }
5166
5167 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5168                                                        struct radeon_ps *radeon_new_state)
5169 {
5170         const struct si_power_info *si_pi = si_get_pi(rdev);
5171         const struct si_ulv_param *ulv = &si_pi->ulv;
5172
5173         if (ulv->supported) {
5174                 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5175                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5176                                 0 : -EINVAL;
5177         }
5178         return 0;
5179 }
5180
5181 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5182                                          struct radeon_ps *radeon_state,
5183                                          SISLANDS_SMC_SWSTATE *smc_state)
5184 {
5185         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5186         struct ni_power_info *ni_pi = ni_get_pi(rdev);
5187         struct si_power_info *si_pi = si_get_pi(rdev);
5188         struct ni_ps *state = ni_get_ps(radeon_state);
5189         int i, ret;
5190         u32 threshold;
5191         u32 sclk_in_sr = 1350; /* ??? */
5192
5193         if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5194                 return -EINVAL;
5195
5196         threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5197
5198         if (radeon_state->vclk && radeon_state->dclk) {
5199                 eg_pi->uvd_enabled = true;
5200                 if (eg_pi->smu_uvd_hs)
5201                         smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5202         } else {
5203                 eg_pi->uvd_enabled = false;
5204         }
5205
5206         if (state->dc_compatible)
5207                 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5208
5209         smc_state->levelCount = 0;
5210         for (i = 0; i < state->performance_level_count; i++) {
5211                 if (eg_pi->sclk_deep_sleep) {
5212                         if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5213                                 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5214                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5215                                 else
5216                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5217                         }
5218                 }
5219
5220                 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5221                                                     &smc_state->levels[i]);
5222                 smc_state->levels[i].arbRefreshState =
5223                         (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5224
5225                 if (ret)
5226                         return ret;
5227
5228                 if (ni_pi->enable_power_containment)
5229                         smc_state->levels[i].displayWatermark =
5230                                 (state->performance_levels[i].sclk < threshold) ?
5231                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5232                 else
5233                         smc_state->levels[i].displayWatermark = (i < 2) ?
5234                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5235
5236                 if (eg_pi->dynamic_ac_timing)
5237                         smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5238                 else
5239                         smc_state->levels[i].ACIndex = 0;
5240
5241                 smc_state->levelCount++;
5242         }
5243
5244         si_write_smc_soft_register(rdev,
5245                                    SI_SMC_SOFT_REGISTER_watermark_threshold,
5246                                    threshold / 512);
5247
5248         si_populate_smc_sp(rdev, radeon_state, smc_state);
5249
5250         ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5251         if (ret)
5252                 ni_pi->enable_power_containment = false;
5253
5254         ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5255         if (ret)
5256                 ni_pi->enable_sq_ramping = false;
5257
5258         return si_populate_smc_t(rdev, radeon_state, smc_state);
5259 }
5260
5261 static int si_upload_sw_state(struct radeon_device *rdev,
5262                               struct radeon_ps *radeon_new_state)
5263 {
5264         struct si_power_info *si_pi = si_get_pi(rdev);
5265         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5266         int ret;
5267         u32 address = si_pi->state_table_start +
5268                 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5269         u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5270                 ((new_state->performance_level_count - 1) *
5271                  sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5272         SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5273
5274         memset(smc_state, 0, state_size);
5275
5276         ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5277         if (ret)
5278                 return ret;
5279
5280         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5281                                    state_size, si_pi->sram_end);
5282
5283         return ret;
5284 }
5285
5286 static int si_upload_ulv_state(struct radeon_device *rdev)
5287 {
5288         struct si_power_info *si_pi = si_get_pi(rdev);
5289         struct si_ulv_param *ulv = &si_pi->ulv;
5290         int ret = 0;
5291
5292         if (ulv->supported && ulv->pl.vddc) {
5293                 u32 address = si_pi->state_table_start +
5294                         offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5295                 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5296                 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5297
5298                 memset(smc_state, 0, state_size);
5299
5300                 ret = si_populate_ulv_state(rdev, smc_state);
5301                 if (!ret)
5302                         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5303                                                    state_size, si_pi->sram_end);
5304         }
5305
5306         return ret;
5307 }
5308
5309 static int si_upload_smc_data(struct radeon_device *rdev)
5310 {
5311         struct radeon_crtc *radeon_crtc = NULL;
5312         int i;
5313
5314         if (rdev->pm.dpm.new_active_crtc_count == 0)
5315                 return 0;
5316
5317         for (i = 0; i < rdev->num_crtc; i++) {
5318                 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5319                         radeon_crtc = rdev->mode_info.crtcs[i];
5320                         break;
5321                 }
5322         }
5323
5324         if (radeon_crtc == NULL)
5325                 return 0;
5326
5327         if (radeon_crtc->line_time <= 0)
5328                 return 0;
5329
5330         if (si_write_smc_soft_register(rdev,
5331                                        SI_SMC_SOFT_REGISTER_crtc_index,
5332                                        radeon_crtc->crtc_id) != PPSMC_Result_OK)
5333                 return 0;
5334
5335         if (si_write_smc_soft_register(rdev,
5336                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5337                                        radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5338                 return 0;
5339
5340         if (si_write_smc_soft_register(rdev,
5341                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5342                                        radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5343                 return 0;
5344
5345         return 0;
5346 }
5347
5348 static int si_set_mc_special_registers(struct radeon_device *rdev,
5349                                        struct si_mc_reg_table *table)
5350 {
5351         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5352         u8 i, j, k;
5353         u32 temp_reg;
5354
5355         for (i = 0, j = table->last; i < table->last; i++) {
5356                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5357                         return -EINVAL;
5358                 switch (table->mc_reg_address[i].s1 << 2) {
5359                 case MC_SEQ_MISC1:
5360                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
5361                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5362                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5363                         for (k = 0; k < table->num_entries; k++)
5364                                 table->mc_reg_table_entry[k].mc_data[j] =
5365                                         ((temp_reg & 0xffff0000)) |
5366                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5367                         j++;
5368                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5369                                 return -EINVAL;
5370
5371                         temp_reg = RREG32(MC_PMG_CMD_MRS);
5372                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5373                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5374                         for (k = 0; k < table->num_entries; k++) {
5375                                 table->mc_reg_table_entry[k].mc_data[j] =
5376                                         (temp_reg & 0xffff0000) |
5377                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5378                                 if (!pi->mem_gddr5)
5379                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5380                         }
5381                         j++;
5382                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5383                                 return -EINVAL;
5384
5385                         if (!pi->mem_gddr5) {
5386                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5387                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5388                                 for (k = 0; k < table->num_entries; k++)
5389                                         table->mc_reg_table_entry[k].mc_data[j] =
5390                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5391                                 j++;
5392                                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5393                                         return -EINVAL;
5394                         }
5395                         break;
5396                 case MC_SEQ_RESERVE_M:
5397                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
5398                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5399                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5400                         for(k = 0; k < table->num_entries; k++)
5401                                 table->mc_reg_table_entry[k].mc_data[j] =
5402                                         (temp_reg & 0xffff0000) |
5403                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5404                         j++;
5405                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5406                                 return -EINVAL;
5407                         break;
5408                 default:
5409                         break;
5410                 }
5411         }
5412
5413         table->last = j;
5414
5415         return 0;
5416 }
5417
5418 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5419 {
5420         bool result = true;
5421
5422         switch (in_reg) {
5423         case  MC_SEQ_RAS_TIMING >> 2:
5424                 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5425                 break;
5426         case MC_SEQ_CAS_TIMING >> 2:
5427                 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5428                 break;
5429         case MC_SEQ_MISC_TIMING >> 2:
5430                 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5431                 break;
5432         case MC_SEQ_MISC_TIMING2 >> 2:
5433                 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5434                 break;
5435         case MC_SEQ_RD_CTL_D0 >> 2:
5436                 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5437                 break;
5438         case MC_SEQ_RD_CTL_D1 >> 2:
5439                 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5440                 break;
5441         case MC_SEQ_WR_CTL_D0 >> 2:
5442                 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5443                 break;
5444         case MC_SEQ_WR_CTL_D1 >> 2:
5445                 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5446                 break;
5447         case MC_PMG_CMD_EMRS >> 2:
5448                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5449                 break;
5450         case MC_PMG_CMD_MRS >> 2:
5451                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5452                 break;
5453         case MC_PMG_CMD_MRS1 >> 2:
5454                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5455                 break;
5456         case MC_SEQ_PMG_TIMING >> 2:
5457                 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5458                 break;
5459         case MC_PMG_CMD_MRS2 >> 2:
5460                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5461                 break;
5462         case MC_SEQ_WR_CTL_2 >> 2:
5463                 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5464                 break;
5465         default:
5466                 result = false;
5467                 break;
5468         }
5469
5470         return result;
5471 }
5472
5473 static void si_set_valid_flag(struct si_mc_reg_table *table)
5474 {
5475         u8 i, j;
5476
5477         for (i = 0; i < table->last; i++) {
5478                 for (j = 1; j < table->num_entries; j++) {
5479                         if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5480                                 table->valid_flag |= 1 << i;
5481                                 break;
5482                         }
5483                 }
5484         }
5485 }
5486
5487 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5488 {
5489         u32 i;
5490         u16 address;
5491
5492         for (i = 0; i < table->last; i++)
5493                 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5494                         address : table->mc_reg_address[i].s1;
5495
5496 }
5497
5498 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5499                                       struct si_mc_reg_table *si_table)
5500 {
5501         u8 i, j;
5502
5503         if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5504                 return -EINVAL;
5505         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5506                 return -EINVAL;
5507
5508         for (i = 0; i < table->last; i++)
5509                 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5510         si_table->last = table->last;
5511
5512         for (i = 0; i < table->num_entries; i++) {
5513                 si_table->mc_reg_table_entry[i].mclk_max =
5514                         table->mc_reg_table_entry[i].mclk_max;
5515                 for (j = 0; j < table->last; j++) {
5516                         si_table->mc_reg_table_entry[i].mc_data[j] =
5517                                 table->mc_reg_table_entry[i].mc_data[j];
5518                 }
5519         }
5520         si_table->num_entries = table->num_entries;
5521
5522         return 0;
5523 }
5524
5525 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5526 {
5527         struct si_power_info *si_pi = si_get_pi(rdev);
5528         struct atom_mc_reg_table *table;
5529         struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5530         u8 module_index = rv770_get_memory_module_index(rdev);
5531         int ret;
5532
5533         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5534         if (!table)
5535                 return -ENOMEM;
5536
5537         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5538         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5539         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5540         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5541         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5542         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5543         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5544         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5545         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5546         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5547         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5548         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5549         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5550         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5551
5552         ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5553         if (ret)
5554                 goto init_mc_done;
5555
5556         ret = si_copy_vbios_mc_reg_table(table, si_table);
5557         if (ret)
5558                 goto init_mc_done;
5559
5560         si_set_s0_mc_reg_index(si_table);
5561
5562         ret = si_set_mc_special_registers(rdev, si_table);
5563         if (ret)
5564                 goto init_mc_done;
5565
5566         si_set_valid_flag(si_table);
5567
5568 init_mc_done:
5569         kfree(table);
5570
5571         return ret;
5572
5573 }
5574
5575 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5576                                          SMC_SIslands_MCRegisters *mc_reg_table)
5577 {
5578         struct si_power_info *si_pi = si_get_pi(rdev);
5579         u32 i, j;
5580
5581         for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5582                 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5583                         if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5584                                 break;
5585                         mc_reg_table->address[i].s0 =
5586                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5587                         mc_reg_table->address[i].s1 =
5588                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5589                         i++;
5590                 }
5591         }
5592         mc_reg_table->last = (u8)i;
5593 }
5594
5595 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5596                                     SMC_SIslands_MCRegisterSet *data,
5597                                     u32 num_entries, u32 valid_flag)
5598 {
5599         u32 i, j;
5600
5601         for(i = 0, j = 0; j < num_entries; j++) {
5602                 if (valid_flag & (1 << j)) {
5603                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
5604                         i++;
5605                 }
5606         }
5607 }
5608
5609 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5610                                                  struct rv7xx_pl *pl,
5611                                                  SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5612 {
5613         struct si_power_info *si_pi = si_get_pi(rdev);
5614         u32 i = 0;
5615
5616         for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5617                 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5618                         break;
5619         }
5620
5621         if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5622                 --i;
5623
5624         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5625                                 mc_reg_table_data, si_pi->mc_reg_table.last,
5626                                 si_pi->mc_reg_table.valid_flag);
5627 }
5628
5629 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5630                                            struct radeon_ps *radeon_state,
5631                                            SMC_SIslands_MCRegisters *mc_reg_table)
5632 {
5633         struct ni_ps *state = ni_get_ps(radeon_state);
5634         int i;
5635
5636         for (i = 0; i < state->performance_level_count; i++) {
5637                 si_convert_mc_reg_table_entry_to_smc(rdev,
5638                                                      &state->performance_levels[i],
5639                                                      &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5640         }
5641 }
5642
5643 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5644                                     struct radeon_ps *radeon_boot_state)
5645 {
5646         struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5647         struct si_power_info *si_pi = si_get_pi(rdev);
5648         struct si_ulv_param *ulv = &si_pi->ulv;
5649         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5650
5651         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5652
5653         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5654
5655         si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5656
5657         si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5658                                              &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5659
5660         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5661                                 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5662                                 si_pi->mc_reg_table.last,
5663                                 si_pi->mc_reg_table.valid_flag);
5664
5665         if (ulv->supported && ulv->pl.vddc != 0)
5666                 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5667                                                      &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5668         else
5669                 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5670                                         &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5671                                         si_pi->mc_reg_table.last,
5672                                         si_pi->mc_reg_table.valid_flag);
5673
5674         si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5675
5676         return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5677                                     (u8 *)smc_mc_reg_table,
5678                                     sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5679 }
5680
5681 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5682                                   struct radeon_ps *radeon_new_state)
5683 {
5684         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5685         struct si_power_info *si_pi = si_get_pi(rdev);
5686         u32 address = si_pi->mc_reg_table_start +
5687                 offsetof(SMC_SIslands_MCRegisters,
5688                          data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5689         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5690
5691         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5692
5693         si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5694
5695
5696         return si_copy_bytes_to_smc(rdev, address,
5697                                     (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5698                                     sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5699                                     si_pi->sram_end);
5700
5701 }
5702
5703 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5704 {
5705         if (enable)
5706                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5707         else
5708                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5709 }
5710
5711 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5712                                                       struct radeon_ps *radeon_state)
5713 {
5714         struct ni_ps *state = ni_get_ps(radeon_state);
5715         int i;
5716         u16 pcie_speed, max_speed = 0;
5717
5718         for (i = 0; i < state->performance_level_count; i++) {
5719                 pcie_speed = state->performance_levels[i].pcie_gen;
5720                 if (max_speed < pcie_speed)
5721                         max_speed = pcie_speed;
5722         }
5723         return max_speed;
5724 }
5725
5726 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5727 {
5728         u32 speed_cntl;
5729
5730         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5731         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5732
5733         return (u16)speed_cntl;
5734 }
5735
5736 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5737                                                              struct radeon_ps *radeon_new_state,
5738                                                              struct radeon_ps *radeon_current_state)
5739 {
5740         struct si_power_info *si_pi = si_get_pi(rdev);
5741         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5742         enum radeon_pcie_gen current_link_speed;
5743
5744         if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5745                 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5746         else
5747                 current_link_speed = si_pi->force_pcie_gen;
5748
5749         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5750         si_pi->pspp_notify_required = false;
5751         if (target_link_speed > current_link_speed) {
5752                 switch (target_link_speed) {
5753 #if defined(CONFIG_ACPI)
5754                 case RADEON_PCIE_GEN3:
5755                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5756                                 break;
5757                         si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5758                         if (current_link_speed == RADEON_PCIE_GEN2)
5759                                 break;
5760                 case RADEON_PCIE_GEN2:
5761                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5762                                 break;
5763 #endif
5764                 default:
5765                         si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5766                         break;
5767                 }
5768         } else {
5769                 if (target_link_speed < current_link_speed)
5770                         si_pi->pspp_notify_required = true;
5771         }
5772 }
5773
5774 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5775                                                            struct radeon_ps *radeon_new_state,
5776                                                            struct radeon_ps *radeon_current_state)
5777 {
5778         struct si_power_info *si_pi = si_get_pi(rdev);
5779         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5780         u8 request;
5781
5782         if (si_pi->pspp_notify_required) {
5783                 if (target_link_speed == RADEON_PCIE_GEN3)
5784                         request = PCIE_PERF_REQ_PECI_GEN3;
5785                 else if (target_link_speed == RADEON_PCIE_GEN2)
5786                         request = PCIE_PERF_REQ_PECI_GEN2;
5787                 else
5788                         request = PCIE_PERF_REQ_PECI_GEN1;
5789
5790                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5791                     (si_get_current_pcie_speed(rdev) > 0))
5792                         return;
5793
5794 #if defined(CONFIG_ACPI)
5795                 radeon_acpi_pcie_performance_request(rdev, request, false);
5796 #endif
5797         }
5798 }
5799
5800 #if 0
5801 static int si_ds_request(struct radeon_device *rdev,
5802                          bool ds_status_on, u32 count_write)
5803 {
5804         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5805
5806         if (eg_pi->sclk_deep_sleep) {
5807                 if (ds_status_on)
5808                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5809                                 PPSMC_Result_OK) ?
5810                                 0 : -EINVAL;
5811                 else
5812                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5813                                 PPSMC_Result_OK) ? 0 : -EINVAL;
5814         }
5815         return 0;
5816 }
5817 #endif
5818
5819 static void si_set_max_cu_value(struct radeon_device *rdev)
5820 {
5821         struct si_power_info *si_pi = si_get_pi(rdev);
5822
5823         if (rdev->family == CHIP_VERDE) {
5824                 switch (rdev->pdev->device) {
5825                 case 0x6820:
5826                 case 0x6825:
5827                 case 0x6821:
5828                 case 0x6823:
5829                 case 0x6827:
5830                         si_pi->max_cu = 10;
5831                         break;
5832                 case 0x682D:
5833                 case 0x6824:
5834                 case 0x682F:
5835                 case 0x6826:
5836                         si_pi->max_cu = 8;
5837                         break;
5838                 case 0x6828:
5839                 case 0x6830:
5840                 case 0x6831:
5841                 case 0x6838:
5842                 case 0x6839:
5843                 case 0x683D:
5844                         si_pi->max_cu = 10;
5845                         break;
5846                 case 0x683B:
5847                 case 0x683F:
5848                 case 0x6829:
5849                         si_pi->max_cu = 8;
5850                         break;
5851                 default:
5852                         si_pi->max_cu = 0;
5853                         break;
5854                 }
5855         } else {
5856                 si_pi->max_cu = 0;
5857         }
5858 }
5859
5860 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5861                                                              struct radeon_clock_voltage_dependency_table *table)
5862 {
5863         u32 i;
5864         int j;
5865         u16 leakage_voltage;
5866
5867         if (table) {
5868                 for (i = 0; i < table->count; i++) {
5869                         switch (si_get_leakage_voltage_from_leakage_index(rdev,
5870                                                                           table->entries[i].v,
5871                                                                           &leakage_voltage)) {
5872                         case 0:
5873                                 table->entries[i].v = leakage_voltage;
5874                                 break;
5875                         case -EAGAIN:
5876                                 return -EINVAL;
5877                         case -EINVAL:
5878                         default:
5879                                 break;
5880                         }
5881                 }
5882
5883                 for (j = (table->count - 2); j >= 0; j--) {
5884                         table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5885                                 table->entries[j].v : table->entries[j + 1].v;
5886                 }
5887         }
5888         return 0;
5889 }
5890
5891 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5892 {
5893         int ret = 0;
5894
5895         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5896                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5897         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5898                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5899         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5900                                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5901         return ret;
5902 }
5903
5904 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5905                                           struct radeon_ps *radeon_new_state,
5906                                           struct radeon_ps *radeon_current_state)
5907 {
5908         u32 lane_width;
5909         u32 new_lane_width =
5910                 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5911         u32 current_lane_width =
5912                 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5913
5914         if (new_lane_width != current_lane_width) {
5915                 radeon_set_pcie_lanes(rdev, new_lane_width);
5916                 lane_width = radeon_get_pcie_lanes(rdev);
5917                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5918         }
5919 }
5920
5921 static void si_set_vce_clock(struct radeon_device *rdev,
5922                              struct radeon_ps *new_rps,
5923                              struct radeon_ps *old_rps)
5924 {
5925         if ((old_rps->evclk != new_rps->evclk) ||
5926             (old_rps->ecclk != new_rps->ecclk)) {
5927                 /* turn the clocks on when encoding, off otherwise */
5928                 if (new_rps->evclk || new_rps->ecclk)
5929                         vce_v1_0_enable_mgcg(rdev, false);
5930                 else
5931                         vce_v1_0_enable_mgcg(rdev, true);
5932                 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk);
5933         }
5934 }
5935
5936 void si_dpm_setup_asic(struct radeon_device *rdev)
5937 {
5938         int r;
5939
5940         r = si_mc_load_microcode(rdev);
5941         if (r)
5942                 DRM_ERROR("Failed to load MC firmware!\n");
5943         rv770_get_memory_type(rdev);
5944         si_read_clock_registers(rdev);
5945         si_enable_acpi_power_management(rdev);
5946 }
5947
5948 static int si_thermal_enable_alert(struct radeon_device *rdev,
5949                                    bool enable)
5950 {
5951         u32 thermal_int = RREG32(CG_THERMAL_INT);
5952
5953         if (enable) {
5954                 PPSMC_Result result;
5955
5956                 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
5957                 WREG32(CG_THERMAL_INT, thermal_int);
5958                 rdev->irq.dpm_thermal = false;
5959                 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5960                 if (result != PPSMC_Result_OK) {
5961                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5962                         return -EINVAL;
5963                 }
5964         } else {
5965                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
5966                 WREG32(CG_THERMAL_INT, thermal_int);
5967                 rdev->irq.dpm_thermal = true;
5968         }
5969
5970         return 0;
5971 }
5972
5973 static int si_thermal_set_temperature_range(struct radeon_device *rdev,
5974                                             int min_temp, int max_temp)
5975 {
5976         int low_temp = 0 * 1000;
5977         int high_temp = 255 * 1000;
5978
5979         if (low_temp < min_temp)
5980                 low_temp = min_temp;
5981         if (high_temp > max_temp)
5982                 high_temp = max_temp;
5983         if (high_temp < low_temp) {
5984                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
5985                 return -EINVAL;
5986         }
5987
5988         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
5989         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
5990         WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
5991
5992         rdev->pm.dpm.thermal.min_temp = low_temp;
5993         rdev->pm.dpm.thermal.max_temp = high_temp;
5994
5995         return 0;
5996 }
5997
5998 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
5999 {
6000         struct si_power_info *si_pi = si_get_pi(rdev);
6001         u32 tmp;
6002
6003         if (si_pi->fan_ctrl_is_in_default_mode) {
6004                 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6005                 si_pi->fan_ctrl_default_mode = tmp;
6006                 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6007                 si_pi->t_min = tmp;
6008                 si_pi->fan_ctrl_is_in_default_mode = false;
6009         }
6010
6011         tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6012         tmp |= TMIN(0);
6013         WREG32(CG_FDO_CTRL2, tmp);
6014
6015         tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6016         tmp |= FDO_PWM_MODE(mode);
6017         WREG32(CG_FDO_CTRL2, tmp);
6018 }
6019
6020 static int si_thermal_setup_fan_table(struct radeon_device *rdev)
6021 {
6022         struct si_power_info *si_pi = si_get_pi(rdev);
6023         PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6024         u32 duty100;
6025         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6026         u16 fdo_min, slope1, slope2;
6027         u32 reference_clock, tmp;
6028         int ret;
6029         u64 tmp64;
6030
6031         if (!si_pi->fan_table_start) {
6032                 rdev->pm.dpm.fan.ucode_fan_control = false;
6033                 return 0;
6034         }
6035
6036         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6037
6038         if (duty100 == 0) {
6039                 rdev->pm.dpm.fan.ucode_fan_control = false;
6040                 return 0;
6041         }
6042
6043         tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
6044         do_div(tmp64, 10000);
6045         fdo_min = (u16)tmp64;
6046
6047         t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
6048         t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
6049
6050         pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
6051         pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
6052
6053         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6054         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6055
6056         fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
6057         fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
6058         fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
6059
6060         fan_table.slope1 = cpu_to_be16(slope1);
6061         fan_table.slope2 = cpu_to_be16(slope2);
6062
6063         fan_table.fdo_min = cpu_to_be16(fdo_min);
6064
6065         fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
6066
6067         fan_table.hys_up = cpu_to_be16(1);
6068
6069         fan_table.hys_slope = cpu_to_be16(1);
6070
6071         fan_table.temp_resp_lim = cpu_to_be16(5);
6072
6073         reference_clock = radeon_get_xclk(rdev);
6074
6075         fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
6076                                                 reference_clock) / 1600);
6077
6078         fan_table.fdo_max = cpu_to_be16((u16)duty100);
6079
6080         tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6081         fan_table.temp_src = (uint8_t)tmp;
6082
6083         ret = si_copy_bytes_to_smc(rdev,
6084                                    si_pi->fan_table_start,
6085                                    (u8 *)(&fan_table),
6086                                    sizeof(fan_table),
6087                                    si_pi->sram_end);
6088
6089         if (ret) {
6090                 DRM_ERROR("Failed to load fan table to the SMC.");
6091                 rdev->pm.dpm.fan.ucode_fan_control = false;
6092         }
6093
6094         return 0;
6095 }
6096
6097 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
6098 {
6099         struct si_power_info *si_pi = si_get_pi(rdev);
6100         PPSMC_Result ret;
6101
6102         ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl);
6103         if (ret == PPSMC_Result_OK) {
6104                 si_pi->fan_is_controlled_by_smc = true;
6105                 return 0;
6106         } else {
6107                 return -EINVAL;
6108         }
6109 }
6110
6111 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
6112 {
6113         struct si_power_info *si_pi = si_get_pi(rdev);
6114         PPSMC_Result ret;
6115
6116         ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl);
6117
6118         if (ret == PPSMC_Result_OK) {
6119                 si_pi->fan_is_controlled_by_smc = false;
6120                 return 0;
6121         } else {
6122                 return -EINVAL;
6123         }
6124 }
6125
6126 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
6127                                       u32 *speed)
6128 {
6129         u32 duty, duty100;
6130         u64 tmp64;
6131
6132         if (rdev->pm.no_fan)
6133                 return -ENOENT;
6134
6135         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6136         duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6137
6138         if (duty100 == 0)
6139                 return -EINVAL;
6140
6141         tmp64 = (u64)duty * 100;
6142         do_div(tmp64, duty100);
6143         *speed = (u32)tmp64;
6144
6145         if (*speed > 100)
6146                 *speed = 100;
6147
6148         return 0;
6149 }
6150
6151 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
6152                                       u32 speed)
6153 {
6154         struct si_power_info *si_pi = si_get_pi(rdev);
6155         u32 tmp;
6156         u32 duty, duty100;
6157         u64 tmp64;
6158
6159         if (rdev->pm.no_fan)
6160                 return -ENOENT;
6161
6162         if (si_pi->fan_is_controlled_by_smc)
6163                 return -EINVAL;
6164
6165         if (speed > 100)
6166                 return -EINVAL;
6167
6168         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6169
6170         if (duty100 == 0)
6171                 return -EINVAL;
6172
6173         tmp64 = (u64)speed * duty100;
6174         do_div(tmp64, 100);
6175         duty = (u32)tmp64;
6176
6177         tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6178         tmp |= FDO_STATIC_DUTY(duty);
6179         WREG32(CG_FDO_CTRL0, tmp);
6180
6181         return 0;
6182 }
6183
6184 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
6185 {
6186         if (mode) {
6187                 /* stop auto-manage */
6188                 if (rdev->pm.dpm.fan.ucode_fan_control)
6189                         si_fan_ctrl_stop_smc_fan_control(rdev);
6190                 si_fan_ctrl_set_static_mode(rdev, mode);
6191         } else {
6192                 /* restart auto-manage */
6193                 if (rdev->pm.dpm.fan.ucode_fan_control)
6194                         si_thermal_start_smc_fan_control(rdev);
6195                 else
6196                         si_fan_ctrl_set_default_mode(rdev);
6197         }
6198 }
6199
6200 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev)
6201 {
6202         struct si_power_info *si_pi = si_get_pi(rdev);
6203         u32 tmp;
6204
6205         if (si_pi->fan_is_controlled_by_smc)
6206                 return 0;
6207
6208         tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6209         return (tmp >> FDO_PWM_MODE_SHIFT);
6210 }
6211
6212 #if 0
6213 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6214                                          u32 *speed)
6215 {
6216         u32 tach_period;
6217         u32 xclk = radeon_get_xclk(rdev);
6218
6219         if (rdev->pm.no_fan)
6220                 return -ENOENT;
6221
6222         if (rdev->pm.fan_pulses_per_revolution == 0)
6223                 return -ENOENT;
6224
6225         tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6226         if (tach_period == 0)
6227                 return -ENOENT;
6228
6229         *speed = 60 * xclk * 10000 / tach_period;
6230
6231         return 0;
6232 }
6233
6234 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6235                                          u32 speed)
6236 {
6237         u32 tach_period, tmp;
6238         u32 xclk = radeon_get_xclk(rdev);
6239
6240         if (rdev->pm.no_fan)
6241                 return -ENOENT;
6242
6243         if (rdev->pm.fan_pulses_per_revolution == 0)
6244                 return -ENOENT;
6245
6246         if ((speed < rdev->pm.fan_min_rpm) ||
6247             (speed > rdev->pm.fan_max_rpm))
6248                 return -EINVAL;
6249
6250         if (rdev->pm.dpm.fan.ucode_fan_control)
6251                 si_fan_ctrl_stop_smc_fan_control(rdev);
6252
6253         tach_period = 60 * xclk * 10000 / (8 * speed);
6254         tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6255         tmp |= TARGET_PERIOD(tach_period);
6256         WREG32(CG_TACH_CTRL, tmp);
6257
6258         si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6259
6260         return 0;
6261 }
6262 #endif
6263
6264 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
6265 {
6266         struct si_power_info *si_pi = si_get_pi(rdev);
6267         u32 tmp;
6268
6269         if (!si_pi->fan_ctrl_is_in_default_mode) {
6270                 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6271                 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6272                 WREG32(CG_FDO_CTRL2, tmp);
6273
6274                 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6275                 tmp |= TMIN(si_pi->t_min);
6276                 WREG32(CG_FDO_CTRL2, tmp);
6277                 si_pi->fan_ctrl_is_in_default_mode = true;
6278         }
6279 }
6280
6281 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
6282 {
6283         if (rdev->pm.dpm.fan.ucode_fan_control) {
6284                 si_fan_ctrl_start_smc_fan_control(rdev);
6285                 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6286         }
6287 }
6288
6289 static void si_thermal_initialize(struct radeon_device *rdev)
6290 {
6291         u32 tmp;
6292
6293         if (rdev->pm.fan_pulses_per_revolution) {
6294                 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6295                 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
6296                 WREG32(CG_TACH_CTRL, tmp);
6297         }
6298
6299         tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6300         tmp |= TACH_PWM_RESP_RATE(0x28);
6301         WREG32(CG_FDO_CTRL2, tmp);
6302 }
6303
6304 static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
6305 {
6306         int ret;
6307
6308         si_thermal_initialize(rdev);
6309         ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6310         if (ret)
6311                 return ret;
6312         ret = si_thermal_enable_alert(rdev, true);
6313         if (ret)
6314                 return ret;
6315         if (rdev->pm.dpm.fan.ucode_fan_control) {
6316                 ret = si_halt_smc(rdev);
6317                 if (ret)
6318                         return ret;
6319                 ret = si_thermal_setup_fan_table(rdev);
6320                 if (ret)
6321                         return ret;
6322                 ret = si_resume_smc(rdev);
6323                 if (ret)
6324                         return ret;
6325                 si_thermal_start_smc_fan_control(rdev);
6326         }
6327
6328         return 0;
6329 }
6330
6331 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
6332 {
6333         if (!rdev->pm.no_fan) {
6334                 si_fan_ctrl_set_default_mode(rdev);
6335                 si_fan_ctrl_stop_smc_fan_control(rdev);
6336         }
6337 }
6338
6339 int si_dpm_enable(struct radeon_device *rdev)
6340 {
6341         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6342         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6343         struct si_power_info *si_pi = si_get_pi(rdev);
6344         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6345         int ret;
6346
6347         if (si_is_smc_running(rdev))
6348                 return -EINVAL;
6349         if (pi->voltage_control || si_pi->voltage_control_svi2)
6350                 si_enable_voltage_control(rdev, true);
6351         if (pi->mvdd_control)
6352                 si_get_mvdd_configuration(rdev);
6353         if (pi->voltage_control || si_pi->voltage_control_svi2) {
6354                 ret = si_construct_voltage_tables(rdev);
6355                 if (ret) {
6356                         DRM_ERROR("si_construct_voltage_tables failed\n");
6357                         return ret;
6358                 }
6359         }
6360         if (eg_pi->dynamic_ac_timing) {
6361                 ret = si_initialize_mc_reg_table(rdev);
6362                 if (ret)
6363                         eg_pi->dynamic_ac_timing = false;
6364         }
6365         if (pi->dynamic_ss)
6366                 si_enable_spread_spectrum(rdev, true);
6367         if (pi->thermal_protection)
6368                 si_enable_thermal_protection(rdev, true);
6369         si_setup_bsp(rdev);
6370         si_program_git(rdev);
6371         si_program_tp(rdev);
6372         si_program_tpp(rdev);
6373         si_program_sstp(rdev);
6374         si_enable_display_gap(rdev);
6375         si_program_vc(rdev);
6376         ret = si_upload_firmware(rdev);
6377         if (ret) {
6378                 DRM_ERROR("si_upload_firmware failed\n");
6379                 return ret;
6380         }
6381         ret = si_process_firmware_header(rdev);
6382         if (ret) {
6383                 DRM_ERROR("si_process_firmware_header failed\n");
6384                 return ret;
6385         }
6386         ret = si_initial_switch_from_arb_f0_to_f1(rdev);
6387         if (ret) {
6388                 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6389                 return ret;
6390         }
6391         ret = si_init_smc_table(rdev);
6392         if (ret) {
6393                 DRM_ERROR("si_init_smc_table failed\n");
6394                 return ret;
6395         }
6396         ret = si_init_smc_spll_table(rdev);
6397         if (ret) {
6398                 DRM_ERROR("si_init_smc_spll_table failed\n");
6399                 return ret;
6400         }
6401         ret = si_init_arb_table_index(rdev);
6402         if (ret) {
6403                 DRM_ERROR("si_init_arb_table_index failed\n");
6404                 return ret;
6405         }
6406         if (eg_pi->dynamic_ac_timing) {
6407                 ret = si_populate_mc_reg_table(rdev, boot_ps);
6408                 if (ret) {
6409                         DRM_ERROR("si_populate_mc_reg_table failed\n");
6410                         return ret;
6411                 }
6412         }
6413         ret = si_initialize_smc_cac_tables(rdev);
6414         if (ret) {
6415                 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6416                 return ret;
6417         }
6418         ret = si_initialize_hardware_cac_manager(rdev);
6419         if (ret) {
6420                 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6421                 return ret;
6422         }
6423         ret = si_initialize_smc_dte_tables(rdev);
6424         if (ret) {
6425                 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6426                 return ret;
6427         }
6428         ret = si_populate_smc_tdp_limits(rdev, boot_ps);
6429         if (ret) {
6430                 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6431                 return ret;
6432         }
6433         ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
6434         if (ret) {
6435                 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6436                 return ret;
6437         }
6438         si_program_response_times(rdev);
6439         si_program_ds_registers(rdev);
6440         si_dpm_start_smc(rdev);
6441         ret = si_notify_smc_display_change(rdev, false);
6442         if (ret) {
6443                 DRM_ERROR("si_notify_smc_display_change failed\n");
6444                 return ret;
6445         }
6446         si_enable_sclk_control(rdev, true);
6447         si_start_dpm(rdev);
6448
6449         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6450
6451         si_thermal_start_thermal_controller(rdev);
6452
6453         ni_update_current_ps(rdev, boot_ps);
6454
6455         return 0;
6456 }
6457
6458 static int si_set_temperature_range(struct radeon_device *rdev)
6459 {
6460         int ret;
6461
6462         ret = si_thermal_enable_alert(rdev, false);
6463         if (ret)
6464                 return ret;
6465         ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6466         if (ret)
6467                 return ret;
6468         ret = si_thermal_enable_alert(rdev, true);
6469         if (ret)
6470                 return ret;
6471
6472         return ret;
6473 }
6474
6475 int si_dpm_late_enable(struct radeon_device *rdev)
6476 {
6477         int ret;
6478
6479         ret = si_set_temperature_range(rdev);
6480         if (ret)
6481                 return ret;
6482
6483         return ret;
6484 }
6485
6486 void si_dpm_disable(struct radeon_device *rdev)
6487 {
6488         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6489         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6490
6491         if (!si_is_smc_running(rdev))
6492                 return;
6493         si_thermal_stop_thermal_controller(rdev);
6494         si_disable_ulv(rdev);
6495         si_clear_vc(rdev);
6496         if (pi->thermal_protection)
6497                 si_enable_thermal_protection(rdev, false);
6498         si_enable_power_containment(rdev, boot_ps, false);
6499         si_enable_smc_cac(rdev, boot_ps, false);
6500         si_enable_spread_spectrum(rdev, false);
6501         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6502         si_stop_dpm(rdev);
6503         si_reset_to_default(rdev);
6504         si_dpm_stop_smc(rdev);
6505         si_force_switch_to_arb_f0(rdev);
6506
6507         ni_update_current_ps(rdev, boot_ps);
6508 }
6509
6510 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6511 {
6512         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6513         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6514         struct radeon_ps *new_ps = &requested_ps;
6515
6516         ni_update_requested_ps(rdev, new_ps);
6517
6518         si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6519
6520         return 0;
6521 }
6522
6523 static int si_power_control_set_level(struct radeon_device *rdev)
6524 {
6525         struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6526         int ret;
6527
6528         ret = si_restrict_performance_levels_before_switch(rdev);
6529         if (ret)
6530                 return ret;
6531         ret = si_halt_smc(rdev);
6532         if (ret)
6533                 return ret;
6534         ret = si_populate_smc_tdp_limits(rdev, new_ps);
6535         if (ret)
6536                 return ret;
6537         ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6538         if (ret)
6539                 return ret;
6540         ret = si_resume_smc(rdev);
6541         if (ret)
6542                 return ret;
6543         ret = si_set_sw_state(rdev);
6544         if (ret)
6545                 return ret;
6546         return 0;
6547 }
6548
6549 int si_dpm_set_power_state(struct radeon_device *rdev)
6550 {
6551         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6552         struct radeon_ps *new_ps = &eg_pi->requested_rps;
6553         struct radeon_ps *old_ps = &eg_pi->current_rps;
6554         int ret;
6555
6556         ret = si_disable_ulv(rdev);
6557         if (ret) {
6558                 DRM_ERROR("si_disable_ulv failed\n");
6559                 return ret;
6560         }
6561         ret = si_restrict_performance_levels_before_switch(rdev);
6562         if (ret) {
6563                 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6564                 return ret;
6565         }
6566         if (eg_pi->pcie_performance_request)
6567                 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6568         ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6569         ret = si_enable_power_containment(rdev, new_ps, false);
6570         if (ret) {
6571                 DRM_ERROR("si_enable_power_containment failed\n");
6572                 return ret;
6573         }
6574         ret = si_enable_smc_cac(rdev, new_ps, false);
6575         if (ret) {
6576                 DRM_ERROR("si_enable_smc_cac failed\n");
6577                 return ret;
6578         }
6579         ret = si_halt_smc(rdev);
6580         if (ret) {
6581                 DRM_ERROR("si_halt_smc failed\n");
6582                 return ret;
6583         }
6584         ret = si_upload_sw_state(rdev, new_ps);
6585         if (ret) {
6586                 DRM_ERROR("si_upload_sw_state failed\n");
6587                 return ret;
6588         }
6589         ret = si_upload_smc_data(rdev);
6590         if (ret) {
6591                 DRM_ERROR("si_upload_smc_data failed\n");
6592                 return ret;
6593         }
6594         ret = si_upload_ulv_state(rdev);
6595         if (ret) {
6596                 DRM_ERROR("si_upload_ulv_state failed\n");
6597                 return ret;
6598         }
6599         if (eg_pi->dynamic_ac_timing) {
6600                 ret = si_upload_mc_reg_table(rdev, new_ps);
6601                 if (ret) {
6602                         DRM_ERROR("si_upload_mc_reg_table failed\n");
6603                         return ret;
6604                 }
6605         }
6606         ret = si_program_memory_timing_parameters(rdev, new_ps);
6607         if (ret) {
6608                 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6609                 return ret;
6610         }
6611         si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6612
6613         ret = si_resume_smc(rdev);
6614         if (ret) {
6615                 DRM_ERROR("si_resume_smc failed\n");
6616                 return ret;
6617         }
6618         ret = si_set_sw_state(rdev);
6619         if (ret) {
6620                 DRM_ERROR("si_set_sw_state failed\n");
6621                 return ret;
6622         }
6623         ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6624         si_set_vce_clock(rdev, new_ps, old_ps);
6625         if (eg_pi->pcie_performance_request)
6626                 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6627         ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6628         if (ret) {
6629                 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6630                 return ret;
6631         }
6632         ret = si_enable_smc_cac(rdev, new_ps, true);
6633         if (ret) {
6634                 DRM_ERROR("si_enable_smc_cac failed\n");
6635                 return ret;
6636         }
6637         ret = si_enable_power_containment(rdev, new_ps, true);
6638         if (ret) {
6639                 DRM_ERROR("si_enable_power_containment failed\n");
6640                 return ret;
6641         }
6642
6643         ret = si_power_control_set_level(rdev);
6644         if (ret) {
6645                 DRM_ERROR("si_power_control_set_level failed\n");
6646                 return ret;
6647         }
6648
6649         return 0;
6650 }
6651
6652 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6653 {
6654         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6655         struct radeon_ps *new_ps = &eg_pi->requested_rps;
6656
6657         ni_update_current_ps(rdev, new_ps);
6658 }
6659
6660 #if 0
6661 void si_dpm_reset_asic(struct radeon_device *rdev)
6662 {
6663         si_restrict_performance_levels_before_switch(rdev);
6664         si_disable_ulv(rdev);
6665         si_set_boot_state(rdev);
6666 }
6667 #endif
6668
6669 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6670 {
6671         si_program_display_gap(rdev);
6672 }
6673
6674 union power_info {
6675         struct _ATOM_POWERPLAY_INFO info;
6676         struct _ATOM_POWERPLAY_INFO_V2 info_2;
6677         struct _ATOM_POWERPLAY_INFO_V3 info_3;
6678         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6679         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6680         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6681 };
6682
6683 union pplib_clock_info {
6684         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6685         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6686         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6687         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6688         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6689 };
6690
6691 union pplib_power_state {
6692         struct _ATOM_PPLIB_STATE v1;
6693         struct _ATOM_PPLIB_STATE_V2 v2;
6694 };
6695
6696 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6697                                           struct radeon_ps *rps,
6698                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6699                                           u8 table_rev)
6700 {
6701         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6702         rps->class = le16_to_cpu(non_clock_info->usClassification);
6703         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6704
6705         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6706                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6707                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6708         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6709                 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6710                 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6711         } else {
6712                 rps->vclk = 0;
6713                 rps->dclk = 0;
6714         }
6715
6716         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6717                 rdev->pm.dpm.boot_ps = rps;
6718         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6719                 rdev->pm.dpm.uvd_ps = rps;
6720 }
6721
6722 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6723                                       struct radeon_ps *rps, int index,
6724                                       union pplib_clock_info *clock_info)
6725 {
6726         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6727         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6728         struct si_power_info *si_pi = si_get_pi(rdev);
6729         struct ni_ps *ps = ni_get_ps(rps);
6730         u16 leakage_voltage;
6731         struct rv7xx_pl *pl = &ps->performance_levels[index];
6732         int ret;
6733
6734         ps->performance_level_count = index + 1;
6735
6736         pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6737         pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6738         pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6739         pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6740
6741         pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6742         pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6743         pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6744         pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6745                                                  si_pi->sys_pcie_mask,
6746                                                  si_pi->boot_pcie_gen,
6747                                                  clock_info->si.ucPCIEGen);
6748
6749         /* patch up vddc if necessary */
6750         ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6751                                                         &leakage_voltage);
6752         if (ret == 0)
6753                 pl->vddc = leakage_voltage;
6754
6755         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6756                 pi->acpi_vddc = pl->vddc;
6757                 eg_pi->acpi_vddci = pl->vddci;
6758                 si_pi->acpi_pcie_gen = pl->pcie_gen;
6759         }
6760
6761         if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6762             index == 0) {
6763                 /* XXX disable for A0 tahiti */
6764                 si_pi->ulv.supported = false;
6765                 si_pi->ulv.pl = *pl;
6766                 si_pi->ulv.one_pcie_lane_in_ulv = false;
6767                 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6768                 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6769                 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6770         }
6771
6772         if (pi->min_vddc_in_table > pl->vddc)
6773                 pi->min_vddc_in_table = pl->vddc;
6774
6775         if (pi->max_vddc_in_table < pl->vddc)
6776                 pi->max_vddc_in_table = pl->vddc;
6777
6778         /* patch up boot state */
6779         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6780                 u16 vddc, vddci, mvdd;
6781                 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6782                 pl->mclk = rdev->clock.default_mclk;
6783                 pl->sclk = rdev->clock.default_sclk;
6784                 pl->vddc = vddc;
6785                 pl->vddci = vddci;
6786                 si_pi->mvdd_bootup_value = mvdd;
6787         }
6788
6789         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6790             ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6791                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6792                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6793                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6794                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6795         }
6796 }
6797
6798 static int si_parse_power_table(struct radeon_device *rdev)
6799 {
6800         struct radeon_mode_info *mode_info = &rdev->mode_info;
6801         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6802         union pplib_power_state *power_state;
6803         int i, j, k, non_clock_array_index, clock_array_index;
6804         union pplib_clock_info *clock_info;
6805         struct _StateArray *state_array;
6806         struct _ClockInfoArray *clock_info_array;
6807         struct _NonClockInfoArray *non_clock_info_array;
6808         union power_info *power_info;
6809         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6810         u16 data_offset;
6811         u8 frev, crev;
6812         u8 *power_state_offset;
6813         struct ni_ps *ps;
6814
6815         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6816                                    &frev, &crev, &data_offset))
6817                 return -EINVAL;
6818         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6819
6820         state_array = (struct _StateArray *)
6821                 (mode_info->atom_context->bios + data_offset +
6822                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
6823         clock_info_array = (struct _ClockInfoArray *)
6824                 (mode_info->atom_context->bios + data_offset +
6825                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6826         non_clock_info_array = (struct _NonClockInfoArray *)
6827                 (mode_info->atom_context->bios + data_offset +
6828                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6829
6830         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6831                                   state_array->ucNumEntries, GFP_KERNEL);
6832         if (!rdev->pm.dpm.ps)
6833                 return -ENOMEM;
6834         power_state_offset = (u8 *)state_array->states;
6835         for (i = 0; i < state_array->ucNumEntries; i++) {
6836                 u8 *idx;
6837                 power_state = (union pplib_power_state *)power_state_offset;
6838                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6839                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6840                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
6841                 if (!rdev->pm.power_state[i].clock_info)
6842                         return -EINVAL;
6843                 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6844                 if (ps == NULL) {
6845                         kfree(rdev->pm.dpm.ps);
6846                         return -ENOMEM;
6847                 }
6848                 rdev->pm.dpm.ps[i].ps_priv = ps;
6849                 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6850                                               non_clock_info,
6851                                               non_clock_info_array->ucEntrySize);
6852                 k = 0;
6853                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6854                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6855                         clock_array_index = idx[j];
6856                         if (clock_array_index >= clock_info_array->ucNumEntries)
6857                                 continue;
6858                         if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6859                                 break;
6860                         clock_info = (union pplib_clock_info *)
6861                                 ((u8 *)&clock_info_array->clockInfo[0] +
6862                                  (clock_array_index * clock_info_array->ucEntrySize));
6863                         si_parse_pplib_clock_info(rdev,
6864                                                   &rdev->pm.dpm.ps[i], k,
6865                                                   clock_info);
6866                         k++;
6867                 }
6868                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6869         }
6870         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6871
6872         /* fill in the vce power states */
6873         for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
6874                 u32 sclk, mclk;
6875                 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
6876                 clock_info = (union pplib_clock_info *)
6877                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
6878                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6879                 sclk |= clock_info->si.ucEngineClockHigh << 16;
6880                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6881                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
6882                 rdev->pm.dpm.vce_states[i].sclk = sclk;
6883                 rdev->pm.dpm.vce_states[i].mclk = mclk;
6884         }
6885
6886         return 0;
6887 }
6888
6889 int si_dpm_init(struct radeon_device *rdev)
6890 {
6891         struct rv7xx_power_info *pi;
6892         struct evergreen_power_info *eg_pi;
6893         struct ni_power_info *ni_pi;
6894         struct si_power_info *si_pi;
6895         struct atom_clock_dividers dividers;
6896         int ret;
6897         u32 mask;
6898
6899         si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6900         if (si_pi == NULL)
6901                 return -ENOMEM;
6902         rdev->pm.dpm.priv = si_pi;
6903         ni_pi = &si_pi->ni;
6904         eg_pi = &ni_pi->eg;
6905         pi = &eg_pi->rv7xx;
6906
6907         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6908         if (ret)
6909                 si_pi->sys_pcie_mask = 0;
6910         else
6911                 si_pi->sys_pcie_mask = mask;
6912         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6913         si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6914
6915         si_set_max_cu_value(rdev);
6916
6917         rv770_get_max_vddc(rdev);
6918         si_get_leakage_vddc(rdev);
6919         si_patch_dependency_tables_based_on_leakage(rdev);
6920
6921         pi->acpi_vddc = 0;
6922         eg_pi->acpi_vddci = 0;
6923         pi->min_vddc_in_table = 0;
6924         pi->max_vddc_in_table = 0;
6925
6926         ret = r600_get_platform_caps(rdev);
6927         if (ret)
6928                 return ret;
6929
6930         ret = r600_parse_extended_power_table(rdev);
6931         if (ret)
6932                 return ret;
6933
6934         ret = si_parse_power_table(rdev);
6935         if (ret)
6936                 return ret;
6937
6938         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6939                 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6940         if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6941                 r600_free_extended_power_table(rdev);
6942                 return -ENOMEM;
6943         }
6944         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6945         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6946         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6947         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6948         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6949         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6950         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6951         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6952         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6953
6954         if (rdev->pm.dpm.voltage_response_time == 0)
6955                 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6956         if (rdev->pm.dpm.backbias_response_time == 0)
6957                 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6958
6959         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6960                                              0, false, &dividers);
6961         if (ret)
6962                 pi->ref_div = dividers.ref_div + 1;
6963         else
6964                 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6965
6966         eg_pi->smu_uvd_hs = false;
6967
6968         pi->mclk_strobe_mode_threshold = 40000;
6969         if (si_is_special_1gb_platform(rdev))
6970                 pi->mclk_stutter_mode_threshold = 0;
6971         else
6972                 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6973         pi->mclk_edc_enable_threshold = 40000;
6974         eg_pi->mclk_edc_wr_enable_threshold = 40000;
6975
6976         ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6977
6978         pi->voltage_control =
6979                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6980                                             VOLTAGE_OBJ_GPIO_LUT);
6981         if (!pi->voltage_control) {
6982                 si_pi->voltage_control_svi2 =
6983                         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6984                                                     VOLTAGE_OBJ_SVID2);
6985                 if (si_pi->voltage_control_svi2)
6986                         radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6987                                                   &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
6988         }
6989
6990         pi->mvdd_control =
6991                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
6992                                             VOLTAGE_OBJ_GPIO_LUT);
6993
6994         eg_pi->vddci_control =
6995                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
6996                                             VOLTAGE_OBJ_GPIO_LUT);
6997         if (!eg_pi->vddci_control)
6998                 si_pi->vddci_control_svi2 =
6999                         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7000                                                     VOLTAGE_OBJ_SVID2);
7001
7002         si_pi->vddc_phase_shed_control =
7003                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7004                                             VOLTAGE_OBJ_PHASE_LUT);
7005
7006         rv770_get_engine_memory_ss(rdev);
7007
7008         pi->asi = RV770_ASI_DFLT;
7009         pi->pasi = CYPRESS_HASI_DFLT;
7010         pi->vrc = SISLANDS_VRC_DFLT;
7011
7012         pi->gfx_clock_gating = true;
7013
7014         eg_pi->sclk_deep_sleep = true;
7015         si_pi->sclk_deep_sleep_above_low = false;
7016
7017         if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7018                 pi->thermal_protection = true;
7019         else
7020                 pi->thermal_protection = false;
7021
7022         eg_pi->dynamic_ac_timing = true;
7023
7024         eg_pi->light_sleep = true;
7025 #if defined(CONFIG_ACPI)
7026         eg_pi->pcie_performance_request =
7027                 radeon_acpi_is_pcie_performance_request_supported(rdev);
7028 #else
7029         eg_pi->pcie_performance_request = false;
7030 #endif
7031
7032         si_pi->sram_end = SMC_RAM_END;
7033
7034         rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7035         rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7036         rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7037         rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7038         rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7039         rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7040         rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7041
7042         si_initialize_powertune_defaults(rdev);
7043
7044         /* make sure dc limits are valid */
7045         if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7046             (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7047                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7048                         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7049
7050         si_pi->fan_ctrl_is_in_default_mode = true;
7051
7052         return 0;
7053 }
7054
7055 void si_dpm_fini(struct radeon_device *rdev)
7056 {
7057         int i;
7058
7059         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
7060                 kfree(rdev->pm.dpm.ps[i].ps_priv);
7061         }
7062         kfree(rdev->pm.dpm.ps);
7063         kfree(rdev->pm.dpm.priv);
7064         kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7065         r600_free_extended_power_table(rdev);
7066 }
7067
7068 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
7069                                                     struct seq_file *m)
7070 {
7071         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7072         struct radeon_ps *rps = &eg_pi->current_rps;
7073         struct ni_ps *ps = ni_get_ps(rps);
7074         struct rv7xx_pl *pl;
7075         u32 current_index =
7076                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7077                 CURRENT_STATE_INDEX_SHIFT;
7078
7079         if (current_index >= ps->performance_level_count) {
7080                 seq_printf(m, "invalid dpm profile %d\n", current_index);
7081         } else {
7082                 pl = &ps->performance_levels[current_index];
7083                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7084                 seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7085                            current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7086         }
7087 }
7088
7089 u32 si_dpm_get_current_sclk(struct radeon_device *rdev)
7090 {
7091         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7092         struct radeon_ps *rps = &eg_pi->current_rps;
7093         struct ni_ps *ps = ni_get_ps(rps);
7094         struct rv7xx_pl *pl;
7095         u32 current_index =
7096                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7097                 CURRENT_STATE_INDEX_SHIFT;
7098
7099         if (current_index >= ps->performance_level_count) {
7100                 return 0;
7101         } else {
7102                 pl = &ps->performance_levels[current_index];
7103                 return pl->sclk;
7104         }
7105 }
7106
7107 u32 si_dpm_get_current_mclk(struct radeon_device *rdev)
7108 {
7109         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7110         struct radeon_ps *rps = &eg_pi->current_rps;
7111         struct ni_ps *ps = ni_get_ps(rps);
7112         struct rv7xx_pl *pl;
7113         u32 current_index =
7114                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7115                 CURRENT_STATE_INDEX_SHIFT;
7116
7117         if (current_index >= ps->performance_level_count) {
7118                 return 0;
7119         } else {
7120                 pl = &ps->performance_levels[current_index];
7121                 return pl->mclk;
7122         }
7123 }