2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
29 #include "radeon_asic.h"
30 #include "radeon_audio.h"
31 #include <drm/radeon_drm.h>
34 #include "si_blit_shaders.h"
35 #include "clearstate_si.h"
36 #include "radeon_ucode.h"
39 MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
40 MODULE_FIRMWARE("radeon/TAHITI_me.bin");
41 MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
42 MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
43 MODULE_FIRMWARE("radeon/TAHITI_mc2.bin");
44 MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
45 MODULE_FIRMWARE("radeon/TAHITI_smc.bin");
47 MODULE_FIRMWARE("radeon/tahiti_pfp.bin");
48 MODULE_FIRMWARE("radeon/tahiti_me.bin");
49 MODULE_FIRMWARE("radeon/tahiti_ce.bin");
50 MODULE_FIRMWARE("radeon/tahiti_mc.bin");
51 MODULE_FIRMWARE("radeon/tahiti_rlc.bin");
52 MODULE_FIRMWARE("radeon/tahiti_smc.bin");
54 MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
55 MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
56 MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
57 MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
58 MODULE_FIRMWARE("radeon/PITCAIRN_mc2.bin");
59 MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
60 MODULE_FIRMWARE("radeon/PITCAIRN_smc.bin");
62 MODULE_FIRMWARE("radeon/pitcairn_pfp.bin");
63 MODULE_FIRMWARE("radeon/pitcairn_me.bin");
64 MODULE_FIRMWARE("radeon/pitcairn_ce.bin");
65 MODULE_FIRMWARE("radeon/pitcairn_mc.bin");
66 MODULE_FIRMWARE("radeon/pitcairn_rlc.bin");
67 MODULE_FIRMWARE("radeon/pitcairn_smc.bin");
68 MODULE_FIRMWARE("radeon/pitcairn_k_smc.bin");
70 MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
71 MODULE_FIRMWARE("radeon/VERDE_me.bin");
72 MODULE_FIRMWARE("radeon/VERDE_ce.bin");
73 MODULE_FIRMWARE("radeon/VERDE_mc.bin");
74 MODULE_FIRMWARE("radeon/VERDE_mc2.bin");
75 MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
76 MODULE_FIRMWARE("radeon/VERDE_smc.bin");
78 MODULE_FIRMWARE("radeon/verde_pfp.bin");
79 MODULE_FIRMWARE("radeon/verde_me.bin");
80 MODULE_FIRMWARE("radeon/verde_ce.bin");
81 MODULE_FIRMWARE("radeon/verde_mc.bin");
82 MODULE_FIRMWARE("radeon/verde_rlc.bin");
83 MODULE_FIRMWARE("radeon/verde_smc.bin");
84 MODULE_FIRMWARE("radeon/verde_k_smc.bin");
86 MODULE_FIRMWARE("radeon/OLAND_pfp.bin");
87 MODULE_FIRMWARE("radeon/OLAND_me.bin");
88 MODULE_FIRMWARE("radeon/OLAND_ce.bin");
89 MODULE_FIRMWARE("radeon/OLAND_mc.bin");
90 MODULE_FIRMWARE("radeon/OLAND_mc2.bin");
91 MODULE_FIRMWARE("radeon/OLAND_rlc.bin");
92 MODULE_FIRMWARE("radeon/OLAND_smc.bin");
94 MODULE_FIRMWARE("radeon/oland_pfp.bin");
95 MODULE_FIRMWARE("radeon/oland_me.bin");
96 MODULE_FIRMWARE("radeon/oland_ce.bin");
97 MODULE_FIRMWARE("radeon/oland_mc.bin");
98 MODULE_FIRMWARE("radeon/oland_rlc.bin");
99 MODULE_FIRMWARE("radeon/oland_smc.bin");
100 MODULE_FIRMWARE("radeon/oland_k_smc.bin");
102 MODULE_FIRMWARE("radeon/HAINAN_pfp.bin");
103 MODULE_FIRMWARE("radeon/HAINAN_me.bin");
104 MODULE_FIRMWARE("radeon/HAINAN_ce.bin");
105 MODULE_FIRMWARE("radeon/HAINAN_mc.bin");
106 MODULE_FIRMWARE("radeon/HAINAN_mc2.bin");
107 MODULE_FIRMWARE("radeon/HAINAN_rlc.bin");
108 MODULE_FIRMWARE("radeon/HAINAN_smc.bin");
110 MODULE_FIRMWARE("radeon/hainan_pfp.bin");
111 MODULE_FIRMWARE("radeon/hainan_me.bin");
112 MODULE_FIRMWARE("radeon/hainan_ce.bin");
113 MODULE_FIRMWARE("radeon/hainan_mc.bin");
114 MODULE_FIRMWARE("radeon/hainan_rlc.bin");
115 MODULE_FIRMWARE("radeon/hainan_smc.bin");
116 MODULE_FIRMWARE("radeon/hainan_k_smc.bin");
117 MODULE_FIRMWARE("radeon/banks_k_2_smc.bin");
119 MODULE_FIRMWARE("radeon/si58_mc.bin");
121 static u32 si_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh);
122 static void si_pcie_gen3_enable(struct radeon_device *rdev);
123 static void si_program_aspm(struct radeon_device *rdev);
124 extern void sumo_rlc_fini(struct radeon_device *rdev);
125 extern int sumo_rlc_init(struct radeon_device *rdev);
126 extern int r600_ih_ring_alloc(struct radeon_device *rdev);
127 extern void r600_ih_ring_fini(struct radeon_device *rdev);
128 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
129 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
130 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
131 extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
132 extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
133 extern bool evergreen_is_display_hung(struct radeon_device *rdev);
134 static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
136 static void si_init_pg(struct radeon_device *rdev);
137 static void si_init_cg(struct radeon_device *rdev);
138 static void si_fini_pg(struct radeon_device *rdev);
139 static void si_fini_cg(struct radeon_device *rdev);
140 static void si_rlc_stop(struct radeon_device *rdev);
142 static const u32 verde_rlc_save_restore_register_list[] =
144 (0x8000 << 16) | (0x98f4 >> 2),
146 (0x8040 << 16) | (0x98f4 >> 2),
148 (0x8000 << 16) | (0xe80 >> 2),
150 (0x8040 << 16) | (0xe80 >> 2),
152 (0x8000 << 16) | (0x89bc >> 2),
154 (0x8040 << 16) | (0x89bc >> 2),
156 (0x8000 << 16) | (0x8c1c >> 2),
158 (0x8040 << 16) | (0x8c1c >> 2),
160 (0x9c00 << 16) | (0x98f0 >> 2),
162 (0x9c00 << 16) | (0xe7c >> 2),
164 (0x8000 << 16) | (0x9148 >> 2),
166 (0x8040 << 16) | (0x9148 >> 2),
168 (0x9c00 << 16) | (0x9150 >> 2),
170 (0x9c00 << 16) | (0x897c >> 2),
172 (0x9c00 << 16) | (0x8d8c >> 2),
174 (0x9c00 << 16) | (0xac54 >> 2),
177 (0x9c00 << 16) | (0x98f8 >> 2),
179 (0x9c00 << 16) | (0x9910 >> 2),
181 (0x9c00 << 16) | (0x9914 >> 2),
183 (0x9c00 << 16) | (0x9918 >> 2),
185 (0x9c00 << 16) | (0x991c >> 2),
187 (0x9c00 << 16) | (0x9920 >> 2),
189 (0x9c00 << 16) | (0x9924 >> 2),
191 (0x9c00 << 16) | (0x9928 >> 2),
193 (0x9c00 << 16) | (0x992c >> 2),
195 (0x9c00 << 16) | (0x9930 >> 2),
197 (0x9c00 << 16) | (0x9934 >> 2),
199 (0x9c00 << 16) | (0x9938 >> 2),
201 (0x9c00 << 16) | (0x993c >> 2),
203 (0x9c00 << 16) | (0x9940 >> 2),
205 (0x9c00 << 16) | (0x9944 >> 2),
207 (0x9c00 << 16) | (0x9948 >> 2),
209 (0x9c00 << 16) | (0x994c >> 2),
211 (0x9c00 << 16) | (0x9950 >> 2),
213 (0x9c00 << 16) | (0x9954 >> 2),
215 (0x9c00 << 16) | (0x9958 >> 2),
217 (0x9c00 << 16) | (0x995c >> 2),
219 (0x9c00 << 16) | (0x9960 >> 2),
221 (0x9c00 << 16) | (0x9964 >> 2),
223 (0x9c00 << 16) | (0x9968 >> 2),
225 (0x9c00 << 16) | (0x996c >> 2),
227 (0x9c00 << 16) | (0x9970 >> 2),
229 (0x9c00 << 16) | (0x9974 >> 2),
231 (0x9c00 << 16) | (0x9978 >> 2),
233 (0x9c00 << 16) | (0x997c >> 2),
235 (0x9c00 << 16) | (0x9980 >> 2),
237 (0x9c00 << 16) | (0x9984 >> 2),
239 (0x9c00 << 16) | (0x9988 >> 2),
241 (0x9c00 << 16) | (0x998c >> 2),
243 (0x9c00 << 16) | (0x8c00 >> 2),
245 (0x9c00 << 16) | (0x8c14 >> 2),
247 (0x9c00 << 16) | (0x8c04 >> 2),
249 (0x9c00 << 16) | (0x8c08 >> 2),
251 (0x8000 << 16) | (0x9b7c >> 2),
253 (0x8040 << 16) | (0x9b7c >> 2),
255 (0x8000 << 16) | (0xe84 >> 2),
257 (0x8040 << 16) | (0xe84 >> 2),
259 (0x8000 << 16) | (0x89c0 >> 2),
261 (0x8040 << 16) | (0x89c0 >> 2),
263 (0x8000 << 16) | (0x914c >> 2),
265 (0x8040 << 16) | (0x914c >> 2),
267 (0x8000 << 16) | (0x8c20 >> 2),
269 (0x8040 << 16) | (0x8c20 >> 2),
271 (0x8000 << 16) | (0x9354 >> 2),
273 (0x8040 << 16) | (0x9354 >> 2),
275 (0x9c00 << 16) | (0x9060 >> 2),
277 (0x9c00 << 16) | (0x9364 >> 2),
279 (0x9c00 << 16) | (0x9100 >> 2),
281 (0x9c00 << 16) | (0x913c >> 2),
283 (0x8000 << 16) | (0x90e0 >> 2),
285 (0x8000 << 16) | (0x90e4 >> 2),
287 (0x8000 << 16) | (0x90e8 >> 2),
289 (0x8040 << 16) | (0x90e0 >> 2),
291 (0x8040 << 16) | (0x90e4 >> 2),
293 (0x8040 << 16) | (0x90e8 >> 2),
295 (0x9c00 << 16) | (0x8bcc >> 2),
297 (0x9c00 << 16) | (0x8b24 >> 2),
299 (0x9c00 << 16) | (0x88c4 >> 2),
301 (0x9c00 << 16) | (0x8e50 >> 2),
303 (0x9c00 << 16) | (0x8c0c >> 2),
305 (0x9c00 << 16) | (0x8e58 >> 2),
307 (0x9c00 << 16) | (0x8e5c >> 2),
309 (0x9c00 << 16) | (0x9508 >> 2),
311 (0x9c00 << 16) | (0x950c >> 2),
313 (0x9c00 << 16) | (0x9494 >> 2),
315 (0x9c00 << 16) | (0xac0c >> 2),
317 (0x9c00 << 16) | (0xac10 >> 2),
319 (0x9c00 << 16) | (0xac14 >> 2),
321 (0x9c00 << 16) | (0xae00 >> 2),
323 (0x9c00 << 16) | (0xac08 >> 2),
325 (0x9c00 << 16) | (0x88d4 >> 2),
327 (0x9c00 << 16) | (0x88c8 >> 2),
329 (0x9c00 << 16) | (0x88cc >> 2),
331 (0x9c00 << 16) | (0x89b0 >> 2),
333 (0x9c00 << 16) | (0x8b10 >> 2),
335 (0x9c00 << 16) | (0x8a14 >> 2),
337 (0x9c00 << 16) | (0x9830 >> 2),
339 (0x9c00 << 16) | (0x9834 >> 2),
341 (0x9c00 << 16) | (0x9838 >> 2),
343 (0x9c00 << 16) | (0x9a10 >> 2),
345 (0x8000 << 16) | (0x9870 >> 2),
347 (0x8000 << 16) | (0x9874 >> 2),
349 (0x8001 << 16) | (0x9870 >> 2),
351 (0x8001 << 16) | (0x9874 >> 2),
353 (0x8040 << 16) | (0x9870 >> 2),
355 (0x8040 << 16) | (0x9874 >> 2),
357 (0x8041 << 16) | (0x9870 >> 2),
359 (0x8041 << 16) | (0x9874 >> 2),
364 static const u32 tahiti_golden_rlc_registers[] =
366 0xc424, 0xffffffff, 0x00601005,
367 0xc47c, 0xffffffff, 0x10104040,
368 0xc488, 0xffffffff, 0x0100000a,
369 0xc314, 0xffffffff, 0x00000800,
370 0xc30c, 0xffffffff, 0x800000f4,
371 0xf4a8, 0xffffffff, 0x00000000
374 static const u32 tahiti_golden_registers[] =
376 0x9a10, 0x00010000, 0x00018208,
377 0x9830, 0xffffffff, 0x00000000,
378 0x9834, 0xf00fffff, 0x00000400,
379 0x9838, 0x0002021c, 0x00020200,
380 0xc78, 0x00000080, 0x00000000,
381 0xd030, 0x000300c0, 0x00800040,
382 0xd830, 0x000300c0, 0x00800040,
383 0x5bb0, 0x000000f0, 0x00000070,
384 0x5bc0, 0x00200000, 0x50100000,
385 0x7030, 0x31000311, 0x00000011,
386 0x277c, 0x00000003, 0x000007ff,
387 0x240c, 0x000007ff, 0x00000000,
388 0x8a14, 0xf000001f, 0x00000007,
389 0x8b24, 0xffffffff, 0x00ffffff,
390 0x8b10, 0x0000ff0f, 0x00000000,
391 0x28a4c, 0x07ffffff, 0x4e000000,
392 0x28350, 0x3f3f3fff, 0x2a00126a,
393 0x30, 0x000000ff, 0x0040,
394 0x34, 0x00000040, 0x00004040,
395 0x9100, 0x07ffffff, 0x03000000,
396 0x8e88, 0x01ff1f3f, 0x00000000,
397 0x8e84, 0x01ff1f3f, 0x00000000,
398 0x9060, 0x0000007f, 0x00000020,
399 0x9508, 0x00010000, 0x00010000,
400 0xac14, 0x00000200, 0x000002fb,
401 0xac10, 0xffffffff, 0x0000543b,
402 0xac0c, 0xffffffff, 0xa9210876,
403 0x88d0, 0xffffffff, 0x000fff40,
404 0x88d4, 0x0000001f, 0x00000010,
405 0x1410, 0x20000000, 0x20fffed8,
406 0x15c0, 0x000c0fc0, 0x000c0400
409 static const u32 tahiti_golden_registers2[] =
411 0xc64, 0x00000001, 0x00000001
414 static const u32 pitcairn_golden_rlc_registers[] =
416 0xc424, 0xffffffff, 0x00601004,
417 0xc47c, 0xffffffff, 0x10102020,
418 0xc488, 0xffffffff, 0x01000020,
419 0xc314, 0xffffffff, 0x00000800,
420 0xc30c, 0xffffffff, 0x800000a4
423 static const u32 pitcairn_golden_registers[] =
425 0x9a10, 0x00010000, 0x00018208,
426 0x9830, 0xffffffff, 0x00000000,
427 0x9834, 0xf00fffff, 0x00000400,
428 0x9838, 0x0002021c, 0x00020200,
429 0xc78, 0x00000080, 0x00000000,
430 0xd030, 0x000300c0, 0x00800040,
431 0xd830, 0x000300c0, 0x00800040,
432 0x5bb0, 0x000000f0, 0x00000070,
433 0x5bc0, 0x00200000, 0x50100000,
434 0x7030, 0x31000311, 0x00000011,
435 0x2ae4, 0x00073ffe, 0x000022a2,
436 0x240c, 0x000007ff, 0x00000000,
437 0x8a14, 0xf000001f, 0x00000007,
438 0x8b24, 0xffffffff, 0x00ffffff,
439 0x8b10, 0x0000ff0f, 0x00000000,
440 0x28a4c, 0x07ffffff, 0x4e000000,
441 0x28350, 0x3f3f3fff, 0x2a00126a,
442 0x30, 0x000000ff, 0x0040,
443 0x34, 0x00000040, 0x00004040,
444 0x9100, 0x07ffffff, 0x03000000,
445 0x9060, 0x0000007f, 0x00000020,
446 0x9508, 0x00010000, 0x00010000,
447 0xac14, 0x000003ff, 0x000000f7,
448 0xac10, 0xffffffff, 0x00000000,
449 0xac0c, 0xffffffff, 0x32761054,
450 0x88d4, 0x0000001f, 0x00000010,
451 0x15c0, 0x000c0fc0, 0x000c0400
454 static const u32 verde_golden_rlc_registers[] =
456 0xc424, 0xffffffff, 0x033f1005,
457 0xc47c, 0xffffffff, 0x10808020,
458 0xc488, 0xffffffff, 0x00800008,
459 0xc314, 0xffffffff, 0x00001000,
460 0xc30c, 0xffffffff, 0x80010014
463 static const u32 verde_golden_registers[] =
465 0x9a10, 0x00010000, 0x00018208,
466 0x9830, 0xffffffff, 0x00000000,
467 0x9834, 0xf00fffff, 0x00000400,
468 0x9838, 0x0002021c, 0x00020200,
469 0xc78, 0x00000080, 0x00000000,
470 0xd030, 0x000300c0, 0x00800040,
471 0xd030, 0x000300c0, 0x00800040,
472 0xd830, 0x000300c0, 0x00800040,
473 0xd830, 0x000300c0, 0x00800040,
474 0x5bb0, 0x000000f0, 0x00000070,
475 0x5bc0, 0x00200000, 0x50100000,
476 0x7030, 0x31000311, 0x00000011,
477 0x2ae4, 0x00073ffe, 0x000022a2,
478 0x2ae4, 0x00073ffe, 0x000022a2,
479 0x2ae4, 0x00073ffe, 0x000022a2,
480 0x240c, 0x000007ff, 0x00000000,
481 0x240c, 0x000007ff, 0x00000000,
482 0x240c, 0x000007ff, 0x00000000,
483 0x8a14, 0xf000001f, 0x00000007,
484 0x8a14, 0xf000001f, 0x00000007,
485 0x8a14, 0xf000001f, 0x00000007,
486 0x8b24, 0xffffffff, 0x00ffffff,
487 0x8b10, 0x0000ff0f, 0x00000000,
488 0x28a4c, 0x07ffffff, 0x4e000000,
489 0x28350, 0x3f3f3fff, 0x0000124a,
490 0x28350, 0x3f3f3fff, 0x0000124a,
491 0x28350, 0x3f3f3fff, 0x0000124a,
492 0x30, 0x000000ff, 0x0040,
493 0x34, 0x00000040, 0x00004040,
494 0x9100, 0x07ffffff, 0x03000000,
495 0x9100, 0x07ffffff, 0x03000000,
496 0x8e88, 0x01ff1f3f, 0x00000000,
497 0x8e88, 0x01ff1f3f, 0x00000000,
498 0x8e88, 0x01ff1f3f, 0x00000000,
499 0x8e84, 0x01ff1f3f, 0x00000000,
500 0x8e84, 0x01ff1f3f, 0x00000000,
501 0x8e84, 0x01ff1f3f, 0x00000000,
502 0x9060, 0x0000007f, 0x00000020,
503 0x9508, 0x00010000, 0x00010000,
504 0xac14, 0x000003ff, 0x00000003,
505 0xac14, 0x000003ff, 0x00000003,
506 0xac14, 0x000003ff, 0x00000003,
507 0xac10, 0xffffffff, 0x00000000,
508 0xac10, 0xffffffff, 0x00000000,
509 0xac10, 0xffffffff, 0x00000000,
510 0xac0c, 0xffffffff, 0x00001032,
511 0xac0c, 0xffffffff, 0x00001032,
512 0xac0c, 0xffffffff, 0x00001032,
513 0x88d4, 0x0000001f, 0x00000010,
514 0x88d4, 0x0000001f, 0x00000010,
515 0x88d4, 0x0000001f, 0x00000010,
516 0x15c0, 0x000c0fc0, 0x000c0400
519 static const u32 oland_golden_rlc_registers[] =
521 0xc424, 0xffffffff, 0x00601005,
522 0xc47c, 0xffffffff, 0x10104040,
523 0xc488, 0xffffffff, 0x0100000a,
524 0xc314, 0xffffffff, 0x00000800,
525 0xc30c, 0xffffffff, 0x800000f4
528 static const u32 oland_golden_registers[] =
530 0x9a10, 0x00010000, 0x00018208,
531 0x9830, 0xffffffff, 0x00000000,
532 0x9834, 0xf00fffff, 0x00000400,
533 0x9838, 0x0002021c, 0x00020200,
534 0xc78, 0x00000080, 0x00000000,
535 0xd030, 0x000300c0, 0x00800040,
536 0xd830, 0x000300c0, 0x00800040,
537 0x5bb0, 0x000000f0, 0x00000070,
538 0x5bc0, 0x00200000, 0x50100000,
539 0x7030, 0x31000311, 0x00000011,
540 0x2ae4, 0x00073ffe, 0x000022a2,
541 0x240c, 0x000007ff, 0x00000000,
542 0x8a14, 0xf000001f, 0x00000007,
543 0x8b24, 0xffffffff, 0x00ffffff,
544 0x8b10, 0x0000ff0f, 0x00000000,
545 0x28a4c, 0x07ffffff, 0x4e000000,
546 0x28350, 0x3f3f3fff, 0x00000082,
547 0x30, 0x000000ff, 0x0040,
548 0x34, 0x00000040, 0x00004040,
549 0x9100, 0x07ffffff, 0x03000000,
550 0x9060, 0x0000007f, 0x00000020,
551 0x9508, 0x00010000, 0x00010000,
552 0xac14, 0x000003ff, 0x000000f3,
553 0xac10, 0xffffffff, 0x00000000,
554 0xac0c, 0xffffffff, 0x00003210,
555 0x88d4, 0x0000001f, 0x00000010,
556 0x15c0, 0x000c0fc0, 0x000c0400
559 static const u32 hainan_golden_registers[] =
561 0x9a10, 0x00010000, 0x00018208,
562 0x9830, 0xffffffff, 0x00000000,
563 0x9834, 0xf00fffff, 0x00000400,
564 0x9838, 0x0002021c, 0x00020200,
565 0xd0c0, 0xff000fff, 0x00000100,
566 0xd030, 0x000300c0, 0x00800040,
567 0xd8c0, 0xff000fff, 0x00000100,
568 0xd830, 0x000300c0, 0x00800040,
569 0x2ae4, 0x00073ffe, 0x000022a2,
570 0x240c, 0x000007ff, 0x00000000,
571 0x8a14, 0xf000001f, 0x00000007,
572 0x8b24, 0xffffffff, 0x00ffffff,
573 0x8b10, 0x0000ff0f, 0x00000000,
574 0x28a4c, 0x07ffffff, 0x4e000000,
575 0x28350, 0x3f3f3fff, 0x00000000,
576 0x30, 0x000000ff, 0x0040,
577 0x34, 0x00000040, 0x00004040,
578 0x9100, 0x03e00000, 0x03600000,
579 0x9060, 0x0000007f, 0x00000020,
580 0x9508, 0x00010000, 0x00010000,
581 0xac14, 0x000003ff, 0x000000f1,
582 0xac10, 0xffffffff, 0x00000000,
583 0xac0c, 0xffffffff, 0x00003210,
584 0x88d4, 0x0000001f, 0x00000010,
585 0x15c0, 0x000c0fc0, 0x000c0400
588 static const u32 hainan_golden_registers2[] =
590 0x98f8, 0xffffffff, 0x02010001
593 static const u32 tahiti_mgcg_cgcg_init[] =
595 0xc400, 0xffffffff, 0xfffffffc,
596 0x802c, 0xffffffff, 0xe0000000,
597 0x9a60, 0xffffffff, 0x00000100,
598 0x92a4, 0xffffffff, 0x00000100,
599 0xc164, 0xffffffff, 0x00000100,
600 0x9774, 0xffffffff, 0x00000100,
601 0x8984, 0xffffffff, 0x06000100,
602 0x8a18, 0xffffffff, 0x00000100,
603 0x92a0, 0xffffffff, 0x00000100,
604 0xc380, 0xffffffff, 0x00000100,
605 0x8b28, 0xffffffff, 0x00000100,
606 0x9144, 0xffffffff, 0x00000100,
607 0x8d88, 0xffffffff, 0x00000100,
608 0x8d8c, 0xffffffff, 0x00000100,
609 0x9030, 0xffffffff, 0x00000100,
610 0x9034, 0xffffffff, 0x00000100,
611 0x9038, 0xffffffff, 0x00000100,
612 0x903c, 0xffffffff, 0x00000100,
613 0xad80, 0xffffffff, 0x00000100,
614 0xac54, 0xffffffff, 0x00000100,
615 0x897c, 0xffffffff, 0x06000100,
616 0x9868, 0xffffffff, 0x00000100,
617 0x9510, 0xffffffff, 0x00000100,
618 0xaf04, 0xffffffff, 0x00000100,
619 0xae04, 0xffffffff, 0x00000100,
620 0x949c, 0xffffffff, 0x00000100,
621 0x802c, 0xffffffff, 0xe0000000,
622 0x9160, 0xffffffff, 0x00010000,
623 0x9164, 0xffffffff, 0x00030002,
624 0x9168, 0xffffffff, 0x00040007,
625 0x916c, 0xffffffff, 0x00060005,
626 0x9170, 0xffffffff, 0x00090008,
627 0x9174, 0xffffffff, 0x00020001,
628 0x9178, 0xffffffff, 0x00040003,
629 0x917c, 0xffffffff, 0x00000007,
630 0x9180, 0xffffffff, 0x00060005,
631 0x9184, 0xffffffff, 0x00090008,
632 0x9188, 0xffffffff, 0x00030002,
633 0x918c, 0xffffffff, 0x00050004,
634 0x9190, 0xffffffff, 0x00000008,
635 0x9194, 0xffffffff, 0x00070006,
636 0x9198, 0xffffffff, 0x000a0009,
637 0x919c, 0xffffffff, 0x00040003,
638 0x91a0, 0xffffffff, 0x00060005,
639 0x91a4, 0xffffffff, 0x00000009,
640 0x91a8, 0xffffffff, 0x00080007,
641 0x91ac, 0xffffffff, 0x000b000a,
642 0x91b0, 0xffffffff, 0x00050004,
643 0x91b4, 0xffffffff, 0x00070006,
644 0x91b8, 0xffffffff, 0x0008000b,
645 0x91bc, 0xffffffff, 0x000a0009,
646 0x91c0, 0xffffffff, 0x000d000c,
647 0x91c4, 0xffffffff, 0x00060005,
648 0x91c8, 0xffffffff, 0x00080007,
649 0x91cc, 0xffffffff, 0x0000000b,
650 0x91d0, 0xffffffff, 0x000a0009,
651 0x91d4, 0xffffffff, 0x000d000c,
652 0x91d8, 0xffffffff, 0x00070006,
653 0x91dc, 0xffffffff, 0x00090008,
654 0x91e0, 0xffffffff, 0x0000000c,
655 0x91e4, 0xffffffff, 0x000b000a,
656 0x91e8, 0xffffffff, 0x000e000d,
657 0x91ec, 0xffffffff, 0x00080007,
658 0x91f0, 0xffffffff, 0x000a0009,
659 0x91f4, 0xffffffff, 0x0000000d,
660 0x91f8, 0xffffffff, 0x000c000b,
661 0x91fc, 0xffffffff, 0x000f000e,
662 0x9200, 0xffffffff, 0x00090008,
663 0x9204, 0xffffffff, 0x000b000a,
664 0x9208, 0xffffffff, 0x000c000f,
665 0x920c, 0xffffffff, 0x000e000d,
666 0x9210, 0xffffffff, 0x00110010,
667 0x9214, 0xffffffff, 0x000a0009,
668 0x9218, 0xffffffff, 0x000c000b,
669 0x921c, 0xffffffff, 0x0000000f,
670 0x9220, 0xffffffff, 0x000e000d,
671 0x9224, 0xffffffff, 0x00110010,
672 0x9228, 0xffffffff, 0x000b000a,
673 0x922c, 0xffffffff, 0x000d000c,
674 0x9230, 0xffffffff, 0x00000010,
675 0x9234, 0xffffffff, 0x000f000e,
676 0x9238, 0xffffffff, 0x00120011,
677 0x923c, 0xffffffff, 0x000c000b,
678 0x9240, 0xffffffff, 0x000e000d,
679 0x9244, 0xffffffff, 0x00000011,
680 0x9248, 0xffffffff, 0x0010000f,
681 0x924c, 0xffffffff, 0x00130012,
682 0x9250, 0xffffffff, 0x000d000c,
683 0x9254, 0xffffffff, 0x000f000e,
684 0x9258, 0xffffffff, 0x00100013,
685 0x925c, 0xffffffff, 0x00120011,
686 0x9260, 0xffffffff, 0x00150014,
687 0x9264, 0xffffffff, 0x000e000d,
688 0x9268, 0xffffffff, 0x0010000f,
689 0x926c, 0xffffffff, 0x00000013,
690 0x9270, 0xffffffff, 0x00120011,
691 0x9274, 0xffffffff, 0x00150014,
692 0x9278, 0xffffffff, 0x000f000e,
693 0x927c, 0xffffffff, 0x00110010,
694 0x9280, 0xffffffff, 0x00000014,
695 0x9284, 0xffffffff, 0x00130012,
696 0x9288, 0xffffffff, 0x00160015,
697 0x928c, 0xffffffff, 0x0010000f,
698 0x9290, 0xffffffff, 0x00120011,
699 0x9294, 0xffffffff, 0x00000015,
700 0x9298, 0xffffffff, 0x00140013,
701 0x929c, 0xffffffff, 0x00170016,
702 0x9150, 0xffffffff, 0x96940200,
703 0x8708, 0xffffffff, 0x00900100,
704 0xc478, 0xffffffff, 0x00000080,
705 0xc404, 0xffffffff, 0x0020003f,
706 0x30, 0xffffffff, 0x0000001c,
707 0x34, 0x000f0000, 0x000f0000,
708 0x160c, 0xffffffff, 0x00000100,
709 0x1024, 0xffffffff, 0x00000100,
710 0x102c, 0x00000101, 0x00000000,
711 0x20a8, 0xffffffff, 0x00000104,
712 0x264c, 0x000c0000, 0x000c0000,
713 0x2648, 0x000c0000, 0x000c0000,
714 0x55e4, 0xff000fff, 0x00000100,
715 0x55e8, 0x00000001, 0x00000001,
716 0x2f50, 0x00000001, 0x00000001,
717 0x30cc, 0xc0000fff, 0x00000104,
718 0xc1e4, 0x00000001, 0x00000001,
719 0xd0c0, 0xfffffff0, 0x00000100,
720 0xd8c0, 0xfffffff0, 0x00000100
723 static const u32 pitcairn_mgcg_cgcg_init[] =
725 0xc400, 0xffffffff, 0xfffffffc,
726 0x802c, 0xffffffff, 0xe0000000,
727 0x9a60, 0xffffffff, 0x00000100,
728 0x92a4, 0xffffffff, 0x00000100,
729 0xc164, 0xffffffff, 0x00000100,
730 0x9774, 0xffffffff, 0x00000100,
731 0x8984, 0xffffffff, 0x06000100,
732 0x8a18, 0xffffffff, 0x00000100,
733 0x92a0, 0xffffffff, 0x00000100,
734 0xc380, 0xffffffff, 0x00000100,
735 0x8b28, 0xffffffff, 0x00000100,
736 0x9144, 0xffffffff, 0x00000100,
737 0x8d88, 0xffffffff, 0x00000100,
738 0x8d8c, 0xffffffff, 0x00000100,
739 0x9030, 0xffffffff, 0x00000100,
740 0x9034, 0xffffffff, 0x00000100,
741 0x9038, 0xffffffff, 0x00000100,
742 0x903c, 0xffffffff, 0x00000100,
743 0xad80, 0xffffffff, 0x00000100,
744 0xac54, 0xffffffff, 0x00000100,
745 0x897c, 0xffffffff, 0x06000100,
746 0x9868, 0xffffffff, 0x00000100,
747 0x9510, 0xffffffff, 0x00000100,
748 0xaf04, 0xffffffff, 0x00000100,
749 0xae04, 0xffffffff, 0x00000100,
750 0x949c, 0xffffffff, 0x00000100,
751 0x802c, 0xffffffff, 0xe0000000,
752 0x9160, 0xffffffff, 0x00010000,
753 0x9164, 0xffffffff, 0x00030002,
754 0x9168, 0xffffffff, 0x00040007,
755 0x916c, 0xffffffff, 0x00060005,
756 0x9170, 0xffffffff, 0x00090008,
757 0x9174, 0xffffffff, 0x00020001,
758 0x9178, 0xffffffff, 0x00040003,
759 0x917c, 0xffffffff, 0x00000007,
760 0x9180, 0xffffffff, 0x00060005,
761 0x9184, 0xffffffff, 0x00090008,
762 0x9188, 0xffffffff, 0x00030002,
763 0x918c, 0xffffffff, 0x00050004,
764 0x9190, 0xffffffff, 0x00000008,
765 0x9194, 0xffffffff, 0x00070006,
766 0x9198, 0xffffffff, 0x000a0009,
767 0x919c, 0xffffffff, 0x00040003,
768 0x91a0, 0xffffffff, 0x00060005,
769 0x91a4, 0xffffffff, 0x00000009,
770 0x91a8, 0xffffffff, 0x00080007,
771 0x91ac, 0xffffffff, 0x000b000a,
772 0x91b0, 0xffffffff, 0x00050004,
773 0x91b4, 0xffffffff, 0x00070006,
774 0x91b8, 0xffffffff, 0x0008000b,
775 0x91bc, 0xffffffff, 0x000a0009,
776 0x91c0, 0xffffffff, 0x000d000c,
777 0x9200, 0xffffffff, 0x00090008,
778 0x9204, 0xffffffff, 0x000b000a,
779 0x9208, 0xffffffff, 0x000c000f,
780 0x920c, 0xffffffff, 0x000e000d,
781 0x9210, 0xffffffff, 0x00110010,
782 0x9214, 0xffffffff, 0x000a0009,
783 0x9218, 0xffffffff, 0x000c000b,
784 0x921c, 0xffffffff, 0x0000000f,
785 0x9220, 0xffffffff, 0x000e000d,
786 0x9224, 0xffffffff, 0x00110010,
787 0x9228, 0xffffffff, 0x000b000a,
788 0x922c, 0xffffffff, 0x000d000c,
789 0x9230, 0xffffffff, 0x00000010,
790 0x9234, 0xffffffff, 0x000f000e,
791 0x9238, 0xffffffff, 0x00120011,
792 0x923c, 0xffffffff, 0x000c000b,
793 0x9240, 0xffffffff, 0x000e000d,
794 0x9244, 0xffffffff, 0x00000011,
795 0x9248, 0xffffffff, 0x0010000f,
796 0x924c, 0xffffffff, 0x00130012,
797 0x9250, 0xffffffff, 0x000d000c,
798 0x9254, 0xffffffff, 0x000f000e,
799 0x9258, 0xffffffff, 0x00100013,
800 0x925c, 0xffffffff, 0x00120011,
801 0x9260, 0xffffffff, 0x00150014,
802 0x9150, 0xffffffff, 0x96940200,
803 0x8708, 0xffffffff, 0x00900100,
804 0xc478, 0xffffffff, 0x00000080,
805 0xc404, 0xffffffff, 0x0020003f,
806 0x30, 0xffffffff, 0x0000001c,
807 0x34, 0x000f0000, 0x000f0000,
808 0x160c, 0xffffffff, 0x00000100,
809 0x1024, 0xffffffff, 0x00000100,
810 0x102c, 0x00000101, 0x00000000,
811 0x20a8, 0xffffffff, 0x00000104,
812 0x55e4, 0xff000fff, 0x00000100,
813 0x55e8, 0x00000001, 0x00000001,
814 0x2f50, 0x00000001, 0x00000001,
815 0x30cc, 0xc0000fff, 0x00000104,
816 0xc1e4, 0x00000001, 0x00000001,
817 0xd0c0, 0xfffffff0, 0x00000100,
818 0xd8c0, 0xfffffff0, 0x00000100
821 static const u32 verde_mgcg_cgcg_init[] =
823 0xc400, 0xffffffff, 0xfffffffc,
824 0x802c, 0xffffffff, 0xe0000000,
825 0x9a60, 0xffffffff, 0x00000100,
826 0x92a4, 0xffffffff, 0x00000100,
827 0xc164, 0xffffffff, 0x00000100,
828 0x9774, 0xffffffff, 0x00000100,
829 0x8984, 0xffffffff, 0x06000100,
830 0x8a18, 0xffffffff, 0x00000100,
831 0x92a0, 0xffffffff, 0x00000100,
832 0xc380, 0xffffffff, 0x00000100,
833 0x8b28, 0xffffffff, 0x00000100,
834 0x9144, 0xffffffff, 0x00000100,
835 0x8d88, 0xffffffff, 0x00000100,
836 0x8d8c, 0xffffffff, 0x00000100,
837 0x9030, 0xffffffff, 0x00000100,
838 0x9034, 0xffffffff, 0x00000100,
839 0x9038, 0xffffffff, 0x00000100,
840 0x903c, 0xffffffff, 0x00000100,
841 0xad80, 0xffffffff, 0x00000100,
842 0xac54, 0xffffffff, 0x00000100,
843 0x897c, 0xffffffff, 0x06000100,
844 0x9868, 0xffffffff, 0x00000100,
845 0x9510, 0xffffffff, 0x00000100,
846 0xaf04, 0xffffffff, 0x00000100,
847 0xae04, 0xffffffff, 0x00000100,
848 0x949c, 0xffffffff, 0x00000100,
849 0x802c, 0xffffffff, 0xe0000000,
850 0x9160, 0xffffffff, 0x00010000,
851 0x9164, 0xffffffff, 0x00030002,
852 0x9168, 0xffffffff, 0x00040007,
853 0x916c, 0xffffffff, 0x00060005,
854 0x9170, 0xffffffff, 0x00090008,
855 0x9174, 0xffffffff, 0x00020001,
856 0x9178, 0xffffffff, 0x00040003,
857 0x917c, 0xffffffff, 0x00000007,
858 0x9180, 0xffffffff, 0x00060005,
859 0x9184, 0xffffffff, 0x00090008,
860 0x9188, 0xffffffff, 0x00030002,
861 0x918c, 0xffffffff, 0x00050004,
862 0x9190, 0xffffffff, 0x00000008,
863 0x9194, 0xffffffff, 0x00070006,
864 0x9198, 0xffffffff, 0x000a0009,
865 0x919c, 0xffffffff, 0x00040003,
866 0x91a0, 0xffffffff, 0x00060005,
867 0x91a4, 0xffffffff, 0x00000009,
868 0x91a8, 0xffffffff, 0x00080007,
869 0x91ac, 0xffffffff, 0x000b000a,
870 0x91b0, 0xffffffff, 0x00050004,
871 0x91b4, 0xffffffff, 0x00070006,
872 0x91b8, 0xffffffff, 0x0008000b,
873 0x91bc, 0xffffffff, 0x000a0009,
874 0x91c0, 0xffffffff, 0x000d000c,
875 0x9200, 0xffffffff, 0x00090008,
876 0x9204, 0xffffffff, 0x000b000a,
877 0x9208, 0xffffffff, 0x000c000f,
878 0x920c, 0xffffffff, 0x000e000d,
879 0x9210, 0xffffffff, 0x00110010,
880 0x9214, 0xffffffff, 0x000a0009,
881 0x9218, 0xffffffff, 0x000c000b,
882 0x921c, 0xffffffff, 0x0000000f,
883 0x9220, 0xffffffff, 0x000e000d,
884 0x9224, 0xffffffff, 0x00110010,
885 0x9228, 0xffffffff, 0x000b000a,
886 0x922c, 0xffffffff, 0x000d000c,
887 0x9230, 0xffffffff, 0x00000010,
888 0x9234, 0xffffffff, 0x000f000e,
889 0x9238, 0xffffffff, 0x00120011,
890 0x923c, 0xffffffff, 0x000c000b,
891 0x9240, 0xffffffff, 0x000e000d,
892 0x9244, 0xffffffff, 0x00000011,
893 0x9248, 0xffffffff, 0x0010000f,
894 0x924c, 0xffffffff, 0x00130012,
895 0x9250, 0xffffffff, 0x000d000c,
896 0x9254, 0xffffffff, 0x000f000e,
897 0x9258, 0xffffffff, 0x00100013,
898 0x925c, 0xffffffff, 0x00120011,
899 0x9260, 0xffffffff, 0x00150014,
900 0x9150, 0xffffffff, 0x96940200,
901 0x8708, 0xffffffff, 0x00900100,
902 0xc478, 0xffffffff, 0x00000080,
903 0xc404, 0xffffffff, 0x0020003f,
904 0x30, 0xffffffff, 0x0000001c,
905 0x34, 0x000f0000, 0x000f0000,
906 0x160c, 0xffffffff, 0x00000100,
907 0x1024, 0xffffffff, 0x00000100,
908 0x102c, 0x00000101, 0x00000000,
909 0x20a8, 0xffffffff, 0x00000104,
910 0x264c, 0x000c0000, 0x000c0000,
911 0x2648, 0x000c0000, 0x000c0000,
912 0x55e4, 0xff000fff, 0x00000100,
913 0x55e8, 0x00000001, 0x00000001,
914 0x2f50, 0x00000001, 0x00000001,
915 0x30cc, 0xc0000fff, 0x00000104,
916 0xc1e4, 0x00000001, 0x00000001,
917 0xd0c0, 0xfffffff0, 0x00000100,
918 0xd8c0, 0xfffffff0, 0x00000100
921 static const u32 oland_mgcg_cgcg_init[] =
923 0xc400, 0xffffffff, 0xfffffffc,
924 0x802c, 0xffffffff, 0xe0000000,
925 0x9a60, 0xffffffff, 0x00000100,
926 0x92a4, 0xffffffff, 0x00000100,
927 0xc164, 0xffffffff, 0x00000100,
928 0x9774, 0xffffffff, 0x00000100,
929 0x8984, 0xffffffff, 0x06000100,
930 0x8a18, 0xffffffff, 0x00000100,
931 0x92a0, 0xffffffff, 0x00000100,
932 0xc380, 0xffffffff, 0x00000100,
933 0x8b28, 0xffffffff, 0x00000100,
934 0x9144, 0xffffffff, 0x00000100,
935 0x8d88, 0xffffffff, 0x00000100,
936 0x8d8c, 0xffffffff, 0x00000100,
937 0x9030, 0xffffffff, 0x00000100,
938 0x9034, 0xffffffff, 0x00000100,
939 0x9038, 0xffffffff, 0x00000100,
940 0x903c, 0xffffffff, 0x00000100,
941 0xad80, 0xffffffff, 0x00000100,
942 0xac54, 0xffffffff, 0x00000100,
943 0x897c, 0xffffffff, 0x06000100,
944 0x9868, 0xffffffff, 0x00000100,
945 0x9510, 0xffffffff, 0x00000100,
946 0xaf04, 0xffffffff, 0x00000100,
947 0xae04, 0xffffffff, 0x00000100,
948 0x949c, 0xffffffff, 0x00000100,
949 0x802c, 0xffffffff, 0xe0000000,
950 0x9160, 0xffffffff, 0x00010000,
951 0x9164, 0xffffffff, 0x00030002,
952 0x9168, 0xffffffff, 0x00040007,
953 0x916c, 0xffffffff, 0x00060005,
954 0x9170, 0xffffffff, 0x00090008,
955 0x9174, 0xffffffff, 0x00020001,
956 0x9178, 0xffffffff, 0x00040003,
957 0x917c, 0xffffffff, 0x00000007,
958 0x9180, 0xffffffff, 0x00060005,
959 0x9184, 0xffffffff, 0x00090008,
960 0x9188, 0xffffffff, 0x00030002,
961 0x918c, 0xffffffff, 0x00050004,
962 0x9190, 0xffffffff, 0x00000008,
963 0x9194, 0xffffffff, 0x00070006,
964 0x9198, 0xffffffff, 0x000a0009,
965 0x919c, 0xffffffff, 0x00040003,
966 0x91a0, 0xffffffff, 0x00060005,
967 0x91a4, 0xffffffff, 0x00000009,
968 0x91a8, 0xffffffff, 0x00080007,
969 0x91ac, 0xffffffff, 0x000b000a,
970 0x91b0, 0xffffffff, 0x00050004,
971 0x91b4, 0xffffffff, 0x00070006,
972 0x91b8, 0xffffffff, 0x0008000b,
973 0x91bc, 0xffffffff, 0x000a0009,
974 0x91c0, 0xffffffff, 0x000d000c,
975 0x91c4, 0xffffffff, 0x00060005,
976 0x91c8, 0xffffffff, 0x00080007,
977 0x91cc, 0xffffffff, 0x0000000b,
978 0x91d0, 0xffffffff, 0x000a0009,
979 0x91d4, 0xffffffff, 0x000d000c,
980 0x9150, 0xffffffff, 0x96940200,
981 0x8708, 0xffffffff, 0x00900100,
982 0xc478, 0xffffffff, 0x00000080,
983 0xc404, 0xffffffff, 0x0020003f,
984 0x30, 0xffffffff, 0x0000001c,
985 0x34, 0x000f0000, 0x000f0000,
986 0x160c, 0xffffffff, 0x00000100,
987 0x1024, 0xffffffff, 0x00000100,
988 0x102c, 0x00000101, 0x00000000,
989 0x20a8, 0xffffffff, 0x00000104,
990 0x264c, 0x000c0000, 0x000c0000,
991 0x2648, 0x000c0000, 0x000c0000,
992 0x55e4, 0xff000fff, 0x00000100,
993 0x55e8, 0x00000001, 0x00000001,
994 0x2f50, 0x00000001, 0x00000001,
995 0x30cc, 0xc0000fff, 0x00000104,
996 0xc1e4, 0x00000001, 0x00000001,
997 0xd0c0, 0xfffffff0, 0x00000100,
998 0xd8c0, 0xfffffff0, 0x00000100
1001 static const u32 hainan_mgcg_cgcg_init[] =
1003 0xc400, 0xffffffff, 0xfffffffc,
1004 0x802c, 0xffffffff, 0xe0000000,
1005 0x9a60, 0xffffffff, 0x00000100,
1006 0x92a4, 0xffffffff, 0x00000100,
1007 0xc164, 0xffffffff, 0x00000100,
1008 0x9774, 0xffffffff, 0x00000100,
1009 0x8984, 0xffffffff, 0x06000100,
1010 0x8a18, 0xffffffff, 0x00000100,
1011 0x92a0, 0xffffffff, 0x00000100,
1012 0xc380, 0xffffffff, 0x00000100,
1013 0x8b28, 0xffffffff, 0x00000100,
1014 0x9144, 0xffffffff, 0x00000100,
1015 0x8d88, 0xffffffff, 0x00000100,
1016 0x8d8c, 0xffffffff, 0x00000100,
1017 0x9030, 0xffffffff, 0x00000100,
1018 0x9034, 0xffffffff, 0x00000100,
1019 0x9038, 0xffffffff, 0x00000100,
1020 0x903c, 0xffffffff, 0x00000100,
1021 0xad80, 0xffffffff, 0x00000100,
1022 0xac54, 0xffffffff, 0x00000100,
1023 0x897c, 0xffffffff, 0x06000100,
1024 0x9868, 0xffffffff, 0x00000100,
1025 0x9510, 0xffffffff, 0x00000100,
1026 0xaf04, 0xffffffff, 0x00000100,
1027 0xae04, 0xffffffff, 0x00000100,
1028 0x949c, 0xffffffff, 0x00000100,
1029 0x802c, 0xffffffff, 0xe0000000,
1030 0x9160, 0xffffffff, 0x00010000,
1031 0x9164, 0xffffffff, 0x00030002,
1032 0x9168, 0xffffffff, 0x00040007,
1033 0x916c, 0xffffffff, 0x00060005,
1034 0x9170, 0xffffffff, 0x00090008,
1035 0x9174, 0xffffffff, 0x00020001,
1036 0x9178, 0xffffffff, 0x00040003,
1037 0x917c, 0xffffffff, 0x00000007,
1038 0x9180, 0xffffffff, 0x00060005,
1039 0x9184, 0xffffffff, 0x00090008,
1040 0x9188, 0xffffffff, 0x00030002,
1041 0x918c, 0xffffffff, 0x00050004,
1042 0x9190, 0xffffffff, 0x00000008,
1043 0x9194, 0xffffffff, 0x00070006,
1044 0x9198, 0xffffffff, 0x000a0009,
1045 0x919c, 0xffffffff, 0x00040003,
1046 0x91a0, 0xffffffff, 0x00060005,
1047 0x91a4, 0xffffffff, 0x00000009,
1048 0x91a8, 0xffffffff, 0x00080007,
1049 0x91ac, 0xffffffff, 0x000b000a,
1050 0x91b0, 0xffffffff, 0x00050004,
1051 0x91b4, 0xffffffff, 0x00070006,
1052 0x91b8, 0xffffffff, 0x0008000b,
1053 0x91bc, 0xffffffff, 0x000a0009,
1054 0x91c0, 0xffffffff, 0x000d000c,
1055 0x91c4, 0xffffffff, 0x00060005,
1056 0x91c8, 0xffffffff, 0x00080007,
1057 0x91cc, 0xffffffff, 0x0000000b,
1058 0x91d0, 0xffffffff, 0x000a0009,
1059 0x91d4, 0xffffffff, 0x000d000c,
1060 0x9150, 0xffffffff, 0x96940200,
1061 0x8708, 0xffffffff, 0x00900100,
1062 0xc478, 0xffffffff, 0x00000080,
1063 0xc404, 0xffffffff, 0x0020003f,
1064 0x30, 0xffffffff, 0x0000001c,
1065 0x34, 0x000f0000, 0x000f0000,
1066 0x160c, 0xffffffff, 0x00000100,
1067 0x1024, 0xffffffff, 0x00000100,
1068 0x20a8, 0xffffffff, 0x00000104,
1069 0x264c, 0x000c0000, 0x000c0000,
1070 0x2648, 0x000c0000, 0x000c0000,
1071 0x2f50, 0x00000001, 0x00000001,
1072 0x30cc, 0xc0000fff, 0x00000104,
1073 0xc1e4, 0x00000001, 0x00000001,
1074 0xd0c0, 0xfffffff0, 0x00000100,
1075 0xd8c0, 0xfffffff0, 0x00000100
1078 static u32 verde_pg_init[] =
1080 0x353c, 0xffffffff, 0x40000,
1081 0x3538, 0xffffffff, 0x200010ff,
1082 0x353c, 0xffffffff, 0x0,
1083 0x353c, 0xffffffff, 0x0,
1084 0x353c, 0xffffffff, 0x0,
1085 0x353c, 0xffffffff, 0x0,
1086 0x353c, 0xffffffff, 0x0,
1087 0x353c, 0xffffffff, 0x7007,
1088 0x3538, 0xffffffff, 0x300010ff,
1089 0x353c, 0xffffffff, 0x0,
1090 0x353c, 0xffffffff, 0x0,
1091 0x353c, 0xffffffff, 0x0,
1092 0x353c, 0xffffffff, 0x0,
1093 0x353c, 0xffffffff, 0x0,
1094 0x353c, 0xffffffff, 0x400000,
1095 0x3538, 0xffffffff, 0x100010ff,
1096 0x353c, 0xffffffff, 0x0,
1097 0x353c, 0xffffffff, 0x0,
1098 0x353c, 0xffffffff, 0x0,
1099 0x353c, 0xffffffff, 0x0,
1100 0x353c, 0xffffffff, 0x0,
1101 0x353c, 0xffffffff, 0x120200,
1102 0x3538, 0xffffffff, 0x500010ff,
1103 0x353c, 0xffffffff, 0x0,
1104 0x353c, 0xffffffff, 0x0,
1105 0x353c, 0xffffffff, 0x0,
1106 0x353c, 0xffffffff, 0x0,
1107 0x353c, 0xffffffff, 0x0,
1108 0x353c, 0xffffffff, 0x1e1e16,
1109 0x3538, 0xffffffff, 0x600010ff,
1110 0x353c, 0xffffffff, 0x0,
1111 0x353c, 0xffffffff, 0x0,
1112 0x353c, 0xffffffff, 0x0,
1113 0x353c, 0xffffffff, 0x0,
1114 0x353c, 0xffffffff, 0x0,
1115 0x353c, 0xffffffff, 0x171f1e,
1116 0x3538, 0xffffffff, 0x700010ff,
1117 0x353c, 0xffffffff, 0x0,
1118 0x353c, 0xffffffff, 0x0,
1119 0x353c, 0xffffffff, 0x0,
1120 0x353c, 0xffffffff, 0x0,
1121 0x353c, 0xffffffff, 0x0,
1122 0x353c, 0xffffffff, 0x0,
1123 0x3538, 0xffffffff, 0x9ff,
1124 0x3500, 0xffffffff, 0x0,
1125 0x3504, 0xffffffff, 0x10000800,
1126 0x3504, 0xffffffff, 0xf,
1127 0x3504, 0xffffffff, 0xf,
1128 0x3500, 0xffffffff, 0x4,
1129 0x3504, 0xffffffff, 0x1000051e,
1130 0x3504, 0xffffffff, 0xffff,
1131 0x3504, 0xffffffff, 0xffff,
1132 0x3500, 0xffffffff, 0x8,
1133 0x3504, 0xffffffff, 0x80500,
1134 0x3500, 0xffffffff, 0x12,
1135 0x3504, 0xffffffff, 0x9050c,
1136 0x3500, 0xffffffff, 0x1d,
1137 0x3504, 0xffffffff, 0xb052c,
1138 0x3500, 0xffffffff, 0x2a,
1139 0x3504, 0xffffffff, 0x1053e,
1140 0x3500, 0xffffffff, 0x2d,
1141 0x3504, 0xffffffff, 0x10546,
1142 0x3500, 0xffffffff, 0x30,
1143 0x3504, 0xffffffff, 0xa054e,
1144 0x3500, 0xffffffff, 0x3c,
1145 0x3504, 0xffffffff, 0x1055f,
1146 0x3500, 0xffffffff, 0x3f,
1147 0x3504, 0xffffffff, 0x10567,
1148 0x3500, 0xffffffff, 0x42,
1149 0x3504, 0xffffffff, 0x1056f,
1150 0x3500, 0xffffffff, 0x45,
1151 0x3504, 0xffffffff, 0x10572,
1152 0x3500, 0xffffffff, 0x48,
1153 0x3504, 0xffffffff, 0x20575,
1154 0x3500, 0xffffffff, 0x4c,
1155 0x3504, 0xffffffff, 0x190801,
1156 0x3500, 0xffffffff, 0x67,
1157 0x3504, 0xffffffff, 0x1082a,
1158 0x3500, 0xffffffff, 0x6a,
1159 0x3504, 0xffffffff, 0x1b082d,
1160 0x3500, 0xffffffff, 0x87,
1161 0x3504, 0xffffffff, 0x310851,
1162 0x3500, 0xffffffff, 0xba,
1163 0x3504, 0xffffffff, 0x891,
1164 0x3500, 0xffffffff, 0xbc,
1165 0x3504, 0xffffffff, 0x893,
1166 0x3500, 0xffffffff, 0xbe,
1167 0x3504, 0xffffffff, 0x20895,
1168 0x3500, 0xffffffff, 0xc2,
1169 0x3504, 0xffffffff, 0x20899,
1170 0x3500, 0xffffffff, 0xc6,
1171 0x3504, 0xffffffff, 0x2089d,
1172 0x3500, 0xffffffff, 0xca,
1173 0x3504, 0xffffffff, 0x8a1,
1174 0x3500, 0xffffffff, 0xcc,
1175 0x3504, 0xffffffff, 0x8a3,
1176 0x3500, 0xffffffff, 0xce,
1177 0x3504, 0xffffffff, 0x308a5,
1178 0x3500, 0xffffffff, 0xd3,
1179 0x3504, 0xffffffff, 0x6d08cd,
1180 0x3500, 0xffffffff, 0x142,
1181 0x3504, 0xffffffff, 0x2000095a,
1182 0x3504, 0xffffffff, 0x1,
1183 0x3500, 0xffffffff, 0x144,
1184 0x3504, 0xffffffff, 0x301f095b,
1185 0x3500, 0xffffffff, 0x165,
1186 0x3504, 0xffffffff, 0xc094d,
1187 0x3500, 0xffffffff, 0x173,
1188 0x3504, 0xffffffff, 0xf096d,
1189 0x3500, 0xffffffff, 0x184,
1190 0x3504, 0xffffffff, 0x15097f,
1191 0x3500, 0xffffffff, 0x19b,
1192 0x3504, 0xffffffff, 0xc0998,
1193 0x3500, 0xffffffff, 0x1a9,
1194 0x3504, 0xffffffff, 0x409a7,
1195 0x3500, 0xffffffff, 0x1af,
1196 0x3504, 0xffffffff, 0xcdc,
1197 0x3500, 0xffffffff, 0x1b1,
1198 0x3504, 0xffffffff, 0x800,
1199 0x3508, 0xffffffff, 0x6c9b2000,
1200 0x3510, 0xfc00, 0x2000,
1201 0x3544, 0xffffffff, 0xfc0,
1202 0x28d4, 0x00000100, 0x100
1205 static void si_init_golden_registers(struct radeon_device *rdev)
1207 switch (rdev->family) {
1209 radeon_program_register_sequence(rdev,
1210 tahiti_golden_registers,
1211 (const u32)ARRAY_SIZE(tahiti_golden_registers));
1212 radeon_program_register_sequence(rdev,
1213 tahiti_golden_rlc_registers,
1214 (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
1215 radeon_program_register_sequence(rdev,
1216 tahiti_mgcg_cgcg_init,
1217 (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
1218 radeon_program_register_sequence(rdev,
1219 tahiti_golden_registers2,
1220 (const u32)ARRAY_SIZE(tahiti_golden_registers2));
1223 radeon_program_register_sequence(rdev,
1224 pitcairn_golden_registers,
1225 (const u32)ARRAY_SIZE(pitcairn_golden_registers));
1226 radeon_program_register_sequence(rdev,
1227 pitcairn_golden_rlc_registers,
1228 (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
1229 radeon_program_register_sequence(rdev,
1230 pitcairn_mgcg_cgcg_init,
1231 (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
1234 radeon_program_register_sequence(rdev,
1235 verde_golden_registers,
1236 (const u32)ARRAY_SIZE(verde_golden_registers));
1237 radeon_program_register_sequence(rdev,
1238 verde_golden_rlc_registers,
1239 (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
1240 radeon_program_register_sequence(rdev,
1241 verde_mgcg_cgcg_init,
1242 (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
1243 radeon_program_register_sequence(rdev,
1245 (const u32)ARRAY_SIZE(verde_pg_init));
1248 radeon_program_register_sequence(rdev,
1249 oland_golden_registers,
1250 (const u32)ARRAY_SIZE(oland_golden_registers));
1251 radeon_program_register_sequence(rdev,
1252 oland_golden_rlc_registers,
1253 (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
1254 radeon_program_register_sequence(rdev,
1255 oland_mgcg_cgcg_init,
1256 (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
1259 radeon_program_register_sequence(rdev,
1260 hainan_golden_registers,
1261 (const u32)ARRAY_SIZE(hainan_golden_registers));
1262 radeon_program_register_sequence(rdev,
1263 hainan_golden_registers2,
1264 (const u32)ARRAY_SIZE(hainan_golden_registers2));
1265 radeon_program_register_sequence(rdev,
1266 hainan_mgcg_cgcg_init,
1267 (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
1275 * si_get_allowed_info_register - fetch the register for the info ioctl
1277 * @rdev: radeon_device pointer
1278 * @reg: register offset in bytes
1279 * @val: register value
1281 * Returns 0 for success or -EINVAL for an invalid register
1284 int si_get_allowed_info_register(struct radeon_device *rdev,
1290 case GRBM_STATUS_SE0:
1291 case GRBM_STATUS_SE1:
1294 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET):
1295 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET):
1304 #define PCIE_BUS_CLK 10000
1305 #define TCLK (PCIE_BUS_CLK / 10)
1308 * si_get_xclk - get the xclk
1310 * @rdev: radeon_device pointer
1312 * Returns the reference clock used by the gfx engine
1315 u32 si_get_xclk(struct radeon_device *rdev)
1317 u32 reference_clock = rdev->clock.spll.reference_freq;
1320 tmp = RREG32(CG_CLKPIN_CNTL_2);
1321 if (tmp & MUX_TCLK_TO_XCLK)
1324 tmp = RREG32(CG_CLKPIN_CNTL);
1325 if (tmp & XTALIN_DIVIDE)
1326 return reference_clock / 4;
1328 return reference_clock;
1331 /* get temperature in millidegrees */
1332 int si_get_temp(struct radeon_device *rdev)
1335 int actual_temp = 0;
1337 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
1343 actual_temp = temp & 0x1ff;
1345 actual_temp = (actual_temp * 1000);
1350 #define TAHITI_IO_MC_REGS_SIZE 36
1352 static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1353 {0x0000006f, 0x03044000},
1354 {0x00000070, 0x0480c018},
1355 {0x00000071, 0x00000040},
1356 {0x00000072, 0x01000000},
1357 {0x00000074, 0x000000ff},
1358 {0x00000075, 0x00143400},
1359 {0x00000076, 0x08ec0800},
1360 {0x00000077, 0x040000cc},
1361 {0x00000079, 0x00000000},
1362 {0x0000007a, 0x21000409},
1363 {0x0000007c, 0x00000000},
1364 {0x0000007d, 0xe8000000},
1365 {0x0000007e, 0x044408a8},
1366 {0x0000007f, 0x00000003},
1367 {0x00000080, 0x00000000},
1368 {0x00000081, 0x01000000},
1369 {0x00000082, 0x02000000},
1370 {0x00000083, 0x00000000},
1371 {0x00000084, 0xe3f3e4f4},
1372 {0x00000085, 0x00052024},
1373 {0x00000087, 0x00000000},
1374 {0x00000088, 0x66036603},
1375 {0x00000089, 0x01000000},
1376 {0x0000008b, 0x1c0a0000},
1377 {0x0000008c, 0xff010000},
1378 {0x0000008e, 0xffffefff},
1379 {0x0000008f, 0xfff3efff},
1380 {0x00000090, 0xfff3efbf},
1381 {0x00000094, 0x00101101},
1382 {0x00000095, 0x00000fff},
1383 {0x00000096, 0x00116fff},
1384 {0x00000097, 0x60010000},
1385 {0x00000098, 0x10010000},
1386 {0x00000099, 0x00006000},
1387 {0x0000009a, 0x00001000},
1388 {0x0000009f, 0x00a77400}
1391 static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1392 {0x0000006f, 0x03044000},
1393 {0x00000070, 0x0480c018},
1394 {0x00000071, 0x00000040},
1395 {0x00000072, 0x01000000},
1396 {0x00000074, 0x000000ff},
1397 {0x00000075, 0x00143400},
1398 {0x00000076, 0x08ec0800},
1399 {0x00000077, 0x040000cc},
1400 {0x00000079, 0x00000000},
1401 {0x0000007a, 0x21000409},
1402 {0x0000007c, 0x00000000},
1403 {0x0000007d, 0xe8000000},
1404 {0x0000007e, 0x044408a8},
1405 {0x0000007f, 0x00000003},
1406 {0x00000080, 0x00000000},
1407 {0x00000081, 0x01000000},
1408 {0x00000082, 0x02000000},
1409 {0x00000083, 0x00000000},
1410 {0x00000084, 0xe3f3e4f4},
1411 {0x00000085, 0x00052024},
1412 {0x00000087, 0x00000000},
1413 {0x00000088, 0x66036603},
1414 {0x00000089, 0x01000000},
1415 {0x0000008b, 0x1c0a0000},
1416 {0x0000008c, 0xff010000},
1417 {0x0000008e, 0xffffefff},
1418 {0x0000008f, 0xfff3efff},
1419 {0x00000090, 0xfff3efbf},
1420 {0x00000094, 0x00101101},
1421 {0x00000095, 0x00000fff},
1422 {0x00000096, 0x00116fff},
1423 {0x00000097, 0x60010000},
1424 {0x00000098, 0x10010000},
1425 {0x00000099, 0x00006000},
1426 {0x0000009a, 0x00001000},
1427 {0x0000009f, 0x00a47400}
1430 static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1431 {0x0000006f, 0x03044000},
1432 {0x00000070, 0x0480c018},
1433 {0x00000071, 0x00000040},
1434 {0x00000072, 0x01000000},
1435 {0x00000074, 0x000000ff},
1436 {0x00000075, 0x00143400},
1437 {0x00000076, 0x08ec0800},
1438 {0x00000077, 0x040000cc},
1439 {0x00000079, 0x00000000},
1440 {0x0000007a, 0x21000409},
1441 {0x0000007c, 0x00000000},
1442 {0x0000007d, 0xe8000000},
1443 {0x0000007e, 0x044408a8},
1444 {0x0000007f, 0x00000003},
1445 {0x00000080, 0x00000000},
1446 {0x00000081, 0x01000000},
1447 {0x00000082, 0x02000000},
1448 {0x00000083, 0x00000000},
1449 {0x00000084, 0xe3f3e4f4},
1450 {0x00000085, 0x00052024},
1451 {0x00000087, 0x00000000},
1452 {0x00000088, 0x66036603},
1453 {0x00000089, 0x01000000},
1454 {0x0000008b, 0x1c0a0000},
1455 {0x0000008c, 0xff010000},
1456 {0x0000008e, 0xffffefff},
1457 {0x0000008f, 0xfff3efff},
1458 {0x00000090, 0xfff3efbf},
1459 {0x00000094, 0x00101101},
1460 {0x00000095, 0x00000fff},
1461 {0x00000096, 0x00116fff},
1462 {0x00000097, 0x60010000},
1463 {0x00000098, 0x10010000},
1464 {0x00000099, 0x00006000},
1465 {0x0000009a, 0x00001000},
1466 {0x0000009f, 0x00a37400}
1469 static const u32 oland_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1470 {0x0000006f, 0x03044000},
1471 {0x00000070, 0x0480c018},
1472 {0x00000071, 0x00000040},
1473 {0x00000072, 0x01000000},
1474 {0x00000074, 0x000000ff},
1475 {0x00000075, 0x00143400},
1476 {0x00000076, 0x08ec0800},
1477 {0x00000077, 0x040000cc},
1478 {0x00000079, 0x00000000},
1479 {0x0000007a, 0x21000409},
1480 {0x0000007c, 0x00000000},
1481 {0x0000007d, 0xe8000000},
1482 {0x0000007e, 0x044408a8},
1483 {0x0000007f, 0x00000003},
1484 {0x00000080, 0x00000000},
1485 {0x00000081, 0x01000000},
1486 {0x00000082, 0x02000000},
1487 {0x00000083, 0x00000000},
1488 {0x00000084, 0xe3f3e4f4},
1489 {0x00000085, 0x00052024},
1490 {0x00000087, 0x00000000},
1491 {0x00000088, 0x66036603},
1492 {0x00000089, 0x01000000},
1493 {0x0000008b, 0x1c0a0000},
1494 {0x0000008c, 0xff010000},
1495 {0x0000008e, 0xffffefff},
1496 {0x0000008f, 0xfff3efff},
1497 {0x00000090, 0xfff3efbf},
1498 {0x00000094, 0x00101101},
1499 {0x00000095, 0x00000fff},
1500 {0x00000096, 0x00116fff},
1501 {0x00000097, 0x60010000},
1502 {0x00000098, 0x10010000},
1503 {0x00000099, 0x00006000},
1504 {0x0000009a, 0x00001000},
1505 {0x0000009f, 0x00a17730}
1508 static const u32 hainan_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1509 {0x0000006f, 0x03044000},
1510 {0x00000070, 0x0480c018},
1511 {0x00000071, 0x00000040},
1512 {0x00000072, 0x01000000},
1513 {0x00000074, 0x000000ff},
1514 {0x00000075, 0x00143400},
1515 {0x00000076, 0x08ec0800},
1516 {0x00000077, 0x040000cc},
1517 {0x00000079, 0x00000000},
1518 {0x0000007a, 0x21000409},
1519 {0x0000007c, 0x00000000},
1520 {0x0000007d, 0xe8000000},
1521 {0x0000007e, 0x044408a8},
1522 {0x0000007f, 0x00000003},
1523 {0x00000080, 0x00000000},
1524 {0x00000081, 0x01000000},
1525 {0x00000082, 0x02000000},
1526 {0x00000083, 0x00000000},
1527 {0x00000084, 0xe3f3e4f4},
1528 {0x00000085, 0x00052024},
1529 {0x00000087, 0x00000000},
1530 {0x00000088, 0x66036603},
1531 {0x00000089, 0x01000000},
1532 {0x0000008b, 0x1c0a0000},
1533 {0x0000008c, 0xff010000},
1534 {0x0000008e, 0xffffefff},
1535 {0x0000008f, 0xfff3efff},
1536 {0x00000090, 0xfff3efbf},
1537 {0x00000094, 0x00101101},
1538 {0x00000095, 0x00000fff},
1539 {0x00000096, 0x00116fff},
1540 {0x00000097, 0x60010000},
1541 {0x00000098, 0x10010000},
1542 {0x00000099, 0x00006000},
1543 {0x0000009a, 0x00001000},
1544 {0x0000009f, 0x00a07730}
1548 int si_mc_load_microcode(struct radeon_device *rdev)
1550 const __be32 *fw_data = NULL;
1551 const __le32 *new_fw_data = NULL;
1553 u32 *io_mc_regs = NULL;
1554 const __le32 *new_io_mc_regs = NULL;
1555 int i, regs_size, ucode_size;
1561 const struct mc_firmware_header_v1_0 *hdr =
1562 (const struct mc_firmware_header_v1_0 *)rdev->mc_fw->data;
1564 radeon_ucode_print_mc_hdr(&hdr->header);
1565 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
1566 new_io_mc_regs = (const __le32 *)
1567 (rdev->mc_fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
1568 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1569 new_fw_data = (const __le32 *)
1570 (rdev->mc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1572 ucode_size = rdev->mc_fw->size / 4;
1574 switch (rdev->family) {
1576 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
1577 regs_size = TAHITI_IO_MC_REGS_SIZE;
1580 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
1581 regs_size = TAHITI_IO_MC_REGS_SIZE;
1585 io_mc_regs = (u32 *)&verde_io_mc_regs;
1586 regs_size = TAHITI_IO_MC_REGS_SIZE;
1589 io_mc_regs = (u32 *)&oland_io_mc_regs;
1590 regs_size = TAHITI_IO_MC_REGS_SIZE;
1593 io_mc_regs = (u32 *)&hainan_io_mc_regs;
1594 regs_size = TAHITI_IO_MC_REGS_SIZE;
1597 fw_data = (const __be32 *)rdev->mc_fw->data;
1600 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
1603 /* reset the engine and set to writable */
1604 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1605 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
1607 /* load mc io regs */
1608 for (i = 0; i < regs_size; i++) {
1610 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
1611 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
1613 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
1614 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
1617 /* load the MC ucode */
1618 for (i = 0; i < ucode_size; i++) {
1620 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
1622 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
1625 /* put the engine back into the active state */
1626 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1627 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
1628 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
1630 /* wait for training to complete */
1631 for (i = 0; i < rdev->usec_timeout; i++) {
1632 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
1636 for (i = 0; i < rdev->usec_timeout; i++) {
1637 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
1646 static int si_init_microcode(struct radeon_device *rdev)
1648 const char *chip_name;
1649 const char *new_chip_name;
1650 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
1651 size_t smc_req_size, mc2_req_size;
1655 bool new_smc = false;
1656 bool si58_fw = false;
1657 bool banks2_fw = false;
1661 switch (rdev->family) {
1663 chip_name = "TAHITI";
1664 new_chip_name = "tahiti";
1665 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1666 me_req_size = SI_PM4_UCODE_SIZE * 4;
1667 ce_req_size = SI_CE_UCODE_SIZE * 4;
1668 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1669 mc_req_size = SI_MC_UCODE_SIZE * 4;
1670 mc2_req_size = TAHITI_MC_UCODE_SIZE * 4;
1671 smc_req_size = ALIGN(TAHITI_SMC_UCODE_SIZE, 4);
1674 chip_name = "PITCAIRN";
1675 if ((rdev->pdev->revision == 0x81) &&
1676 ((rdev->pdev->device == 0x6810) ||
1677 (rdev->pdev->device == 0x6811)))
1679 new_chip_name = "pitcairn";
1680 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1681 me_req_size = SI_PM4_UCODE_SIZE * 4;
1682 ce_req_size = SI_CE_UCODE_SIZE * 4;
1683 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1684 mc_req_size = SI_MC_UCODE_SIZE * 4;
1685 mc2_req_size = PITCAIRN_MC_UCODE_SIZE * 4;
1686 smc_req_size = ALIGN(PITCAIRN_SMC_UCODE_SIZE, 4);
1689 chip_name = "VERDE";
1690 if (((rdev->pdev->device == 0x6820) &&
1691 ((rdev->pdev->revision == 0x81) ||
1692 (rdev->pdev->revision == 0x83))) ||
1693 ((rdev->pdev->device == 0x6821) &&
1694 ((rdev->pdev->revision == 0x83) ||
1695 (rdev->pdev->revision == 0x87))) ||
1696 ((rdev->pdev->revision == 0x87) &&
1697 ((rdev->pdev->device == 0x6823) ||
1698 (rdev->pdev->device == 0x682b))))
1700 new_chip_name = "verde";
1701 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1702 me_req_size = SI_PM4_UCODE_SIZE * 4;
1703 ce_req_size = SI_CE_UCODE_SIZE * 4;
1704 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1705 mc_req_size = SI_MC_UCODE_SIZE * 4;
1706 mc2_req_size = VERDE_MC_UCODE_SIZE * 4;
1707 smc_req_size = ALIGN(VERDE_SMC_UCODE_SIZE, 4);
1710 chip_name = "OLAND";
1711 if (((rdev->pdev->revision == 0x81) &&
1712 ((rdev->pdev->device == 0x6600) ||
1713 (rdev->pdev->device == 0x6604) ||
1714 (rdev->pdev->device == 0x6605) ||
1715 (rdev->pdev->device == 0x6610))) ||
1716 ((rdev->pdev->revision == 0x83) &&
1717 (rdev->pdev->device == 0x6610)))
1719 new_chip_name = "oland";
1720 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1721 me_req_size = SI_PM4_UCODE_SIZE * 4;
1722 ce_req_size = SI_CE_UCODE_SIZE * 4;
1723 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1724 mc_req_size = mc2_req_size = OLAND_MC_UCODE_SIZE * 4;
1725 smc_req_size = ALIGN(OLAND_SMC_UCODE_SIZE, 4);
1728 chip_name = "HAINAN";
1729 if (((rdev->pdev->revision == 0x81) &&
1730 (rdev->pdev->device == 0x6660)) ||
1731 ((rdev->pdev->revision == 0x83) &&
1732 ((rdev->pdev->device == 0x6660) ||
1733 (rdev->pdev->device == 0x6663) ||
1734 (rdev->pdev->device == 0x6665) ||
1735 (rdev->pdev->device == 0x6667))))
1737 else if ((rdev->pdev->revision == 0xc3) &&
1738 (rdev->pdev->device == 0x6665))
1740 new_chip_name = "hainan";
1741 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1742 me_req_size = SI_PM4_UCODE_SIZE * 4;
1743 ce_req_size = SI_CE_UCODE_SIZE * 4;
1744 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1745 mc_req_size = mc2_req_size = OLAND_MC_UCODE_SIZE * 4;
1746 smc_req_size = ALIGN(HAINAN_SMC_UCODE_SIZE, 4);
1751 /* this memory configuration requires special firmware */
1752 if (((RREG32(MC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
1755 DRM_INFO("Loading %s Microcode\n", new_chip_name);
1757 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", new_chip_name);
1758 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
1760 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1761 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
1764 if (rdev->pfp_fw->size != pfp_req_size) {
1765 pr_err("si_cp: Bogus length %zu in firmware \"%s\"\n",
1766 rdev->pfp_fw->size, fw_name);
1771 err = radeon_ucode_validate(rdev->pfp_fw);
1773 pr_err("si_cp: validation failed for firmware \"%s\"\n",
1781 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", new_chip_name);
1782 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1784 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1785 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1788 if (rdev->me_fw->size != me_req_size) {
1789 pr_err("si_cp: Bogus length %zu in firmware \"%s\"\n",
1790 rdev->me_fw->size, fw_name);
1794 err = radeon_ucode_validate(rdev->me_fw);
1796 pr_err("si_cp: validation failed for firmware \"%s\"\n",
1804 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", new_chip_name);
1805 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
1807 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
1808 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
1811 if (rdev->ce_fw->size != ce_req_size) {
1812 pr_err("si_cp: Bogus length %zu in firmware \"%s\"\n",
1813 rdev->ce_fw->size, fw_name);
1817 err = radeon_ucode_validate(rdev->ce_fw);
1819 pr_err("si_cp: validation failed for firmware \"%s\"\n",
1827 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", new_chip_name);
1828 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
1830 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
1831 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
1834 if (rdev->rlc_fw->size != rlc_req_size) {
1835 pr_err("si_rlc: Bogus length %zu in firmware \"%s\"\n",
1836 rdev->rlc_fw->size, fw_name);
1840 err = radeon_ucode_validate(rdev->rlc_fw);
1842 pr_err("si_cp: validation failed for firmware \"%s\"\n",
1851 snprintf(fw_name, sizeof(fw_name), "radeon/si58_mc.bin");
1853 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", new_chip_name);
1854 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1856 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc2.bin", chip_name);
1857 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1859 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
1860 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1864 if ((rdev->mc_fw->size != mc_req_size) &&
1865 (rdev->mc_fw->size != mc2_req_size)) {
1866 pr_err("si_mc: Bogus length %zu in firmware \"%s\"\n",
1867 rdev->mc_fw->size, fw_name);
1870 DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->size);
1872 err = radeon_ucode_validate(rdev->mc_fw);
1874 pr_err("si_cp: validation failed for firmware \"%s\"\n",
1883 snprintf(fw_name, sizeof(fw_name), "radeon/banks_k_2_smc.bin");
1885 snprintf(fw_name, sizeof(fw_name), "radeon/%s_k_smc.bin", new_chip_name);
1887 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", new_chip_name);
1888 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
1890 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
1891 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
1893 pr_err("smc: error loading firmware \"%s\"\n", fw_name);
1894 release_firmware(rdev->smc_fw);
1895 rdev->smc_fw = NULL;
1897 } else if (rdev->smc_fw->size != smc_req_size) {
1898 pr_err("si_smc: Bogus length %zu in firmware \"%s\"\n",
1899 rdev->smc_fw->size, fw_name);
1903 err = radeon_ucode_validate(rdev->smc_fw);
1905 pr_err("si_cp: validation failed for firmware \"%s\"\n",
1914 rdev->new_fw = false;
1915 } else if (new_fw < 6) {
1916 pr_err("si_fw: mixing new and old firmware!\n");
1919 rdev->new_fw = true;
1924 pr_err("si_cp: Failed to load firmware \"%s\"\n",
1926 release_firmware(rdev->pfp_fw);
1927 rdev->pfp_fw = NULL;
1928 release_firmware(rdev->me_fw);
1930 release_firmware(rdev->ce_fw);
1932 release_firmware(rdev->rlc_fw);
1933 rdev->rlc_fw = NULL;
1934 release_firmware(rdev->mc_fw);
1936 release_firmware(rdev->smc_fw);
1937 rdev->smc_fw = NULL;
1942 /* watermark setup */
1943 static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
1944 struct radeon_crtc *radeon_crtc,
1945 struct drm_display_mode *mode,
1946 struct drm_display_mode *other_mode)
1948 u32 tmp, buffer_alloc, i;
1949 u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
1952 * There are 3 line buffers, each one shared by 2 display controllers.
1953 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
1954 * the display controllers. The paritioning is done via one of four
1955 * preset allocations specified in bits 21:20:
1957 * 2 - whole lb, other crtc must be disabled
1959 /* this can get tricky if we have two large displays on a paired group
1960 * of crtcs. Ideally for multiple large displays we'd assign them to
1961 * non-linked crtcs for maximum line buffer allocation.
1963 if (radeon_crtc->base.enabled && mode) {
1968 tmp = 2; /* whole */
1976 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
1977 DC_LB_MEMORY_CONFIG(tmp));
1979 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1980 DMIF_BUFFERS_ALLOCATED(buffer_alloc));
1981 for (i = 0; i < rdev->usec_timeout; i++) {
1982 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
1983 DMIF_BUFFERS_ALLOCATED_COMPLETED)
1988 if (radeon_crtc->base.enabled && mode) {
1998 /* controller not enabled, so no lb used */
2002 static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)
2004 u32 tmp = RREG32(MC_SHARED_CHMAP);
2006 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2029 struct dce6_wm_params {
2030 u32 dram_channels; /* number of dram channels */
2031 u32 yclk; /* bandwidth per dram data pin in kHz */
2032 u32 sclk; /* engine clock in kHz */
2033 u32 disp_clk; /* display clock in kHz */
2034 u32 src_width; /* viewport width */
2035 u32 active_time; /* active display time in ns */
2036 u32 blank_time; /* blank time in ns */
2037 bool interlaced; /* mode is interlaced */
2038 fixed20_12 vsc; /* vertical scale ratio */
2039 u32 num_heads; /* number of active crtcs */
2040 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
2041 u32 lb_size; /* line buffer allocated to pipe */
2042 u32 vtaps; /* vertical scaler taps */
2045 static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
2047 /* Calculate raw DRAM Bandwidth */
2048 fixed20_12 dram_efficiency; /* 0.7 */
2049 fixed20_12 yclk, dram_channels, bandwidth;
2052 a.full = dfixed_const(1000);
2053 yclk.full = dfixed_const(wm->yclk);
2054 yclk.full = dfixed_div(yclk, a);
2055 dram_channels.full = dfixed_const(wm->dram_channels * 4);
2056 a.full = dfixed_const(10);
2057 dram_efficiency.full = dfixed_const(7);
2058 dram_efficiency.full = dfixed_div(dram_efficiency, a);
2059 bandwidth.full = dfixed_mul(dram_channels, yclk);
2060 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
2062 return dfixed_trunc(bandwidth);
2065 static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
2067 /* Calculate DRAM Bandwidth and the part allocated to display. */
2068 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
2069 fixed20_12 yclk, dram_channels, bandwidth;
2072 a.full = dfixed_const(1000);
2073 yclk.full = dfixed_const(wm->yclk);
2074 yclk.full = dfixed_div(yclk, a);
2075 dram_channels.full = dfixed_const(wm->dram_channels * 4);
2076 a.full = dfixed_const(10);
2077 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
2078 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
2079 bandwidth.full = dfixed_mul(dram_channels, yclk);
2080 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
2082 return dfixed_trunc(bandwidth);
2085 static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
2087 /* Calculate the display Data return Bandwidth */
2088 fixed20_12 return_efficiency; /* 0.8 */
2089 fixed20_12 sclk, bandwidth;
2092 a.full = dfixed_const(1000);
2093 sclk.full = dfixed_const(wm->sclk);
2094 sclk.full = dfixed_div(sclk, a);
2095 a.full = dfixed_const(10);
2096 return_efficiency.full = dfixed_const(8);
2097 return_efficiency.full = dfixed_div(return_efficiency, a);
2098 a.full = dfixed_const(32);
2099 bandwidth.full = dfixed_mul(a, sclk);
2100 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
2102 return dfixed_trunc(bandwidth);
2105 static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
2110 static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
2112 /* Calculate the DMIF Request Bandwidth */
2113 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
2114 fixed20_12 disp_clk, sclk, bandwidth;
2115 fixed20_12 a, b1, b2;
2118 a.full = dfixed_const(1000);
2119 disp_clk.full = dfixed_const(wm->disp_clk);
2120 disp_clk.full = dfixed_div(disp_clk, a);
2121 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
2122 b1.full = dfixed_mul(a, disp_clk);
2124 a.full = dfixed_const(1000);
2125 sclk.full = dfixed_const(wm->sclk);
2126 sclk.full = dfixed_div(sclk, a);
2127 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
2128 b2.full = dfixed_mul(a, sclk);
2130 a.full = dfixed_const(10);
2131 disp_clk_request_efficiency.full = dfixed_const(8);
2132 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
2134 min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
2136 a.full = dfixed_const(min_bandwidth);
2137 bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
2139 return dfixed_trunc(bandwidth);
2142 static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
2144 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
2145 u32 dram_bandwidth = dce6_dram_bandwidth(wm);
2146 u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
2147 u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
2149 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
2152 static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
2154 /* Calculate the display mode Average Bandwidth
2155 * DisplayMode should contain the source and destination dimensions,
2159 fixed20_12 line_time;
2160 fixed20_12 src_width;
2161 fixed20_12 bandwidth;
2164 a.full = dfixed_const(1000);
2165 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
2166 line_time.full = dfixed_div(line_time, a);
2167 bpp.full = dfixed_const(wm->bytes_per_pixel);
2168 src_width.full = dfixed_const(wm->src_width);
2169 bandwidth.full = dfixed_mul(src_width, bpp);
2170 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
2171 bandwidth.full = dfixed_div(bandwidth, line_time);
2173 return dfixed_trunc(bandwidth);
2176 static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
2178 /* First calcualte the latency in ns */
2179 u32 mc_latency = 2000; /* 2000 ns. */
2180 u32 available_bandwidth = dce6_available_bandwidth(wm);
2181 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
2182 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
2183 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
2184 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
2185 (wm->num_heads * cursor_line_pair_return_time);
2186 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
2187 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
2188 u32 tmp, dmif_size = 12288;
2191 if (wm->num_heads == 0)
2194 a.full = dfixed_const(2);
2195 b.full = dfixed_const(1);
2196 if ((wm->vsc.full > a.full) ||
2197 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
2199 ((wm->vsc.full >= a.full) && wm->interlaced))
2200 max_src_lines_per_dst_line = 4;
2202 max_src_lines_per_dst_line = 2;
2204 a.full = dfixed_const(available_bandwidth);
2205 b.full = dfixed_const(wm->num_heads);
2206 a.full = dfixed_div(a, b);
2207 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
2208 tmp = min(dfixed_trunc(a), tmp);
2210 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
2212 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
2213 b.full = dfixed_const(1000);
2214 c.full = dfixed_const(lb_fill_bw);
2215 b.full = dfixed_div(c, b);
2216 a.full = dfixed_div(a, b);
2217 line_fill_time = dfixed_trunc(a);
2219 if (line_fill_time < wm->active_time)
2222 return latency + (line_fill_time - wm->active_time);
2226 static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
2228 if (dce6_average_bandwidth(wm) <=
2229 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
2235 static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
2237 if (dce6_average_bandwidth(wm) <=
2238 (dce6_available_bandwidth(wm) / wm->num_heads))
2244 static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
2246 u32 lb_partitions = wm->lb_size / wm->src_width;
2247 u32 line_time = wm->active_time + wm->blank_time;
2248 u32 latency_tolerant_lines;
2252 a.full = dfixed_const(1);
2253 if (wm->vsc.full > a.full)
2254 latency_tolerant_lines = 1;
2256 if (lb_partitions <= (wm->vtaps + 1))
2257 latency_tolerant_lines = 1;
2259 latency_tolerant_lines = 2;
2262 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
2264 if (dce6_latency_watermark(wm) <= latency_hiding)
2270 static void dce6_program_watermarks(struct radeon_device *rdev,
2271 struct radeon_crtc *radeon_crtc,
2272 u32 lb_size, u32 num_heads)
2274 struct drm_display_mode *mode = &radeon_crtc->base.mode;
2275 struct dce6_wm_params wm_low, wm_high;
2279 u32 latency_watermark_a = 0, latency_watermark_b = 0;
2280 u32 priority_a_mark = 0, priority_b_mark = 0;
2281 u32 priority_a_cnt = PRIORITY_OFF;
2282 u32 priority_b_cnt = PRIORITY_OFF;
2283 u32 tmp, arb_control3;
2286 if (radeon_crtc->base.enabled && num_heads && mode) {
2287 active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
2288 line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
2292 if (rdev->family == CHIP_ARUBA)
2293 dram_channels = evergreen_get_number_of_dram_channels(rdev);
2295 dram_channels = si_get_number_of_dram_channels(rdev);
2297 /* watermark for high clocks */
2298 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
2300 radeon_dpm_get_mclk(rdev, false) * 10;
2302 radeon_dpm_get_sclk(rdev, false) * 10;
2304 wm_high.yclk = rdev->pm.current_mclk * 10;
2305 wm_high.sclk = rdev->pm.current_sclk * 10;
2308 wm_high.disp_clk = mode->clock;
2309 wm_high.src_width = mode->crtc_hdisplay;
2310 wm_high.active_time = active_time;
2311 wm_high.blank_time = line_time - wm_high.active_time;
2312 wm_high.interlaced = false;
2313 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2314 wm_high.interlaced = true;
2315 wm_high.vsc = radeon_crtc->vsc;
2317 if (radeon_crtc->rmx_type != RMX_OFF)
2319 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
2320 wm_high.lb_size = lb_size;
2321 wm_high.dram_channels = dram_channels;
2322 wm_high.num_heads = num_heads;
2324 /* watermark for low clocks */
2325 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
2327 radeon_dpm_get_mclk(rdev, true) * 10;
2329 radeon_dpm_get_sclk(rdev, true) * 10;
2331 wm_low.yclk = rdev->pm.current_mclk * 10;
2332 wm_low.sclk = rdev->pm.current_sclk * 10;
2335 wm_low.disp_clk = mode->clock;
2336 wm_low.src_width = mode->crtc_hdisplay;
2337 wm_low.active_time = active_time;
2338 wm_low.blank_time = line_time - wm_low.active_time;
2339 wm_low.interlaced = false;
2340 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2341 wm_low.interlaced = true;
2342 wm_low.vsc = radeon_crtc->vsc;
2344 if (radeon_crtc->rmx_type != RMX_OFF)
2346 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
2347 wm_low.lb_size = lb_size;
2348 wm_low.dram_channels = dram_channels;
2349 wm_low.num_heads = num_heads;
2351 /* set for high clocks */
2352 latency_watermark_a = min(dce6_latency_watermark(&wm_high), (u32)65535);
2353 /* set for low clocks */
2354 latency_watermark_b = min(dce6_latency_watermark(&wm_low), (u32)65535);
2356 /* possibly force display priority to high */
2357 /* should really do this at mode validation time... */
2358 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
2359 !dce6_average_bandwidth_vs_available_bandwidth(&wm_high) ||
2360 !dce6_check_latency_hiding(&wm_high) ||
2361 (rdev->disp_priority == 2)) {
2362 DRM_DEBUG_KMS("force priority to high\n");
2363 priority_a_cnt |= PRIORITY_ALWAYS_ON;
2364 priority_b_cnt |= PRIORITY_ALWAYS_ON;
2366 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
2367 !dce6_average_bandwidth_vs_available_bandwidth(&wm_low) ||
2368 !dce6_check_latency_hiding(&wm_low) ||
2369 (rdev->disp_priority == 2)) {
2370 DRM_DEBUG_KMS("force priority to high\n");
2371 priority_a_cnt |= PRIORITY_ALWAYS_ON;
2372 priority_b_cnt |= PRIORITY_ALWAYS_ON;
2375 a.full = dfixed_const(1000);
2376 b.full = dfixed_const(mode->clock);
2377 b.full = dfixed_div(b, a);
2378 c.full = dfixed_const(latency_watermark_a);
2379 c.full = dfixed_mul(c, b);
2380 c.full = dfixed_mul(c, radeon_crtc->hsc);
2381 c.full = dfixed_div(c, a);
2382 a.full = dfixed_const(16);
2383 c.full = dfixed_div(c, a);
2384 priority_a_mark = dfixed_trunc(c);
2385 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
2387 a.full = dfixed_const(1000);
2388 b.full = dfixed_const(mode->clock);
2389 b.full = dfixed_div(b, a);
2390 c.full = dfixed_const(latency_watermark_b);
2391 c.full = dfixed_mul(c, b);
2392 c.full = dfixed_mul(c, radeon_crtc->hsc);
2393 c.full = dfixed_div(c, a);
2394 a.full = dfixed_const(16);
2395 c.full = dfixed_div(c, a);
2396 priority_b_mark = dfixed_trunc(c);
2397 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
2399 /* Save number of lines the linebuffer leads before the scanout */
2400 radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
2404 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
2406 tmp &= ~LATENCY_WATERMARK_MASK(3);
2407 tmp |= LATENCY_WATERMARK_MASK(1);
2408 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
2409 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
2410 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
2411 LATENCY_HIGH_WATERMARK(line_time)));
2413 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
2414 tmp &= ~LATENCY_WATERMARK_MASK(3);
2415 tmp |= LATENCY_WATERMARK_MASK(2);
2416 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
2417 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
2418 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
2419 LATENCY_HIGH_WATERMARK(line_time)));
2420 /* restore original selection */
2421 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
2423 /* write the priority marks */
2424 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
2425 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
2427 /* save values for DPM */
2428 radeon_crtc->line_time = line_time;
2429 radeon_crtc->wm_high = latency_watermark_a;
2430 radeon_crtc->wm_low = latency_watermark_b;
2433 void dce6_bandwidth_update(struct radeon_device *rdev)
2435 struct drm_display_mode *mode0 = NULL;
2436 struct drm_display_mode *mode1 = NULL;
2437 u32 num_heads = 0, lb_size;
2440 if (!rdev->mode_info.mode_config_initialized)
2443 radeon_update_display_priority(rdev);
2445 for (i = 0; i < rdev->num_crtc; i++) {
2446 if (rdev->mode_info.crtcs[i]->base.enabled)
2449 for (i = 0; i < rdev->num_crtc; i += 2) {
2450 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
2451 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
2452 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
2453 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
2454 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
2455 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
2462 static void si_tiling_mode_table_init(struct radeon_device *rdev)
2464 u32 *tile = rdev->config.si.tile_mode_array;
2465 const u32 num_tile_mode_states =
2466 ARRAY_SIZE(rdev->config.si.tile_mode_array);
2467 u32 reg_offset, split_equal_to_row_size;
2469 switch (rdev->config.si.mem_row_size_in_kb) {
2471 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
2475 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
2478 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
2482 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2483 tile[reg_offset] = 0;
2485 switch(rdev->family) {
2488 /* non-AA compressed depth or any compressed stencil */
2489 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2490 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2491 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2492 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2493 NUM_BANKS(ADDR_SURF_16_BANK) |
2494 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2495 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2496 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2497 /* 2xAA/4xAA compressed depth only */
2498 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2499 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2500 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2501 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2502 NUM_BANKS(ADDR_SURF_16_BANK) |
2503 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2504 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2505 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2506 /* 8xAA compressed depth only */
2507 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2508 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2509 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2510 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2511 NUM_BANKS(ADDR_SURF_16_BANK) |
2512 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2513 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2514 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2515 /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
2516 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2517 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2518 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2519 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2520 NUM_BANKS(ADDR_SURF_16_BANK) |
2521 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2524 /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
2525 tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2526 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2527 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2528 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2529 NUM_BANKS(ADDR_SURF_16_BANK) |
2530 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2531 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2532 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2533 /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
2534 tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2535 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2536 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2537 TILE_SPLIT(split_equal_to_row_size) |
2538 NUM_BANKS(ADDR_SURF_16_BANK) |
2539 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2540 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2541 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2542 /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
2543 tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2544 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2545 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2546 TILE_SPLIT(split_equal_to_row_size) |
2547 NUM_BANKS(ADDR_SURF_16_BANK) |
2548 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2549 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2550 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2551 /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
2552 tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2553 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2554 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2555 TILE_SPLIT(split_equal_to_row_size) |
2556 NUM_BANKS(ADDR_SURF_16_BANK) |
2557 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2558 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2559 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2560 /* 1D and 1D Array Surfaces */
2561 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2562 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2563 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2564 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2565 NUM_BANKS(ADDR_SURF_16_BANK) |
2566 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2567 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2568 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2569 /* Displayable maps. */
2570 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2571 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2572 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2573 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2574 NUM_BANKS(ADDR_SURF_16_BANK) |
2575 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2576 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2577 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2579 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2580 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2581 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2582 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2583 NUM_BANKS(ADDR_SURF_16_BANK) |
2584 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2585 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2586 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2587 /* Display 16bpp. */
2588 tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2589 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2590 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2591 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2592 NUM_BANKS(ADDR_SURF_16_BANK) |
2593 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2594 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2595 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2596 /* Display 32bpp. */
2597 tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2598 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2599 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2600 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2601 NUM_BANKS(ADDR_SURF_16_BANK) |
2602 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2603 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2604 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2606 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2607 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2608 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2609 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2610 NUM_BANKS(ADDR_SURF_16_BANK) |
2611 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2612 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2613 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2615 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2616 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2617 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2618 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2619 NUM_BANKS(ADDR_SURF_16_BANK) |
2620 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2621 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2622 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2624 tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2625 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2626 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2627 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2628 NUM_BANKS(ADDR_SURF_16_BANK) |
2629 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2630 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2631 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2633 tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2634 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2635 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2636 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2637 NUM_BANKS(ADDR_SURF_16_BANK) |
2638 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2639 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2640 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2642 tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2643 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2644 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2645 TILE_SPLIT(split_equal_to_row_size) |
2646 NUM_BANKS(ADDR_SURF_16_BANK) |
2647 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2648 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2649 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2651 tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2652 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2653 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2654 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2655 NUM_BANKS(ADDR_SURF_16_BANK) |
2656 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2657 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2658 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2660 tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2661 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2662 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2663 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2664 NUM_BANKS(ADDR_SURF_16_BANK) |
2665 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2666 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2667 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2669 tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2670 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2671 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2672 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2673 NUM_BANKS(ADDR_SURF_16_BANK) |
2674 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2675 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2676 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2678 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2679 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2680 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2681 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2682 NUM_BANKS(ADDR_SURF_16_BANK) |
2683 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2684 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2685 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2687 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2688 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2689 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2690 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
2691 NUM_BANKS(ADDR_SURF_8_BANK) |
2692 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2693 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2694 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2696 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2697 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
2703 /* non-AA compressed depth or any compressed stencil */
2704 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2705 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2706 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2707 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2708 NUM_BANKS(ADDR_SURF_16_BANK) |
2709 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2710 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2711 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2712 /* 2xAA/4xAA compressed depth only */
2713 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2714 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2715 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2716 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2717 NUM_BANKS(ADDR_SURF_16_BANK) |
2718 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2719 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2720 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2721 /* 8xAA compressed depth only */
2722 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2723 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2724 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2725 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2726 NUM_BANKS(ADDR_SURF_16_BANK) |
2727 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2728 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2729 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2730 /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
2731 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2732 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2733 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2734 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2735 NUM_BANKS(ADDR_SURF_16_BANK) |
2736 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2737 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2738 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2739 /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
2740 tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2741 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2742 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2743 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2744 NUM_BANKS(ADDR_SURF_16_BANK) |
2745 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2746 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2747 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2748 /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
2749 tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2750 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2751 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2752 TILE_SPLIT(split_equal_to_row_size) |
2753 NUM_BANKS(ADDR_SURF_16_BANK) |
2754 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2755 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2756 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2757 /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
2758 tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2759 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2760 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2761 TILE_SPLIT(split_equal_to_row_size) |
2762 NUM_BANKS(ADDR_SURF_16_BANK) |
2763 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2764 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2765 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2766 /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
2767 tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2768 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2769 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2770 TILE_SPLIT(split_equal_to_row_size) |
2771 NUM_BANKS(ADDR_SURF_16_BANK) |
2772 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2773 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2774 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2775 /* 1D and 1D Array Surfaces */
2776 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2777 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2778 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2779 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2780 NUM_BANKS(ADDR_SURF_16_BANK) |
2781 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2782 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2783 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2784 /* Displayable maps. */
2785 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2786 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2787 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2788 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2789 NUM_BANKS(ADDR_SURF_16_BANK) |
2790 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2791 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2792 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2794 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2795 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2796 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2797 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2798 NUM_BANKS(ADDR_SURF_16_BANK) |
2799 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2800 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2801 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2802 /* Display 16bpp. */
2803 tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2804 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2805 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2806 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2807 NUM_BANKS(ADDR_SURF_16_BANK) |
2808 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2809 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2810 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2811 /* Display 32bpp. */
2812 tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2813 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2814 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2815 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2816 NUM_BANKS(ADDR_SURF_16_BANK) |
2817 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2818 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2819 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2821 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2822 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2823 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2824 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2825 NUM_BANKS(ADDR_SURF_16_BANK) |
2826 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2827 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2828 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2830 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2831 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2832 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2833 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2834 NUM_BANKS(ADDR_SURF_16_BANK) |
2835 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2836 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2837 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2839 tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2840 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2841 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2842 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2843 NUM_BANKS(ADDR_SURF_16_BANK) |
2844 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2845 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2846 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2848 tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2849 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2850 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2851 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2852 NUM_BANKS(ADDR_SURF_16_BANK) |
2853 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2854 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2855 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2857 tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2858 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2859 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2860 TILE_SPLIT(split_equal_to_row_size) |
2861 NUM_BANKS(ADDR_SURF_16_BANK) |
2862 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2863 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2864 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2866 tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2867 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2868 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2869 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2870 NUM_BANKS(ADDR_SURF_16_BANK) |
2871 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2872 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2873 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2875 tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2876 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2877 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2878 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2879 NUM_BANKS(ADDR_SURF_16_BANK) |
2880 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2881 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2882 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2884 tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2885 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2886 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2887 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2888 NUM_BANKS(ADDR_SURF_16_BANK) |
2889 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2890 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2891 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2893 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2894 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2895 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2896 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2897 NUM_BANKS(ADDR_SURF_16_BANK) |
2898 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2899 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2900 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2902 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2903 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2904 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2905 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
2906 NUM_BANKS(ADDR_SURF_8_BANK) |
2907 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2908 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2909 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2911 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2912 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
2916 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
2920 static void si_select_se_sh(struct radeon_device *rdev,
2921 u32 se_num, u32 sh_num)
2923 u32 data = INSTANCE_BROADCAST_WRITES;
2925 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
2926 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
2927 else if (se_num == 0xffffffff)
2928 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
2929 else if (sh_num == 0xffffffff)
2930 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
2932 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
2933 WREG32(GRBM_GFX_INDEX, data);
2936 static u32 si_create_bitmask(u32 bit_width)
2940 for (i = 0; i < bit_width; i++) {
2947 static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
2951 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
2953 data &= INACTIVE_CUS_MASK;
2956 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
2958 data >>= INACTIVE_CUS_SHIFT;
2960 mask = si_create_bitmask(cu_per_sh);
2962 return ~data & mask;
2965 static void si_setup_spi(struct radeon_device *rdev,
2966 u32 se_num, u32 sh_per_se,
2970 u32 data, mask, active_cu;
2972 for (i = 0; i < se_num; i++) {
2973 for (j = 0; j < sh_per_se; j++) {
2974 si_select_se_sh(rdev, i, j);
2975 data = RREG32(SPI_STATIC_THREAD_MGMT_3);
2976 active_cu = si_get_cu_enabled(rdev, cu_per_sh);
2979 for (k = 0; k < 16; k++) {
2981 if (active_cu & mask) {
2983 WREG32(SPI_STATIC_THREAD_MGMT_3, data);
2989 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
2992 static u32 si_get_rb_disabled(struct radeon_device *rdev,
2993 u32 max_rb_num_per_se,
2998 data = RREG32(CC_RB_BACKEND_DISABLE);
3000 data &= BACKEND_DISABLE_MASK;
3003 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
3005 data >>= BACKEND_DISABLE_SHIFT;
3007 mask = si_create_bitmask(max_rb_num_per_se / sh_per_se);
3012 static void si_setup_rb(struct radeon_device *rdev,
3013 u32 se_num, u32 sh_per_se,
3014 u32 max_rb_num_per_se)
3018 u32 disabled_rbs = 0;
3019 u32 enabled_rbs = 0;
3021 for (i = 0; i < se_num; i++) {
3022 for (j = 0; j < sh_per_se; j++) {
3023 si_select_se_sh(rdev, i, j);
3024 data = si_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
3025 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
3028 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3031 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
3032 if (!(disabled_rbs & mask))
3033 enabled_rbs |= mask;
3037 rdev->config.si.backend_enable_mask = enabled_rbs;
3039 for (i = 0; i < se_num; i++) {
3040 si_select_se_sh(rdev, i, 0xffffffff);
3042 for (j = 0; j < sh_per_se; j++) {
3043 switch (enabled_rbs & 3) {
3045 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
3048 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
3052 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
3057 WREG32(PA_SC_RASTER_CONFIG, data);
3059 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3062 static void si_gpu_init(struct radeon_device *rdev)
3064 u32 gb_addr_config = 0;
3065 u32 mc_shared_chmap, mc_arb_ramcfg;
3067 u32 hdp_host_path_cntl;
3071 switch (rdev->family) {
3073 rdev->config.si.max_shader_engines = 2;
3074 rdev->config.si.max_tile_pipes = 12;
3075 rdev->config.si.max_cu_per_sh = 8;
3076 rdev->config.si.max_sh_per_se = 2;
3077 rdev->config.si.max_backends_per_se = 4;
3078 rdev->config.si.max_texture_channel_caches = 12;
3079 rdev->config.si.max_gprs = 256;
3080 rdev->config.si.max_gs_threads = 32;
3081 rdev->config.si.max_hw_contexts = 8;
3083 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3084 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
3085 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3086 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3087 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
3090 rdev->config.si.max_shader_engines = 2;
3091 rdev->config.si.max_tile_pipes = 8;
3092 rdev->config.si.max_cu_per_sh = 5;
3093 rdev->config.si.max_sh_per_se = 2;
3094 rdev->config.si.max_backends_per_se = 4;
3095 rdev->config.si.max_texture_channel_caches = 8;
3096 rdev->config.si.max_gprs = 256;
3097 rdev->config.si.max_gs_threads = 32;
3098 rdev->config.si.max_hw_contexts = 8;
3100 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3101 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
3102 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3103 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3104 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
3108 rdev->config.si.max_shader_engines = 1;
3109 rdev->config.si.max_tile_pipes = 4;
3110 rdev->config.si.max_cu_per_sh = 5;
3111 rdev->config.si.max_sh_per_se = 2;
3112 rdev->config.si.max_backends_per_se = 4;
3113 rdev->config.si.max_texture_channel_caches = 4;
3114 rdev->config.si.max_gprs = 256;
3115 rdev->config.si.max_gs_threads = 32;
3116 rdev->config.si.max_hw_contexts = 8;
3118 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3119 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
3120 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3121 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3122 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
3125 rdev->config.si.max_shader_engines = 1;
3126 rdev->config.si.max_tile_pipes = 4;
3127 rdev->config.si.max_cu_per_sh = 6;
3128 rdev->config.si.max_sh_per_se = 1;
3129 rdev->config.si.max_backends_per_se = 2;
3130 rdev->config.si.max_texture_channel_caches = 4;
3131 rdev->config.si.max_gprs = 256;
3132 rdev->config.si.max_gs_threads = 16;
3133 rdev->config.si.max_hw_contexts = 8;
3135 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3136 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
3137 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3138 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3139 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
3142 rdev->config.si.max_shader_engines = 1;
3143 rdev->config.si.max_tile_pipes = 4;
3144 rdev->config.si.max_cu_per_sh = 5;
3145 rdev->config.si.max_sh_per_se = 1;
3146 rdev->config.si.max_backends_per_se = 1;
3147 rdev->config.si.max_texture_channel_caches = 2;
3148 rdev->config.si.max_gprs = 256;
3149 rdev->config.si.max_gs_threads = 16;
3150 rdev->config.si.max_hw_contexts = 8;
3152 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3153 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
3154 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3155 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3156 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
3160 /* Initialize HDP */
3161 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
3162 WREG32((0x2c14 + j), 0x00000000);
3163 WREG32((0x2c18 + j), 0x00000000);
3164 WREG32((0x2c1c + j), 0x00000000);
3165 WREG32((0x2c20 + j), 0x00000000);
3166 WREG32((0x2c24 + j), 0x00000000);
3169 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
3170 WREG32(SRBM_INT_CNTL, 1);
3171 WREG32(SRBM_INT_ACK, 1);
3173 evergreen_fix_pci_max_read_req_size(rdev);
3175 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
3177 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
3178 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
3180 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
3181 rdev->config.si.mem_max_burst_length_bytes = 256;
3182 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
3183 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
3184 if (rdev->config.si.mem_row_size_in_kb > 4)
3185 rdev->config.si.mem_row_size_in_kb = 4;
3186 /* XXX use MC settings? */
3187 rdev->config.si.shader_engine_tile_size = 32;
3188 rdev->config.si.num_gpus = 1;
3189 rdev->config.si.multi_gpu_tile_size = 64;
3191 /* fix up row size */
3192 gb_addr_config &= ~ROW_SIZE_MASK;
3193 switch (rdev->config.si.mem_row_size_in_kb) {
3196 gb_addr_config |= ROW_SIZE(0);
3199 gb_addr_config |= ROW_SIZE(1);
3202 gb_addr_config |= ROW_SIZE(2);
3206 /* setup tiling info dword. gb_addr_config is not adequate since it does
3207 * not have bank info, so create a custom tiling dword.
3208 * bits 3:0 num_pipes
3209 * bits 7:4 num_banks
3210 * bits 11:8 group_size
3211 * bits 15:12 row_size
3213 rdev->config.si.tile_config = 0;
3214 switch (rdev->config.si.num_tile_pipes) {
3216 rdev->config.si.tile_config |= (0 << 0);
3219 rdev->config.si.tile_config |= (1 << 0);
3222 rdev->config.si.tile_config |= (2 << 0);
3226 /* XXX what about 12? */
3227 rdev->config.si.tile_config |= (3 << 0);
3230 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
3231 case 0: /* four banks */
3232 rdev->config.si.tile_config |= 0 << 4;
3234 case 1: /* eight banks */
3235 rdev->config.si.tile_config |= 1 << 4;
3237 case 2: /* sixteen banks */
3239 rdev->config.si.tile_config |= 2 << 4;
3242 rdev->config.si.tile_config |=
3243 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
3244 rdev->config.si.tile_config |=
3245 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
3247 WREG32(GB_ADDR_CONFIG, gb_addr_config);
3248 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
3249 WREG32(DMIF_ADDR_CALC, gb_addr_config);
3250 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
3251 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
3252 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
3253 if (rdev->has_uvd) {
3254 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
3255 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
3256 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
3259 si_tiling_mode_table_init(rdev);
3261 si_setup_rb(rdev, rdev->config.si.max_shader_engines,
3262 rdev->config.si.max_sh_per_se,
3263 rdev->config.si.max_backends_per_se);
3265 si_setup_spi(rdev, rdev->config.si.max_shader_engines,
3266 rdev->config.si.max_sh_per_se,
3267 rdev->config.si.max_cu_per_sh);
3269 rdev->config.si.active_cus = 0;
3270 for (i = 0; i < rdev->config.si.max_shader_engines; i++) {
3271 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) {
3272 rdev->config.si.active_cus +=
3273 hweight32(si_get_cu_active_bitmap(rdev, i, j));
3277 /* set HW defaults for 3D engine */
3278 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
3279 ROQ_IB2_START(0x2b)));
3280 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
3282 sx_debug_1 = RREG32(SX_DEBUG_1);
3283 WREG32(SX_DEBUG_1, sx_debug_1);
3285 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
3287 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
3288 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |
3289 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |
3290 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));
3292 WREG32(VGT_NUM_INSTANCES, 1);
3294 WREG32(CP_PERFMON_CNTL, 0);
3296 WREG32(SQ_CONFIG, 0);
3298 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
3299 FORCE_EOV_MAX_REZ_CNT(255)));
3301 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
3302 AUTO_INVLD_EN(ES_AND_GS_AUTO));
3304 WREG32(VGT_GS_VERTEX_REUSE, 16);
3305 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
3307 WREG32(CB_PERFCOUNTER0_SELECT0, 0);
3308 WREG32(CB_PERFCOUNTER0_SELECT1, 0);
3309 WREG32(CB_PERFCOUNTER1_SELECT0, 0);
3310 WREG32(CB_PERFCOUNTER1_SELECT1, 0);
3311 WREG32(CB_PERFCOUNTER2_SELECT0, 0);
3312 WREG32(CB_PERFCOUNTER2_SELECT1, 0);
3313 WREG32(CB_PERFCOUNTER3_SELECT0, 0);
3314 WREG32(CB_PERFCOUNTER3_SELECT1, 0);
3316 tmp = RREG32(HDP_MISC_CNTL);
3317 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
3318 WREG32(HDP_MISC_CNTL, tmp);
3320 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
3321 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
3323 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
3329 * GPU scratch registers helpers function.
3331 static void si_scratch_init(struct radeon_device *rdev)
3335 rdev->scratch.num_reg = 7;
3336 rdev->scratch.reg_base = SCRATCH_REG0;
3337 for (i = 0; i < rdev->scratch.num_reg; i++) {
3338 rdev->scratch.free[i] = true;
3339 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3343 void si_fence_ring_emit(struct radeon_device *rdev,
3344 struct radeon_fence *fence)
3346 struct radeon_ring *ring = &rdev->ring[fence->ring];
3347 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3349 /* flush read cache over gart */
3350 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3351 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
3352 radeon_ring_write(ring, 0);
3353 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3354 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3355 PACKET3_TC_ACTION_ENA |
3356 PACKET3_SH_KCACHE_ACTION_ENA |
3357 PACKET3_SH_ICACHE_ACTION_ENA);
3358 radeon_ring_write(ring, 0xFFFFFFFF);
3359 radeon_ring_write(ring, 0);
3360 radeon_ring_write(ring, 10); /* poll interval */
3361 /* EVENT_WRITE_EOP - flush caches, send int */
3362 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3363 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
3364 radeon_ring_write(ring, lower_32_bits(addr));
3365 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
3366 radeon_ring_write(ring, fence->seq);
3367 radeon_ring_write(ring, 0);
3373 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3375 struct radeon_ring *ring = &rdev->ring[ib->ring];
3376 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0;
3379 if (ib->is_const_ib) {
3380 /* set switch buffer packet before const IB */
3381 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3382 radeon_ring_write(ring, 0);
3384 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3387 if (ring->rptr_save_reg) {
3388 next_rptr = ring->wptr + 3 + 4 + 8;
3389 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3390 radeon_ring_write(ring, ((ring->rptr_save_reg -
3391 PACKET3_SET_CONFIG_REG_START) >> 2));
3392 radeon_ring_write(ring, next_rptr);
3393 } else if (rdev->wb.enabled) {
3394 next_rptr = ring->wptr + 5 + 4 + 8;
3395 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3396 radeon_ring_write(ring, (1 << 8));
3397 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3398 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
3399 radeon_ring_write(ring, next_rptr);
3402 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3405 radeon_ring_write(ring, header);
3406 radeon_ring_write(ring,
3410 (ib->gpu_addr & 0xFFFFFFFC));
3411 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3412 radeon_ring_write(ring, ib->length_dw | (vm_id << 24));
3414 if (!ib->is_const_ib) {
3415 /* flush read cache over gart for this vmid */
3416 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3417 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
3418 radeon_ring_write(ring, vm_id);
3419 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3420 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3421 PACKET3_TC_ACTION_ENA |
3422 PACKET3_SH_KCACHE_ACTION_ENA |
3423 PACKET3_SH_ICACHE_ACTION_ENA);
3424 radeon_ring_write(ring, 0xFFFFFFFF);
3425 radeon_ring_write(ring, 0);
3426 radeon_ring_write(ring, 10); /* poll interval */
3433 static void si_cp_enable(struct radeon_device *rdev, bool enable)
3436 WREG32(CP_ME_CNTL, 0);
3438 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
3439 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3440 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
3441 WREG32(SCRATCH_UMSK, 0);
3442 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3443 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3444 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3449 static int si_cp_load_microcode(struct radeon_device *rdev)
3453 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw)
3456 si_cp_enable(rdev, false);
3459 const struct gfx_firmware_header_v1_0 *pfp_hdr =
3460 (const struct gfx_firmware_header_v1_0 *)rdev->pfp_fw->data;
3461 const struct gfx_firmware_header_v1_0 *ce_hdr =
3462 (const struct gfx_firmware_header_v1_0 *)rdev->ce_fw->data;
3463 const struct gfx_firmware_header_v1_0 *me_hdr =
3464 (const struct gfx_firmware_header_v1_0 *)rdev->me_fw->data;
3465 const __le32 *fw_data;
3468 radeon_ucode_print_gfx_hdr(&pfp_hdr->header);
3469 radeon_ucode_print_gfx_hdr(&ce_hdr->header);
3470 radeon_ucode_print_gfx_hdr(&me_hdr->header);
3473 fw_data = (const __le32 *)
3474 (rdev->pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
3475 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
3476 WREG32(CP_PFP_UCODE_ADDR, 0);
3477 for (i = 0; i < fw_size; i++)
3478 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
3479 WREG32(CP_PFP_UCODE_ADDR, 0);
3482 fw_data = (const __le32 *)
3483 (rdev->ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
3484 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
3485 WREG32(CP_CE_UCODE_ADDR, 0);
3486 for (i = 0; i < fw_size; i++)
3487 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
3488 WREG32(CP_CE_UCODE_ADDR, 0);
3491 fw_data = (const __be32 *)
3492 (rdev->me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
3493 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
3494 WREG32(CP_ME_RAM_WADDR, 0);
git.samba.org / sfrench / cifs-2.6.git / blob