drivers/gpu/drm/radeon/rv6xx_dpm.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24
  25 #include "drmP.h"
  26 #include "radeon.h"
  27 #include "radeon_asic.h"
  28 #include "rv6xxd.h"
  29 #include "r600_dpm.h"
  30 #include "rv6xx_dpm.h"
  31 #include "atom.h"
  32 #include <linux/seq_file.h>
  33
  34 static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev,
  35                                         u32 unscaled_count, u32 unit);
  36
  37 static struct rv6xx_ps *rv6xx_get_ps(struct radeon_ps *rps)
  38 {
  39         struct rv6xx_ps *ps = rps->ps_priv;
  40
  41         return ps;
  42 }
  43
  44 static struct rv6xx_power_info *rv6xx_get_pi(struct radeon_device *rdev)
  45 {
  46         struct rv6xx_power_info *pi = rdev->pm.dpm.priv;
  47
  48         return pi;
  49 }
  50
  51 static void rv6xx_force_pcie_gen1(struct radeon_device *rdev)
  52 {
  53         u32 tmp;
  54         int i;
  55
  56         tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  57         tmp &= LC_GEN2_EN;
  58         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
  59
  60         tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  61         tmp |= LC_INITIATE_LINK_SPEED_CHANGE;
  62         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
  63
  64         for (i = 0; i < rdev->usec_timeout; i++) {
  65                 if (!(RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE))
  66                         break;
  67                 udelay(1);
  68         }
  69
  70         tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  71         tmp &= ~LC_INITIATE_LINK_SPEED_CHANGE;
  72         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
  73 }
  74
  75 static void rv6xx_enable_pcie_gen2_support(struct radeon_device *rdev)
  76 {
  77         u32 tmp;
  78
  79         tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  80
  81         if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
  82             (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
  83                 tmp |= LC_GEN2_EN;
  84                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
  85         }
  86 }
  87
  88 static void rv6xx_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
  89                                                bool enable)
  90 {
  91         u32 tmp;
  92
  93         tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
  94         if (enable)
  95                 tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
  96         else
  97                 tmp |= LC_HW_VOLTAGE_IF_CONTROL(0);
  98         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
  99 }
 100
 101 static void rv6xx_enable_l0s(struct radeon_device *rdev)
 102 {
 103         u32 tmp;
 104
 105         tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L0S_INACTIVITY_MASK;
 106         tmp |= LC_L0S_INACTIVITY(3);
 107         WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
 108 }
 109
 110 static void rv6xx_enable_l1(struct radeon_device *rdev)
 111 {
 112         u32 tmp;
 113
 114         tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL);
 115         tmp &= ~LC_L1_INACTIVITY_MASK;
 116         tmp |= LC_L1_INACTIVITY(4);
 117         tmp &= ~LC_PMI_TO_L1_DIS;
 118         tmp &= ~LC_ASPM_TO_L1_DIS;
 119         WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
 120 }
 121
 122 static void rv6xx_enable_pll_sleep_in_l1(struct radeon_device *rdev)
 123 {
 124         u32 tmp;
 125
 126         tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L1_INACTIVITY_MASK;
 127         tmp |= LC_L1_INACTIVITY(8);
 128         WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
 129
 130         /* NOTE, this is a PCIE indirect reg, not PCIE PORT */
 131         tmp = RREG32_PCIE(PCIE_P_CNTL);
 132         tmp |= P_PLL_PWRDN_IN_L1L23;
 133         tmp &= ~P_PLL_BUF_PDNB;
 134         tmp &= ~P_PLL_PDNB;
 135         tmp |= P_ALLOW_PRX_FRONTEND_SHUTOFF;
 136         WREG32_PCIE(PCIE_P_CNTL, tmp);
 137 }
 138
 139 static int rv6xx_convert_clock_to_stepping(struct radeon_device *rdev,
 140                                            u32 clock, struct rv6xx_sclk_stepping *step)
 141 {
 142         int ret;
 143         struct atom_clock_dividers dividers;
 144
 145         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 146                                              clock, false, &dividers);
 147         if (ret)
 148                 return ret;
 149
 150         if (dividers.enable_post_div)
 151                 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4);
 152         else
 153                 step->post_divider = 1;
 154
 155         step->vco_frequency = clock * step->post_divider;
 156
 157         return 0;
 158 }
 159
 160 static void rv6xx_output_stepping(struct radeon_device *rdev,
 161                                   u32 step_index, struct rv6xx_sclk_stepping *step)
 162 {
 163         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 164         u32 ref_clk = rdev->clock.spll.reference_freq;
 165         u32 fb_divider;
 166         u32 spll_step_count = rv6xx_scale_count_given_unit(rdev,
 167                                                            R600_SPLLSTEPTIME_DFLT *
 168                                                            pi->spll_ref_div,
 169                                                            R600_SPLLSTEPUNIT_DFLT);
 170
 171         r600_engine_clock_entry_enable(rdev, step_index, true);
 172         r600_engine_clock_entry_enable_pulse_skipping(rdev, step_index, false);
 173
 174         if (step->post_divider == 1)
 175                 r600_engine_clock_entry_enable_post_divider(rdev, step_index, false);
 176         else {
 177                 u32 lo_len = (step->post_divider - 2) / 2;
 178                 u32 hi_len = step->post_divider - 2 - lo_len;
 179
 180                 r600_engine_clock_entry_enable_post_divider(rdev, step_index, true);
 181                 r600_engine_clock_entry_set_post_divider(rdev, step_index, (hi_len << 4) | lo_len);
 182         }
 183
 184         fb_divider = ((step->vco_frequency * pi->spll_ref_div) / ref_clk) >>
 185                 pi->fb_div_scale;
 186
 187         r600_engine_clock_entry_set_reference_divider(rdev, step_index,
 188                                                       pi->spll_ref_div - 1);
 189         r600_engine_clock_entry_set_feedback_divider(rdev, step_index, fb_divider);
 190         r600_engine_clock_entry_set_step_time(rdev, step_index, spll_step_count);
 191
 192 }
 193
 194 static struct rv6xx_sclk_stepping rv6xx_next_vco_step(struct radeon_device *rdev,
 195                                                       struct rv6xx_sclk_stepping *cur,
 196                                                       bool increasing_vco, u32 step_size)
 197 {
 198         struct rv6xx_sclk_stepping next;
 199
 200         next.post_divider = cur->post_divider;
 201
 202         if (increasing_vco)
 203                 next.vco_frequency = (cur->vco_frequency * (100 + step_size)) / 100;
 204         else
 205                 next.vco_frequency = (cur->vco_frequency * 100 + 99 + step_size) / (100 + step_size);
 206
 207         return next;
 208 }
 209
 210 static bool rv6xx_can_step_post_div(struct radeon_device *rdev,
 211                                     struct rv6xx_sclk_stepping *cur,
 212                                     struct rv6xx_sclk_stepping *target)
 213 {
 214         return (cur->post_divider > target->post_divider) &&
 215                 ((cur->vco_frequency * target->post_divider) <=
 216                  (target->vco_frequency * (cur->post_divider - 1)));
 217 }
 218
 219 static struct rv6xx_sclk_stepping rv6xx_next_post_div_step(struct radeon_device *rdev,
 220                                                            struct rv6xx_sclk_stepping *cur,
 221                                                            struct rv6xx_sclk_stepping *target)
 222 {
 223         struct rv6xx_sclk_stepping next = *cur;
 224
 225         while (rv6xx_can_step_post_div(rdev, &next, target))
 226                 next.post_divider--;
 227
 228         return next;
 229 }
 230
 231 static bool rv6xx_reached_stepping_target(struct radeon_device *rdev,
 232                                           struct rv6xx_sclk_stepping *cur,
 233                                           struct rv6xx_sclk_stepping *target,
 234                                           bool increasing_vco)
 235 {
 236         return (increasing_vco && (cur->vco_frequency >= target->vco_frequency)) ||
 237                 (!increasing_vco && (cur->vco_frequency <= target->vco_frequency));
 238 }
 239
 240 static void rv6xx_generate_steps(struct radeon_device *rdev,
 241                                  u32 low, u32 high,
 242                                  u32 start_index, u8 *end_index)
 243 {
 244         struct rv6xx_sclk_stepping cur;
 245         struct rv6xx_sclk_stepping target;
 246         bool increasing_vco;
 247         u32 step_index = start_index;
 248
 249         rv6xx_convert_clock_to_stepping(rdev, low, &cur);
 250         rv6xx_convert_clock_to_stepping(rdev, high, &target);
 251
 252         rv6xx_output_stepping(rdev, step_index++, &cur);
 253
 254         increasing_vco = (target.vco_frequency >= cur.vco_frequency);
 255
 256         if (target.post_divider > cur.post_divider)
 257                 cur.post_divider = target.post_divider;
 258
 259         while (1) {
 260                 struct rv6xx_sclk_stepping next;
 261
 262                 if (rv6xx_can_step_post_div(rdev, &cur, &target))
 263                         next = rv6xx_next_post_div_step(rdev, &cur, &target);
 264                 else
 265                         next = rv6xx_next_vco_step(rdev, &cur, increasing_vco, R600_VCOSTEPPCT_DFLT);
 266
 267                 if (rv6xx_reached_stepping_target(rdev, &next, &target, increasing_vco)) {
 268                         struct rv6xx_sclk_stepping tiny =
 269                                 rv6xx_next_vco_step(rdev, &target, !increasing_vco, R600_ENDINGVCOSTEPPCT_DFLT);
 270                         tiny.post_divider = next.post_divider;
 271
 272                         if (!rv6xx_reached_stepping_target(rdev, &tiny, &cur, !increasing_vco))
 273                                 rv6xx_output_stepping(rdev, step_index++, &tiny);
 274
 275                         if ((next.post_divider != target.post_divider) &&
 276                             (next.vco_frequency != target.vco_frequency)) {
 277                                 struct rv6xx_sclk_stepping final_vco;
 278
 279                                 final_vco.vco_frequency = target.vco_frequency;
 280                                 final_vco.post_divider = next.post_divider;
 281
 282                                 rv6xx_output_stepping(rdev, step_index++, &final_vco);
 283                         }
 284
 285                         rv6xx_output_stepping(rdev, step_index++, &target);
 286                         break;
 287                 } else
 288                         rv6xx_output_stepping(rdev, step_index++, &next);
 289
 290                 cur = next;
 291         }
 292
 293         *end_index = (u8)step_index - 1;
 294
 295 }
 296
 297 static void rv6xx_generate_single_step(struct radeon_device *rdev,
 298                                        u32 clock, u32 index)
 299 {
 300         struct rv6xx_sclk_stepping step;
 301
 302         rv6xx_convert_clock_to_stepping(rdev, clock, &step);
 303         rv6xx_output_stepping(rdev, index, &step);
 304 }
 305
 306 static void rv6xx_invalidate_intermediate_steps_range(struct radeon_device *rdev,
 307                                                       u32 start_index, u32 end_index)
 308 {
 309         u32 step_index;
 310
 311         for (step_index = start_index + 1; step_index < end_index; step_index++)
 312                 r600_engine_clock_entry_enable(rdev, step_index, false);
 313 }
 314
 315 static void rv6xx_set_engine_spread_spectrum_clk_s(struct radeon_device *rdev,
 316                                                    u32 index, u32 clk_s)
 317 {
 318         WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
 319                  CLKS(clk_s), ~CLKS_MASK);
 320 }
 321
 322 static void rv6xx_set_engine_spread_spectrum_clk_v(struct radeon_device *rdev,
 323                                                    u32 index, u32 clk_v)
 324 {
 325         WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
 326                  CLKV(clk_v), ~CLKV_MASK);
 327 }
 328
 329 static void rv6xx_enable_engine_spread_spectrum(struct radeon_device *rdev,
 330                                                 u32 index, bool enable)
 331 {
 332         if (enable)
 333                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
 334                          SSEN, ~SSEN);
 335         else
 336                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
 337                          0, ~SSEN);
 338 }
 339
 340 static void rv6xx_set_memory_spread_spectrum_clk_s(struct radeon_device *rdev,
 341                                                    u32 clk_s)
 342 {
 343         WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKS(clk_s), ~CLKS_MASK);
 344 }
 345
 346 static void rv6xx_set_memory_spread_spectrum_clk_v(struct radeon_device *rdev,
 347                                                    u32 clk_v)
 348 {
 349         WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKV(clk_v), ~CLKV_MASK);
 350 }
 351
 352 static void rv6xx_enable_memory_spread_spectrum(struct radeon_device *rdev,
 353                                                 bool enable)
 354 {
 355         if (enable)
 356                 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, SSEN, ~SSEN);
 357         else
 358                 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN);
 359 }
 360
 361 static void rv6xx_enable_dynamic_spread_spectrum(struct radeon_device *rdev,
 362                                                  bool enable)
 363 {
 364         if (enable)
 365                 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
 366         else
 367                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
 368 }
 369
 370 static void rv6xx_memory_clock_entry_enable_post_divider(struct radeon_device *rdev,
 371                                                          u32 index, bool enable)
 372 {
 373         if (enable)
 374                 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
 375                          LEVEL0_MPLL_DIV_EN, ~LEVEL0_MPLL_DIV_EN);
 376         else
 377                 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), 0, ~LEVEL0_MPLL_DIV_EN);
 378 }
 379
 380 static void rv6xx_memory_clock_entry_set_post_divider(struct radeon_device *rdev,
 381                                                       u32 index, u32 divider)
 382 {
 383         WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
 384                  LEVEL0_MPLL_POST_DIV(divider), ~LEVEL0_MPLL_POST_DIV_MASK);
 385 }
 386
 387 static void rv6xx_memory_clock_entry_set_feedback_divider(struct radeon_device *rdev,
 388                                                           u32 index, u32 divider)
 389 {
 390         WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), LEVEL0_MPLL_FB_DIV(divider),
 391                  ~LEVEL0_MPLL_FB_DIV_MASK);
 392 }
 393
 394 static void rv6xx_memory_clock_entry_set_reference_divider(struct radeon_device *rdev,
 395                                                            u32 index, u32 divider)
 396 {
 397         WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
 398                  LEVEL0_MPLL_REF_DIV(divider), ~LEVEL0_MPLL_REF_DIV_MASK);
 399 }
 400
 401 static void rv6xx_vid_response_set_brt(struct radeon_device *rdev, u32 rt)
 402 {
 403         WREG32_P(VID_RT, BRT(rt), ~BRT_MASK);
 404 }
 405
 406 static void rv6xx_enable_engine_feedback_and_reference_sync(struct radeon_device *rdev)
 407 {
 408         WREG32_P(SPLL_CNTL_MODE, SPLL_DIV_SYNC, ~SPLL_DIV_SYNC);
 409 }
 410
 411 static u32 rv6xx_clocks_per_unit(u32 unit)
 412 {
 413         u32 tmp = 1 << (2 * unit);
 414
 415         return tmp;
 416 }
 417
 418 static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev,
 419                                         u32 unscaled_count, u32 unit)
 420 {
 421         u32 count_per_unit = rv6xx_clocks_per_unit(unit);
 422
 423         return (unscaled_count + count_per_unit - 1) / count_per_unit;
 424 }
 425
 426 static u32 rv6xx_compute_count_for_delay(struct radeon_device *rdev,
 427                                          u32 delay_us, u32 unit)
 428 {
 429         u32 ref_clk = rdev->clock.spll.reference_freq;
 430
 431         return rv6xx_scale_count_given_unit(rdev, delay_us * (ref_clk / 100), unit);
 432 }
 433
 434 static void rv6xx_calculate_engine_speed_stepping_parameters(struct radeon_device *rdev,
 435                                                              struct rv6xx_ps *state)
 436 {
 437         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 438
 439         pi->hw.sclks[R600_POWER_LEVEL_LOW] =
 440                 state->low.sclk;
 441         pi->hw.sclks[R600_POWER_LEVEL_MEDIUM] =
 442                 state->medium.sclk;
 443         pi->hw.sclks[R600_POWER_LEVEL_HIGH] =
 444                 state->high.sclk;
 445
 446         pi->hw.low_sclk_index = R600_POWER_LEVEL_LOW;
 447         pi->hw.medium_sclk_index = R600_POWER_LEVEL_MEDIUM;
 448         pi->hw.high_sclk_index = R600_POWER_LEVEL_HIGH;
 449 }
 450
 451 static void rv6xx_calculate_memory_clock_stepping_parameters(struct radeon_device *rdev,
 452                                                              struct rv6xx_ps *state)
 453 {
 454         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 455
 456         pi->hw.mclks[R600_POWER_LEVEL_CTXSW] =
 457                 state->high.mclk;
 458         pi->hw.mclks[R600_POWER_LEVEL_HIGH] =
 459                 state->high.mclk;
 460         pi->hw.mclks[R600_POWER_LEVEL_MEDIUM] =
 461                 state->medium.mclk;
 462         pi->hw.mclks[R600_POWER_LEVEL_LOW] =
 463                 state->low.mclk;
 464
 465         pi->hw.high_mclk_index = R600_POWER_LEVEL_HIGH;
 466
 467         if (state->high.mclk == state->medium.mclk)
 468                 pi->hw.medium_mclk_index =
 469                         pi->hw.high_mclk_index;
 470         else
 471                 pi->hw.medium_mclk_index = R600_POWER_LEVEL_MEDIUM;
 472
 473
 474         if (state->medium.mclk == state->low.mclk)
 475                 pi->hw.low_mclk_index =
 476                         pi->hw.medium_mclk_index;
 477         else
 478                 pi->hw.low_mclk_index = R600_POWER_LEVEL_LOW;
 479 }
 480
 481 static void rv6xx_calculate_voltage_stepping_parameters(struct radeon_device *rdev,
 482                                                         struct rv6xx_ps *state)
 483 {
 484         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 485
 486         pi->hw.vddc[R600_POWER_LEVEL_CTXSW] = state->high.vddc;
 487         pi->hw.vddc[R600_POWER_LEVEL_HIGH] = state->high.vddc;
 488         pi->hw.vddc[R600_POWER_LEVEL_MEDIUM] = state->medium.vddc;
 489         pi->hw.vddc[R600_POWER_LEVEL_LOW] = state->low.vddc;
 490
 491         pi->hw.backbias[R600_POWER_LEVEL_CTXSW] =
 492                 (state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
 493         pi->hw.backbias[R600_POWER_LEVEL_HIGH] =
 494                 (state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
 495         pi->hw.backbias[R600_POWER_LEVEL_MEDIUM] =
 496                 (state->medium.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
 497         pi->hw.backbias[R600_POWER_LEVEL_LOW] =
 498                 (state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
 499
 500         pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH] =
 501                 (state->high.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false;
 502         pi->hw.pcie_gen2[R600_POWER_LEVEL_MEDIUM] =
 503                 (state->medium.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false;
 504         pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW] =
 505                 (state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false;
 506
 507         pi->hw.high_vddc_index = R600_POWER_LEVEL_HIGH;
 508
 509         if ((state->high.vddc == state->medium.vddc) &&
 510             ((state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ==
 511              (state->medium.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE)))
 512                 pi->hw.medium_vddc_index =
 513                         pi->hw.high_vddc_index;
 514         else
 515                 pi->hw.medium_vddc_index = R600_POWER_LEVEL_MEDIUM;
 516
 517         if ((state->medium.vddc == state->low.vddc) &&
 518             ((state->medium.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ==
 519              (state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE)))
 520                 pi->hw.low_vddc_index =
 521                         pi->hw.medium_vddc_index;
 522         else
 523                 pi->hw.medium_vddc_index = R600_POWER_LEVEL_LOW;
 524 }
 525
 526 static inline u32 rv6xx_calculate_vco_frequency(u32 ref_clock,
 527                                                 struct atom_clock_dividers *dividers,
 528                                                 u32 fb_divider_scale)
 529 {
 530         return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) /
 531                 (dividers->ref_div + 1);
 532 }
 533
 534 static inline u32 rv6xx_calculate_spread_spectrum_clk_v(u32 vco_freq, u32 ref_freq,
 535                                                         u32 ss_rate, u32 ss_percent,
 536                                                         u32 fb_divider_scale)
 537 {
 538         u32 fb_divider = vco_freq / ref_freq;
 539
 540         return (ss_percent * ss_rate * 4 * (fb_divider * fb_divider) /
 541                 (5375 * ((vco_freq * 10) / (4096 >> fb_divider_scale))));
 542 }
 543
 544 static inline u32 rv6xx_calculate_spread_spectrum_clk_s(u32 ss_rate, u32 ref_freq)
 545 {
 546         return (((ref_freq * 10) / (ss_rate * 2)) - 1) / 4;
 547 }
 548
 549 static void rv6xx_program_engine_spread_spectrum(struct radeon_device *rdev,
 550                                                  u32 clock, enum r600_power_level level)
 551 {
 552         u32 ref_clk = rdev->clock.spll.reference_freq;
 553         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 554         struct atom_clock_dividers dividers;
 555         struct radeon_atom_ss ss;
 556         u32 vco_freq, clk_v, clk_s;
 557
 558         rv6xx_enable_engine_spread_spectrum(rdev, level, false);
 559
 560         if (clock && pi->sclk_ss) {
 561                 if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, &dividers) == 0) {
 562                         vco_freq = rv6xx_calculate_vco_frequency(ref_clk, &dividers,
 563                                                                  pi->fb_div_scale);
 564
 565                         if (radeon_atombios_get_asic_ss_info(rdev, &ss,
 566                                                              ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
 567                                 clk_v = rv6xx_calculate_spread_spectrum_clk_v(vco_freq,
 568                                                                               (ref_clk / (dividers.ref_div + 1)),
 569                                                                               ss.rate,
 570                                                                               ss.percentage,
 571                                                                               pi->fb_div_scale);
 572
 573                                 clk_s = rv6xx_calculate_spread_spectrum_clk_s(ss.rate,
 574                                                                               (ref_clk / (dividers.ref_div + 1)));
 575
 576                                 rv6xx_set_engine_spread_spectrum_clk_v(rdev, level, clk_v);
 577                                 rv6xx_set_engine_spread_spectrum_clk_s(rdev, level, clk_s);
 578                                 rv6xx_enable_engine_spread_spectrum(rdev, level, true);
 579                         }
 580                 }
 581         }
 582 }
 583
 584 static void rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry(struct radeon_device *rdev)
 585 {
 586         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 587
 588         rv6xx_program_engine_spread_spectrum(rdev,
 589                                              pi->hw.sclks[R600_POWER_LEVEL_HIGH],
 590                                              R600_POWER_LEVEL_HIGH);
 591
 592         rv6xx_program_engine_spread_spectrum(rdev,
 593                                              pi->hw.sclks[R600_POWER_LEVEL_MEDIUM],
 594                                              R600_POWER_LEVEL_MEDIUM);
 595
 596 }
 597
 598 static int rv6xx_program_mclk_stepping_entry(struct radeon_device *rdev,
 599                                              u32 entry, u32 clock)
 600 {
 601         struct atom_clock_dividers dividers;
 602
 603         if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, clock, false, &dividers))
 604             return -EINVAL;
 605
 606
 607         rv6xx_memory_clock_entry_set_reference_divider(rdev, entry, dividers.ref_div);
 608         rv6xx_memory_clock_entry_set_feedback_divider(rdev, entry, dividers.fb_div);
 609         rv6xx_memory_clock_entry_set_post_divider(rdev, entry, dividers.post_div);
 610
 611         if (dividers.enable_post_div)
 612                 rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, true);
 613         else
 614                 rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, false);
 615
 616         return 0;
 617 }
 618
 619 static void rv6xx_program_mclk_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
 620 {
 621         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 622         int i;
 623
 624         for (i = 1; i < R600_PM_NUMBER_OF_MCLKS; i++) {
 625                 if (pi->hw.mclks[i])
 626                         rv6xx_program_mclk_stepping_entry(rdev, i,
 627                                                           pi->hw.mclks[i]);
 628         }
 629 }
 630
 631 static void rv6xx_find_memory_clock_with_highest_vco(struct radeon_device *rdev,
 632                                                      u32 requested_memory_clock,
 633                                                      u32 ref_clk,
 634                                                      struct atom_clock_dividers *dividers,
 635                                                      u32 *vco_freq)
 636 {
 637         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 638         struct atom_clock_dividers req_dividers;
 639         u32 vco_freq_temp;
 640
 641         if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
 642                                            requested_memory_clock, false, &req_dividers) == 0) {
 643                 vco_freq_temp = rv6xx_calculate_vco_frequency(ref_clk, &req_dividers,
 644                                                               pi->fb_div_scale);
 645
 646                 if (vco_freq_temp > *vco_freq) {
 647                         *dividers = req_dividers;
 648                         *vco_freq = vco_freq_temp;
 649                 }
 650         }
 651 }
 652
 653 static void rv6xx_program_mclk_spread_spectrum_parameters(struct radeon_device *rdev)
 654 {
 655         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 656         u32 ref_clk = rdev->clock.mpll.reference_freq;
 657         struct atom_clock_dividers dividers;
 658         struct radeon_atom_ss ss;
 659         u32 vco_freq = 0, clk_v, clk_s;
 660
 661         rv6xx_enable_memory_spread_spectrum(rdev, false);
 662
 663         if (pi->mclk_ss) {
 664                 rv6xx_find_memory_clock_with_highest_vco(rdev,
 665                                                          pi->hw.mclks[pi->hw.high_mclk_index],
 666                                                          ref_clk,
 667                                                          &dividers,
 668                                                          &vco_freq);
 669
 670                 rv6xx_find_memory_clock_with_highest_vco(rdev,
 671                                                          pi->hw.mclks[pi->hw.medium_mclk_index],
 672                                                          ref_clk,
 673                                                          &dividers,
 674                                                          &vco_freq);
 675
 676                 rv6xx_find_memory_clock_with_highest_vco(rdev,
 677                                                          pi->hw.mclks[pi->hw.low_mclk_index],
 678                                                          ref_clk,
 679                                                          &dividers,
 680                                                          &vco_freq);
 681
 682                 if (vco_freq) {
 683                         if (radeon_atombios_get_asic_ss_info(rdev, &ss,
 684                                                              ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
 685                                 clk_v = rv6xx_calculate_spread_spectrum_clk_v(vco_freq,
 686                                                                              (ref_clk / (dividers.ref_div + 1)),
 687                                                                              ss.rate,
 688                                                                              ss.percentage,
 689                                                                              pi->fb_div_scale);
 690
 691                                 clk_s = rv6xx_calculate_spread_spectrum_clk_s(ss.rate,
 692                                                                              (ref_clk / (dividers.ref_div + 1)));
 693
 694                                 rv6xx_set_memory_spread_spectrum_clk_v(rdev, clk_v);
 695                                 rv6xx_set_memory_spread_spectrum_clk_s(rdev, clk_s);
 696                                 rv6xx_enable_memory_spread_spectrum(rdev, true);
 697                         }
 698                 }
 699         }
 700 }
 701
 702 static int rv6xx_program_voltage_stepping_entry(struct radeon_device *rdev,
 703                                                 u32 entry, u16 voltage)
 704 {
 705         u32 mask, set_pins;
 706         int ret;
 707
 708         ret = radeon_atom_get_voltage_gpio_settings(rdev, voltage,
 709                                                     SET_VOLTAGE_TYPE_ASIC_VDDC,
 710                                                     &set_pins, &mask);
 711         if (ret)
 712                 return ret;
 713
 714         r600_voltage_control_program_voltages(rdev, entry, set_pins);
 715
 716         return 0;
 717 }
 718
 719 static void rv6xx_program_voltage_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
 720 {
 721         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 722         int i;
 723
 724         for (i = 1; i < R600_PM_NUMBER_OF_VOLTAGE_LEVELS; i++)
 725                 rv6xx_program_voltage_stepping_entry(rdev, i,
 726                                                      pi->hw.vddc[i]);
 727
 728 }
 729
 730 static void rv6xx_program_backbias_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
 731 {
 732         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 733
 734         if (pi->hw.backbias[1])
 735                 WREG32_P(VID_UPPER_GPIO_CNTL, MEDIUM_BACKBIAS_VALUE, ~MEDIUM_BACKBIAS_VALUE);
 736         else
 737                 WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~MEDIUM_BACKBIAS_VALUE);
 738
 739         if (pi->hw.backbias[2])
 740                 WREG32_P(VID_UPPER_GPIO_CNTL, HIGH_BACKBIAS_VALUE, ~HIGH_BACKBIAS_VALUE);
 741         else
 742                 WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~HIGH_BACKBIAS_VALUE);
 743 }
 744
 745 static void rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry(struct radeon_device *rdev)
 746 {
 747         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 748
 749         rv6xx_program_engine_spread_spectrum(rdev,
 750                                              pi->hw.sclks[R600_POWER_LEVEL_LOW],
 751                                              R600_POWER_LEVEL_LOW);
 752 }
 753
 754 static void rv6xx_program_mclk_stepping_parameters_lowest_entry(struct radeon_device *rdev)
 755 {
 756         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 757
 758         if (pi->hw.mclks[0])
 759                 rv6xx_program_mclk_stepping_entry(rdev, 0,
 760                                                   pi->hw.mclks[0]);
 761 }
 762
 763 static void rv6xx_program_voltage_stepping_parameters_lowest_entry(struct radeon_device *rdev)
 764 {
 765         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 766
 767         rv6xx_program_voltage_stepping_entry(rdev, 0,
 768                                              pi->hw.vddc[0]);
 769
 770 }
 771
 772 static void rv6xx_program_backbias_stepping_parameters_lowest_entry(struct radeon_device *rdev)
 773 {
 774         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 775
 776         if (pi->hw.backbias[0])
 777                 WREG32_P(VID_UPPER_GPIO_CNTL, LOW_BACKBIAS_VALUE, ~LOW_BACKBIAS_VALUE);
 778         else
 779                 WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~LOW_BACKBIAS_VALUE);
 780 }
 781
 782 static u32 calculate_memory_refresh_rate(struct radeon_device *rdev,
 783                                          u32 engine_clock)
 784 {
 785         u32 dram_rows, dram_refresh_rate;
 786         u32 tmp;
 787
 788         tmp = (RREG32(RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
 789         dram_rows = 1 << (tmp + 10);
 790         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_RESERVE_M) & 0x3) + 3);
 791
 792         return ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
 793 }
 794
 795 static void rv6xx_program_memory_timing_parameters(struct radeon_device *rdev)
 796 {
 797         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 798         u32 sqm_ratio;
 799         u32 arb_refresh_rate;
 800         u32 high_clock;
 801
 802         if (pi->hw.sclks[R600_POWER_LEVEL_HIGH] <
 803             (pi->hw.sclks[R600_POWER_LEVEL_LOW] * 0xFF / 0x40))
 804                 high_clock = pi->hw.sclks[R600_POWER_LEVEL_HIGH];
 805         else
 806                 high_clock =
 807                         pi->hw.sclks[R600_POWER_LEVEL_LOW] * 0xFF / 0x40;
 808
 809         radeon_atom_set_engine_dram_timings(rdev, high_clock, 0);
 810
 811         sqm_ratio = (STATE0(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_LOW]) |
 812                      STATE1(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_MEDIUM]) |
 813                      STATE2(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_HIGH]) |
 814                      STATE3(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_HIGH]));
 815         WREG32(SQM_RATIO, sqm_ratio);
 816
 817         arb_refresh_rate =
 818                 (POWERMODE0(calculate_memory_refresh_rate(rdev,
 819                                                           pi->hw.sclks[R600_POWER_LEVEL_LOW])) |
 820                  POWERMODE1(calculate_memory_refresh_rate(rdev,
 821                                                           pi->hw.sclks[R600_POWER_LEVEL_MEDIUM])) |
 822                  POWERMODE2(calculate_memory_refresh_rate(rdev,
 823                                                           pi->hw.sclks[R600_POWER_LEVEL_HIGH])) |
 824                  POWERMODE3(calculate_memory_refresh_rate(rdev,
 825                                                           pi->hw.sclks[R600_POWER_LEVEL_HIGH])));
 826         WREG32(ARB_RFSH_RATE, arb_refresh_rate);
 827 }
 828
 829 static void rv6xx_program_mpll_timing_parameters(struct radeon_device *rdev)
 830 {
 831         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 832
 833         r600_set_mpll_lock_time(rdev, R600_MPLLLOCKTIME_DFLT *
 834                                 pi->mpll_ref_div);
 835         r600_set_mpll_reset_time(rdev, R600_MPLLRESETTIME_DFLT);
 836 }
 837
 838 static void rv6xx_program_bsp(struct radeon_device *rdev)
 839 {
 840         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 841         u32 ref_clk = rdev->clock.spll.reference_freq;
 842
 843         r600_calculate_u_and_p(R600_ASI_DFLT,
 844                                ref_clk, 16,
 845                                &pi->bsp,
 846                                &pi->bsu);
 847
 848         r600_set_bsp(rdev, pi->bsu, pi->bsp);
 849 }
 850
 851 static void rv6xx_program_at(struct radeon_device *rdev)
 852 {
 853         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 854
 855         r600_set_at(rdev,
 856                     (pi->hw.rp[0] * pi->bsp) / 200,
 857                     (pi->hw.rp[1] * pi->bsp) / 200,
 858                     (pi->hw.lp[2] * pi->bsp) / 200,
 859                     (pi->hw.lp[1] * pi->bsp) / 200);
 860 }
 861
 862 static void rv6xx_program_git(struct radeon_device *rdev)
 863 {
 864         r600_set_git(rdev, R600_GICST_DFLT);
 865 }
 866
 867 static void rv6xx_program_tp(struct radeon_device *rdev)
 868 {
 869         int i;
 870
 871         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
 872                 r600_set_tc(rdev, i, r600_utc[i], r600_dtc[i]);
 873
 874         r600_select_td(rdev, R600_TD_DFLT);
 875 }
 876
 877 static void rv6xx_program_vc(struct radeon_device *rdev)
 878 {
 879         r600_set_vrc(rdev, R600_VRC_DFLT);
 880 }
 881
 882 static void rv6xx_clear_vc(struct radeon_device *rdev)
 883 {
 884         r600_set_vrc(rdev, 0);
 885 }
 886
 887 static void rv6xx_program_tpp(struct radeon_device *rdev)
 888 {
 889         r600_set_tpu(rdev, R600_TPU_DFLT);
 890         r600_set_tpc(rdev, R600_TPC_DFLT);
 891 }
 892
 893 static void rv6xx_program_sstp(struct radeon_device *rdev)
 894 {
 895         r600_set_sstu(rdev, R600_SSTU_DFLT);
 896         r600_set_sst(rdev, R600_SST_DFLT);
 897 }
 898
 899 static void rv6xx_program_fcp(struct radeon_device *rdev)
 900 {
 901         r600_set_fctu(rdev, R600_FCTU_DFLT);
 902         r600_set_fct(rdev, R600_FCT_DFLT);
 903 }
 904
 905 static void rv6xx_program_vddc3d_parameters(struct radeon_device *rdev)
 906 {
 907         r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT);
 908         r600_set_vddc3d_oorphc(rdev, R600_VDDC3DOORPHC_DFLT);
 909         r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT);
 910         r600_set_ctxcgtt3d_rphc(rdev, R600_CTXCGTT3DRPHC_DFLT);
 911         r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT);
 912 }
 913
 914 static void rv6xx_program_voltage_timing_parameters(struct radeon_device *rdev)
 915 {
 916         u32 rt;
 917
 918         r600_vid_rt_set_vru(rdev, R600_VRU_DFLT);
 919
 920         r600_vid_rt_set_vrt(rdev,
 921                             rv6xx_compute_count_for_delay(rdev,
 922                                                           rdev->pm.dpm.voltage_response_time,
 923                                                           R600_VRU_DFLT));
 924
 925         rt = rv6xx_compute_count_for_delay(rdev,
 926                                            rdev->pm.dpm.backbias_response_time,
 927                                            R600_VRU_DFLT);
 928
 929         rv6xx_vid_response_set_brt(rdev, (rt + 0x1F) >> 5);
 930 }
 931
 932 static void rv6xx_program_engine_speed_parameters(struct radeon_device *rdev)
 933 {
 934         r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT);
 935         rv6xx_enable_engine_feedback_and_reference_sync(rdev);
 936 }
 937
 938 static u64 rv6xx_get_master_voltage_mask(struct radeon_device *rdev)
 939 {
 940         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 941         u64 master_mask = 0;
 942         int i;
 943
 944         for (i = 0; i < R600_PM_NUMBER_OF_VOLTAGE_LEVELS; i++) {
 945                 u32 tmp_mask, tmp_set_pins;
 946                 int ret;
 947
 948                 ret = radeon_atom_get_voltage_gpio_settings(rdev,
 949                                                             pi->hw.vddc[i],
 950                                                             SET_VOLTAGE_TYPE_ASIC_VDDC,
 951                                                             &tmp_set_pins, &tmp_mask);
 952
 953                 if (ret == 0)
 954                         master_mask |= tmp_mask;
 955         }
 956
 957         return master_mask;
 958 }
 959
 960 static void rv6xx_program_voltage_gpio_pins(struct radeon_device *rdev)
 961 {
 962         r600_voltage_control_enable_pins(rdev,
 963                                          rv6xx_get_master_voltage_mask(rdev));
 964 }
 965
 966 static void rv6xx_enable_static_voltage_control(struct radeon_device *rdev,
 967                                                 struct radeon_ps *new_ps,
 968                                                 bool enable)
 969 {
 970         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
 971
 972         if (enable)
 973                 radeon_atom_set_voltage(rdev,
 974                                         new_state->low.vddc,
 975                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
 976         else
 977                 r600_voltage_control_deactivate_static_control(rdev,
 978                                                                rv6xx_get_master_voltage_mask(rdev));
 979 }
 980
 981 static void rv6xx_enable_display_gap(struct radeon_device *rdev, bool enable)
 982 {
 983         if (enable) {
 984                 u32 tmp = (DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM) |
 985                            DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM) |
 986                            DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) |
 987                            DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) |
 988                            VBI_TIMER_COUNT(0x3FFF) |
 989                            VBI_TIMER_UNIT(7));
 990                 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
 991
 992                 WREG32_P(MCLK_PWRMGT_CNTL, USE_DISPLAY_GAP, ~USE_DISPLAY_GAP);
 993         } else
 994                 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~USE_DISPLAY_GAP);
 995 }
 996
 997 static void rv6xx_program_power_level_enter_state(struct radeon_device *rdev)
 998 {
 999         r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_MEDIUM);
1000 }
1001
1002 static void rv6xx_calculate_t(u32 l_f, u32 h_f, int h,
1003                               int d_l, int d_r, u8 *l, u8 *r)
1004 {
1005         int a_n, a_d, h_r, l_r;
1006
1007         h_r = d_l;
1008         l_r = 100 - d_r;
1009
1010         a_n = (int)h_f * d_l + (int)l_f * (h - d_r);
1011         a_d = (int)l_f * l_r + (int)h_f * h_r;
1012
1013         if (a_d != 0) {
1014                 *l = d_l - h_r * a_n / a_d;
1015                 *r = d_r + l_r * a_n / a_d;
1016         }
1017 }
1018
1019 static void rv6xx_calculate_ap(struct radeon_device *rdev,
1020                                struct rv6xx_ps *state)
1021 {
1022         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1023
1024         pi->hw.lp[0] = 0;
1025         pi->hw.rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS - 1]
1026                 = 100;
1027
1028         rv6xx_calculate_t(state->low.sclk,
1029                           state->medium.sclk,
1030                           R600_AH_DFLT,
1031                           R600_LMP_DFLT,
1032                           R600_RLP_DFLT,
1033                           &pi->hw.lp[1],
1034                           &pi->hw.rp[0]);
1035
1036         rv6xx_calculate_t(state->medium.sclk,
1037                           state->high.sclk,
1038                           R600_AH_DFLT,
1039                           R600_LHP_DFLT,
1040                           R600_RMP_DFLT,
1041                           &pi->hw.lp[2],
1042                           &pi->hw.rp[1]);
1043
1044 }
1045
1046 static void rv6xx_calculate_stepping_parameters(struct radeon_device *rdev,
1047                                                 struct radeon_ps *new_ps)
1048 {
1049         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1050
1051         rv6xx_calculate_engine_speed_stepping_parameters(rdev, new_state);
1052         rv6xx_calculate_memory_clock_stepping_parameters(rdev, new_state);
1053         rv6xx_calculate_voltage_stepping_parameters(rdev, new_state);
1054         rv6xx_calculate_ap(rdev, new_state);
1055 }
1056
1057 static void rv6xx_program_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
1058 {
1059         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1060
1061         rv6xx_program_mclk_stepping_parameters_except_lowest_entry(rdev);
1062         if (pi->voltage_control)
1063                 rv6xx_program_voltage_stepping_parameters_except_lowest_entry(rdev);
1064         rv6xx_program_backbias_stepping_parameters_except_lowest_entry(rdev);
1065         rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry(rdev);
1066         rv6xx_program_mclk_spread_spectrum_parameters(rdev);
1067         rv6xx_program_memory_timing_parameters(rdev);
1068 }
1069
1070 static void rv6xx_program_stepping_parameters_lowest_entry(struct radeon_device *rdev)
1071 {
1072         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1073
1074         rv6xx_program_mclk_stepping_parameters_lowest_entry(rdev);
1075         if (pi->voltage_control)
1076                 rv6xx_program_voltage_stepping_parameters_lowest_entry(rdev);
1077         rv6xx_program_backbias_stepping_parameters_lowest_entry(rdev);
1078         rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry(rdev);
1079 }
1080
1081 static void rv6xx_program_power_level_low(struct radeon_device *rdev)
1082 {
1083         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1084
1085         r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW,
1086                                            pi->hw.low_vddc_index);
1087         r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW,
1088                                              pi->hw.low_mclk_index);
1089         r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW,
1090                                              pi->hw.low_sclk_index);
1091         r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW,
1092                                           R600_DISPLAY_WATERMARK_LOW);
1093         r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_LOW,
1094                                        pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
1095 }
1096
1097 static void rv6xx_program_power_level_low_to_lowest_state(struct radeon_device *rdev)
1098 {
1099         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1100
1101         r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, 0);
1102         r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
1103         r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
1104
1105         r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW,
1106                                           R600_DISPLAY_WATERMARK_LOW);
1107
1108         r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_LOW,
1109                                        pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
1110
1111 }
1112
1113 static void rv6xx_program_power_level_medium(struct radeon_device *rdev)
1114 {
1115         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1116
1117         r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM,
1118                                           pi->hw.medium_vddc_index);
1119         r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
1120                                             pi->hw.medium_mclk_index);
1121         r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
1122                                             pi->hw.medium_sclk_index);
1123         r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM,
1124                                          R600_DISPLAY_WATERMARK_LOW);
1125         r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_MEDIUM,
1126                                       pi->hw.pcie_gen2[R600_POWER_LEVEL_MEDIUM]);
1127 }
1128
1129 static void rv6xx_program_power_level_medium_for_transition(struct radeon_device *rdev)
1130 {
1131         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1132
1133         rv6xx_program_mclk_stepping_entry(rdev,
1134                                           R600_POWER_LEVEL_CTXSW,
1135                                           pi->hw.mclks[pi->hw.low_mclk_index]);
1136
1137         r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, 1);
1138
1139         r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
1140                                              R600_POWER_LEVEL_CTXSW);
1141         r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
1142                                              pi->hw.medium_sclk_index);
1143
1144         r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM,
1145                                           R600_DISPLAY_WATERMARK_LOW);
1146
1147         rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM, false);
1148
1149         r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_MEDIUM,
1150                                        pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
1151 }
1152
1153 static void rv6xx_program_power_level_high(struct radeon_device *rdev)
1154 {
1155         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1156
1157         r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH,
1158                                            pi->hw.high_vddc_index);
1159         r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH,
1160                                              pi->hw.high_mclk_index);
1161         r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH,
1162                                              pi->hw.high_sclk_index);
1163
1164         r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH,
1165                                           R600_DISPLAY_WATERMARK_HIGH);
1166
1167         r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_HIGH,
1168                                        pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH]);
1169 }
1170
1171 static void rv6xx_enable_backbias(struct radeon_device *rdev, bool enable)
1172 {
1173         if (enable)
1174                 WREG32_P(GENERAL_PWRMGT, BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL,
1175                          ~(BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL));
1176         else
1177                 WREG32_P(GENERAL_PWRMGT, 0,
1178                          ~(BACKBIAS_VALUE | BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL));
1179 }
1180
1181 static void rv6xx_program_display_gap(struct radeon_device *rdev)
1182 {
1183         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
1184
1185         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
1186         if (rdev->pm.dpm.new_active_crtcs & 1) {
1187                 tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
1188                 tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1189         } else if (rdev->pm.dpm.new_active_crtcs & 2) {
1190                 tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1191                 tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
1192         } else {
1193                 tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1194                 tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1195         }
1196         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
1197 }
1198
1199 static void rv6xx_set_sw_voltage_to_safe(struct radeon_device *rdev,
1200                                          struct radeon_ps *new_ps,
1201                                          struct radeon_ps *old_ps)
1202 {
1203         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1204         struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1205         u16 safe_voltage;
1206
1207         safe_voltage = (new_state->low.vddc >= old_state->low.vddc) ?
1208                 new_state->low.vddc : old_state->low.vddc;
1209
1210         rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW,
1211                                              safe_voltage);
1212
1213         WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW),
1214                  ~SW_GPIO_INDEX_MASK);
1215 }
1216
1217 static void rv6xx_set_sw_voltage_to_low(struct radeon_device *rdev,
1218                                         struct radeon_ps *old_ps)
1219 {
1220         struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1221
1222         rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW,
1223                                              old_state->low.vddc);
1224
1225         WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW),
1226                 ~SW_GPIO_INDEX_MASK);
1227 }
1228
1229 static void rv6xx_set_safe_backbias(struct radeon_device *rdev,
1230                                     struct radeon_ps *new_ps,
1231                                     struct radeon_ps *old_ps)
1232 {
1233         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1234         struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1235
1236         if ((new_state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) &&
1237             (old_state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE))
1238                 WREG32_P(GENERAL_PWRMGT, BACKBIAS_VALUE, ~BACKBIAS_VALUE);
1239         else
1240                 WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_VALUE);
1241 }
1242
1243 static void rv6xx_set_safe_pcie_gen2(struct radeon_device *rdev,
1244                                      struct radeon_ps *new_ps,
1245                                      struct radeon_ps *old_ps)
1246 {
1247         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1248         struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1249
1250         if ((new_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) !=
1251             (old_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2))
1252                 rv6xx_force_pcie_gen1(rdev);
1253 }
1254
1255 static void rv6xx_enable_dynamic_voltage_control(struct radeon_device *rdev,
1256                                                  bool enable)
1257 {
1258         if (enable)
1259                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
1260         else
1261                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
1262 }
1263
1264 static void rv6xx_enable_dynamic_backbias_control(struct radeon_device *rdev,
1265                                                   bool enable)
1266 {
1267         if (enable)
1268                 WREG32_P(GENERAL_PWRMGT, BACKBIAS_DPM_CNTL, ~BACKBIAS_DPM_CNTL);
1269         else
1270                 WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_DPM_CNTL);
1271 }
1272
1273 static int rv6xx_step_sw_voltage(struct radeon_device *rdev,
1274                                  u16 initial_voltage,
1275                                  u16 target_voltage)
1276 {
1277         u16 current_voltage;
1278         u16 true_target_voltage;
1279         u16 voltage_step;
1280         int signed_voltage_step;
1281
1282         if ((radeon_atom_get_voltage_step(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
1283                                           &voltage_step)) ||
1284             (radeon_atom_round_to_true_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
1285                                                initial_voltage, &current_voltage)) ||
1286             (radeon_atom_round_to_true_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
1287                                                target_voltage, &true_target_voltage)))
1288                 return -EINVAL;
1289
1290         if (true_target_voltage < current_voltage)
1291                 signed_voltage_step = -(int)voltage_step;
1292         else
1293                 signed_voltage_step = voltage_step;
1294
1295         while (current_voltage != true_target_voltage) {
1296                 current_voltage += signed_voltage_step;
1297                 rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW,
1298                                                      current_voltage);
1299                 msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000);
1300         }
1301
1302         return 0;
1303 }
1304
1305 static int rv6xx_step_voltage_if_increasing(struct radeon_device *rdev,
1306                                             struct radeon_ps *new_ps,
1307                                             struct radeon_ps *old_ps)
1308 {
1309         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1310         struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1311
1312         if (new_state->low.vddc > old_state->low.vddc)
1313                 return rv6xx_step_sw_voltage(rdev,
1314                                              old_state->low.vddc,
1315                                              new_state->low.vddc);
1316
1317         return 0;
1318 }
1319
1320 static int rv6xx_step_voltage_if_decreasing(struct radeon_device *rdev,
1321                                             struct radeon_ps *new_ps,
1322                                             struct radeon_ps *old_ps)
1323 {
1324         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1325         struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1326
1327         if (new_state->low.vddc < old_state->low.vddc)
1328                 return rv6xx_step_sw_voltage(rdev,
1329                                              old_state->low.vddc,
1330                                              new_state->low.vddc);
1331         else
1332                 return 0;
1333 }
1334
1335 static void rv6xx_enable_high(struct radeon_device *rdev)
1336 {
1337         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1338
1339         if ((pi->restricted_levels < 1) ||
1340             (pi->restricted_levels == 3))
1341                 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true);
1342 }
1343
1344 static void rv6xx_enable_medium(struct radeon_device *rdev)
1345 {
1346         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1347
1348         if (pi->restricted_levels < 2)
1349                 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
1350 }
1351
1352 static void rv6xx_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
1353 {
1354         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1355         bool want_thermal_protection;
1356         enum radeon_dpm_event_src dpm_event_src;
1357
1358         switch (sources) {
1359         case 0:
1360         default:
1361                 want_thermal_protection = false;
1362                 break;
1363         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
1364                 want_thermal_protection = true;
1365                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
1366                 break;
1367
1368         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1369                 want_thermal_protection = true;
1370                 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
1371                 break;
1372
1373         case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1374               (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1375                 want_thermal_protection = true;
1376                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1377                 break;
1378         }
1379
1380         if (want_thermal_protection) {
1381                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
1382                 if (pi->thermal_protection)
1383                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
1384         } else {
1385                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
1386         }
1387 }
1388
1389 static void rv6xx_enable_auto_throttle_source(struct radeon_device *rdev,
1390                                               enum radeon_dpm_auto_throttle_src source,
1391                                               bool enable)
1392 {
1393         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1394
1395         if (enable) {
1396                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1397                         pi->active_auto_throttle_sources |= 1 << source;
1398                         rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1399                 }
1400         } else {
1401                 if (pi->active_auto_throttle_sources & (1 << source)) {
1402                         pi->active_auto_throttle_sources &= ~(1 << source);
1403                         rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1404                 }
1405         }
1406 }
1407
1408
1409 static void rv6xx_enable_thermal_protection(struct radeon_device *rdev,
1410                                             bool enable)
1411 {
1412         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1413
1414         if (pi->active_auto_throttle_sources)
1415                 r600_enable_thermal_protection(rdev, enable);
1416 }
1417
1418 static void rv6xx_generate_transition_stepping(struct radeon_device *rdev,
1419                                                struct radeon_ps *new_ps,
1420                                                struct radeon_ps *old_ps)
1421 {
1422         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1423         struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1424         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1425
1426         rv6xx_generate_steps(rdev,
1427                              old_state->low.sclk,
1428                              new_state->low.sclk,
1429                              0, &pi->hw.medium_sclk_index);
1430 }
1431
1432 static void rv6xx_generate_low_step(struct radeon_device *rdev,
1433                                     struct radeon_ps *new_ps)
1434 {
1435         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1436         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1437
1438         pi->hw.low_sclk_index = 0;
1439         rv6xx_generate_single_step(rdev,
1440                                    new_state->low.sclk,
1441                                    0);
1442 }
1443
1444 static void rv6xx_invalidate_intermediate_steps(struct radeon_device *rdev)
1445 {
1446         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1447
1448         rv6xx_invalidate_intermediate_steps_range(rdev, 0,
1449                                                   pi->hw.medium_sclk_index);
1450 }
1451
1452 static void rv6xx_generate_stepping_table(struct radeon_device *rdev,
1453                                           struct radeon_ps *new_ps)
1454 {
1455         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1456         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1457
1458         pi->hw.low_sclk_index = 0;
1459
1460         rv6xx_generate_steps(rdev,
1461                              new_state->low.sclk,
1462                              new_state->medium.sclk,
1463                              0,
1464                              &pi->hw.medium_sclk_index);
1465         rv6xx_generate_steps(rdev,
1466                              new_state->medium.sclk,
1467                              new_state->high.sclk,
1468                              pi->hw.medium_sclk_index,
1469                              &pi->hw.high_sclk_index);
1470 }
1471
1472 static void rv6xx_enable_spread_spectrum(struct radeon_device *rdev,
1473                                          bool enable)
1474 {
1475         if (enable)
1476                 rv6xx_enable_dynamic_spread_spectrum(rdev, true);
1477         else {
1478                 rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_LOW, false);
1479                 rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM, false);
1480                 rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_HIGH, false);
1481                 rv6xx_enable_dynamic_spread_spectrum(rdev, false);
1482                 rv6xx_enable_memory_spread_spectrum(rdev, false);
1483         }
1484 }
1485
1486 static void rv6xx_reset_lvtm_data_sync(struct radeon_device *rdev)
1487 {
1488         if (ASIC_IS_DCE3(rdev))
1489                 WREG32_P(DCE3_LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG);
1490         else
1491                 WREG32_P(LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG);
1492 }
1493
1494 static void rv6xx_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
1495                                            struct radeon_ps *new_ps,
1496                                            bool enable)
1497 {
1498         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1499
1500         if (enable) {
1501                 rv6xx_enable_bif_dynamic_pcie_gen2(rdev, true);
1502                 rv6xx_enable_pcie_gen2_support(rdev);
1503                 r600_enable_dynamic_pcie_gen2(rdev, true);
1504         } else {
1505                 if (!(new_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2))
1506                         rv6xx_force_pcie_gen1(rdev);
1507                 rv6xx_enable_bif_dynamic_pcie_gen2(rdev, false);
1508                 r600_enable_dynamic_pcie_gen2(rdev, false);
1509         }
1510 }
1511
1512 static void rv6xx_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
1513                                                      struct radeon_ps *new_ps,
1514                                                      struct radeon_ps *old_ps)
1515 {
1516         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1517         struct rv6xx_ps *current_state = rv6xx_get_ps(old_ps);
1518
1519         if ((new_ps->vclk == old_ps->vclk) &&
1520             (new_ps->dclk == old_ps->dclk))
1521                 return;
1522
1523         if (new_state->high.sclk >= current_state->high.sclk)
1524                 return;
1525
1526         radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
1527 }
1528
1529 static void rv6xx_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
1530                                                     struct radeon_ps *new_ps,
1531                                                     struct radeon_ps *old_ps)
1532 {
1533         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1534         struct rv6xx_ps *current_state = rv6xx_get_ps(old_ps);
1535
1536         if ((new_ps->vclk == old_ps->vclk) &&
1537             (new_ps->dclk == old_ps->dclk))
1538                 return;
1539
1540         if (new_state->high.sclk < current_state->high.sclk)
1541                 return;
1542
1543         radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
1544 }
1545
1546 int rv6xx_dpm_enable(struct radeon_device *rdev)
1547 {
1548         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1549         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1550
1551         if (r600_dynamicpm_enabled(rdev))
1552                 return -EINVAL;
1553
1554         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1555                 rv6xx_enable_backbias(rdev, true);
1556
1557         if (pi->dynamic_ss)
1558                 rv6xx_enable_spread_spectrum(rdev, true);
1559
1560         rv6xx_program_mpll_timing_parameters(rdev);
1561         rv6xx_program_bsp(rdev);
1562         rv6xx_program_git(rdev);
1563         rv6xx_program_tp(rdev);
1564         rv6xx_program_tpp(rdev);
1565         rv6xx_program_sstp(rdev);
1566         rv6xx_program_fcp(rdev);
1567         rv6xx_program_vddc3d_parameters(rdev);
1568         rv6xx_program_voltage_timing_parameters(rdev);
1569         rv6xx_program_engine_speed_parameters(rdev);
1570
1571         rv6xx_enable_display_gap(rdev, true);
1572         if (pi->display_gap == false)
1573                 rv6xx_enable_display_gap(rdev, false);
1574
1575         rv6xx_program_power_level_enter_state(rdev);
1576
1577         rv6xx_calculate_stepping_parameters(rdev, boot_ps);
1578
1579         if (pi->voltage_control)
1580                 rv6xx_program_voltage_gpio_pins(rdev);
1581
1582         rv6xx_generate_stepping_table(rdev, boot_ps);
1583
1584         rv6xx_program_stepping_parameters_except_lowest_entry(rdev);
1585         rv6xx_program_stepping_parameters_lowest_entry(rdev);
1586
1587         rv6xx_program_power_level_low(rdev);
1588         rv6xx_program_power_level_medium(rdev);
1589         rv6xx_program_power_level_high(rdev);
1590         rv6xx_program_vc(rdev);
1591         rv6xx_program_at(rdev);
1592
1593         r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
1594         r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
1595         r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true);
1596
1597         rv6xx_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
1598
1599         r600_start_dpm(rdev);
1600
1601         if (pi->voltage_control)
1602                 rv6xx_enable_static_voltage_control(rdev, boot_ps, false);
1603
1604         if (pi->dynamic_pcie_gen2)
1605                 rv6xx_enable_dynamic_pcie_gen2(rdev, boot_ps, true);
1606
1607         if (pi->gfx_clock_gating)
1608                 r600_gfx_clockgating_enable(rdev, true);
1609
1610         return 0;
1611 }
1612
1613 void rv6xx_dpm_disable(struct radeon_device *rdev)
1614 {
1615         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1616         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1617
1618         if (!r600_dynamicpm_enabled(rdev))
1619                 return;
1620
1621         r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
1622         r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
1623         rv6xx_enable_display_gap(rdev, false);
1624         rv6xx_clear_vc(rdev);
1625         r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF);
1626
1627         if (pi->thermal_protection)
1628                 r600_enable_thermal_protection(rdev, false);
1629
1630         r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
1631         r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
1632         r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
1633
1634         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1635                 rv6xx_enable_backbias(rdev, false);
1636
1637         rv6xx_enable_spread_spectrum(rdev, false);
1638
1639         if (pi->voltage_control)
1640                 rv6xx_enable_static_voltage_control(rdev, boot_ps, true);
1641
1642         if (pi->dynamic_pcie_gen2)
1643                 rv6xx_enable_dynamic_pcie_gen2(rdev, boot_ps, false);
1644
1645         if (rdev->irq.installed &&
1646             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1647                 rdev->irq.dpm_thermal = false;
1648                 radeon_irq_set(rdev);
1649         }
1650
1651         if (pi->gfx_clock_gating)
1652                 r600_gfx_clockgating_enable(rdev, false);
1653
1654         r600_stop_dpm(rdev);
1655 }
1656
1657 int rv6xx_dpm_set_power_state(struct radeon_device *rdev)
1658 {
1659         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1660         struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
1661         struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
1662         int ret;
1663
1664         pi->restricted_levels = 0;
1665
1666         rv6xx_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
1667
1668         rv6xx_clear_vc(rdev);
1669         r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
1670         r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF);
1671
1672         if (pi->thermal_protection)
1673                 r600_enable_thermal_protection(rdev, false);
1674
1675         r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
1676         r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
1677         r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
1678
1679         rv6xx_generate_transition_stepping(rdev, new_ps, old_ps);
1680         rv6xx_program_power_level_medium_for_transition(rdev);
1681
1682         if (pi->voltage_control) {
1683                 rv6xx_set_sw_voltage_to_safe(rdev, new_ps, old_ps);
1684                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1685                         rv6xx_set_sw_voltage_to_low(rdev, old_ps);
1686         }
1687
1688         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1689                 rv6xx_set_safe_backbias(rdev, new_ps, old_ps);
1690
1691         if (pi->dynamic_pcie_gen2)
1692                 rv6xx_set_safe_pcie_gen2(rdev, new_ps, old_ps);
1693
1694         if (pi->voltage_control)
1695                 rv6xx_enable_dynamic_voltage_control(rdev, false);
1696
1697         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1698                 rv6xx_enable_dynamic_backbias_control(rdev, false);
1699
1700         if (pi->voltage_control) {
1701                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1702                         rv6xx_step_voltage_if_increasing(rdev, new_ps, old_ps);
1703                 msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000);
1704         }
1705
1706         r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
1707         r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false);
1708         r600_wait_for_power_level_unequal(rdev, R600_POWER_LEVEL_LOW);
1709
1710         rv6xx_generate_low_step(rdev, new_ps);
1711         rv6xx_invalidate_intermediate_steps(rdev);
1712         rv6xx_calculate_stepping_parameters(rdev, new_ps);
1713         rv6xx_program_stepping_parameters_lowest_entry(rdev);
1714         rv6xx_program_power_level_low_to_lowest_state(rdev);
1715
1716         r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
1717         r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
1718         r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
1719
1720         if (pi->voltage_control) {
1721                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) {
1722                         ret = rv6xx_step_voltage_if_decreasing(rdev, new_ps, old_ps);
1723                         if (ret)
1724                                 return ret;
1725                 }
1726                 rv6xx_enable_dynamic_voltage_control(rdev, true);
1727         }
1728
1729         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1730                 rv6xx_enable_dynamic_backbias_control(rdev, true);
1731
1732         if (pi->dynamic_pcie_gen2)
1733                 rv6xx_enable_dynamic_pcie_gen2(rdev, new_ps, true);
1734
1735         rv6xx_reset_lvtm_data_sync(rdev);
1736
1737         rv6xx_generate_stepping_table(rdev, new_ps);
1738         rv6xx_program_stepping_parameters_except_lowest_entry(rdev);
1739         rv6xx_program_power_level_low(rdev);
1740         rv6xx_program_power_level_medium(rdev);
1741         rv6xx_program_power_level_high(rdev);
1742         rv6xx_enable_medium(rdev);
1743         rv6xx_enable_high(rdev);
1744
1745         if (pi->thermal_protection)
1746                 rv6xx_enable_thermal_protection(rdev, true);
1747         rv6xx_program_vc(rdev);
1748         rv6xx_program_at(rdev);
1749
1750         rv6xx_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
1751
1752         return 0;
1753 }
1754
1755 void rv6xx_setup_asic(struct radeon_device *rdev)
1756 {
1757         r600_enable_acpi_pm(rdev);
1758
1759         if (radeon_aspm != 0) {
1760                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s)
1761                         rv6xx_enable_l0s(rdev);
1762                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1)
1763                         rv6xx_enable_l1(rdev);
1764                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1)
1765                         rv6xx_enable_pll_sleep_in_l1(rdev);
1766         }
1767 }
1768
1769 void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev)
1770 {
1771         rv6xx_program_display_gap(rdev);
1772 }
1773
1774 union power_info {
1775         struct _ATOM_POWERPLAY_INFO info;
1776         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1777         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1778         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1779         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1780         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1781 };
1782
1783 union pplib_clock_info {
1784         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1785         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1786         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1787         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1788 };
1789
1790 union pplib_power_state {
1791         struct _ATOM_PPLIB_STATE v1;
1792         struct _ATOM_PPLIB_STATE_V2 v2;
1793 };
1794
1795 static void rv6xx_parse_pplib_non_clock_info(struct radeon_device *rdev,
1796                                              struct radeon_ps *rps,
1797                                              struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
1798 {
1799         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1800         rps->class = le16_to_cpu(non_clock_info->usClassification);
1801         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
1802
1803         if (r600_is_uvd_state(rps->class, rps->class2)) {
1804                 rps->vclk = RV6XX_DEFAULT_VCLK_FREQ;
1805                 rps->dclk = RV6XX_DEFAULT_DCLK_FREQ;
1806         } else {
1807                 rps->vclk = 0;
1808                 rps->dclk = 0;
1809         }
1810
1811         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
1812                 rdev->pm.dpm.boot_ps = rps;
1813         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
1814                 rdev->pm.dpm.uvd_ps = rps;
1815 }
1816
1817 static void rv6xx_parse_pplib_clock_info(struct radeon_device *rdev,
1818                                          struct radeon_ps *rps, int index,
1819                                          union pplib_clock_info *clock_info)
1820 {
1821         struct rv6xx_ps *ps = rv6xx_get_ps(rps);
1822         u32 sclk, mclk;
1823         u16 vddc;
1824         struct rv6xx_pl *pl;
1825
1826         switch (index) {
1827         case 0:
1828                 pl = &ps->low;
1829                 break;
1830         case 1:
1831                 pl = &ps->medium;
1832                 break;
1833         case 2:
1834         default:
1835                 pl = &ps->high;
1836                 break;
1837         }
1838
1839         sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
1840         sclk |= clock_info->r600.ucEngineClockHigh << 16;
1841         mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
1842         mclk |= clock_info->r600.ucMemoryClockHigh << 16;
1843
1844         pl->mclk = mclk;
1845         pl->sclk = sclk;
1846         pl->vddc = le16_to_cpu(clock_info->r600.usVDDC);
1847         pl->flags = le32_to_cpu(clock_info->r600.ulFlags);
1848
1849         /* patch up vddc if necessary */
1850         if (pl->vddc == 0xff01) {
1851                 if (radeon_atom_get_max_vddc(rdev, 0, 0, &vddc) == 0)
1852                         pl->vddc = vddc;
1853         }
1854
1855         /* fix up pcie gen2 */
1856         if (pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) {
1857                 if ((rdev->family == CHIP_RV610) || (rdev->family == CHIP_RV630)) {
1858                         if (pl->vddc < 1100)
1859                                 pl->flags &= ~ATOM_PPLIB_R600_FLAGS_PCIEGEN2;
1860                 }
1861         }
1862
1863         /* patch up boot state */
1864         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1865                 u16 vddc, vddci, mvdd;
1866                 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
1867                 pl->mclk = rdev->clock.default_mclk;
1868                 pl->sclk = rdev->clock.default_sclk;
1869                 pl->vddc = vddc;
1870         }
1871 }
1872
1873 static int rv6xx_parse_power_table(struct radeon_device *rdev)
1874 {
1875         struct radeon_mode_info *mode_info = &rdev->mode_info;
1876         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1877         union pplib_power_state *power_state;
1878         int i, j;
1879         union pplib_clock_info *clock_info;
1880         union power_info *power_info;
1881         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1882         u16 data_offset;
1883         u8 frev, crev;
1884         struct rv6xx_ps *ps;
1885
1886         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1887                                    &frev, &crev, &data_offset))
1888                 return -EINVAL;
1889         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1890
1891         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
1892                                   power_info->pplib.ucNumStates, GFP_KERNEL);
1893         if (!rdev->pm.dpm.ps)
1894                 return -ENOMEM;
1895
1896         for (i = 0; i < power_info->pplib.ucNumStates; i++) {
1897                 power_state = (union pplib_power_state *)
1898                         (mode_info->atom_context->bios + data_offset +
1899                          le16_to_cpu(power_info->pplib.usStateArrayOffset) +
1900                          i * power_info->pplib.ucStateEntrySize);
1901                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1902                         (mode_info->atom_context->bios + data_offset +
1903                          le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
1904                          (power_state->v1.ucNonClockStateIndex *
1905                           power_info->pplib.ucNonClockSize));
1906                 if (power_info->pplib.ucStateEntrySize - 1) {
1907                         u8 *idx;
1908                         ps = kzalloc(sizeof(struct rv6xx_ps), GFP_KERNEL);
1909                         if (ps == NULL) {
1910                                 kfree(rdev->pm.dpm.ps);
1911                                 return -ENOMEM;
1912                         }
1913                         rdev->pm.dpm.ps[i].ps_priv = ps;
1914                         rv6xx_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
1915                                                          non_clock_info);
1916                         idx = (u8 *)&power_state->v1.ucClockStateIndices[0];
1917                         for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
1918                                 clock_info = (union pplib_clock_info *)
1919                                         (mode_info->atom_context->bios + data_offset +
1920                                          le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
1921                                          (idx[j] * power_info->pplib.ucClockInfoSize));
1922                                 rv6xx_parse_pplib_clock_info(rdev,
1923                                                              &rdev->pm.dpm.ps[i], j,
1924                                                              clock_info);
1925                         }
1926                 }
1927         }
1928         rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
1929         return 0;
1930 }
1931
1932 int rv6xx_dpm_init(struct radeon_device *rdev)
1933 {
1934         struct radeon_atom_ss ss;
1935         struct atom_clock_dividers dividers;
1936         struct rv6xx_power_info *pi;
1937         int ret;
1938
1939         pi = kzalloc(sizeof(struct rv6xx_power_info), GFP_KERNEL);
1940         if (pi == NULL)
1941                 return -ENOMEM;
1942         rdev->pm.dpm.priv = pi;
1943
1944         ret = r600_get_platform_caps(rdev);
1945         if (ret)
1946                 return ret;
1947
1948         ret = rv6xx_parse_power_table(rdev);
1949         if (ret)
1950                 return ret;
1951
1952         if (rdev->pm.dpm.voltage_response_time == 0)
1953                 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
1954         if (rdev->pm.dpm.backbias_response_time == 0)
1955                 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
1956
1957         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1958                                              0, false, &dividers);
1959         if (ret)
1960                 pi->spll_ref_div = dividers.ref_div + 1;
1961         else
1962                 pi->spll_ref_div = R600_REFERENCEDIVIDER_DFLT;
1963
1964         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
1965                                              0, false, &dividers);
1966         if (ret)
1967                 pi->mpll_ref_div = dividers.ref_div + 1;
1968         else
1969                 pi->mpll_ref_div = R600_REFERENCEDIVIDER_DFLT;
1970
1971         if (rdev->family >= CHIP_RV670)
1972                 pi->fb_div_scale = 1;
1973         else
1974                 pi->fb_div_scale = 0;
1975
1976         pi->voltage_control =
1977                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0);
1978
1979         pi->gfx_clock_gating = true;
1980
1981         pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
1982                                                        ASIC_INTERNAL_ENGINE_SS, 0);
1983         pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
1984                                                        ASIC_INTERNAL_MEMORY_SS, 0);
1985
1986         /* Disable sclk ss, causes hangs on a lot of systems */
1987         pi->sclk_ss = false;
1988
1989         if (pi->sclk_ss || pi->mclk_ss)
1990                 pi->dynamic_ss = true;
1991         else
1992                 pi->dynamic_ss = false;
1993
1994         pi->dynamic_pcie_gen2 = true;
1995
1996         if (pi->gfx_clock_gating &&
1997             (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
1998                 pi->thermal_protection = true;
1999         else
2000                 pi->thermal_protection = false;
2001
2002         pi->display_gap = true;
2003
2004         return 0;
2005 }
2006
2007 void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
2008                                  struct radeon_ps *rps)
2009 {
2010         struct rv6xx_ps *ps = rv6xx_get_ps(rps);
2011         struct rv6xx_pl *pl;
2012
2013         r600_dpm_print_class_info(rps->class, rps->class2);
2014         r600_dpm_print_cap_info(rps->caps);
2015         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
2016         pl = &ps->low;
2017         printk("\t\tpower level 0    sclk: %u mclk: %u vddc: %u\n",
2018                pl->sclk, pl->mclk, pl->vddc);
2019         pl = &ps->medium;
2020         printk("\t\tpower level 1    sclk: %u mclk: %u vddc: %u\n",
2021                pl->sclk, pl->mclk, pl->vddc);
2022         pl = &ps->high;
2023         printk("\t\tpower level 2    sclk: %u mclk: %u vddc: %u\n",
2024                pl->sclk, pl->mclk, pl->vddc);
2025         r600_dpm_print_ps_status(rdev, rps);
2026 }
2027
2028 void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
2029                                                        struct seq_file *m)
2030 {
2031         struct radeon_ps *rps = rdev->pm.dpm.current_ps;
2032         struct rv6xx_ps *ps = rv6xx_get_ps(rps);
2033         struct rv6xx_pl *pl;
2034         u32 current_index =
2035                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
2036                 CURRENT_PROFILE_INDEX_SHIFT;
2037
2038         if (current_index > 2) {
2039                 seq_printf(m, "invalid dpm profile %d\n", current_index);
2040         } else {
2041                 if (current_index == 0)
2042                         pl = &ps->low;
2043                 else if (current_index == 1)
2044                         pl = &ps->medium;
2045                 else /* current_index == 2 */
2046                         pl = &ps->high;
2047                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
2048                 seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u\n",
2049                            current_index, pl->sclk, pl->mclk, pl->vddc);
2050         }
2051 }
2052
2053 void rv6xx_dpm_fini(struct radeon_device *rdev)
2054 {
2055         int i;
2056
2057         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2058                 kfree(rdev->pm.dpm.ps[i].ps_priv);
2059         }
2060         kfree(rdev->pm.dpm.ps);
2061         kfree(rdev->pm.dpm.priv);
2062 }
2063
2064 u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low)
2065 {
2066         struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps);
2067
2068         if (low)
2069                 return requested_state->low.sclk;
2070         else
2071                 return requested_state->high.sclk;
2072 }
2073
2074 u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low)
2075 {
2076         struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps);
2077
2078         if (low)
2079                 return requested_state->low.mclk;
2080         else
2081                 return requested_state->high.mclk;
2082 }
2083
2084 int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
2085                                       enum radeon_dpm_forced_level level)
2086 {
2087         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
2088
2089         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
2090                 pi->restricted_levels = 3;
2091         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
2092                 pi->restricted_levels = 2;
2093         } else {
2094                 pi->restricted_levels = 0;
2095         }
2096
2097         rv6xx_clear_vc(rdev);
2098         r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
2099         r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF);
2100         r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
2101         r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
2102         r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
2103         rv6xx_enable_medium(rdev);
2104         rv6xx_enable_high(rdev);
2105         if (pi->restricted_levels == 3)
2106                 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false);
2107         rv6xx_program_vc(rdev);
2108         rv6xx_program_at(rdev);
2109
2110         rdev->pm.dpm.forced_level = level;
2111
2112         return 0;
2113 }