drivers/gpu/drm/radeon/rv515.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "rv515d.h"
  32 #include "radeon.h"
  33 #include "radeon_asic.h"
  34 #include "atom.h"
  35 #include "rv515_reg_safe.h"
  36
  37 /* This files gather functions specifics to: rv515 */
  38 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
  39 int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
  40 void rv515_gpu_init(struct radeon_device *rdev);
  41 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
  42
  43 void rv515_debugfs(struct radeon_device *rdev)
  44 {
  45         if (r100_debugfs_rbbm_init(rdev)) {
  46                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  47         }
  48         if (rv515_debugfs_pipes_info_init(rdev)) {
  49                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  50         }
  51         if (rv515_debugfs_ga_info_init(rdev)) {
  52                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  53         }
  54 }
  55
  56 void rv515_ring_start(struct radeon_device *rdev)
  57 {
  58         int r;
  59
  60         r = radeon_ring_lock(rdev, 64);
  61         if (r) {
  62                 return;
  63         }
  64         radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0));
  65         radeon_ring_write(rdev,
  66                           ISYNC_ANY2D_IDLE3D |
  67                           ISYNC_ANY3D_IDLE2D |
  68                           ISYNC_WAIT_IDLEGUI |
  69                           ISYNC_CPSCRATCH_IDLEGUI);
  70         radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
  71         radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
  72         radeon_ring_write(rdev, PACKET0(0x170C, 0));
  73         radeon_ring_write(rdev, 1 << 31);
  74         radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));
  75         radeon_ring_write(rdev, 0);
  76         radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));
  77         radeon_ring_write(rdev, 0);
  78         radeon_ring_write(rdev, PACKET0(0x42C8, 0));
  79         radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
  80         radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));
  81         radeon_ring_write(rdev, 0);
  82         radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
  83         radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
  84         radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
  85         radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
  86         radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
  87         radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
  88         radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0));
  89         radeon_ring_write(rdev, 0);
  90         radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
  91         radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
  92         radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
  93         radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
  94         radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0));
  95         radeon_ring_write(rdev,
  96                           ((6 << MS_X0_SHIFT) |
  97                            (6 << MS_Y0_SHIFT) |
  98                            (6 << MS_X1_SHIFT) |
  99                            (6 << MS_Y1_SHIFT) |
 100                            (6 << MS_X2_SHIFT) |
 101                            (6 << MS_Y2_SHIFT) |
 102                            (6 << MSBD0_Y_SHIFT) |
 103                            (6 << MSBD0_X_SHIFT)));
 104         radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0));
 105         radeon_ring_write(rdev,
 106                           ((6 << MS_X3_SHIFT) |
 107                            (6 << MS_Y3_SHIFT) |
 108                            (6 << MS_X4_SHIFT) |
 109                            (6 << MS_Y4_SHIFT) |
 110                            (6 << MS_X5_SHIFT) |
 111                            (6 << MS_Y5_SHIFT) |
 112                            (6 << MSBD1_SHIFT)));
 113         radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0));
 114         radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
 115         radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0));
 116         radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
 117         radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0));
 118         radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
 119         radeon_ring_write(rdev, PACKET0(0x20C8, 0));
 120         radeon_ring_write(rdev, 0);
 121         radeon_ring_unlock_commit(rdev);
 122 }
 123
 124 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
 125 {
 126         unsigned i;
 127         uint32_t tmp;
 128
 129         for (i = 0; i < rdev->usec_timeout; i++) {
 130                 /* read MC_STATUS */
 131                 tmp = RREG32_MC(MC_STATUS);
 132                 if (tmp & MC_STATUS_IDLE) {
 133                         return 0;
 134                 }
 135                 DRM_UDELAY(1);
 136         }
 137         return -1;
 138 }
 139
 140 void rv515_vga_render_disable(struct radeon_device *rdev)
 141 {
 142         WREG32(R_000300_VGA_RENDER_CONTROL,
 143                 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
 144 }
 145
 146 void rv515_gpu_init(struct radeon_device *rdev)
 147 {
 148         unsigned pipe_select_current, gb_pipe_select, tmp;
 149
 150         if (r100_gui_wait_for_idle(rdev)) {
 151                 printk(KERN_WARNING "Failed to wait GUI idle while "
 152                        "reseting GPU. Bad things might happen.\n");
 153         }
 154         rv515_vga_render_disable(rdev);
 155         r420_pipes_init(rdev);
 156         gb_pipe_select = RREG32(0x402C);
 157         tmp = RREG32(0x170C);
 158         pipe_select_current = (tmp >> 2) & 3;
 159         tmp = (1 << pipe_select_current) |
 160               (((gb_pipe_select >> 8) & 0xF) << 4);
 161         WREG32_PLL(0x000D, tmp);
 162         if (r100_gui_wait_for_idle(rdev)) {
 163                 printk(KERN_WARNING "Failed to wait GUI idle while "
 164                        "reseting GPU. Bad things might happen.\n");
 165         }
 166         if (rv515_mc_wait_for_idle(rdev)) {
 167                 printk(KERN_WARNING "Failed to wait MC idle while "
 168                        "programming pipes. Bad things might happen.\n");
 169         }
 170 }
 171
 172 static void rv515_vram_get_type(struct radeon_device *rdev)
 173 {
 174         uint32_t tmp;
 175
 176         rdev->mc.vram_width = 128;
 177         rdev->mc.vram_is_ddr = true;
 178         tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
 179         switch (tmp) {
 180         case 0:
 181                 rdev->mc.vram_width = 64;
 182                 break;
 183         case 1:
 184                 rdev->mc.vram_width = 128;
 185                 break;
 186         default:
 187                 rdev->mc.vram_width = 128;
 188                 break;
 189         }
 190 }
 191
 192 void rv515_mc_init(struct radeon_device *rdev)
 193 {
 194
 195         rv515_vram_get_type(rdev);
 196         r100_vram_init_sizes(rdev);
 197         radeon_vram_location(rdev, &rdev->mc, 0);
 198         if (!(rdev->flags & RADEON_IS_AGP))
 199                 radeon_gtt_location(rdev, &rdev->mc);
 200         radeon_update_bandwidth_info(rdev);
 201 }
 202
 203 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 204 {
 205         uint32_t r;
 206
 207         WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
 208         r = RREG32(MC_IND_DATA);
 209         WREG32(MC_IND_INDEX, 0);
 210         return r;
 211 }
 212
 213 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 214 {
 215         WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
 216         WREG32(MC_IND_DATA, (v));
 217         WREG32(MC_IND_INDEX, 0);
 218 }
 219
 220 #if defined(CONFIG_DEBUG_FS)
 221 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
 222 {
 223         struct drm_info_node *node = (struct drm_info_node *) m->private;
 224         struct drm_device *dev = node->minor->dev;
 225         struct radeon_device *rdev = dev->dev_private;
 226         uint32_t tmp;
 227
 228         tmp = RREG32(GB_PIPE_SELECT);
 229         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
 230         tmp = RREG32(SU_REG_DEST);
 231         seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
 232         tmp = RREG32(GB_TILE_CONFIG);
 233         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
 234         tmp = RREG32(DST_PIPE_CONFIG);
 235         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
 236         return 0;
 237 }
 238
 239 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
 240 {
 241         struct drm_info_node *node = (struct drm_info_node *) m->private;
 242         struct drm_device *dev = node->minor->dev;
 243         struct radeon_device *rdev = dev->dev_private;
 244         uint32_t tmp;
 245
 246         tmp = RREG32(0x2140);
 247         seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
 248         radeon_asic_reset(rdev);
 249         tmp = RREG32(0x425C);
 250         seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
 251         return 0;
 252 }
 253
 254 static struct drm_info_list rv515_pipes_info_list[] = {
 255         {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
 256 };
 257
 258 static struct drm_info_list rv515_ga_info_list[] = {
 259         {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
 260 };
 261 #endif
 262
 263 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
 264 {
 265 #if defined(CONFIG_DEBUG_FS)
 266         return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
 267 #else
 268         return 0;
 269 #endif
 270 }
 271
 272 int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
 273 {
 274 #if defined(CONFIG_DEBUG_FS)
 275         return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
 276 #else
 277         return 0;
 278 #endif
 279 }
 280
 281 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
 282 {
 283         save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL);
 284         save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL);
 285         save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
 286         save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
 287         save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL);
 288         save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
 289
 290         /* Stop all video */
 291         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
 292         WREG32(R_000300_VGA_RENDER_CONTROL, 0);
 293         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
 294         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
 295         WREG32(R_006080_D1CRTC_CONTROL, 0);
 296         WREG32(R_006880_D2CRTC_CONTROL, 0);
 297         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
 298         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
 299         WREG32(R_000330_D1VGA_CONTROL, 0);
 300         WREG32(R_000338_D2VGA_CONTROL, 0);
 301 }
 302
 303 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
 304 {
 305         WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
 306         WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
 307         WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
 308         WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
 309         WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
 310         /* Unlock host access */
 311         WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
 312         mdelay(1);
 313         /* Restore video state */
 314         WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
 315         WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
 316         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
 317         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
 318         WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
 319         WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
 320         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
 321         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
 322         WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
 323 }
 324
 325 void rv515_mc_program(struct radeon_device *rdev)
 326 {
 327         struct rv515_mc_save save;
 328
 329         /* Stops all mc clients */
 330         rv515_mc_stop(rdev, &save);
 331
 332         /* Wait for mc idle */
 333         if (rv515_mc_wait_for_idle(rdev))
 334                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 335         /* Write VRAM size in case we are limiting it */
 336         WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
 337         /* Program MC, should be a 32bits limited address space */
 338         WREG32_MC(R_000001_MC_FB_LOCATION,
 339                         S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
 340                         S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
 341         WREG32(R_000134_HDP_FB_LOCATION,
 342                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 343         if (rdev->flags & RADEON_IS_AGP) {
 344                 WREG32_MC(R_000002_MC_AGP_LOCATION,
 345                         S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
 346                         S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
 347                 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
 348                 WREG32_MC(R_000004_MC_AGP_BASE_2,
 349                         S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
 350         } else {
 351                 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
 352                 WREG32_MC(R_000003_MC_AGP_BASE, 0);
 353                 WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
 354         }
 355
 356         rv515_mc_resume(rdev, &save);
 357 }
 358
 359 void rv515_clock_startup(struct radeon_device *rdev)
 360 {
 361         if (radeon_dynclks != -1 && radeon_dynclks)
 362                 radeon_atom_set_clock_gating(rdev, 1);
 363         /* We need to force on some of the block */
 364         WREG32_PLL(R_00000F_CP_DYN_CNTL,
 365                 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
 366         WREG32_PLL(R_000011_E2_DYN_CNTL,
 367                 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
 368         WREG32_PLL(R_000013_IDCT_DYN_CNTL,
 369                 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
 370 }
 371
 372 static int rv515_startup(struct radeon_device *rdev)
 373 {
 374         int r;
 375
 376         rv515_mc_program(rdev);
 377         /* Resume clock */
 378         rv515_clock_startup(rdev);
 379         /* Initialize GPU configuration (# pipes, ...) */
 380         rv515_gpu_init(rdev);
 381         /* Initialize GART (initialize after TTM so we can allocate
 382          * memory through TTM but finalize after TTM) */
 383         if (rdev->flags & RADEON_IS_PCIE) {
 384                 r = rv370_pcie_gart_enable(rdev);
 385                 if (r)
 386                         return r;
 387         }
 388         /* Enable IRQ */
 389         rs600_irq_set(rdev);
 390         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 391         /* 1M ring buffer */
 392         r = r100_cp_init(rdev, 1024 * 1024);
 393         if (r) {
 394                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
 395                 return r;
 396         }
 397         r = r100_wb_init(rdev);
 398         if (r)
 399                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
 400         r = r100_ib_init(rdev);
 401         if (r) {
 402                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
 403                 return r;
 404         }
 405         return 0;
 406 }
 407
 408 int rv515_resume(struct radeon_device *rdev)
 409 {
 410         /* Make sur GART are not working */
 411         if (rdev->flags & RADEON_IS_PCIE)
 412                 rv370_pcie_gart_disable(rdev);
 413         /* Resume clock before doing reset */
 414         rv515_clock_startup(rdev);
 415         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 416         if (radeon_asic_reset(rdev)) {
 417                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 418                         RREG32(R_000E40_RBBM_STATUS),
 419                         RREG32(R_0007C0_CP_STAT));
 420         }
 421         /* post */
 422         atom_asic_init(rdev->mode_info.atom_context);
 423         /* Resume clock after posting */
 424         rv515_clock_startup(rdev);
 425         /* Initialize surface registers */
 426         radeon_surface_init(rdev);
 427         return rv515_startup(rdev);
 428 }
 429
 430 int rv515_suspend(struct radeon_device *rdev)
 431 {
 432         r100_cp_disable(rdev);
 433         r100_wb_disable(rdev);
 434         rs600_irq_disable(rdev);
 435         if (rdev->flags & RADEON_IS_PCIE)
 436                 rv370_pcie_gart_disable(rdev);
 437         return 0;
 438 }
 439
 440 void rv515_set_safe_registers(struct radeon_device *rdev)
 441 {
 442         rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
 443         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
 444 }
 445
 446 void rv515_fini(struct radeon_device *rdev)
 447 {
 448         r100_cp_fini(rdev);
 449         r100_wb_fini(rdev);
 450         r100_ib_fini(rdev);
 451         radeon_gem_fini(rdev);
 452         rv370_pcie_gart_fini(rdev);
 453         radeon_agp_fini(rdev);
 454         radeon_irq_kms_fini(rdev);
 455         radeon_fence_driver_fini(rdev);
 456         radeon_bo_fini(rdev);
 457         radeon_atombios_fini(rdev);
 458         kfree(rdev->bios);
 459         rdev->bios = NULL;
 460 }
 461
 462 int rv515_init(struct radeon_device *rdev)
 463 {
 464         int r;
 465
 466         /* Initialize scratch registers */
 467         radeon_scratch_init(rdev);
 468         /* Initialize surface registers */
 469         radeon_surface_init(rdev);
 470         /* TODO: disable VGA need to use VGA request */
 471         /* BIOS*/
 472         if (!radeon_get_bios(rdev)) {
 473                 if (ASIC_IS_AVIVO(rdev))
 474                         return -EINVAL;
 475         }
 476         if (rdev->is_atom_bios) {
 477                 r = radeon_atombios_init(rdev);
 478                 if (r)
 479                         return r;
 480         } else {
 481                 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
 482                 return -EINVAL;
 483         }
 484         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 485         if (radeon_asic_reset(rdev)) {
 486                 dev_warn(rdev->dev,
 487                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 488                         RREG32(R_000E40_RBBM_STATUS),
 489                         RREG32(R_0007C0_CP_STAT));
 490         }
 491         /* check if cards are posted or not */
 492         if (radeon_boot_test_post_card(rdev) == false)
 493                 return -EINVAL;
 494         /* Initialize clocks */
 495         radeon_get_clock_info(rdev->ddev);
 496         /* initialize AGP */
 497         if (rdev->flags & RADEON_IS_AGP) {
 498                 r = radeon_agp_init(rdev);
 499                 if (r) {
 500                         radeon_agp_disable(rdev);
 501                 }
 502         }
 503         /* initialize memory controller */
 504         rv515_mc_init(rdev);
 505         rv515_debugfs(rdev);
 506         /* Fence driver */
 507         r = radeon_fence_driver_init(rdev);
 508         if (r)
 509                 return r;
 510         r = radeon_irq_kms_init(rdev);
 511         if (r)
 512                 return r;
 513         /* Memory manager */
 514         r = radeon_bo_init(rdev);
 515         if (r)
 516                 return r;
 517         r = rv370_pcie_gart_init(rdev);
 518         if (r)
 519                 return r;
 520         rv515_set_safe_registers(rdev);
 521         rdev->accel_working = true;
 522         r = rv515_startup(rdev);
 523         if (r) {
 524                 /* Somethings want wront with the accel init stop accel */
 525                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 526                 r100_cp_fini(rdev);
 527                 r100_wb_fini(rdev);
 528                 r100_ib_fini(rdev);
 529                 radeon_irq_kms_fini(rdev);
 530                 rv370_pcie_gart_fini(rdev);
 531                 radeon_agp_fini(rdev);
 532                 rdev->accel_working = false;
 533         }
 534         return 0;
 535 }
 536
 537 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
 538 {
 539         int index_reg = 0x6578 + crtc->crtc_offset;
 540         int data_reg = 0x657c + crtc->crtc_offset;
 541
 542         WREG32(0x659C + crtc->crtc_offset, 0x0);
 543         WREG32(0x6594 + crtc->crtc_offset, 0x705);
 544         WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
 545         WREG32(0x65D8 + crtc->crtc_offset, 0x0);
 546         WREG32(0x65B0 + crtc->crtc_offset, 0x0);
 547         WREG32(0x65C0 + crtc->crtc_offset, 0x0);
 548         WREG32(0x65D4 + crtc->crtc_offset, 0x0);
 549         WREG32(index_reg, 0x0);
 550         WREG32(data_reg, 0x841880A8);
 551         WREG32(index_reg, 0x1);
 552         WREG32(data_reg, 0x84208680);
 553         WREG32(index_reg, 0x2);
 554         WREG32(data_reg, 0xBFF880B0);
 555         WREG32(index_reg, 0x100);
 556         WREG32(data_reg, 0x83D88088);
 557         WREG32(index_reg, 0x101);
 558         WREG32(data_reg, 0x84608680);
 559         WREG32(index_reg, 0x102);
 560         WREG32(data_reg, 0xBFF080D0);
 561         WREG32(index_reg, 0x200);
 562         WREG32(data_reg, 0x83988068);
 563         WREG32(index_reg, 0x201);
 564         WREG32(data_reg, 0x84A08680);
 565         WREG32(index_reg, 0x202);
 566         WREG32(data_reg, 0xBFF080F8);
 567         WREG32(index_reg, 0x300);
 568         WREG32(data_reg, 0x83588058);
 569         WREG32(index_reg, 0x301);
 570         WREG32(data_reg, 0x84E08660);
 571         WREG32(index_reg, 0x302);
 572         WREG32(data_reg, 0xBFF88120);
 573         WREG32(index_reg, 0x400);
 574         WREG32(data_reg, 0x83188040);
 575         WREG32(index_reg, 0x401);
 576         WREG32(data_reg, 0x85008660);
 577         WREG32(index_reg, 0x402);
 578         WREG32(data_reg, 0xBFF88150);
 579         WREG32(index_reg, 0x500);
 580         WREG32(data_reg, 0x82D88030);
 581         WREG32(index_reg, 0x501);
 582         WREG32(data_reg, 0x85408640);
 583         WREG32(index_reg, 0x502);
 584         WREG32(data_reg, 0xBFF88180);
 585         WREG32(index_reg, 0x600);
 586         WREG32(data_reg, 0x82A08018);
 587         WREG32(index_reg, 0x601);
 588         WREG32(data_reg, 0x85808620);
 589         WREG32(index_reg, 0x602);
 590         WREG32(data_reg, 0xBFF081B8);
 591         WREG32(index_reg, 0x700);
 592         WREG32(data_reg, 0x82608010);
 593         WREG32(index_reg, 0x701);
 594         WREG32(data_reg, 0x85A08600);
 595         WREG32(index_reg, 0x702);
 596         WREG32(data_reg, 0x800081F0);
 597         WREG32(index_reg, 0x800);
 598         WREG32(data_reg, 0x8228BFF8);
 599         WREG32(index_reg, 0x801);
 600         WREG32(data_reg, 0x85E085E0);
 601         WREG32(index_reg, 0x802);
 602         WREG32(data_reg, 0xBFF88228);
 603         WREG32(index_reg, 0x10000);
 604         WREG32(data_reg, 0x82A8BF00);
 605         WREG32(index_reg, 0x10001);
 606         WREG32(data_reg, 0x82A08CC0);
 607         WREG32(index_reg, 0x10002);
 608         WREG32(data_reg, 0x8008BEF8);
 609         WREG32(index_reg, 0x10100);
 610         WREG32(data_reg, 0x81F0BF28);
 611         WREG32(index_reg, 0x10101);
 612         WREG32(data_reg, 0x83608CA0);
 613         WREG32(index_reg, 0x10102);
 614         WREG32(data_reg, 0x8018BED0);
 615         WREG32(index_reg, 0x10200);
 616         WREG32(data_reg, 0x8148BF38);
 617         WREG32(index_reg, 0x10201);
 618         WREG32(data_reg, 0x84408C80);
 619         WREG32(index_reg, 0x10202);
 620         WREG32(data_reg, 0x8008BEB8);
 621         WREG32(index_reg, 0x10300);
 622         WREG32(data_reg, 0x80B0BF78);
 623         WREG32(index_reg, 0x10301);
 624         WREG32(data_reg, 0x85008C20);
 625         WREG32(index_reg, 0x10302);
 626         WREG32(data_reg, 0x8020BEA0);
 627         WREG32(index_reg, 0x10400);
 628         WREG32(data_reg, 0x8028BF90);
 629         WREG32(index_reg, 0x10401);
 630         WREG32(data_reg, 0x85E08BC0);
 631         WREG32(index_reg, 0x10402);
 632         WREG32(data_reg, 0x8018BE90);
 633         WREG32(index_reg, 0x10500);
 634         WREG32(data_reg, 0xBFB8BFB0);
 635         WREG32(index_reg, 0x10501);
 636         WREG32(data_reg, 0x86C08B40);
 637         WREG32(index_reg, 0x10502);
 638         WREG32(data_reg, 0x8010BE90);
 639         WREG32(index_reg, 0x10600);
 640         WREG32(data_reg, 0xBF58BFC8);
 641         WREG32(index_reg, 0x10601);
 642         WREG32(data_reg, 0x87A08AA0);
 643         WREG32(index_reg, 0x10602);
 644         WREG32(data_reg, 0x8010BE98);
 645         WREG32(index_reg, 0x10700);
 646         WREG32(data_reg, 0xBF10BFF0);
 647         WREG32(index_reg, 0x10701);
 648         WREG32(data_reg, 0x886089E0);
 649         WREG32(index_reg, 0x10702);
 650         WREG32(data_reg, 0x8018BEB0);
 651         WREG32(index_reg, 0x10800);
 652         WREG32(data_reg, 0xBED8BFE8);
 653         WREG32(index_reg, 0x10801);
 654         WREG32(data_reg, 0x89408940);
 655         WREG32(index_reg, 0x10802);
 656         WREG32(data_reg, 0xBFE8BED8);
 657         WREG32(index_reg, 0x20000);
 658         WREG32(data_reg, 0x80008000);
 659         WREG32(index_reg, 0x20001);
 660         WREG32(data_reg, 0x90008000);
 661         WREG32(index_reg, 0x20002);
 662         WREG32(data_reg, 0x80008000);
 663         WREG32(index_reg, 0x20003);
 664         WREG32(data_reg, 0x80008000);
 665         WREG32(index_reg, 0x20100);
 666         WREG32(data_reg, 0x80108000);
 667         WREG32(index_reg, 0x20101);
 668         WREG32(data_reg, 0x8FE0BF70);
 669         WREG32(index_reg, 0x20102);
 670         WREG32(data_reg, 0xBFE880C0);
 671         WREG32(index_reg, 0x20103);
 672         WREG32(data_reg, 0x80008000);
 673         WREG32(index_reg, 0x20200);
 674         WREG32(data_reg, 0x8018BFF8);
 675         WREG32(index_reg, 0x20201);
 676         WREG32(data_reg, 0x8F80BF08);
 677         WREG32(index_reg, 0x20202);
 678         WREG32(data_reg, 0xBFD081A0);
 679         WREG32(index_reg, 0x20203);
 680         WREG32(data_reg, 0xBFF88000);
 681         WREG32(index_reg, 0x20300);
 682         WREG32(data_reg, 0x80188000);
 683         WREG32(index_reg, 0x20301);
 684         WREG32(data_reg, 0x8EE0BEC0);
 685         WREG32(index_reg, 0x20302);
 686         WREG32(data_reg, 0xBFB082A0);
 687         WREG32(index_reg, 0x20303);
 688         WREG32(data_reg, 0x80008000);
 689         WREG32(index_reg, 0x20400);
 690         WREG32(data_reg, 0x80188000);
 691         WREG32(index_reg, 0x20401);
 692         WREG32(data_reg, 0x8E00BEA0);
 693         WREG32(index_reg, 0x20402);
 694         WREG32(data_reg, 0xBF8883C0);
 695         WREG32(index_reg, 0x20403);
 696         WREG32(data_reg, 0x80008000);
 697         WREG32(index_reg, 0x20500);
 698         WREG32(data_reg, 0x80188000);
 699         WREG32(index_reg, 0x20501);
 700         WREG32(data_reg, 0x8D00BE90);
 701         WREG32(index_reg, 0x20502);
 702         WREG32(data_reg, 0xBF588500);
 703         WREG32(index_reg, 0x20503);
 704         WREG32(data_reg, 0x80008008);
 705         WREG32(index_reg, 0x20600);
 706         WREG32(data_reg, 0x80188000);
 707         WREG32(index_reg, 0x20601);
 708         WREG32(data_reg, 0x8BC0BE98);
 709         WREG32(index_reg, 0x20602);
 710         WREG32(data_reg, 0xBF308660);
 711         WREG32(index_reg, 0x20603);
 712         WREG32(data_reg, 0x80008008);
 713         WREG32(index_reg, 0x20700);
 714         WREG32(data_reg, 0x80108000);
 715         WREG32(index_reg, 0x20701);
 716         WREG32(data_reg, 0x8A80BEB0);
 717         WREG32(index_reg, 0x20702);
 718         WREG32(data_reg, 0xBF0087C0);
 719         WREG32(index_reg, 0x20703);
 720         WREG32(data_reg, 0x80008008);
 721         WREG32(index_reg, 0x20800);
 722         WREG32(data_reg, 0x80108000);
 723         WREG32(index_reg, 0x20801);
 724         WREG32(data_reg, 0x8920BED0);
 725         WREG32(index_reg, 0x20802);
 726         WREG32(data_reg, 0xBED08920);
 727         WREG32(index_reg, 0x20803);
 728         WREG32(data_reg, 0x80008010);
 729         WREG32(index_reg, 0x30000);
 730         WREG32(data_reg, 0x90008000);
 731         WREG32(index_reg, 0x30001);
 732         WREG32(data_reg, 0x80008000);
 733         WREG32(index_reg, 0x30100);
 734         WREG32(data_reg, 0x8FE0BF90);
 735         WREG32(index_reg, 0x30101);
 736         WREG32(data_reg, 0xBFF880A0);
 737         WREG32(index_reg, 0x30200);
 738         WREG32(data_reg, 0x8F60BF40);
 739         WREG32(index_reg, 0x30201);
 740         WREG32(data_reg, 0xBFE88180);
 741         WREG32(index_reg, 0x30300);
 742         WREG32(data_reg, 0x8EC0BF00);
 743         WREG32(index_reg, 0x30301);
 744         WREG32(data_reg, 0xBFC88280);
 745         WREG32(index_reg, 0x30400);
 746         WREG32(data_reg, 0x8DE0BEE0);
 747         WREG32(index_reg, 0x30401);
 748         WREG32(data_reg, 0xBFA083A0);
 749         WREG32(index_reg, 0x30500);
 750         WREG32(data_reg, 0x8CE0BED0);
 751         WREG32(index_reg, 0x30501);
 752         WREG32(data_reg, 0xBF7884E0);
 753         WREG32(index_reg, 0x30600);
 754         WREG32(data_reg, 0x8BA0BED8);
 755         WREG32(index_reg, 0x30601);
 756         WREG32(data_reg, 0xBF508640);
 757         WREG32(index_reg, 0x30700);
 758         WREG32(data_reg, 0x8A60BEE8);
 759         WREG32(index_reg, 0x30701);
 760         WREG32(data_reg, 0xBF2087A0);
 761         WREG32(index_reg, 0x30800);
 762         WREG32(data_reg, 0x8900BF00);
 763         WREG32(index_reg, 0x30801);
 764         WREG32(data_reg, 0xBF008900);
 765 }
 766
 767 struct rv515_watermark {
 768         u32        lb_request_fifo_depth;
 769         fixed20_12 num_line_pair;
 770         fixed20_12 estimated_width;
 771         fixed20_12 worst_case_latency;
 772         fixed20_12 consumption_rate;
 773         fixed20_12 active_time;
 774         fixed20_12 dbpp;
 775         fixed20_12 priority_mark_max;
 776         fixed20_12 priority_mark;
 777         fixed20_12 sclk;
 778 };
 779
 780 void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
 781                                   struct radeon_crtc *crtc,
 782                                   struct rv515_watermark *wm)
 783 {
 784         struct drm_display_mode *mode = &crtc->base.mode;
 785         fixed20_12 a, b, c;
 786         fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
 787         fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
 788
 789         if (!crtc->base.enabled) {
 790                 /* FIXME: wouldn't it better to set priority mark to maximum */
 791                 wm->lb_request_fifo_depth = 4;
 792                 return;
 793         }
 794
 795         if (crtc->vsc.full > dfixed_const(2))
 796                 wm->num_line_pair.full = dfixed_const(2);
 797         else
 798                 wm->num_line_pair.full = dfixed_const(1);
 799
 800         b.full = dfixed_const(mode->crtc_hdisplay);
 801         c.full = dfixed_const(256);
 802         a.full = dfixed_div(b, c);
 803         request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
 804         request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
 805         if (a.full < dfixed_const(4)) {
 806                 wm->lb_request_fifo_depth = 4;
 807         } else {
 808                 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
 809         }
 810
 811         /* Determine consumption rate
 812          *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
 813          *  vtaps = number of vertical taps,
 814          *  vsc = vertical scaling ratio, defined as source/destination
 815          *  hsc = horizontal scaling ration, defined as source/destination
 816          */
 817         a.full = dfixed_const(mode->clock);
 818         b.full = dfixed_const(1000);
 819         a.full = dfixed_div(a, b);
 820         pclk.full = dfixed_div(b, a);
 821         if (crtc->rmx_type != RMX_OFF) {
 822                 b.full = dfixed_const(2);
 823                 if (crtc->vsc.full > b.full)
 824                         b.full = crtc->vsc.full;
 825                 b.full = dfixed_mul(b, crtc->hsc);
 826                 c.full = dfixed_const(2);
 827                 b.full = dfixed_div(b, c);
 828                 consumption_time.full = dfixed_div(pclk, b);
 829         } else {
 830                 consumption_time.full = pclk.full;
 831         }
 832         a.full = dfixed_const(1);
 833         wm->consumption_rate.full = dfixed_div(a, consumption_time);
 834
 835
 836         /* Determine line time
 837          *  LineTime = total time for one line of displayhtotal
 838          *  LineTime = total number of horizontal pixels
 839          *  pclk = pixel clock period(ns)
 840          */
 841         a.full = dfixed_const(crtc->base.mode.crtc_htotal);
 842         line_time.full = dfixed_mul(a, pclk);
 843
 844         /* Determine active time
 845          *  ActiveTime = time of active region of display within one line,
 846          *  hactive = total number of horizontal active pixels
 847          *  htotal = total number of horizontal pixels
 848          */
 849         a.full = dfixed_const(crtc->base.mode.crtc_htotal);
 850         b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
 851         wm->active_time.full = dfixed_mul(line_time, b);
 852         wm->active_time.full = dfixed_div(wm->active_time, a);
 853
 854         /* Determine chunk time
 855          * ChunkTime = the time it takes the DCP to send one chunk of data
 856          * to the LB which consists of pipeline delay and inter chunk gap
 857          * sclk = system clock(Mhz)
 858          */
 859         a.full = dfixed_const(600 * 1000);
 860         chunk_time.full = dfixed_div(a, rdev->pm.sclk);
 861         read_delay_latency.full = dfixed_const(1000);
 862
 863         /* Determine the worst case latency
 864          * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
 865          * WorstCaseLatency = worst case time from urgent to when the MC starts
 866          *                    to return data
 867          * READ_DELAY_IDLE_MAX = constant of 1us
 868          * ChunkTime = time it takes the DCP to send one chunk of data to the LB
 869          *             which consists of pipeline delay and inter chunk gap
 870          */
 871         if (dfixed_trunc(wm->num_line_pair) > 1) {
 872                 a.full = dfixed_const(3);
 873                 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
 874                 wm->worst_case_latency.full += read_delay_latency.full;
 875         } else {
 876                 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
 877         }
 878
 879         /* Determine the tolerable latency
 880          * TolerableLatency = Any given request has only 1 line time
 881          *                    for the data to be returned
 882          * LBRequestFifoDepth = Number of chunk requests the LB can
 883          *                      put into the request FIFO for a display
 884          *  LineTime = total time for one line of display
 885          *  ChunkTime = the time it takes the DCP to send one chunk
 886          *              of data to the LB which consists of
 887          *  pipeline delay and inter chunk gap
 888          */
 889         if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
 890                 tolerable_latency.full = line_time.full;
 891         } else {
 892                 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
 893                 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
 894                 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
 895                 tolerable_latency.full = line_time.full - tolerable_latency.full;
 896         }
 897         /* We assume worst case 32bits (4 bytes) */
 898         wm->dbpp.full = dfixed_const(2 * 16);
 899
 900         /* Determine the maximum priority mark
 901          *  width = viewport width in pixels
 902          */
 903         a.full = dfixed_const(16);
 904         wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
 905         wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
 906         wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
 907
 908         /* Determine estimated width */
 909         estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
 910         estimated_width.full = dfixed_div(estimated_width, consumption_time);
 911         if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
 912                 wm->priority_mark.full = wm->priority_mark_max.full;
 913         } else {
 914                 a.full = dfixed_const(16);
 915                 wm->priority_mark.full = dfixed_div(estimated_width, a);
 916                 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
 917                 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
 918         }
 919 }
 920
 921 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
 922 {
 923         struct drm_display_mode *mode0 = NULL;
 924         struct drm_display_mode *mode1 = NULL;
 925         struct rv515_watermark wm0;
 926         struct rv515_watermark wm1;
 927         u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt;
 928         fixed20_12 priority_mark02, priority_mark12, fill_rate;
 929         fixed20_12 a, b;
 930
 931         if (rdev->mode_info.crtcs[0]->base.enabled)
 932                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
 933         if (rdev->mode_info.crtcs[1]->base.enabled)
 934                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
 935         rs690_line_buffer_adjust(rdev, mode0, mode1);
 936
 937         rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
 938         rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
 939
 940         tmp = wm0.lb_request_fifo_depth;
 941         tmp |= wm1.lb_request_fifo_depth << 16;
 942         WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
 943
 944         if (mode0 && mode1) {
 945                 if (dfixed_trunc(wm0.dbpp) > 64)
 946                         a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
 947                 else
 948                         a.full = wm0.num_line_pair.full;
 949                 if (dfixed_trunc(wm1.dbpp) > 64)
 950                         b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
 951                 else
 952                         b.full = wm1.num_line_pair.full;
 953                 a.full += b.full;
 954                 fill_rate.full = dfixed_div(wm0.sclk, a);
 955                 if (wm0.consumption_rate.full > fill_rate.full) {
 956                         b.full = wm0.consumption_rate.full - fill_rate.full;
 957                         b.full = dfixed_mul(b, wm0.active_time);
 958                         a.full = dfixed_const(16);
 959                         b.full = dfixed_div(b, a);
 960                         a.full = dfixed_mul(wm0.worst_case_latency,
 961                                                 wm0.consumption_rate);
 962                         priority_mark02.full = a.full + b.full;
 963                 } else {
 964                         a.full = dfixed_mul(wm0.worst_case_latency,
 965                                                 wm0.consumption_rate);
 966                         b.full = dfixed_const(16 * 1000);
 967                         priority_mark02.full = dfixed_div(a, b);
 968                 }
 969                 if (wm1.consumption_rate.full > fill_rate.full) {
 970                         b.full = wm1.consumption_rate.full - fill_rate.full;
 971                         b.full = dfixed_mul(b, wm1.active_time);
 972                         a.full = dfixed_const(16);
 973                         b.full = dfixed_div(b, a);
 974                         a.full = dfixed_mul(wm1.worst_case_latency,
 975                                                 wm1.consumption_rate);
 976                         priority_mark12.full = a.full + b.full;
 977                 } else {
 978                         a.full = dfixed_mul(wm1.worst_case_latency,
 979                                                 wm1.consumption_rate);
 980                         b.full = dfixed_const(16 * 1000);
 981                         priority_mark12.full = dfixed_div(a, b);
 982                 }
 983                 if (wm0.priority_mark.full > priority_mark02.full)
 984                         priority_mark02.full = wm0.priority_mark.full;
 985                 if (dfixed_trunc(priority_mark02) < 0)
 986                         priority_mark02.full = 0;
 987                 if (wm0.priority_mark_max.full > priority_mark02.full)
 988                         priority_mark02.full = wm0.priority_mark_max.full;
 989                 if (wm1.priority_mark.full > priority_mark12.full)
 990                         priority_mark12.full = wm1.priority_mark.full;
 991                 if (dfixed_trunc(priority_mark12) < 0)
 992                         priority_mark12.full = 0;
 993                 if (wm1.priority_mark_max.full > priority_mark12.full)
 994                         priority_mark12.full = wm1.priority_mark_max.full;
 995                 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
 996                 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
 997                 if (rdev->disp_priority == 2) {
 998                         d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
 999                         d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1000                 }
1001                 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1002                 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
1003                 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1004                 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
1005         } else if (mode0) {
1006                 if (dfixed_trunc(wm0.dbpp) > 64)
1007                         a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
1008                 else
1009                         a.full = wm0.num_line_pair.full;
1010                 fill_rate.full = dfixed_div(wm0.sclk, a);
1011                 if (wm0.consumption_rate.full > fill_rate.full) {
1012                         b.full = wm0.consumption_rate.full - fill_rate.full;
1013                         b.full = dfixed_mul(b, wm0.active_time);
1014                         a.full = dfixed_const(16);
1015                         b.full = dfixed_div(b, a);
1016                         a.full = dfixed_mul(wm0.worst_case_latency,
1017                                                 wm0.consumption_rate);
1018                         priority_mark02.full = a.full + b.full;
1019                 } else {
1020                         a.full = dfixed_mul(wm0.worst_case_latency,
1021                                                 wm0.consumption_rate);
1022                         b.full = dfixed_const(16);
1023                         priority_mark02.full = dfixed_div(a, b);
1024                 }
1025                 if (wm0.priority_mark.full > priority_mark02.full)
1026                         priority_mark02.full = wm0.priority_mark.full;
1027                 if (dfixed_trunc(priority_mark02) < 0)
1028                         priority_mark02.full = 0;
1029                 if (wm0.priority_mark_max.full > priority_mark02.full)
1030                         priority_mark02.full = wm0.priority_mark_max.full;
1031                 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1032                 if (rdev->disp_priority == 2)
1033                         d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1034                 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1035                 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
1036                 WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1037                 WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1038         } else {
1039                 if (dfixed_trunc(wm1.dbpp) > 64)
1040                         a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
1041                 else
1042                         a.full = wm1.num_line_pair.full;
1043                 fill_rate.full = dfixed_div(wm1.sclk, a);
1044                 if (wm1.consumption_rate.full > fill_rate.full) {
1045                         b.full = wm1.consumption_rate.full - fill_rate.full;
1046                         b.full = dfixed_mul(b, wm1.active_time);
1047                         a.full = dfixed_const(16);
1048                         b.full = dfixed_div(b, a);
1049                         a.full = dfixed_mul(wm1.worst_case_latency,
1050                                                 wm1.consumption_rate);
1051                         priority_mark12.full = a.full + b.full;
1052                 } else {
1053                         a.full = dfixed_mul(wm1.worst_case_latency,
1054                                                 wm1.consumption_rate);
1055                         b.full = dfixed_const(16 * 1000);
1056                         priority_mark12.full = dfixed_div(a, b);
1057                 }
1058                 if (wm1.priority_mark.full > priority_mark12.full)
1059                         priority_mark12.full = wm1.priority_mark.full;
1060                 if (dfixed_trunc(priority_mark12) < 0)
1061                         priority_mark12.full = 0;
1062                 if (wm1.priority_mark_max.full > priority_mark12.full)
1063                         priority_mark12.full = wm1.priority_mark_max.full;
1064                 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1065                 if (rdev->disp_priority == 2)
1066                         d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1067                 WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1068                 WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1069                 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1070                 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
1071         }
1072 }
1073
1074 void rv515_bandwidth_update(struct radeon_device *rdev)
1075 {
1076         uint32_t tmp;
1077         struct drm_display_mode *mode0 = NULL;
1078         struct drm_display_mode *mode1 = NULL;
1079
1080         radeon_update_display_priority(rdev);
1081
1082         if (rdev->mode_info.crtcs[0]->base.enabled)
1083                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1084         if (rdev->mode_info.crtcs[1]->base.enabled)
1085                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1086         /*
1087          * Set display0/1 priority up in the memory controller for
1088          * modes if the user specifies HIGH for displaypriority
1089          * option.
1090          */
1091         if ((rdev->disp_priority == 2) &&
1092             (rdev->family == CHIP_RV515)) {
1093                 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1094                 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1095                 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1096                 if (mode1)
1097                         tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1098                 if (mode0)
1099                         tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1100                 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1101         }
1102         rv515_bandwidth_avivo_update(rdev);
1103 }