Merge tag 'v2.6.35-rc6' into drm-radeon-next
[sfrench/cifs-2.6.git] / drivers / gpu / drm / radeon / rs400.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include <drm/drmP.h>
31 #include "radeon.h"
32 #include "radeon_asic.h"
33 #include "rs400d.h"
34
35 /* This files gather functions specifics to : rs400,rs480 */
36 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
37
38 void rs400_gart_adjust_size(struct radeon_device *rdev)
39 {
40         /* Check gart size */
41         switch (rdev->mc.gtt_size/(1024*1024)) {
42         case 32:
43         case 64:
44         case 128:
45         case 256:
46         case 512:
47         case 1024:
48         case 2048:
49                 break;
50         default:
51                 DRM_ERROR("Unable to use IGP GART size %uM\n",
52                           (unsigned)(rdev->mc.gtt_size >> 20));
53                 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
54                 DRM_ERROR("Forcing to 32M GART size\n");
55                 rdev->mc.gtt_size = 32 * 1024 * 1024;
56                 return;
57         }
58         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
59                 /* FIXME: RS400 & RS480 seems to have issue with GART size
60                  * if 4G of system memory (needs more testing)
61                  */
62                 /* XXX is this still an issue with proper alignment? */
63                 rdev->mc.gtt_size = 32 * 1024 * 1024;
64                 DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n");
65         }
66 }
67
68 void rs400_gart_tlb_flush(struct radeon_device *rdev)
69 {
70         uint32_t tmp;
71         unsigned int timeout = rdev->usec_timeout;
72
73         WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
74         do {
75                 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
76                 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
77                         break;
78                 DRM_UDELAY(1);
79                 timeout--;
80         } while (timeout > 0);
81         WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
82 }
83
84 int rs400_gart_init(struct radeon_device *rdev)
85 {
86         int r;
87
88         if (rdev->gart.table.ram.ptr) {
89                 WARN(1, "RS400 GART already initialized.\n");
90                 return 0;
91         }
92         /* Check gart size */
93         switch(rdev->mc.gtt_size / (1024 * 1024)) {
94         case 32:
95         case 64:
96         case 128:
97         case 256:
98         case 512:
99         case 1024:
100         case 2048:
101                 break;
102         default:
103                 return -EINVAL;
104         }
105         /* Initialize common gart structure */
106         r = radeon_gart_init(rdev);
107         if (r)
108                 return r;
109         if (rs400_debugfs_pcie_gart_info_init(rdev))
110                 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
111         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
112         return radeon_gart_table_ram_alloc(rdev);
113 }
114
115 int rs400_gart_enable(struct radeon_device *rdev)
116 {
117         uint32_t size_reg;
118         uint32_t tmp;
119
120         radeon_gart_restore(rdev);
121         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
122         tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
123         WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
124         /* Check gart size */
125         switch(rdev->mc.gtt_size / (1024 * 1024)) {
126         case 32:
127                 size_reg = RS480_VA_SIZE_32MB;
128                 break;
129         case 64:
130                 size_reg = RS480_VA_SIZE_64MB;
131                 break;
132         case 128:
133                 size_reg = RS480_VA_SIZE_128MB;
134                 break;
135         case 256:
136                 size_reg = RS480_VA_SIZE_256MB;
137                 break;
138         case 512:
139                 size_reg = RS480_VA_SIZE_512MB;
140                 break;
141         case 1024:
142                 size_reg = RS480_VA_SIZE_1GB;
143                 break;
144         case 2048:
145                 size_reg = RS480_VA_SIZE_2GB;
146                 break;
147         default:
148                 return -EINVAL;
149         }
150         /* It should be fine to program it to max value */
151         if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
152                 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
153                 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
154         } else {
155                 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
156                 WREG32(RS480_AGP_BASE_2, 0);
157         }
158         tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
159         tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
160         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
161                 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
162                 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
163                 WREG32(RADEON_BUS_CNTL, tmp);
164         } else {
165                 WREG32(RADEON_MC_AGP_LOCATION, tmp);
166                 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
167                 WREG32(RADEON_BUS_CNTL, tmp);
168         }
169         /* Table should be in 32bits address space so ignore bits above. */
170         tmp = (u32)rdev->gart.table_addr & 0xfffff000;
171         tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
172
173         WREG32_MC(RS480_GART_BASE, tmp);
174         /* TODO: more tweaking here */
175         WREG32_MC(RS480_GART_FEATURE_ID,
176                   (RS480_TLB_ENABLE |
177                    RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
178         /* Disable snooping */
179         WREG32_MC(RS480_AGP_MODE_CNTL,
180                   (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
181         /* Disable AGP mode */
182         /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
183          * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
184         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
185                 WREG32_MC(RS480_MC_MISC_CNTL,
186                           (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN));
187         } else {
188                 WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
189         }
190         /* Enable gart */
191         WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
192         rs400_gart_tlb_flush(rdev);
193         rdev->gart.ready = true;
194         return 0;
195 }
196
197 void rs400_gart_disable(struct radeon_device *rdev)
198 {
199         uint32_t tmp;
200
201         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
202         tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
203         WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
204         WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
205 }
206
207 void rs400_gart_fini(struct radeon_device *rdev)
208 {
209         radeon_gart_fini(rdev);
210         rs400_gart_disable(rdev);
211         radeon_gart_table_ram_free(rdev);
212 }
213
214 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
215 {
216         uint32_t entry;
217
218         if (i < 0 || i > rdev->gart.num_gpu_pages) {
219                 return -EINVAL;
220         }
221
222         entry = (lower_32_bits(addr) & PAGE_MASK) |
223                 ((upper_32_bits(addr) & 0xff) << 4) |
224                 0xc;
225         entry = cpu_to_le32(entry);
226         rdev->gart.table.ram.ptr[i] = entry;
227         return 0;
228 }
229
230 int rs400_mc_wait_for_idle(struct radeon_device *rdev)
231 {
232         unsigned i;
233         uint32_t tmp;
234
235         for (i = 0; i < rdev->usec_timeout; i++) {
236                 /* read MC_STATUS */
237                 tmp = RREG32(0x0150);
238                 if (tmp & (1 << 2)) {
239                         return 0;
240                 }
241                 DRM_UDELAY(1);
242         }
243         return -1;
244 }
245
246 void rs400_gpu_init(struct radeon_device *rdev)
247 {
248         /* FIXME: is this correct ? */
249         r420_pipes_init(rdev);
250         if (rs400_mc_wait_for_idle(rdev)) {
251                 printk(KERN_WARNING "rs400: Failed to wait MC idle while "
252                        "programming pipes. Bad things might happen. %08x\n", RREG32(0x150));
253         }
254 }
255
256 void rs400_mc_init(struct radeon_device *rdev)
257 {
258         u64 base;
259
260         rs400_gart_adjust_size(rdev);
261         rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
262         /* DDR for all card after R300 & IGP */
263         rdev->mc.vram_is_ddr = true;
264         rdev->mc.vram_width = 128;
265         r100_vram_init_sizes(rdev);
266         base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
267         radeon_vram_location(rdev, &rdev->mc, base);
268         rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
269         radeon_gtt_location(rdev, &rdev->mc);
270         radeon_update_bandwidth_info(rdev);
271 }
272
273 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
274 {
275         uint32_t r;
276
277         WREG32(RS480_NB_MC_INDEX, reg & 0xff);
278         r = RREG32(RS480_NB_MC_DATA);
279         WREG32(RS480_NB_MC_INDEX, 0xff);
280         return r;
281 }
282
283 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
284 {
285         WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
286         WREG32(RS480_NB_MC_DATA, (v));
287         WREG32(RS480_NB_MC_INDEX, 0xff);
288 }
289
290 #if defined(CONFIG_DEBUG_FS)
291 static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
292 {
293         struct drm_info_node *node = (struct drm_info_node *) m->private;
294         struct drm_device *dev = node->minor->dev;
295         struct radeon_device *rdev = dev->dev_private;
296         uint32_t tmp;
297
298         tmp = RREG32(RADEON_HOST_PATH_CNTL);
299         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
300         tmp = RREG32(RADEON_BUS_CNTL);
301         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
302         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
303         seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
304         if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
305                 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
306                 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
307                 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
308                 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
309                 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
310                 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
311                 tmp = RREG32_MC(0x100);
312                 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
313                 tmp = RREG32(0x134);
314                 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
315         } else {
316                 tmp = RREG32(RADEON_AGP_BASE);
317                 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
318                 tmp = RREG32(RS480_AGP_BASE_2);
319                 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
320                 tmp = RREG32(RADEON_MC_AGP_LOCATION);
321                 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
322         }
323         tmp = RREG32_MC(RS480_GART_BASE);
324         seq_printf(m, "GART_BASE 0x%08x\n", tmp);
325         tmp = RREG32_MC(RS480_GART_FEATURE_ID);
326         seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
327         tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
328         seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
329         tmp = RREG32_MC(RS480_MC_MISC_CNTL);
330         seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
331         tmp = RREG32_MC(0x5F);
332         seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
333         tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
334         seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
335         tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
336         seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
337         tmp = RREG32_MC(0x3B);
338         seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
339         tmp = RREG32_MC(0x3C);
340         seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
341         tmp = RREG32_MC(0x30);
342         seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
343         tmp = RREG32_MC(0x31);
344         seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
345         tmp = RREG32_MC(0x32);
346         seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
347         tmp = RREG32_MC(0x33);
348         seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
349         tmp = RREG32_MC(0x34);
350         seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
351         tmp = RREG32_MC(0x35);
352         seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
353         tmp = RREG32_MC(0x36);
354         seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
355         tmp = RREG32_MC(0x37);
356         seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
357         return 0;
358 }
359
360 static struct drm_info_list rs400_gart_info_list[] = {
361         {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},
362 };
363 #endif
364
365 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
366 {
367 #if defined(CONFIG_DEBUG_FS)
368         return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
369 #else
370         return 0;
371 #endif
372 }
373
374 void rs400_mc_program(struct radeon_device *rdev)
375 {
376         struct r100_mc_save save;
377
378         /* Stops all mc clients */
379         r100_mc_stop(rdev, &save);
380
381         /* Wait for mc idle */
382         if (rs400_mc_wait_for_idle(rdev))
383                 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
384         WREG32(R_000148_MC_FB_LOCATION,
385                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
386                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
387
388         r100_mc_resume(rdev, &save);
389 }
390
391 static int rs400_startup(struct radeon_device *rdev)
392 {
393         int r;
394
395         r100_set_common_regs(rdev);
396
397         rs400_mc_program(rdev);
398         /* Resume clock */
399         r300_clock_startup(rdev);
400         /* Initialize GPU configuration (# pipes, ...) */
401         rs400_gpu_init(rdev);
402         r100_enable_bm(rdev);
403         /* Initialize GART (initialize after TTM so we can allocate
404          * memory through TTM but finalize after TTM) */
405         r = rs400_gart_enable(rdev);
406         if (r)
407                 return r;
408         /* Enable IRQ */
409         r100_irq_set(rdev);
410         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
411         /* 1M ring buffer */
412         r = r100_cp_init(rdev, 1024 * 1024);
413         if (r) {
414                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
415                 return r;
416         }
417         r = r100_wb_init(rdev);
418         if (r)
419                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
420         r = r100_ib_init(rdev);
421         if (r) {
422                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
423                 return r;
424         }
425         return 0;
426 }
427
428 int rs400_resume(struct radeon_device *rdev)
429 {
430         /* Make sur GART are not working */
431         rs400_gart_disable(rdev);
432         /* Resume clock before doing reset */
433         r300_clock_startup(rdev);
434         /* setup MC before calling post tables */
435         rs400_mc_program(rdev);
436         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
437         if (radeon_asic_reset(rdev)) {
438                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
439                         RREG32(R_000E40_RBBM_STATUS),
440                         RREG32(R_0007C0_CP_STAT));
441         }
442         /* post */
443         radeon_combios_asic_init(rdev->ddev);
444         /* Resume clock after posting */
445         r300_clock_startup(rdev);
446         /* Initialize surface registers */
447         radeon_surface_init(rdev);
448         return rs400_startup(rdev);
449 }
450
451 int rs400_suspend(struct radeon_device *rdev)
452 {
453         r100_cp_disable(rdev);
454         r100_wb_disable(rdev);
455         r100_irq_disable(rdev);
456         rs400_gart_disable(rdev);
457         return 0;
458 }
459
460 void rs400_fini(struct radeon_device *rdev)
461 {
462         r100_cp_fini(rdev);
463         r100_wb_fini(rdev);
464         r100_ib_fini(rdev);
465         radeon_gem_fini(rdev);
466         rs400_gart_fini(rdev);
467         radeon_irq_kms_fini(rdev);
468         radeon_fence_driver_fini(rdev);
469         radeon_bo_fini(rdev);
470         radeon_atombios_fini(rdev);
471         kfree(rdev->bios);
472         rdev->bios = NULL;
473 }
474
475 int rs400_init(struct radeon_device *rdev)
476 {
477         int r;
478
479         /* Disable VGA */
480         r100_vga_render_disable(rdev);
481         /* Initialize scratch registers */
482         radeon_scratch_init(rdev);
483         /* Initialize surface registers */
484         radeon_surface_init(rdev);
485         /* TODO: disable VGA need to use VGA request */
486         /* restore some register to sane defaults */
487         r100_restore_sanity(rdev);
488         /* BIOS*/
489         if (!radeon_get_bios(rdev)) {
490                 if (ASIC_IS_AVIVO(rdev))
491                         return -EINVAL;
492         }
493         if (rdev->is_atom_bios) {
494                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
495                 return -EINVAL;
496         } else {
497                 r = radeon_combios_init(rdev);
498                 if (r)
499                         return r;
500         }
501         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
502         if (radeon_asic_reset(rdev)) {
503                 dev_warn(rdev->dev,
504                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
505                         RREG32(R_000E40_RBBM_STATUS),
506                         RREG32(R_0007C0_CP_STAT));
507         }
508         /* check if cards are posted or not */
509         if (radeon_boot_test_post_card(rdev) == false)
510                 return -EINVAL;
511
512         /* Initialize clocks */
513         radeon_get_clock_info(rdev->ddev);
514         /* initialize memory controller */
515         rs400_mc_init(rdev);
516         /* Fence driver */
517         r = radeon_fence_driver_init(rdev);
518         if (r)
519                 return r;
520         r = radeon_irq_kms_init(rdev);
521         if (r)
522                 return r;
523         /* Memory manager */
524         r = radeon_bo_init(rdev);
525         if (r)
526                 return r;
527         r = rs400_gart_init(rdev);
528         if (r)
529                 return r;
530         r300_set_reg_safe(rdev);
531         rdev->accel_working = true;
532         r = rs400_startup(rdev);
533         if (r) {
534                 /* Somethings want wront with the accel init stop accel */
535                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
536                 r100_cp_fini(rdev);
537                 r100_wb_fini(rdev);
538                 r100_ib_fini(rdev);
539                 rs400_gart_fini(rdev);
540                 radeon_irq_kms_fini(rdev);
541                 rdev->accel_working = false;
542         }
543         return 0;
544 }