Merge branches 'slab/fixes', 'slob/fixes', 'slub/cleanups' and 'slub/fixes' into...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / radeon / radeon_pm.c
1 /*
2  * Permission is hereby granted, free of charge, to any person obtaining a
3  * copy of this software and associated documentation files (the "Software"),
4  * to deal in the Software without restriction, including without limitation
5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6  * and/or sell copies of the Software, and to permit persons to whom the
7  * Software is furnished to do so, subject to the following conditions:
8  *
9  * The above copyright notice and this permission notice shall be included in
10  * all copies or substantial portions of the Software.
11  *
12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18  * OTHER DEALINGS IN THE SOFTWARE.
19  *
20  * Authors: Rafał Miłecki <zajec5@gmail.com>
21  *          Alex Deucher <alexdeucher@gmail.com>
22  */
23 #include "drmP.h"
24 #include "radeon.h"
25 #include "avivod.h"
26 #ifdef CONFIG_ACPI
27 #include <linux/acpi.h>
28 #endif
29 #include <linux/power_supply.h>
30
31 #define RADEON_IDLE_LOOP_MS 100
32 #define RADEON_RECLOCK_DELAY_MS 200
33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
34 #define RADEON_WAIT_IDLE_TIMEOUT 200
35
36 static const char *radeon_pm_state_type_name[5] = {
37         "Default",
38         "Powersave",
39         "Battery",
40         "Balanced",
41         "Performance",
42 };
43
44 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
45 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
46 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
47 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
48 static void radeon_pm_update_profile(struct radeon_device *rdev);
49 static void radeon_pm_set_clocks(struct radeon_device *rdev);
50
51 #define ACPI_AC_CLASS           "ac_adapter"
52
53 #ifdef CONFIG_ACPI
54 static int radeon_acpi_event(struct notifier_block *nb,
55                              unsigned long val,
56                              void *data)
57 {
58         struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
59         struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
60
61         if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
62                 if (power_supply_is_system_supplied() > 0)
63                         DRM_DEBUG("pm: AC\n");
64                 else
65                         DRM_DEBUG("pm: DC\n");
66
67                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
68                         if (rdev->pm.profile == PM_PROFILE_AUTO) {
69                                 mutex_lock(&rdev->pm.mutex);
70                                 radeon_pm_update_profile(rdev);
71                                 radeon_pm_set_clocks(rdev);
72                                 mutex_unlock(&rdev->pm.mutex);
73                         }
74                 }
75         }
76
77         return NOTIFY_OK;
78 }
79 #endif
80
81 static void radeon_pm_update_profile(struct radeon_device *rdev)
82 {
83         switch (rdev->pm.profile) {
84         case PM_PROFILE_DEFAULT:
85                 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
86                 break;
87         case PM_PROFILE_AUTO:
88                 if (power_supply_is_system_supplied() > 0) {
89                         if (rdev->pm.active_crtc_count > 1)
90                                 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
91                         else
92                                 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
93                 } else {
94                         if (rdev->pm.active_crtc_count > 1)
95                                 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
96                         else
97                                 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
98                 }
99                 break;
100         case PM_PROFILE_LOW:
101                 if (rdev->pm.active_crtc_count > 1)
102                         rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
103                 else
104                         rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
105                 break;
106         case PM_PROFILE_MID:
107                 if (rdev->pm.active_crtc_count > 1)
108                         rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
109                 else
110                         rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
111                 break;
112         case PM_PROFILE_HIGH:
113                 if (rdev->pm.active_crtc_count > 1)
114                         rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
115                 else
116                         rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
117                 break;
118         }
119
120         if (rdev->pm.active_crtc_count == 0) {
121                 rdev->pm.requested_power_state_index =
122                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
123                 rdev->pm.requested_clock_mode_index =
124                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
125         } else {
126                 rdev->pm.requested_power_state_index =
127                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
128                 rdev->pm.requested_clock_mode_index =
129                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
130         }
131 }
132
133 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
134 {
135         struct radeon_bo *bo, *n;
136
137         if (list_empty(&rdev->gem.objects))
138                 return;
139
140         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
141                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
142                         ttm_bo_unmap_virtual(&bo->tbo);
143         }
144 }
145
146 static void radeon_sync_with_vblank(struct radeon_device *rdev)
147 {
148         if (rdev->pm.active_crtcs) {
149                 rdev->pm.vblank_sync = false;
150                 wait_event_timeout(
151                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
152                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
153         }
154 }
155
156 static void radeon_set_power_state(struct radeon_device *rdev)
157 {
158         u32 sclk, mclk;
159         bool misc_after = false;
160
161         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
162             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
163                 return;
164
165         if (radeon_gui_idle(rdev)) {
166                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
167                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
168                 if (sclk > rdev->clock.default_sclk)
169                         sclk = rdev->clock.default_sclk;
170
171                 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
172                         clock_info[rdev->pm.requested_clock_mode_index].mclk;
173                 if (mclk > rdev->clock.default_mclk)
174                         mclk = rdev->clock.default_mclk;
175
176                 /* upvolt before raising clocks, downvolt after lowering clocks */
177                 if (sclk < rdev->pm.current_sclk)
178                         misc_after = true;
179
180                 radeon_sync_with_vblank(rdev);
181
182                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
183                         if (!radeon_pm_in_vbl(rdev))
184                                 return;
185                 }
186
187                 radeon_pm_prepare(rdev);
188
189                 if (!misc_after)
190                         /* voltage, pcie lanes, etc.*/
191                         radeon_pm_misc(rdev);
192
193                 /* set engine clock */
194                 if (sclk != rdev->pm.current_sclk) {
195                         radeon_pm_debug_check_in_vbl(rdev, false);
196                         radeon_set_engine_clock(rdev, sclk);
197                         radeon_pm_debug_check_in_vbl(rdev, true);
198                         rdev->pm.current_sclk = sclk;
199                         DRM_DEBUG("Setting: e: %d\n", sclk);
200                 }
201
202                 /* set memory clock */
203                 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
204                         radeon_pm_debug_check_in_vbl(rdev, false);
205                         radeon_set_memory_clock(rdev, mclk);
206                         radeon_pm_debug_check_in_vbl(rdev, true);
207                         rdev->pm.current_mclk = mclk;
208                         DRM_DEBUG("Setting: m: %d\n", mclk);
209                 }
210
211                 if (misc_after)
212                         /* voltage, pcie lanes, etc.*/
213                         radeon_pm_misc(rdev);
214
215                 radeon_pm_finish(rdev);
216
217                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
218                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
219         } else
220                 DRM_DEBUG("pm: GUI not idle!!!\n");
221 }
222
223 static void radeon_pm_set_clocks(struct radeon_device *rdev)
224 {
225         int i;
226
227         mutex_lock(&rdev->ddev->struct_mutex);
228         mutex_lock(&rdev->vram_mutex);
229         mutex_lock(&rdev->cp.mutex);
230
231         /* gui idle int has issues on older chips it seems */
232         if (rdev->family >= CHIP_R600) {
233                 if (rdev->irq.installed) {
234                         /* wait for GPU idle */
235                         rdev->pm.gui_idle = false;
236                         rdev->irq.gui_idle = true;
237                         radeon_irq_set(rdev);
238                         wait_event_interruptible_timeout(
239                                 rdev->irq.idle_queue, rdev->pm.gui_idle,
240                                 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
241                         rdev->irq.gui_idle = false;
242                         radeon_irq_set(rdev);
243                 }
244         } else {
245                 if (rdev->cp.ready) {
246                         struct radeon_fence *fence;
247                         radeon_ring_alloc(rdev, 64);
248                         radeon_fence_create(rdev, &fence);
249                         radeon_fence_emit(rdev, fence);
250                         radeon_ring_commit(rdev);
251                         radeon_fence_wait(fence, false);
252                         radeon_fence_unref(&fence);
253                 }
254         }
255         radeon_unmap_vram_bos(rdev);
256
257         if (rdev->irq.installed) {
258                 for (i = 0; i < rdev->num_crtc; i++) {
259                         if (rdev->pm.active_crtcs & (1 << i)) {
260                                 rdev->pm.req_vblank |= (1 << i);
261                                 drm_vblank_get(rdev->ddev, i);
262                         }
263                 }
264         }
265
266         radeon_set_power_state(rdev);
267
268         if (rdev->irq.installed) {
269                 for (i = 0; i < rdev->num_crtc; i++) {
270                         if (rdev->pm.req_vblank & (1 << i)) {
271                                 rdev->pm.req_vblank &= ~(1 << i);
272                                 drm_vblank_put(rdev->ddev, i);
273                         }
274                 }
275         }
276
277         /* update display watermarks based on new power state */
278         radeon_update_bandwidth_info(rdev);
279         if (rdev->pm.active_crtc_count)
280                 radeon_bandwidth_update(rdev);
281
282         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
283
284         mutex_unlock(&rdev->cp.mutex);
285         mutex_unlock(&rdev->vram_mutex);
286         mutex_unlock(&rdev->ddev->struct_mutex);
287 }
288
289 static void radeon_pm_print_states(struct radeon_device *rdev)
290 {
291         int i, j;
292         struct radeon_power_state *power_state;
293         struct radeon_pm_clock_info *clock_info;
294
295         DRM_DEBUG("%d Power State(s)\n", rdev->pm.num_power_states);
296         for (i = 0; i < rdev->pm.num_power_states; i++) {
297                 power_state = &rdev->pm.power_state[i];
298                 DRM_DEBUG("State %d: %s\n", i,
299                         radeon_pm_state_type_name[power_state->type]);
300                 if (i == rdev->pm.default_power_state_index)
301                         DRM_DEBUG("\tDefault");
302                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
303                         DRM_DEBUG("\t%d PCIE Lanes\n", power_state->pcie_lanes);
304                 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
305                         DRM_DEBUG("\tSingle display only\n");
306                 DRM_DEBUG("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
307                 for (j = 0; j < power_state->num_clock_modes; j++) {
308                         clock_info = &(power_state->clock_info[j]);
309                         if (rdev->flags & RADEON_IS_IGP)
310                                 DRM_DEBUG("\t\t%d e: %d%s\n",
311                                         j,
312                                         clock_info->sclk * 10,
313                                         clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
314                         else
315                                 DRM_DEBUG("\t\t%d e: %d\tm: %d\tv: %d%s\n",
316                                         j,
317                                         clock_info->sclk * 10,
318                                         clock_info->mclk * 10,
319                                         clock_info->voltage.voltage,
320                                         clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
321                 }
322         }
323 }
324
325 static ssize_t radeon_get_pm_profile(struct device *dev,
326                                      struct device_attribute *attr,
327                                      char *buf)
328 {
329         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
330         struct radeon_device *rdev = ddev->dev_private;
331         int cp = rdev->pm.profile;
332
333         return snprintf(buf, PAGE_SIZE, "%s\n",
334                         (cp == PM_PROFILE_AUTO) ? "auto" :
335                         (cp == PM_PROFILE_LOW) ? "low" :
336                         (cp == PM_PROFILE_MID) ? "mid" :
337                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
338 }
339
340 static ssize_t radeon_set_pm_profile(struct device *dev,
341                                      struct device_attribute *attr,
342                                      const char *buf,
343                                      size_t count)
344 {
345         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
346         struct radeon_device *rdev = ddev->dev_private;
347
348         mutex_lock(&rdev->pm.mutex);
349         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
350                 if (strncmp("default", buf, strlen("default")) == 0)
351                         rdev->pm.profile = PM_PROFILE_DEFAULT;
352                 else if (strncmp("auto", buf, strlen("auto")) == 0)
353                         rdev->pm.profile = PM_PROFILE_AUTO;
354                 else if (strncmp("low", buf, strlen("low")) == 0)
355                         rdev->pm.profile = PM_PROFILE_LOW;
356                 else if (strncmp("mid", buf, strlen("mid")) == 0)
357                         rdev->pm.profile = PM_PROFILE_MID;
358                 else if (strncmp("high", buf, strlen("high")) == 0)
359                         rdev->pm.profile = PM_PROFILE_HIGH;
360                 else {
361                         DRM_ERROR("invalid power profile!\n");
362                         goto fail;
363                 }
364                 radeon_pm_update_profile(rdev);
365                 radeon_pm_set_clocks(rdev);
366         }
367 fail:
368         mutex_unlock(&rdev->pm.mutex);
369
370         return count;
371 }
372
373 static ssize_t radeon_get_pm_method(struct device *dev,
374                                     struct device_attribute *attr,
375                                     char *buf)
376 {
377         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
378         struct radeon_device *rdev = ddev->dev_private;
379         int pm = rdev->pm.pm_method;
380
381         return snprintf(buf, PAGE_SIZE, "%s\n",
382                         (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
383 }
384
385 static ssize_t radeon_set_pm_method(struct device *dev,
386                                     struct device_attribute *attr,
387                                     const char *buf,
388                                     size_t count)
389 {
390         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
391         struct radeon_device *rdev = ddev->dev_private;
392
393
394         if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
395                 mutex_lock(&rdev->pm.mutex);
396                 rdev->pm.pm_method = PM_METHOD_DYNPM;
397                 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
398                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
399                 mutex_unlock(&rdev->pm.mutex);
400         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
401                 bool flush_wq = false;
402
403                 mutex_lock(&rdev->pm.mutex);
404                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
405                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
406                         flush_wq = true;
407                 }
408                 /* disable dynpm */
409                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
410                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
411                 rdev->pm.pm_method = PM_METHOD_PROFILE;
412                 mutex_unlock(&rdev->pm.mutex);
413                 if (flush_wq)
414                         flush_workqueue(rdev->wq);
415         } else {
416                 DRM_ERROR("invalid power method!\n");
417                 goto fail;
418         }
419         radeon_pm_compute_clocks(rdev);
420 fail:
421         return count;
422 }
423
424 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
425 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
426
427 void radeon_pm_suspend(struct radeon_device *rdev)
428 {
429         bool flush_wq = false;
430
431         mutex_lock(&rdev->pm.mutex);
432         if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
433                 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
434                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
435                         rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
436                 flush_wq = true;
437         }
438         mutex_unlock(&rdev->pm.mutex);
439         if (flush_wq)
440                 flush_workqueue(rdev->wq);
441 }
442
443 void radeon_pm_resume(struct radeon_device *rdev)
444 {
445         /* asic init will reset the default power state */
446         mutex_lock(&rdev->pm.mutex);
447         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
448         rdev->pm.current_clock_mode_index = 0;
449         rdev->pm.current_sclk = rdev->clock.default_sclk;
450         rdev->pm.current_mclk = rdev->clock.default_mclk;
451         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
452         if (rdev->pm.pm_method == PM_METHOD_DYNPM
453             && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
454                 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
455                 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
456                                         msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
457         }
458         mutex_unlock(&rdev->pm.mutex);
459         radeon_pm_compute_clocks(rdev);
460 }
461
462 int radeon_pm_init(struct radeon_device *rdev)
463 {
464         int ret;
465         /* default to profile method */
466         rdev->pm.pm_method = PM_METHOD_PROFILE;
467         rdev->pm.profile = PM_PROFILE_DEFAULT;
468         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
469         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
470         rdev->pm.dynpm_can_upclock = true;
471         rdev->pm.dynpm_can_downclock = true;
472         rdev->pm.current_sclk = rdev->clock.default_sclk;
473         rdev->pm.current_mclk = rdev->clock.default_mclk;
474
475         if (rdev->bios) {
476                 if (rdev->is_atom_bios)
477                         radeon_atombios_get_power_modes(rdev);
478                 else
479                         radeon_combios_get_power_modes(rdev);
480                 radeon_pm_print_states(rdev);
481                 radeon_pm_init_profile(rdev);
482         }
483
484         if (rdev->pm.num_power_states > 1) {
485                 /* where's the best place to put these? */
486                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
487                 if (ret)
488                         DRM_ERROR("failed to create device file for power profile\n");
489                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
490                 if (ret)
491                         DRM_ERROR("failed to create device file for power method\n");
492
493 #ifdef CONFIG_ACPI
494                 rdev->acpi_nb.notifier_call = radeon_acpi_event;
495                 register_acpi_notifier(&rdev->acpi_nb);
496 #endif
497                 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
498
499                 if (radeon_debugfs_pm_init(rdev)) {
500                         DRM_ERROR("Failed to register debugfs file for PM!\n");
501                 }
502
503                 DRM_INFO("radeon: power management initialized\n");
504         }
505
506         return 0;
507 }
508
509 void radeon_pm_fini(struct radeon_device *rdev)
510 {
511         if (rdev->pm.num_power_states > 1) {
512                 bool flush_wq = false;
513
514                 mutex_lock(&rdev->pm.mutex);
515                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
516                         rdev->pm.profile = PM_PROFILE_DEFAULT;
517                         radeon_pm_update_profile(rdev);
518                         radeon_pm_set_clocks(rdev);
519                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
520                         /* cancel work */
521                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
522                         flush_wq = true;
523                         /* reset default clocks */
524                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
525                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
526                         radeon_pm_set_clocks(rdev);
527                 }
528                 mutex_unlock(&rdev->pm.mutex);
529                 if (flush_wq)
530                         flush_workqueue(rdev->wq);
531
532                 device_remove_file(rdev->dev, &dev_attr_power_profile);
533                 device_remove_file(rdev->dev, &dev_attr_power_method);
534 #ifdef CONFIG_ACPI
535                 unregister_acpi_notifier(&rdev->acpi_nb);
536 #endif
537         }
538
539         if (rdev->pm.i2c_bus)
540                 radeon_i2c_destroy(rdev->pm.i2c_bus);
541 }
542
543 void radeon_pm_compute_clocks(struct radeon_device *rdev)
544 {
545         struct drm_device *ddev = rdev->ddev;
546         struct drm_crtc *crtc;
547         struct radeon_crtc *radeon_crtc;
548
549         if (rdev->pm.num_power_states < 2)
550                 return;
551
552         mutex_lock(&rdev->pm.mutex);
553
554         rdev->pm.active_crtcs = 0;
555         rdev->pm.active_crtc_count = 0;
556         list_for_each_entry(crtc,
557                 &ddev->mode_config.crtc_list, head) {
558                 radeon_crtc = to_radeon_crtc(crtc);
559                 if (radeon_crtc->enabled) {
560                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
561                         rdev->pm.active_crtc_count++;
562                 }
563         }
564
565         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
566                 radeon_pm_update_profile(rdev);
567                 radeon_pm_set_clocks(rdev);
568         } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
569                 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
570                         if (rdev->pm.active_crtc_count > 1) {
571                                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
572                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
573
574                                         rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
575                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
576                                         radeon_pm_get_dynpm_state(rdev);
577                                         radeon_pm_set_clocks(rdev);
578
579                                         DRM_DEBUG("radeon: dynamic power management deactivated\n");
580                                 }
581                         } else if (rdev->pm.active_crtc_count == 1) {
582                                 /* TODO: Increase clocks if needed for current mode */
583
584                                 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
585                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
586                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
587                                         radeon_pm_get_dynpm_state(rdev);
588                                         radeon_pm_set_clocks(rdev);
589
590                                         queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
591                                                            msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
592                                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
593                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
594                                         queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
595                                                            msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
596                                         DRM_DEBUG("radeon: dynamic power management activated\n");
597                                 }
598                         } else { /* count == 0 */
599                                 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
600                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
601
602                                         rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
603                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
604                                         radeon_pm_get_dynpm_state(rdev);
605                                         radeon_pm_set_clocks(rdev);
606                                 }
607                         }
608                 }
609         }
610
611         mutex_unlock(&rdev->pm.mutex);
612 }
613
614 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
615 {
616         u32 stat_crtc = 0, vbl = 0, position = 0;
617         bool in_vbl = true;
618
619         if (ASIC_IS_DCE4(rdev)) {
620                 if (rdev->pm.active_crtcs & (1 << 0)) {
621                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
622                                      EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
623                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
624                                           EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
625                 }
626                 if (rdev->pm.active_crtcs & (1 << 1)) {
627                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
628                                      EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
629                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
630                                           EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
631                 }
632                 if (rdev->pm.active_crtcs & (1 << 2)) {
633                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
634                                      EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
635                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
636                                           EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
637                 }
638                 if (rdev->pm.active_crtcs & (1 << 3)) {
639                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
640                                      EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
641                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
642                                           EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
643                 }
644                 if (rdev->pm.active_crtcs & (1 << 4)) {
645                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
646                                      EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
647                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
648                                           EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
649                 }
650                 if (rdev->pm.active_crtcs & (1 << 5)) {
651                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
652                                      EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
653                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
654                                           EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
655                 }
656         } else if (ASIC_IS_AVIVO(rdev)) {
657                 if (rdev->pm.active_crtcs & (1 << 0)) {
658                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END) & 0xfff;
659                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION) & 0xfff;
660                 }
661                 if (rdev->pm.active_crtcs & (1 << 1)) {
662                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END) & 0xfff;
663                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION) & 0xfff;
664                 }
665                 if (position < vbl && position > 1)
666                         in_vbl = false;
667         } else {
668                 if (rdev->pm.active_crtcs & (1 << 0)) {
669                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
670                         if (!(stat_crtc & 1))
671                                 in_vbl = false;
672                 }
673                 if (rdev->pm.active_crtcs & (1 << 1)) {
674                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
675                         if (!(stat_crtc & 1))
676                                 in_vbl = false;
677                 }
678         }
679
680         if (position < vbl && position > 1)
681                 in_vbl = false;
682
683         return in_vbl;
684 }
685
686 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
687 {
688         u32 stat_crtc = 0;
689         bool in_vbl = radeon_pm_in_vbl(rdev);
690
691         if (in_vbl == false)
692                 DRM_DEBUG("not in vbl for pm change %08x at %s\n", stat_crtc,
693                          finish ? "exit" : "entry");
694         return in_vbl;
695 }
696
697 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
698 {
699         struct radeon_device *rdev;
700         int resched;
701         rdev = container_of(work, struct radeon_device,
702                                 pm.dynpm_idle_work.work);
703
704         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
705         mutex_lock(&rdev->pm.mutex);
706         if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
707                 unsigned long irq_flags;
708                 int not_processed = 0;
709
710                 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
711                 if (!list_empty(&rdev->fence_drv.emited)) {
712                         struct list_head *ptr;
713                         list_for_each(ptr, &rdev->fence_drv.emited) {
714                                 /* count up to 3, that's enought info */
715                                 if (++not_processed >= 3)
716                                         break;
717                         }
718                 }
719                 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
720
721                 if (not_processed >= 3) { /* should upclock */
722                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
723                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
724                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
725                                    rdev->pm.dynpm_can_upclock) {
726                                 rdev->pm.dynpm_planned_action =
727                                         DYNPM_ACTION_UPCLOCK;
728                                 rdev->pm.dynpm_action_timeout = jiffies +
729                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
730                         }
731                 } else if (not_processed == 0) { /* should downclock */
732                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
733                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
734                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
735                                    rdev->pm.dynpm_can_downclock) {
736                                 rdev->pm.dynpm_planned_action =
737                                         DYNPM_ACTION_DOWNCLOCK;
738                                 rdev->pm.dynpm_action_timeout = jiffies +
739                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
740                         }
741                 }
742
743                 /* Note, radeon_pm_set_clocks is called with static_switch set
744                  * to false since we want to wait for vbl to avoid flicker.
745                  */
746                 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
747                     jiffies > rdev->pm.dynpm_action_timeout) {
748                         radeon_pm_get_dynpm_state(rdev);
749                         radeon_pm_set_clocks(rdev);
750                 }
751
752                 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
753                                         msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
754         }
755         mutex_unlock(&rdev->pm.mutex);
756         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
757 }
758
759 /*
760  * Debugfs info
761  */
762 #if defined(CONFIG_DEBUG_FS)
763
764 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
765 {
766         struct drm_info_node *node = (struct drm_info_node *) m->private;
767         struct drm_device *dev = node->minor->dev;
768         struct radeon_device *rdev = dev->dev_private;
769
770         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
771         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
772         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
773         if (rdev->asic->get_memory_clock)
774                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
775         if (rdev->pm.current_vddc)
776                 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
777         if (rdev->asic->get_pcie_lanes)
778                 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
779
780         return 0;
781 }
782
783 static struct drm_info_list radeon_pm_info_list[] = {
784         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
785 };
786 #endif
787
788 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
789 {
790 #if defined(CONFIG_DEBUG_FS)
791         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
792 #else
793         return 0;
794 #endif
795 }