drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include "drmP.h"
  24 #include "radeon.h"
  25 #include "avivod.h"
  26 #ifdef CONFIG_ACPI
  27 #include <linux/acpi.h>
  28 #endif
  29 #include <linux/power_supply.h>
  30
  31 #define RADEON_IDLE_LOOP_MS 100
  32 #define RADEON_RECLOCK_DELAY_MS 200
  33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  34 #define RADEON_WAIT_IDLE_TIMEOUT 200
  35
  36 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
  37 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  38 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
  39 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  40 static void radeon_pm_update_profile(struct radeon_device *rdev);
  41 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  42
  43 #define ACPI_AC_CLASS           "ac_adapter"
  44
  45 #ifdef CONFIG_ACPI
  46 static int radeon_acpi_event(struct notifier_block *nb,
  47                              unsigned long val,
  48                              void *data)
  49 {
  50         struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
  51         struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
  52
  53         if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
  54                 if (power_supply_is_system_supplied() > 0)
  55                         DRM_DEBUG("pm: AC\n");
  56                 else
  57                         DRM_DEBUG("pm: DC\n");
  58
  59                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  60                         if (rdev->pm.profile == PM_PROFILE_AUTO) {
  61                                 mutex_lock(&rdev->pm.mutex);
  62                                 radeon_pm_update_profile(rdev);
  63                                 radeon_pm_set_clocks(rdev);
  64                                 mutex_unlock(&rdev->pm.mutex);
  65                         }
  66                 }
  67         }
  68
  69         return NOTIFY_OK;
  70 }
  71 #endif
  72
  73 static void radeon_pm_update_profile(struct radeon_device *rdev)
  74 {
  75         switch (rdev->pm.profile) {
  76         case PM_PROFILE_DEFAULT:
  77                 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
  78                 break;
  79         case PM_PROFILE_AUTO:
  80                 if (power_supply_is_system_supplied() > 0) {
  81                         if (rdev->pm.active_crtc_count > 1)
  82                                 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
  83                         else
  84                                 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
  85                 } else {
  86                         if (rdev->pm.active_crtc_count > 1)
  87                                 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
  88                         else
  89                                 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
  90                 }
  91                 break;
  92         case PM_PROFILE_LOW:
  93                 if (rdev->pm.active_crtc_count > 1)
  94                         rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
  95                 else
  96                         rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
  97                 break;
  98         case PM_PROFILE_HIGH:
  99                 if (rdev->pm.active_crtc_count > 1)
 100                         rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 101                 else
 102                         rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 103                 break;
 104         }
 105
 106         if (rdev->pm.active_crtc_count == 0) {
 107                 rdev->pm.requested_power_state_index =
 108                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
 109                 rdev->pm.requested_clock_mode_index =
 110                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
 111         } else {
 112                 rdev->pm.requested_power_state_index =
 113                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
 114                 rdev->pm.requested_clock_mode_index =
 115                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
 116         }
 117 }
 118
 119 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
 120 {
 121         struct radeon_bo *bo, *n;
 122
 123         if (list_empty(&rdev->gem.objects))
 124                 return;
 125
 126         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 127                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 128                         ttm_bo_unmap_virtual(&bo->tbo);
 129         }
 130
 131         if (rdev->gart.table.vram.robj)
 132                 ttm_bo_unmap_virtual(&rdev->gart.table.vram.robj->tbo);
 133
 134         if (rdev->stollen_vga_memory)
 135                 ttm_bo_unmap_virtual(&rdev->stollen_vga_memory->tbo);
 136
 137         if (rdev->r600_blit.shader_obj)
 138                 ttm_bo_unmap_virtual(&rdev->r600_blit.shader_obj->tbo);
 139 }
 140
 141 static void radeon_sync_with_vblank(struct radeon_device *rdev)
 142 {
 143         if (rdev->pm.active_crtcs) {
 144                 rdev->pm.vblank_sync = false;
 145                 wait_event_timeout(
 146                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 147                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 148         }
 149 }
 150
 151 static void radeon_set_power_state(struct radeon_device *rdev)
 152 {
 153         u32 sclk, mclk;
 154         bool misc_after = false;
 155
 156         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 157             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 158                 return;
 159
 160         if (radeon_gui_idle(rdev)) {
 161                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 162                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 163                 if (sclk > rdev->clock.default_sclk)
 164                         sclk = rdev->clock.default_sclk;
 165
 166                 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 167                         clock_info[rdev->pm.requested_clock_mode_index].mclk;
 168                 if (mclk > rdev->clock.default_mclk)
 169                         mclk = rdev->clock.default_mclk;
 170
 171                 /* upvolt before raising clocks, downvolt after lowering clocks */
 172                 if (sclk < rdev->pm.current_sclk)
 173                         misc_after = true;
 174
 175                 radeon_sync_with_vblank(rdev);
 176
 177                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 178                         if (!radeon_pm_in_vbl(rdev))
 179                                 return;
 180                 }
 181
 182                 radeon_pm_prepare(rdev);
 183
 184                 if (!misc_after)
 185                         /* voltage, pcie lanes, etc.*/
 186                         radeon_pm_misc(rdev);
 187
 188                 /* set engine clock */
 189                 if (sclk != rdev->pm.current_sclk) {
 190                         radeon_pm_debug_check_in_vbl(rdev, false);
 191                         radeon_set_engine_clock(rdev, sclk);
 192                         radeon_pm_debug_check_in_vbl(rdev, true);
 193                         rdev->pm.current_sclk = sclk;
 194                         DRM_DEBUG("Setting: e: %d\n", sclk);
 195                 }
 196
 197                 /* set memory clock */
 198                 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 199                         radeon_pm_debug_check_in_vbl(rdev, false);
 200                         radeon_set_memory_clock(rdev, mclk);
 201                         radeon_pm_debug_check_in_vbl(rdev, true);
 202                         rdev->pm.current_mclk = mclk;
 203                         DRM_DEBUG("Setting: m: %d\n", mclk);
 204                 }
 205
 206                 if (misc_after)
 207                         /* voltage, pcie lanes, etc.*/
 208                         radeon_pm_misc(rdev);
 209
 210                 radeon_pm_finish(rdev);
 211
 212                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 213                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 214         } else
 215                 DRM_DEBUG("pm: GUI not idle!!!\n");
 216 }
 217
 218 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 219 {
 220         int i;
 221
 222         mutex_lock(&rdev->ddev->struct_mutex);
 223         mutex_lock(&rdev->vram_mutex);
 224         mutex_lock(&rdev->cp.mutex);
 225
 226         /* gui idle int has issues on older chips it seems */
 227         if (rdev->family >= CHIP_R600) {
 228                 if (rdev->irq.installed) {
 229                         /* wait for GPU idle */
 230                         rdev->pm.gui_idle = false;
 231                         rdev->irq.gui_idle = true;
 232                         radeon_irq_set(rdev);
 233                         wait_event_interruptible_timeout(
 234                                 rdev->irq.idle_queue, rdev->pm.gui_idle,
 235                                 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
 236                         rdev->irq.gui_idle = false;
 237                         radeon_irq_set(rdev);
 238                 }
 239         } else {
 240                 if (rdev->cp.ready) {
 241                         struct radeon_fence *fence;
 242                         radeon_ring_alloc(rdev, 64);
 243                         radeon_fence_create(rdev, &fence);
 244                         radeon_fence_emit(rdev, fence);
 245                         radeon_ring_commit(rdev);
 246                         radeon_fence_wait(fence, false);
 247                         radeon_fence_unref(&fence);
 248                 }
 249         }
 250         radeon_unmap_vram_bos(rdev);
 251
 252         if (rdev->irq.installed) {
 253                 for (i = 0; i < rdev->num_crtc; i++) {
 254                         if (rdev->pm.active_crtcs & (1 << i)) {
 255                                 rdev->pm.req_vblank |= (1 << i);
 256                                 drm_vblank_get(rdev->ddev, i);
 257                         }
 258                 }
 259         }
 260
 261         radeon_set_power_state(rdev);
 262
 263         if (rdev->irq.installed) {
 264                 for (i = 0; i < rdev->num_crtc; i++) {
 265                         if (rdev->pm.req_vblank & (1 << i)) {
 266                                 rdev->pm.req_vblank &= ~(1 << i);
 267                                 drm_vblank_put(rdev->ddev, i);
 268                         }
 269                 }
 270         }
 271
 272         /* update display watermarks based on new power state */
 273         radeon_update_bandwidth_info(rdev);
 274         if (rdev->pm.active_crtc_count)
 275                 radeon_bandwidth_update(rdev);
 276
 277         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 278
 279         mutex_unlock(&rdev->cp.mutex);
 280         mutex_unlock(&rdev->vram_mutex);
 281         mutex_unlock(&rdev->ddev->struct_mutex);
 282 }
 283
 284 static ssize_t radeon_get_pm_profile(struct device *dev,
 285                                      struct device_attribute *attr,
 286                                      char *buf)
 287 {
 288         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 289         struct radeon_device *rdev = ddev->dev_private;
 290         int cp = rdev->pm.profile;
 291
 292         return snprintf(buf, PAGE_SIZE, "%s\n",
 293                         (cp == PM_PROFILE_AUTO) ? "auto" :
 294                         (cp == PM_PROFILE_LOW) ? "low" :
 295                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
 296 }
 297
 298 static ssize_t radeon_set_pm_profile(struct device *dev,
 299                                      struct device_attribute *attr,
 300                                      const char *buf,
 301                                      size_t count)
 302 {
 303         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 304         struct radeon_device *rdev = ddev->dev_private;
 305
 306         mutex_lock(&rdev->pm.mutex);
 307         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 308                 if (strncmp("default", buf, strlen("default")) == 0)
 309                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 310                 else if (strncmp("auto", buf, strlen("auto")) == 0)
 311                         rdev->pm.profile = PM_PROFILE_AUTO;
 312                 else if (strncmp("low", buf, strlen("low")) == 0)
 313                         rdev->pm.profile = PM_PROFILE_LOW;
 314                 else if (strncmp("high", buf, strlen("high")) == 0)
 315                         rdev->pm.profile = PM_PROFILE_HIGH;
 316                 else {
 317                         DRM_ERROR("invalid power profile!\n");
 318                         goto fail;
 319                 }
 320                 radeon_pm_update_profile(rdev);
 321                 radeon_pm_set_clocks(rdev);
 322         }
 323 fail:
 324         mutex_unlock(&rdev->pm.mutex);
 325
 326         return count;
 327 }
 328
 329 static ssize_t radeon_get_pm_method(struct device *dev,
 330                                     struct device_attribute *attr,
 331                                     char *buf)
 332 {
 333         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 334         struct radeon_device *rdev = ddev->dev_private;
 335         int pm = rdev->pm.pm_method;
 336
 337         return snprintf(buf, PAGE_SIZE, "%s\n",
 338                         (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
 339 }
 340
 341 static ssize_t radeon_set_pm_method(struct device *dev,
 342                                     struct device_attribute *attr,
 343                                     const char *buf,
 344                                     size_t count)
 345 {
 346         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 347         struct radeon_device *rdev = ddev->dev_private;
 348
 349
 350         if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
 351                 mutex_lock(&rdev->pm.mutex);
 352                 rdev->pm.pm_method = PM_METHOD_DYNPM;
 353                 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 354                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 355                 mutex_unlock(&rdev->pm.mutex);
 356         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
 357                 mutex_lock(&rdev->pm.mutex);
 358                 rdev->pm.pm_method = PM_METHOD_PROFILE;
 359                 /* disable dynpm */
 360                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 361                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 362                 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 363                 mutex_unlock(&rdev->pm.mutex);
 364         } else {
 365                 DRM_ERROR("invalid power method!\n");
 366                 goto fail;
 367         }
 368         radeon_pm_compute_clocks(rdev);
 369 fail:
 370         return count;
 371 }
 372
 373 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
 374 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
 375
 376 void radeon_pm_suspend(struct radeon_device *rdev)
 377 {
 378         mutex_lock(&rdev->pm.mutex);
 379         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 380         rdev->pm.current_power_state_index = -1;
 381         rdev->pm.current_clock_mode_index = -1;
 382         rdev->pm.current_sclk = 0;
 383         rdev->pm.current_mclk = 0;
 384         mutex_unlock(&rdev->pm.mutex);
 385 }
 386
 387 void radeon_pm_resume(struct radeon_device *rdev)
 388 {
 389         radeon_pm_compute_clocks(rdev);
 390 }
 391
 392 int radeon_pm_init(struct radeon_device *rdev)
 393 {
 394         int ret;
 395         /* default to profile method */
 396         rdev->pm.pm_method = PM_METHOD_PROFILE;
 397         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 398         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 399         rdev->pm.dynpm_can_upclock = true;
 400         rdev->pm.dynpm_can_downclock = true;
 401         rdev->pm.current_sclk = 0;
 402         rdev->pm.current_mclk = 0;
 403
 404         if (rdev->bios) {
 405                 if (rdev->is_atom_bios)
 406                         radeon_atombios_get_power_modes(rdev);
 407                 else
 408                         radeon_combios_get_power_modes(rdev);
 409                 radeon_pm_init_profile(rdev);
 410                 rdev->pm.current_power_state_index = -1;
 411                 rdev->pm.current_clock_mode_index = -1;
 412         }
 413
 414         if (rdev->pm.num_power_states > 1) {
 415                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 416                         mutex_lock(&rdev->pm.mutex);
 417                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 418                         radeon_pm_update_profile(rdev);
 419                         radeon_pm_set_clocks(rdev);
 420                         mutex_unlock(&rdev->pm.mutex);
 421                 }
 422
 423                 /* where's the best place to put these? */
 424                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
 425                 if (ret)
 426                         DRM_ERROR("failed to create device file for power profile\n");
 427                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
 428                 if (ret)
 429                         DRM_ERROR("failed to create device file for power method\n");
 430
 431 #ifdef CONFIG_ACPI
 432                 rdev->acpi_nb.notifier_call = radeon_acpi_event;
 433                 register_acpi_notifier(&rdev->acpi_nb);
 434 #endif
 435                 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
 436
 437                 if (radeon_debugfs_pm_init(rdev)) {
 438                         DRM_ERROR("Failed to register debugfs file for PM!\n");
 439                 }
 440
 441                 DRM_INFO("radeon: power management initialized\n");
 442         }
 443
 444         return 0;
 445 }
 446
 447 void radeon_pm_fini(struct radeon_device *rdev)
 448 {
 449         if (rdev->pm.num_power_states > 1) {
 450                 mutex_lock(&rdev->pm.mutex);
 451                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 452                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 453                         radeon_pm_update_profile(rdev);
 454                         radeon_pm_set_clocks(rdev);
 455                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 456                         /* cancel work */
 457                         cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 458                         /* reset default clocks */
 459                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 460                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 461                         radeon_pm_set_clocks(rdev);
 462                 }
 463                 mutex_unlock(&rdev->pm.mutex);
 464
 465                 device_remove_file(rdev->dev, &dev_attr_power_profile);
 466                 device_remove_file(rdev->dev, &dev_attr_power_method);
 467 #ifdef CONFIG_ACPI
 468                 unregister_acpi_notifier(&rdev->acpi_nb);
 469 #endif
 470         }
 471
 472         if (rdev->pm.i2c_bus)
 473                 radeon_i2c_destroy(rdev->pm.i2c_bus);
 474 }
 475
 476 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 477 {
 478         struct drm_device *ddev = rdev->ddev;
 479         struct drm_crtc *crtc;
 480         struct radeon_crtc *radeon_crtc;
 481
 482         if (rdev->pm.num_power_states < 2)
 483                 return;
 484
 485         mutex_lock(&rdev->pm.mutex);
 486
 487         rdev->pm.active_crtcs = 0;
 488         rdev->pm.active_crtc_count = 0;
 489         list_for_each_entry(crtc,
 490                 &ddev->mode_config.crtc_list, head) {
 491                 radeon_crtc = to_radeon_crtc(crtc);
 492                 if (radeon_crtc->enabled) {
 493                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 494                         rdev->pm.active_crtc_count++;
 495                 }
 496         }
 497
 498         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 499                 radeon_pm_update_profile(rdev);
 500                 radeon_pm_set_clocks(rdev);
 501         } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 502                 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
 503                         if (rdev->pm.active_crtc_count > 1) {
 504                                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 505                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 506
 507                                         rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 508                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 509                                         radeon_pm_get_dynpm_state(rdev);
 510                                         radeon_pm_set_clocks(rdev);
 511
 512                                         DRM_DEBUG("radeon: dynamic power management deactivated\n");
 513                                 }
 514                         } else if (rdev->pm.active_crtc_count == 1) {
 515                                 /* TODO: Increase clocks if needed for current mode */
 516
 517                                 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
 518                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 519                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
 520                                         radeon_pm_get_dynpm_state(rdev);
 521                                         radeon_pm_set_clocks(rdev);
 522
 523                                         queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
 524                                                            msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 525                                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
 526                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 527                                         queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
 528                                                            msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 529                                         DRM_DEBUG("radeon: dynamic power management activated\n");
 530                                 }
 531                         } else { /* count == 0 */
 532                                 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
 533                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 534
 535                                         rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
 536                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
 537                                         radeon_pm_get_dynpm_state(rdev);
 538                                         radeon_pm_set_clocks(rdev);
 539                                 }
 540                         }
 541                 }
 542         }
 543
 544         mutex_unlock(&rdev->pm.mutex);
 545 }
 546
 547 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
 548 {
 549         u32 stat_crtc = 0, vbl = 0, position = 0;
 550         bool in_vbl = true;
 551
 552         if (ASIC_IS_DCE4(rdev)) {
 553                 if (rdev->pm.active_crtcs & (1 << 0)) {
 554                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 555                                      EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
 556                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 557                                           EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
 558                 }
 559                 if (rdev->pm.active_crtcs & (1 << 1)) {
 560                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 561                                      EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
 562                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 563                                           EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
 564                 }
 565                 if (rdev->pm.active_crtcs & (1 << 2)) {
 566                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 567                                      EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
 568                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 569                                           EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
 570                 }
 571                 if (rdev->pm.active_crtcs & (1 << 3)) {
 572                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 573                                      EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
 574                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 575                                           EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
 576                 }
 577                 if (rdev->pm.active_crtcs & (1 << 4)) {
 578                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 579                                      EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
 580                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 581                                           EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
 582                 }
 583                 if (rdev->pm.active_crtcs & (1 << 5)) {
 584                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 585                                      EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
 586                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 587                                           EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
 588                 }
 589         } else if (ASIC_IS_AVIVO(rdev)) {
 590                 if (rdev->pm.active_crtcs & (1 << 0)) {
 591                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END) & 0xfff;
 592                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION) & 0xfff;
 593                 }
 594                 if (rdev->pm.active_crtcs & (1 << 1)) {
 595                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END) & 0xfff;
 596                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION) & 0xfff;
 597                 }
 598                 if (position < vbl && position > 1)
 599                         in_vbl = false;
 600         } else {
 601                 if (rdev->pm.active_crtcs & (1 << 0)) {
 602                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
 603                         if (!(stat_crtc & 1))
 604                                 in_vbl = false;
 605                 }
 606                 if (rdev->pm.active_crtcs & (1 << 1)) {
 607                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
 608                         if (!(stat_crtc & 1))
 609                                 in_vbl = false;
 610                 }
 611         }
 612
 613         if (position < vbl && position > 1)
 614                 in_vbl = false;
 615
 616         return in_vbl;
 617 }
 618
 619 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
 620 {
 621         u32 stat_crtc = 0;
 622         bool in_vbl = radeon_pm_in_vbl(rdev);
 623
 624         if (in_vbl == false)
 625                 DRM_DEBUG("not in vbl for pm change %08x at %s\n", stat_crtc,
 626                          finish ? "exit" : "entry");
 627         return in_vbl;
 628 }
 629
 630 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
 631 {
 632         struct radeon_device *rdev;
 633         int resched;
 634         rdev = container_of(work, struct radeon_device,
 635                                 pm.dynpm_idle_work.work);
 636
 637         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
 638         mutex_lock(&rdev->pm.mutex);
 639         if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 640                 unsigned long irq_flags;
 641                 int not_processed = 0;
 642
 643                 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
 644                 if (!list_empty(&rdev->fence_drv.emited)) {
 645                         struct list_head *ptr;
 646                         list_for_each(ptr, &rdev->fence_drv.emited) {
 647                                 /* count up to 3, that's enought info */
 648                                 if (++not_processed >= 3)
 649                                         break;
 650                         }
 651                 }
 652                 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
 653
 654                 if (not_processed >= 3) { /* should upclock */
 655                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
 656                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 657                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 658                                    rdev->pm.dynpm_can_upclock) {
 659                                 rdev->pm.dynpm_planned_action =
 660                                         DYNPM_ACTION_UPCLOCK;
 661                                 rdev->pm.dynpm_action_timeout = jiffies +
 662                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 663                         }
 664                 } else if (not_processed == 0) { /* should downclock */
 665                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
 666                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 667                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 668                                    rdev->pm.dynpm_can_downclock) {
 669                                 rdev->pm.dynpm_planned_action =
 670                                         DYNPM_ACTION_DOWNCLOCK;
 671                                 rdev->pm.dynpm_action_timeout = jiffies +
 672                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 673                         }
 674                 }
 675
 676                 /* Note, radeon_pm_set_clocks is called with static_switch set
 677                  * to false since we want to wait for vbl to avoid flicker.
 678                  */
 679                 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
 680                     jiffies > rdev->pm.dynpm_action_timeout) {
 681                         radeon_pm_get_dynpm_state(rdev);
 682                         radeon_pm_set_clocks(rdev);
 683                 }
 684         }
 685         mutex_unlock(&rdev->pm.mutex);
 686         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
 687
 688         queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
 689                                         msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 690 }
 691
 692 /*
 693  * Debugfs info
 694  */
 695 #if defined(CONFIG_DEBUG_FS)
 696
 697 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 698 {
 699         struct drm_info_node *node = (struct drm_info_node *) m->private;
 700         struct drm_device *dev = node->minor->dev;
 701         struct radeon_device *rdev = dev->dev_private;
 702
 703         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
 704         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 705         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
 706         if (rdev->asic->get_memory_clock)
 707                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 708         if (rdev->asic->get_pcie_lanes)
 709                 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
 710
 711         return 0;
 712 }
 713
 714 static struct drm_info_list radeon_pm_info_list[] = {
 715         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 716 };
 717 #endif
 718
 719 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 720 {
 721 #if defined(CONFIG_DEBUG_FS)
 722         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 723 #else
 724         return 0;
 725 #endif
 726 }