drivers/gpu/drm/radeon/radeon_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/radeon_drm.h>
  36 #include "radeon.h"
  37 #include "radeon_trace.h"
  38
  39
  40 int radeon_ttm_init(struct radeon_device *rdev);
  41 void radeon_ttm_fini(struct radeon_device *rdev);
  42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  43
  44 /*
  45  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  46  * function are calling it.
  47  */
  48
  49 void radeon_bo_clear_va(struct radeon_bo *bo)
  50 {
  51         struct radeon_bo_va *bo_va, *tmp;
  52
  53         list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
  54                 /* remove from all vm address space */
  55                 radeon_vm_bo_rmv(bo->rdev, bo_va);
  56         }
  57 }
  58
  59 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  60 {
  61         struct radeon_bo *bo;
  62
  63         bo = container_of(tbo, struct radeon_bo, tbo);
  64         mutex_lock(&bo->rdev->gem.mutex);
  65         list_del_init(&bo->list);
  66         mutex_unlock(&bo->rdev->gem.mutex);
  67         radeon_bo_clear_surface_reg(bo);
  68         radeon_bo_clear_va(bo);
  69         drm_gem_object_release(&bo->gem_base);
  70         kfree(bo);
  71 }
  72
  73 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
  74 {
  75         if (bo->destroy == &radeon_ttm_bo_destroy)
  76                 return true;
  77         return false;
  78 }
  79
  80 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
  81 {
  82         u32 c = 0;
  83
  84         rbo->placement.fpfn = 0;
  85         rbo->placement.lpfn = 0;
  86         rbo->placement.placement = rbo->placements;
  87         rbo->placement.busy_placement = rbo->placements;
  88         if (domain & RADEON_GEM_DOMAIN_VRAM)
  89                 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  90                                         TTM_PL_FLAG_VRAM;
  91         if (domain & RADEON_GEM_DOMAIN_GTT)
  92                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
  93         if (domain & RADEON_GEM_DOMAIN_CPU)
  94                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  95         if (!c)
  96                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  97         rbo->placement.num_placement = c;
  98         rbo->placement.num_busy_placement = c;
  99 }
 100
 101 int radeon_bo_create(struct radeon_device *rdev,
 102                      unsigned long size, int byte_align, bool kernel, u32 domain,
 103                      struct sg_table *sg, struct radeon_bo **bo_ptr)
 104 {
 105         struct radeon_bo *bo;
 106         enum ttm_bo_type type;
 107         unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 108         size_t acc_size;
 109         int r;
 110
 111         size = ALIGN(size, PAGE_SIZE);
 112
 113         rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
 114         if (kernel) {
 115                 type = ttm_bo_type_kernel;
 116         } else if (sg) {
 117                 type = ttm_bo_type_sg;
 118         } else {
 119                 type = ttm_bo_type_device;
 120         }
 121         *bo_ptr = NULL;
 122
 123         acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
 124                                        sizeof(struct radeon_bo));
 125
 126         bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
 127         if (bo == NULL)
 128                 return -ENOMEM;
 129         r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
 130         if (unlikely(r)) {
 131                 kfree(bo);
 132                 return r;
 133         }
 134         bo->rdev = rdev;
 135         bo->gem_base.driver_private = NULL;
 136         bo->surface_reg = -1;
 137         INIT_LIST_HEAD(&bo->list);
 138         INIT_LIST_HEAD(&bo->va);
 139         radeon_ttm_placement_from_domain(bo, domain);
 140         /* Kernel allocation are uninterruptible */
 141         down_read(&rdev->pm.mclk_lock);
 142         r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
 143                         &bo->placement, page_align, 0, !kernel, NULL,
 144                         acc_size, sg, &radeon_ttm_bo_destroy);
 145         up_read(&rdev->pm.mclk_lock);
 146         if (unlikely(r != 0)) {
 147                 return r;
 148         }
 149         *bo_ptr = bo;
 150
 151         trace_radeon_bo_create(bo);
 152
 153         return 0;
 154 }
 155
 156 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
 157 {
 158         bool is_iomem;
 159         int r;
 160
 161         if (bo->kptr) {
 162                 if (ptr) {
 163                         *ptr = bo->kptr;
 164                 }
 165                 return 0;
 166         }
 167         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 168         if (r) {
 169                 return r;
 170         }
 171         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 172         if (ptr) {
 173                 *ptr = bo->kptr;
 174         }
 175         radeon_bo_check_tiling(bo, 0, 0);
 176         return 0;
 177 }
 178
 179 void radeon_bo_kunmap(struct radeon_bo *bo)
 180 {
 181         if (bo->kptr == NULL)
 182                 return;
 183         bo->kptr = NULL;
 184         radeon_bo_check_tiling(bo, 0, 0);
 185         ttm_bo_kunmap(&bo->kmap);
 186 }
 187
 188 void radeon_bo_unref(struct radeon_bo **bo)
 189 {
 190         struct ttm_buffer_object *tbo;
 191         struct radeon_device *rdev;
 192
 193         if ((*bo) == NULL)
 194                 return;
 195         rdev = (*bo)->rdev;
 196         tbo = &((*bo)->tbo);
 197         down_read(&rdev->pm.mclk_lock);
 198         ttm_bo_unref(&tbo);
 199         up_read(&rdev->pm.mclk_lock);
 200         if (tbo == NULL)
 201                 *bo = NULL;
 202 }
 203
 204 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
 205                              u64 *gpu_addr)
 206 {
 207         int r, i;
 208
 209         if (bo->pin_count) {
 210                 bo->pin_count++;
 211                 if (gpu_addr)
 212                         *gpu_addr = radeon_bo_gpu_offset(bo);
 213
 214                 if (max_offset != 0) {
 215                         u64 domain_start;
 216
 217                         if (domain == RADEON_GEM_DOMAIN_VRAM)
 218                                 domain_start = bo->rdev->mc.vram_start;
 219                         else
 220                                 domain_start = bo->rdev->mc.gtt_start;
 221                         WARN_ON_ONCE(max_offset <
 222                                      (radeon_bo_gpu_offset(bo) - domain_start));
 223                 }
 224
 225                 return 0;
 226         }
 227         radeon_ttm_placement_from_domain(bo, domain);
 228         if (domain == RADEON_GEM_DOMAIN_VRAM) {
 229                 /* force to pin into visible video ram */
 230                 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 231         }
 232         if (max_offset) {
 233                 u64 lpfn = max_offset >> PAGE_SHIFT;
 234
 235                 if (!bo->placement.lpfn)
 236                         bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
 237
 238                 if (lpfn < bo->placement.lpfn)
 239                         bo->placement.lpfn = lpfn;
 240         }
 241         for (i = 0; i < bo->placement.num_placement; i++)
 242                 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
 243         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
 244         if (likely(r == 0)) {
 245                 bo->pin_count = 1;
 246                 if (gpu_addr != NULL)
 247                         *gpu_addr = radeon_bo_gpu_offset(bo);
 248         }
 249         if (unlikely(r != 0))
 250                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
 251         return r;
 252 }
 253
 254 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
 255 {
 256         return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
 257 }
 258
 259 int radeon_bo_unpin(struct radeon_bo *bo)
 260 {
 261         int r, i;
 262
 263         if (!bo->pin_count) {
 264                 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
 265                 return 0;
 266         }
 267         bo->pin_count--;
 268         if (bo->pin_count)
 269                 return 0;
 270         for (i = 0; i < bo->placement.num_placement; i++)
 271                 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
 272         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
 273         if (unlikely(r != 0))
 274                 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
 275         return r;
 276 }
 277
 278 int radeon_bo_evict_vram(struct radeon_device *rdev)
 279 {
 280         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 281         if (0 && (rdev->flags & RADEON_IS_IGP)) {
 282                 if (rdev->mc.igp_sideport_enabled == false)
 283                         /* Useless to evict on IGP chips */
 284                         return 0;
 285         }
 286         return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 287 }
 288
 289 void radeon_bo_force_delete(struct radeon_device *rdev)
 290 {
 291         struct radeon_bo *bo, *n;
 292
 293         if (list_empty(&rdev->gem.objects)) {
 294                 return;
 295         }
 296         dev_err(rdev->dev, "Userspace still has active objects !\n");
 297         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 298                 mutex_lock(&rdev->ddev->struct_mutex);
 299                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
 300                         &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
 301                         *((unsigned long *)&bo->gem_base.refcount));
 302                 mutex_lock(&bo->rdev->gem.mutex);
 303                 list_del_init(&bo->list);
 304                 mutex_unlock(&bo->rdev->gem.mutex);
 305                 /* this should unref the ttm bo */
 306                 drm_gem_object_unreference(&bo->gem_base);
 307                 mutex_unlock(&rdev->ddev->struct_mutex);
 308         }
 309 }
 310
 311 int radeon_bo_init(struct radeon_device *rdev)
 312 {
 313         /* Add an MTRR for the VRAM */
 314         rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
 315                         MTRR_TYPE_WRCOMB, 1);
 316         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 317                 rdev->mc.mc_vram_size >> 20,
 318                 (unsigned long long)rdev->mc.aper_size >> 20);
 319         DRM_INFO("RAM width %dbits %cDR\n",
 320                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 321         return radeon_ttm_init(rdev);
 322 }
 323
 324 void radeon_bo_fini(struct radeon_device *rdev)
 325 {
 326         radeon_ttm_fini(rdev);
 327 }
 328
 329 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
 330                                 struct list_head *head)
 331 {
 332         if (lobj->wdomain) {
 333                 list_add(&lobj->tv.head, head);
 334         } else {
 335                 list_add_tail(&lobj->tv.head, head);
 336         }
 337 }
 338
 339 int radeon_bo_list_validate(struct list_head *head)
 340 {
 341         struct radeon_bo_list *lobj;
 342         struct radeon_bo *bo;
 343         u32 domain;
 344         int r;
 345
 346         r = ttm_eu_reserve_buffers(head);
 347         if (unlikely(r != 0)) {
 348                 return r;
 349         }
 350         list_for_each_entry(lobj, head, tv.head) {
 351                 bo = lobj->bo;
 352                 if (!bo->pin_count) {
 353                         domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
 354
 355                 retry:
 356                         radeon_ttm_placement_from_domain(bo, domain);
 357                         r = ttm_bo_validate(&bo->tbo, &bo->placement,
 358                                                 true, false, false);
 359                         if (unlikely(r)) {
 360                                 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
 361                                         domain |= RADEON_GEM_DOMAIN_GTT;
 362                                         goto retry;
 363                                 }
 364                                 return r;
 365                         }
 366                 }
 367                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
 368                 lobj->tiling_flags = bo->tiling_flags;
 369         }
 370         return 0;
 371 }
 372
 373 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
 374                              struct vm_area_struct *vma)
 375 {
 376         return ttm_fbdev_mmap(vma, &bo->tbo);
 377 }
 378
 379 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
 380 {
 381         struct radeon_device *rdev = bo->rdev;
 382         struct radeon_surface_reg *reg;
 383         struct radeon_bo *old_object;
 384         int steal;
 385         int i;
 386
 387         BUG_ON(!atomic_read(&bo->tbo.reserved));
 388
 389         if (!bo->tiling_flags)
 390                 return 0;
 391
 392         if (bo->surface_reg >= 0) {
 393                 reg = &rdev->surface_regs[bo->surface_reg];
 394                 i = bo->surface_reg;
 395                 goto out;
 396         }
 397
 398         steal = -1;
 399         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 400
 401                 reg = &rdev->surface_regs[i];
 402                 if (!reg->bo)
 403                         break;
 404
 405                 old_object = reg->bo;
 406                 if (old_object->pin_count == 0)
 407                         steal = i;
 408         }
 409
 410         /* if we are all out */
 411         if (i == RADEON_GEM_MAX_SURFACES) {
 412                 if (steal == -1)
 413                         return -ENOMEM;
 414                 /* find someone with a surface reg and nuke their BO */
 415                 reg = &rdev->surface_regs[steal];
 416                 old_object = reg->bo;
 417                 /* blow away the mapping */
 418                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
 419                 ttm_bo_unmap_virtual(&old_object->tbo);
 420                 old_object->surface_reg = -1;
 421                 i = steal;
 422         }
 423
 424         bo->surface_reg = i;
 425         reg->bo = bo;
 426
 427 out:
 428         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
 429                                bo->tbo.mem.start << PAGE_SHIFT,
 430                                bo->tbo.num_pages << PAGE_SHIFT);
 431         return 0;
 432 }
 433
 434 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
 435 {
 436         struct radeon_device *rdev = bo->rdev;
 437         struct radeon_surface_reg *reg;
 438
 439         if (bo->surface_reg == -1)
 440                 return;
 441
 442         reg = &rdev->surface_regs[bo->surface_reg];
 443         radeon_clear_surface_reg(rdev, bo->surface_reg);
 444
 445         reg->bo = NULL;
 446         bo->surface_reg = -1;
 447 }
 448
 449 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
 450                                 uint32_t tiling_flags, uint32_t pitch)
 451 {
 452         struct radeon_device *rdev = bo->rdev;
 453         int r;
 454
 455         if (rdev->family >= CHIP_CEDAR) {
 456                 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
 457
 458                 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
 459                 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
 460                 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
 461                 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
 462                 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
 463                 switch (bankw) {
 464                 case 0:
 465                 case 1:
 466                 case 2:
 467                 case 4:
 468                 case 8:
 469                         break;
 470                 default:
 471                         return -EINVAL;
 472                 }
 473                 switch (bankh) {
 474                 case 0:
 475                 case 1:
 476                 case 2:
 477                 case 4:
 478                 case 8:
 479                         break;
 480                 default:
 481                         return -EINVAL;
 482                 }
 483                 switch (mtaspect) {
 484                 case 0:
 485                 case 1:
 486                 case 2:
 487                 case 4:
 488                 case 8:
 489                         break;
 490                 default:
 491                         return -EINVAL;
 492                 }
 493                 if (tilesplit > 6) {
 494                         return -EINVAL;
 495                 }
 496                 if (stilesplit > 6) {
 497                         return -EINVAL;
 498                 }
 499         }
 500         r = radeon_bo_reserve(bo, false);
 501         if (unlikely(r != 0))
 502                 return r;
 503         bo->tiling_flags = tiling_flags;
 504         bo->pitch = pitch;
 505         radeon_bo_unreserve(bo);
 506         return 0;
 507 }
 508
 509 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
 510                                 uint32_t *tiling_flags,
 511                                 uint32_t *pitch)
 512 {
 513         BUG_ON(!atomic_read(&bo->tbo.reserved));
 514         if (tiling_flags)
 515                 *tiling_flags = bo->tiling_flags;
 516         if (pitch)
 517                 *pitch = bo->pitch;
 518 }
 519
 520 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
 521                                 bool force_drop)
 522 {
 523         BUG_ON(!atomic_read(&bo->tbo.reserved));
 524
 525         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
 526                 return 0;
 527
 528         if (force_drop) {
 529                 radeon_bo_clear_surface_reg(bo);
 530                 return 0;
 531         }
 532
 533         if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
 534                 if (!has_moved)
 535                         return 0;
 536
 537                 if (bo->surface_reg >= 0)
 538                         radeon_bo_clear_surface_reg(bo);
 539                 return 0;
 540         }
 541
 542         if ((bo->surface_reg >= 0) && !has_moved)
 543                 return 0;
 544
 545         return radeon_bo_get_surface_reg(bo);
 546 }
 547
 548 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
 549                            struct ttm_mem_reg *mem)
 550 {
 551         struct radeon_bo *rbo;
 552         if (!radeon_ttm_bo_is_radeon_bo(bo))
 553                 return;
 554         rbo = container_of(bo, struct radeon_bo, tbo);
 555         radeon_bo_check_tiling(rbo, 0, 1);
 556         radeon_vm_bo_invalidate(rbo->rdev, rbo);
 557 }
 558
 559 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 560 {
 561         struct radeon_device *rdev;
 562         struct radeon_bo *rbo;
 563         unsigned long offset, size;
 564         int r;
 565
 566         if (!radeon_ttm_bo_is_radeon_bo(bo))
 567                 return 0;
 568         rbo = container_of(bo, struct radeon_bo, tbo);
 569         radeon_bo_check_tiling(rbo, 0, 0);
 570         rdev = rbo->rdev;
 571         if (bo->mem.mem_type == TTM_PL_VRAM) {
 572                 size = bo->mem.num_pages << PAGE_SHIFT;
 573                 offset = bo->mem.start << PAGE_SHIFT;
 574                 if ((offset + size) > rdev->mc.visible_vram_size) {
 575                         /* hurrah the memory is not visible ! */
 576                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
 577                         rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
 578                         r = ttm_bo_validate(bo, &rbo->placement, false, true, false);
 579                         if (unlikely(r != 0))
 580                                 return r;
 581                         offset = bo->mem.start << PAGE_SHIFT;
 582                         /* this should not happen */
 583                         if ((offset + size) > rdev->mc.visible_vram_size)
 584                                 return -EINVAL;
 585                 }
 586         }
 587         return 0;
 588 }
 589
 590 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
 591 {
 592         int r;
 593
 594         r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
 595         if (unlikely(r != 0))
 596                 return r;
 597         spin_lock(&bo->tbo.bdev->fence_lock);
 598         if (mem_type)
 599                 *mem_type = bo->tbo.mem.mem_type;
 600         if (bo->tbo.sync_obj)
 601                 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
 602         spin_unlock(&bo->tbo.bdev->fence_lock);
 603         ttm_bo_unreserve(&bo->tbo);
 604         return r;
 605 }
 606
 607
 608 /**
 609  * radeon_bo_reserve - reserve bo
 610  * @bo:         bo structure
 611  * @no_intr:    don't return -ERESTARTSYS on pending signal
 612  *
 613  * Returns:
 614  * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
 615  * a signal. Release all buffer reservations and return to user-space.
 616  */
 617 int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr)
 618 {
 619         int r;
 620
 621         r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0);
 622         if (unlikely(r != 0)) {
 623                 if (r != -ERESTARTSYS)
 624                         dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
 625                 return r;
 626         }
 627         return 0;
 628 }