drivers/gpu/drm/radeon/radeon_legacy_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
  33 {
  34         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  35         struct drm_encoder_helper_funcs *encoder_funcs;
  36
  37         encoder_funcs = encoder->helper_private;
  38         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  39         radeon_encoder->active_device = 0;
  40 }
  41
  42 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
  43 {
  44         struct drm_device *dev = encoder->dev;
  45         struct radeon_device *rdev = dev->dev_private;
  46         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  47         uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
  48         int panel_pwr_delay = 2000;
  49         bool is_mac = false;
  50         DRM_DEBUG("\n");
  51
  52         if (radeon_encoder->enc_priv) {
  53                 if (rdev->is_atom_bios) {
  54                         struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
  55                         panel_pwr_delay = lvds->panel_pwr_delay;
  56                 } else {
  57                         struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
  58                         panel_pwr_delay = lvds->panel_pwr_delay;
  59                 }
  60         }
  61
  62         /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
  63          * Taken from radeonfb.
  64          */
  65         if ((rdev->mode_info.connector_table == CT_IBOOK) ||
  66             (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
  67             (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
  68             (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
  69                 is_mac = true;
  70
  71         switch (mode) {
  72         case DRM_MODE_DPMS_ON:
  73                 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
  74                 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
  75                 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
  76                 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  77                 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
  78                 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  79                 udelay(1000);
  80
  81                 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  82                 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
  83                 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  84
  85                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  86                 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON);
  87                 if (is_mac)
  88                         lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
  89                 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
  90                 udelay(panel_pwr_delay * 1000);
  91                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  92                 break;
  93         case DRM_MODE_DPMS_STANDBY:
  94         case DRM_MODE_DPMS_SUSPEND:
  95         case DRM_MODE_DPMS_OFF:
  96                 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
  97                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
  98                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  99                 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 100                 if (is_mac) {
 101                         lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
 102                         WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 103                         lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
 104                 } else {
 105                         WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 106                         lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
 107                 }
 108                 udelay(panel_pwr_delay * 1000);
 109                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 110                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 111                 break;
 112         }
 113
 114         if (rdev->is_atom_bios)
 115                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 116         else
 117                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 118
 119 }
 120
 121 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
 122 {
 123         struct radeon_device *rdev = encoder->dev->dev_private;
 124
 125         if (rdev->is_atom_bios)
 126                 radeon_atom_output_lock(encoder, true);
 127         else
 128                 radeon_combios_output_lock(encoder, true);
 129         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
 130 }
 131
 132 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
 133 {
 134         struct radeon_device *rdev = encoder->dev->dev_private;
 135
 136         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
 137         if (rdev->is_atom_bios)
 138                 radeon_atom_output_lock(encoder, false);
 139         else
 140                 radeon_combios_output_lock(encoder, false);
 141 }
 142
 143 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
 144                                         struct drm_display_mode *mode,
 145                                         struct drm_display_mode *adjusted_mode)
 146 {
 147         struct drm_device *dev = encoder->dev;
 148         struct radeon_device *rdev = dev->dev_private;
 149         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 150         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 151         uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
 152
 153         DRM_DEBUG("\n");
 154
 155         lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
 156         lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
 157
 158         lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
 159         if (rdev->is_atom_bios) {
 160                 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
 161                  * need to call that on resume to set up the reg properly.
 162                  */
 163                 radeon_encoder->pixel_clock = adjusted_mode->clock;
 164                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
 165                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 166         } else {
 167                 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
 168                 if (lvds) {
 169                         DRM_DEBUG("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
 170                         lvds_gen_cntl = lvds->lvds_gen_cntl;
 171                         lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
 172                                               (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
 173                         lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
 174                                              (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
 175                 } else
 176                         lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 177         }
 178         lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 179         lvds_gen_cntl &= ~(RADEON_LVDS_ON |
 180                            RADEON_LVDS_BLON |
 181                            RADEON_LVDS_EN |
 182                            RADEON_LVDS_RST_FM);
 183
 184         if (ASIC_IS_R300(rdev))
 185                 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
 186
 187         if (radeon_crtc->crtc_id == 0) {
 188                 if (ASIC_IS_R300(rdev)) {
 189                         if (radeon_encoder->rmx_type != RMX_OFF)
 190                                 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
 191                 } else
 192                         lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
 193         } else {
 194                 if (ASIC_IS_R300(rdev))
 195                         lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
 196                 else
 197                         lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
 198         }
 199
 200         WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 201         WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 202         WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
 203
 204         if (rdev->family == CHIP_RV410)
 205                 WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
 206
 207         if (rdev->is_atom_bios)
 208                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 209         else
 210                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 211 }
 212
 213 static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
 214                                      struct drm_display_mode *mode,
 215                                      struct drm_display_mode *adjusted_mode)
 216 {
 217         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 218
 219         /* set the active encoder to connector routing */
 220         radeon_encoder_set_active_device(encoder);
 221         drm_mode_set_crtcinfo(adjusted_mode, 0);
 222
 223         /* get the native mode for LVDS */
 224         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
 225                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 226
 227         return true;
 228 }
 229
 230 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
 231         .dpms = radeon_legacy_lvds_dpms,
 232         .mode_fixup = radeon_legacy_mode_fixup,
 233         .prepare = radeon_legacy_lvds_prepare,
 234         .mode_set = radeon_legacy_lvds_mode_set,
 235         .commit = radeon_legacy_lvds_commit,
 236         .disable = radeon_legacy_encoder_disable,
 237 };
 238
 239
 240 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
 241         .destroy = radeon_enc_destroy,
 242 };
 243
 244 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
 245 {
 246         struct drm_device *dev = encoder->dev;
 247         struct radeon_device *rdev = dev->dev_private;
 248         uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 249         uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
 250         uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 251
 252         DRM_DEBUG("\n");
 253
 254         switch (mode) {
 255         case DRM_MODE_DPMS_ON:
 256                 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
 257                 dac_cntl &= ~RADEON_DAC_PDWN;
 258                 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
 259                                     RADEON_DAC_PDWN_G |
 260                                     RADEON_DAC_PDWN_B);
 261                 break;
 262         case DRM_MODE_DPMS_STANDBY:
 263         case DRM_MODE_DPMS_SUSPEND:
 264         case DRM_MODE_DPMS_OFF:
 265                 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
 266                 dac_cntl |= RADEON_DAC_PDWN;
 267                 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
 268                                    RADEON_DAC_PDWN_G |
 269                                    RADEON_DAC_PDWN_B);
 270                 break;
 271         }
 272
 273         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 274         WREG32(RADEON_DAC_CNTL, dac_cntl);
 275         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 276
 277         if (rdev->is_atom_bios)
 278                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 279         else
 280                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 281
 282 }
 283
 284 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
 285 {
 286         struct radeon_device *rdev = encoder->dev->dev_private;
 287
 288         if (rdev->is_atom_bios)
 289                 radeon_atom_output_lock(encoder, true);
 290         else
 291                 radeon_combios_output_lock(encoder, true);
 292         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 293 }
 294
 295 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
 296 {
 297         struct radeon_device *rdev = encoder->dev->dev_private;
 298
 299         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 300
 301         if (rdev->is_atom_bios)
 302                 radeon_atom_output_lock(encoder, false);
 303         else
 304                 radeon_combios_output_lock(encoder, false);
 305 }
 306
 307 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
 308                                                struct drm_display_mode *mode,
 309                                                struct drm_display_mode *adjusted_mode)
 310 {
 311         struct drm_device *dev = encoder->dev;
 312         struct radeon_device *rdev = dev->dev_private;
 313         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 314         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 315         uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
 316
 317         DRM_DEBUG("\n");
 318
 319         if (radeon_crtc->crtc_id == 0) {
 320                 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
 321                         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
 322                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 323                         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 324                 } else {
 325                         dac2_cntl = RREG32(RADEON_DAC_CNTL2)  & ~(RADEON_DAC2_DAC_CLK_SEL);
 326                         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 327                 }
 328         } else {
 329                 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
 330                         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
 331                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 332                         disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
 333                         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 334                 } else {
 335                         dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
 336                         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 337                 }
 338         }
 339
 340         dac_cntl = (RADEON_DAC_MASK_ALL |
 341                     RADEON_DAC_VGA_ADR_EN |
 342                     /* TODO 6-bits */
 343                     RADEON_DAC_8BIT_EN);
 344
 345         WREG32_P(RADEON_DAC_CNTL,
 346                        dac_cntl,
 347                        RADEON_DAC_RANGE_CNTL |
 348                        RADEON_DAC_BLANKING);
 349
 350         if (radeon_encoder->enc_priv) {
 351                 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
 352                 dac_macro_cntl = p_dac->ps2_pdac_adj;
 353         } else
 354                 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 355         dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
 356         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 357
 358         if (rdev->is_atom_bios)
 359                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 360         else
 361                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 362 }
 363
 364 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
 365                                                                   struct drm_connector *connector)
 366 {
 367         struct drm_device *dev = encoder->dev;
 368         struct radeon_device *rdev = dev->dev_private;
 369         uint32_t vclk_ecp_cntl, crtc_ext_cntl;
 370         uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
 371         enum drm_connector_status found = connector_status_disconnected;
 372         bool color = true;
 373
 374         /* save the regs we need */
 375         vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
 376         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 377         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
 378         dac_cntl = RREG32(RADEON_DAC_CNTL);
 379         dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 380
 381         tmp = vclk_ecp_cntl &
 382                 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
 383         WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
 384
 385         tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
 386         WREG32(RADEON_CRTC_EXT_CNTL, tmp);
 387
 388         tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
 389                 RADEON_DAC_FORCE_DATA_EN;
 390
 391         if (color)
 392                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
 393         else
 394                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
 395
 396         if (ASIC_IS_R300(rdev))
 397                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
 398         else
 399                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
 400
 401         WREG32(RADEON_DAC_EXT_CNTL, tmp);
 402
 403         tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
 404         tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
 405         WREG32(RADEON_DAC_CNTL, tmp);
 406
 407         tmp &= ~(RADEON_DAC_PDWN_R |
 408                  RADEON_DAC_PDWN_G |
 409                  RADEON_DAC_PDWN_B);
 410
 411         WREG32(RADEON_DAC_MACRO_CNTL, tmp);
 412
 413         udelay(2000);
 414
 415         if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
 416                 found = connector_status_connected;
 417
 418         /* restore the regs we used */
 419         WREG32(RADEON_DAC_CNTL, dac_cntl);
 420         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 421         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
 422         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 423         WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
 424
 425         return found;
 426 }
 427
 428 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
 429         .dpms = radeon_legacy_primary_dac_dpms,
 430         .mode_fixup = radeon_legacy_mode_fixup,
 431         .prepare = radeon_legacy_primary_dac_prepare,
 432         .mode_set = radeon_legacy_primary_dac_mode_set,
 433         .commit = radeon_legacy_primary_dac_commit,
 434         .detect = radeon_legacy_primary_dac_detect,
 435         .disable = radeon_legacy_encoder_disable,
 436 };
 437
 438
 439 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
 440         .destroy = radeon_enc_destroy,
 441 };
 442
 443 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
 444 {
 445         struct drm_device *dev = encoder->dev;
 446         struct radeon_device *rdev = dev->dev_private;
 447         uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
 448         DRM_DEBUG("\n");
 449
 450         switch (mode) {
 451         case DRM_MODE_DPMS_ON:
 452                 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 453                 break;
 454         case DRM_MODE_DPMS_STANDBY:
 455         case DRM_MODE_DPMS_SUSPEND:
 456         case DRM_MODE_DPMS_OFF:
 457                 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 458                 break;
 459         }
 460
 461         WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 462
 463         if (rdev->is_atom_bios)
 464                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 465         else
 466                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 467
 468 }
 469
 470 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
 471 {
 472         struct radeon_device *rdev = encoder->dev->dev_private;
 473
 474         if (rdev->is_atom_bios)
 475                 radeon_atom_output_lock(encoder, true);
 476         else
 477                 radeon_combios_output_lock(encoder, true);
 478         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
 479 }
 480
 481 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
 482 {
 483         struct radeon_device *rdev = encoder->dev->dev_private;
 484
 485         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
 486
 487         if (rdev->is_atom_bios)
 488                 radeon_atom_output_lock(encoder, true);
 489         else
 490                 radeon_combios_output_lock(encoder, true);
 491 }
 492
 493 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
 494                                             struct drm_display_mode *mode,
 495                                             struct drm_display_mode *adjusted_mode)
 496 {
 497         struct drm_device *dev = encoder->dev;
 498         struct radeon_device *rdev = dev->dev_private;
 499         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 500         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 501         uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
 502         int i;
 503
 504         DRM_DEBUG("\n");
 505
 506         tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
 507         tmp &= 0xfffff;
 508         if (rdev->family == CHIP_RV280) {
 509                 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
 510                 tmp ^= (1 << 22);
 511                 tmds_pll_cntl ^= (1 << 22);
 512         }
 513
 514         if (radeon_encoder->enc_priv) {
 515                 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
 516
 517                 for (i = 0; i < 4; i++) {
 518                         if (tmds->tmds_pll[i].freq == 0)
 519                                 break;
 520                         if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
 521                                 tmp = tmds->tmds_pll[i].value ;
 522                                 break;
 523                         }
 524                 }
 525         }
 526
 527         if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
 528                 if (tmp & 0xfff00000)
 529                         tmds_pll_cntl = tmp;
 530                 else {
 531                         tmds_pll_cntl &= 0xfff00000;
 532                         tmds_pll_cntl |= tmp;
 533                 }
 534         } else
 535                 tmds_pll_cntl = tmp;
 536
 537         tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
 538                 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
 539
 540     if (rdev->family == CHIP_R200 ||
 541         rdev->family == CHIP_R100 ||
 542         ASIC_IS_R300(rdev))
 543             tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
 544     else /* RV chips got this bit reversed */
 545             tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
 546
 547     fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
 548                    (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
 549                     RADEON_FP_CRTC_DONT_SHADOW_HEND));
 550
 551     fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 552
 553     fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
 554                      RADEON_FP_DFP_SYNC_SEL |
 555                      RADEON_FP_CRT_SYNC_SEL |
 556                      RADEON_FP_CRTC_LOCK_8DOT |
 557                      RADEON_FP_USE_SHADOW_EN |
 558                      RADEON_FP_CRTC_USE_SHADOW_VEND |
 559                      RADEON_FP_CRT_SYNC_ALT);
 560
 561     if (1) /*  FIXME rgbBits == 8 */
 562             fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format */
 563     else
 564             fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
 565
 566     if (radeon_crtc->crtc_id == 0) {
 567             if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
 568                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 569                     if (radeon_encoder->rmx_type != RMX_OFF)
 570                             fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
 571                     else
 572                             fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
 573             } else
 574                     fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
 575     } else {
 576             if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
 577                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 578                     fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
 579             } else
 580                     fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
 581     }
 582
 583     WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
 584     WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
 585     WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 586
 587         if (rdev->is_atom_bios)
 588                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 589         else
 590                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 591 }
 592
 593 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
 594         .dpms = radeon_legacy_tmds_int_dpms,
 595         .mode_fixup = radeon_legacy_mode_fixup,
 596         .prepare = radeon_legacy_tmds_int_prepare,
 597         .mode_set = radeon_legacy_tmds_int_mode_set,
 598         .commit = radeon_legacy_tmds_int_commit,
 599         .disable = radeon_legacy_encoder_disable,
 600 };
 601
 602
 603 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
 604         .destroy = radeon_enc_destroy,
 605 };
 606
 607 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
 608 {
 609         struct drm_device *dev = encoder->dev;
 610         struct radeon_device *rdev = dev->dev_private;
 611         uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 612         DRM_DEBUG("\n");
 613
 614         switch (mode) {
 615         case DRM_MODE_DPMS_ON:
 616                 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
 617                 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 618                 break;
 619         case DRM_MODE_DPMS_STANDBY:
 620         case DRM_MODE_DPMS_SUSPEND:
 621         case DRM_MODE_DPMS_OFF:
 622                 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
 623                 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 624                 break;
 625         }
 626
 627         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 628
 629         if (rdev->is_atom_bios)
 630                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 631         else
 632                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 633
 634 }
 635
 636 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
 637 {
 638         struct radeon_device *rdev = encoder->dev->dev_private;
 639
 640         if (rdev->is_atom_bios)
 641                 radeon_atom_output_lock(encoder, true);
 642         else
 643                 radeon_combios_output_lock(encoder, true);
 644         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
 645 }
 646
 647 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
 648 {
 649         struct radeon_device *rdev = encoder->dev->dev_private;
 650         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
 651
 652         if (rdev->is_atom_bios)
 653                 radeon_atom_output_lock(encoder, false);
 654         else
 655                 radeon_combios_output_lock(encoder, false);
 656 }
 657
 658 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
 659                                             struct drm_display_mode *mode,
 660                                             struct drm_display_mode *adjusted_mode)
 661 {
 662         struct drm_device *dev = encoder->dev;
 663         struct radeon_device *rdev = dev->dev_private;
 664         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 665         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 666         uint32_t fp2_gen_cntl;
 667
 668         DRM_DEBUG("\n");
 669
 670         if (rdev->is_atom_bios) {
 671                 radeon_encoder->pixel_clock = adjusted_mode->clock;
 672                 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
 673                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 674         } else {
 675                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 676
 677                 if (1) /*  FIXME rgbBits == 8 */
 678                         fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
 679                 else
 680                         fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
 681
 682                 fp2_gen_cntl &= ~(RADEON_FP2_ON |
 683                                   RADEON_FP2_DVO_EN |
 684                                   RADEON_FP2_DVO_RATE_SEL_SDR);
 685
 686                 /* XXX: these are oem specific */
 687                 if (ASIC_IS_R300(rdev)) {
 688                         if ((dev->pdev->device == 0x4850) &&
 689                             (dev->pdev->subsystem_vendor == 0x1028) &&
 690                             (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
 691                                 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
 692                         else
 693                                 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
 694
 695                         /*if (mode->clock > 165000)
 696                           fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
 697                 }
 698                 if (!radeon_combios_external_tmds_setup(encoder))
 699                         radeon_external_tmds_setup(encoder);
 700         }
 701
 702         if (radeon_crtc->crtc_id == 0) {
 703                 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
 704                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 705                         if (radeon_encoder->rmx_type != RMX_OFF)
 706                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
 707                         else
 708                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
 709                 } else
 710                         fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
 711         } else {
 712                 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
 713                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 714                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
 715                 } else
 716                         fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
 717         }
 718
 719         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 720
 721         if (rdev->is_atom_bios)
 722                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 723         else
 724                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 725 }
 726
 727 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
 728 {
 729         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 730         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
 731         if (tmds) {
 732                 if (tmds->i2c_bus)
 733                         radeon_i2c_destroy(tmds->i2c_bus);
 734         }
 735         kfree(radeon_encoder->enc_priv);
 736         drm_encoder_cleanup(encoder);
 737         kfree(radeon_encoder);
 738 }
 739
 740 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
 741         .dpms = radeon_legacy_tmds_ext_dpms,
 742         .mode_fixup = radeon_legacy_mode_fixup,
 743         .prepare = radeon_legacy_tmds_ext_prepare,
 744         .mode_set = radeon_legacy_tmds_ext_mode_set,
 745         .commit = radeon_legacy_tmds_ext_commit,
 746         .disable = radeon_legacy_encoder_disable,
 747 };
 748
 749
 750 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
 751         .destroy = radeon_ext_tmds_enc_destroy,
 752 };
 753
 754 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
 755 {
 756         struct drm_device *dev = encoder->dev;
 757         struct radeon_device *rdev = dev->dev_private;
 758         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 759         uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
 760         uint32_t tv_master_cntl = 0;
 761         bool is_tv;
 762         DRM_DEBUG("\n");
 763
 764         is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
 765
 766         if (rdev->family == CHIP_R200)
 767                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 768         else {
 769                 if (is_tv)
 770                         tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
 771                 else
 772                         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 773                 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
 774         }
 775
 776         switch (mode) {
 777         case DRM_MODE_DPMS_ON:
 778                 if (rdev->family == CHIP_R200) {
 779                         fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 780                 } else {
 781                         if (is_tv)
 782                                 tv_master_cntl |= RADEON_TV_ON;
 783                         else
 784                                 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
 785
 786                         if (rdev->family == CHIP_R420 ||
 787                             rdev->family == CHIP_R423 ||
 788                             rdev->family == CHIP_RV410)
 789                                 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
 790                                                  R420_TV_DAC_GDACPD |
 791                                                  R420_TV_DAC_BDACPD |
 792                                                  RADEON_TV_DAC_BGSLEEP);
 793                         else
 794                                 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
 795                                                  RADEON_TV_DAC_GDACPD |
 796                                                  RADEON_TV_DAC_BDACPD |
 797                                                  RADEON_TV_DAC_BGSLEEP);
 798                 }
 799                 break;
 800         case DRM_MODE_DPMS_STANDBY:
 801         case DRM_MODE_DPMS_SUSPEND:
 802         case DRM_MODE_DPMS_OFF:
 803                 if (rdev->family == CHIP_R200)
 804                         fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 805                 else {
 806                         if (is_tv)
 807                                 tv_master_cntl &= ~RADEON_TV_ON;
 808                         else
 809                                 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
 810
 811                         if (rdev->family == CHIP_R420 ||
 812                             rdev->family == CHIP_R423 ||
 813                             rdev->family == CHIP_RV410)
 814                                 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
 815                                                 R420_TV_DAC_GDACPD |
 816                                                 R420_TV_DAC_BDACPD |
 817                                                 RADEON_TV_DAC_BGSLEEP);
 818                         else
 819                                 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
 820                                                 RADEON_TV_DAC_GDACPD |
 821                                                 RADEON_TV_DAC_BDACPD |
 822                                                 RADEON_TV_DAC_BGSLEEP);
 823                 }
 824                 break;
 825         }
 826
 827         if (rdev->family == CHIP_R200) {
 828                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 829         } else {
 830                 if (is_tv)
 831                         WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
 832                 else
 833                         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 834                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 835         }
 836
 837         if (rdev->is_atom_bios)
 838                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 839         else
 840                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 841
 842 }
 843
 844 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
 845 {
 846         struct radeon_device *rdev = encoder->dev->dev_private;
 847
 848         if (rdev->is_atom_bios)
 849                 radeon_atom_output_lock(encoder, true);
 850         else
 851                 radeon_combios_output_lock(encoder, true);
 852         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 853 }
 854
 855 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
 856 {
 857         struct radeon_device *rdev = encoder->dev->dev_private;
 858
 859         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 860
 861         if (rdev->is_atom_bios)
 862                 radeon_atom_output_lock(encoder, true);
 863         else
 864                 radeon_combios_output_lock(encoder, true);
 865 }
 866
 867 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
 868                 struct drm_display_mode *mode,
 869                 struct drm_display_mode *adjusted_mode)
 870 {
 871         struct drm_device *dev = encoder->dev;
 872         struct radeon_device *rdev = dev->dev_private;
 873         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 874         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 875         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
 876         uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
 877         uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
 878         bool is_tv = false;
 879
 880         DRM_DEBUG("\n");
 881
 882         is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
 883
 884         if (rdev->family != CHIP_R200) {
 885                 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
 886                 if (rdev->family == CHIP_R420 ||
 887                     rdev->family == CHIP_R423 ||
 888                     rdev->family == CHIP_RV410) {
 889                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
 890                                          RADEON_TV_DAC_BGADJ_MASK |
 891                                          R420_TV_DAC_DACADJ_MASK |
 892                                          R420_TV_DAC_RDACPD |
 893                                          R420_TV_DAC_GDACPD |
 894                                          R420_TV_DAC_BDACPD |
 895                                          R420_TV_DAC_TVENABLE);
 896                 } else {
 897                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
 898                                          RADEON_TV_DAC_BGADJ_MASK |
 899                                          RADEON_TV_DAC_DACADJ_MASK |
 900                                          RADEON_TV_DAC_RDACPD |
 901                                          RADEON_TV_DAC_GDACPD |
 902                                          RADEON_TV_DAC_BDACPD);
 903                 }
 904
 905                 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
 906
 907                 if (is_tv) {
 908                         if (tv_dac->tv_std == TV_STD_NTSC ||
 909                             tv_dac->tv_std == TV_STD_NTSC_J ||
 910                             tv_dac->tv_std == TV_STD_PAL_M ||
 911                             tv_dac->tv_std == TV_STD_PAL_60)
 912                                 tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
 913                         else
 914                                 tv_dac_cntl |= tv_dac->pal_tvdac_adj;
 915
 916                         if (tv_dac->tv_std == TV_STD_NTSC ||
 917                             tv_dac->tv_std == TV_STD_NTSC_J)
 918                                 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
 919                         else
 920                                 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
 921                 } else
 922                         tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
 923                                         tv_dac->ps2_tvdac_adj);
 924
 925                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 926         }
 927
 928         if (ASIC_IS_R300(rdev)) {
 929                 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
 930                 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
 931         } else if (rdev->family != CHIP_R200)
 932                 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
 933         else if (rdev->family == CHIP_R200)
 934                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 935
 936         if (rdev->family >= CHIP_R200)
 937                 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
 938
 939         if (is_tv) {
 940                 uint32_t dac_cntl;
 941
 942                 dac_cntl = RREG32(RADEON_DAC_CNTL);
 943                 dac_cntl &= ~RADEON_DAC_TVO_EN;
 944                 WREG32(RADEON_DAC_CNTL, dac_cntl);
 945
 946                 if (ASIC_IS_R300(rdev))
 947                         gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
 948
 949                 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
 950                 if (radeon_crtc->crtc_id == 0) {
 951                         if (ASIC_IS_R300(rdev)) {
 952                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 953                                 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
 954                                                      RADEON_DISP_TV_SOURCE_CRTC);
 955                         }
 956                         if (rdev->family >= CHIP_R200) {
 957                                 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
 958                         } else {
 959                                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 960                         }
 961                 } else {
 962                         if (ASIC_IS_R300(rdev)) {
 963                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 964                                 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
 965                         }
 966                         if (rdev->family >= CHIP_R200) {
 967                                 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
 968                         } else {
 969                                 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
 970                         }
 971                 }
 972                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 973         } else {
 974
 975                 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
 976
 977                 if (radeon_crtc->crtc_id == 0) {
 978                         if (ASIC_IS_R300(rdev)) {
 979                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 980                                 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
 981                         } else if (rdev->family == CHIP_R200) {
 982                                 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
 983                                                   RADEON_FP2_DVO_RATE_SEL_SDR);
 984                         } else
 985                                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 986                 } else {
 987                         if (ASIC_IS_R300(rdev)) {
 988                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 989                                 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
 990                         } else if (rdev->family == CHIP_R200) {
 991                                 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
 992                                                   RADEON_FP2_DVO_RATE_SEL_SDR);
 993                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
 994                         } else
 995                                 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
 996                 }
 997                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 998         }
 999
1000         if (ASIC_IS_R300(rdev)) {
1001                 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1002                 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1003         } else if (rdev->family != CHIP_R200)
1004                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1005         else if (rdev->family == CHIP_R200)
1006                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1007
1008         if (rdev->family >= CHIP_R200)
1009                 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1010
1011         if (is_tv)
1012                 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
1013
1014         if (rdev->is_atom_bios)
1015                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1016         else
1017                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1018
1019 }
1020
1021 static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1022                                   struct drm_connector *connector)
1023 {
1024         struct drm_device *dev = encoder->dev;
1025         struct radeon_device *rdev = dev->dev_private;
1026         uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1027         uint32_t disp_output_cntl, gpiopad_a, tmp;
1028         bool found = false;
1029
1030         /* save regs needed */
1031         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1032         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1033         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1034         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1035         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1036         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1037
1038         WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1039
1040         WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1041
1042         WREG32(RADEON_CRTC2_GEN_CNTL,
1043                RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1044
1045         tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1046         tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1047         WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1048
1049         WREG32(RADEON_DAC_EXT_CNTL,
1050                RADEON_DAC2_FORCE_BLANK_OFF_EN |
1051                RADEON_DAC2_FORCE_DATA_EN |
1052                RADEON_DAC_FORCE_DATA_SEL_RGB |
1053                (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1054
1055         WREG32(RADEON_TV_DAC_CNTL,
1056                RADEON_TV_DAC_STD_NTSC |
1057                (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1058                (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1059
1060         RREG32(RADEON_TV_DAC_CNTL);
1061         mdelay(4);
1062
1063         WREG32(RADEON_TV_DAC_CNTL,
1064                RADEON_TV_DAC_NBLANK |
1065                RADEON_TV_DAC_NHOLD |
1066                RADEON_TV_MONITOR_DETECT_EN |
1067                RADEON_TV_DAC_STD_NTSC |
1068                (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1069                (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1070
1071         RREG32(RADEON_TV_DAC_CNTL);
1072         mdelay(6);
1073
1074         tmp = RREG32(RADEON_TV_DAC_CNTL);
1075         if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1076                 found = true;
1077                 DRM_DEBUG("S-video TV connection detected\n");
1078         } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1079                 found = true;
1080                 DRM_DEBUG("Composite TV connection detected\n");
1081         }
1082
1083         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1084         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1085         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1086         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1087         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1088         WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1089         return found;
1090 }
1091
1092 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1093                                     struct drm_connector *connector)
1094 {
1095         struct drm_device *dev = encoder->dev;
1096         struct radeon_device *rdev = dev->dev_private;
1097         uint32_t tv_dac_cntl, dac_cntl2;
1098         uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1099         bool found = false;
1100
1101         if (ASIC_IS_R300(rdev))
1102                 return r300_legacy_tv_detect(encoder, connector);
1103
1104         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1105         tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1106         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1107         config_cntl = RREG32(RADEON_CONFIG_CNTL);
1108         tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1109
1110         tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1111         WREG32(RADEON_DAC_CNTL2, tmp);
1112
1113         tmp = tv_master_cntl | RADEON_TV_ON;
1114         tmp &= ~(RADEON_TV_ASYNC_RST |
1115                  RADEON_RESTART_PHASE_FIX |
1116                  RADEON_CRT_FIFO_CE_EN |
1117                  RADEON_TV_FIFO_CE_EN |
1118                  RADEON_RE_SYNC_NOW_SEL_MASK);
1119         tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1120         WREG32(RADEON_TV_MASTER_CNTL, tmp);
1121
1122         tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1123                 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1124                 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1125
1126         if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1127                 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1128         else
1129                 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1130         WREG32(RADEON_TV_DAC_CNTL, tmp);
1131
1132         tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1133                 RADEON_RED_MX_FORCE_DAC_DATA |
1134                 RADEON_GRN_MX_FORCE_DAC_DATA |
1135                 RADEON_BLU_MX_FORCE_DAC_DATA |
1136                 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1137         WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1138
1139         mdelay(3);
1140         tmp = RREG32(RADEON_TV_DAC_CNTL);
1141         if (tmp & RADEON_TV_DAC_GDACDET) {
1142                 found = true;
1143                 DRM_DEBUG("S-video TV connection detected\n");
1144         } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1145                 found = true;
1146                 DRM_DEBUG("Composite TV connection detected\n");
1147         }
1148
1149         WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1150         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1151         WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1152         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1153         return found;
1154 }
1155
1156 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1157                                                              struct drm_connector *connector)
1158 {
1159         struct drm_device *dev = encoder->dev;
1160         struct radeon_device *rdev = dev->dev_private;
1161         uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1162         uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
1163         enum drm_connector_status found = connector_status_disconnected;
1164         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1165         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1166         bool color = true;
1167         struct drm_crtc *crtc;
1168
1169         /* find out if crtc2 is in use or if this encoder is using it */
1170         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1171                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1172                 if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
1173                         if (encoder->crtc != crtc) {
1174                                 return connector_status_disconnected;
1175                         }
1176                 }
1177         }
1178
1179         if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1180             connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1181             connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1182                 bool tv_detect;
1183
1184                 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1185                         return connector_status_disconnected;
1186
1187                 tv_detect = radeon_legacy_tv_detect(encoder, connector);
1188                 if (tv_detect && tv_dac)
1189                         found = connector_status_connected;
1190                 return found;
1191         }
1192
1193         /* don't probe if the encoder is being used for something else not CRT related */
1194         if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1195                 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1196                 return connector_status_disconnected;
1197         }
1198
1199         /* save the regs we need */
1200         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1201         gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
1202         disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
1203         disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
1204         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1205         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1206         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1207         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1208
1209         tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1210                                | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1211         WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1212
1213         if (ASIC_IS_R300(rdev))
1214                 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1215
1216         tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1217         tmp |= RADEON_CRTC2_CRT2_ON |
1218                 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1219
1220         WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1221
1222         if (ASIC_IS_R300(rdev)) {
1223                 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1224                 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1225                 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1226         } else {
1227                 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1228                 WREG32(RADEON_DISP_HW_DEBUG, tmp);
1229         }
1230
1231         tmp = RADEON_TV_DAC_NBLANK |
1232                 RADEON_TV_DAC_NHOLD |
1233                 RADEON_TV_MONITOR_DETECT_EN |
1234                 RADEON_TV_DAC_STD_PS2;
1235
1236         WREG32(RADEON_TV_DAC_CNTL, tmp);
1237
1238         tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1239                 RADEON_DAC2_FORCE_DATA_EN;
1240
1241         if (color)
1242                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1243         else
1244                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1245
1246         if (ASIC_IS_R300(rdev))
1247                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1248         else
1249                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1250
1251         WREG32(RADEON_DAC_EXT_CNTL, tmp);
1252
1253         tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1254         WREG32(RADEON_DAC_CNTL2, tmp);
1255
1256         udelay(10000);
1257
1258         if (ASIC_IS_R300(rdev)) {
1259                 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1260                         found = connector_status_connected;
1261         } else {
1262                 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1263                         found = connector_status_connected;
1264         }
1265
1266         /* restore regs we used */
1267         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1268         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1269         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1270         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1271
1272         if (ASIC_IS_R300(rdev)) {
1273                 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1274                 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1275         } else {
1276                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1277         }
1278         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1279
1280         return found;
1281
1282 }
1283
1284 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1285         .dpms = radeon_legacy_tv_dac_dpms,
1286         .mode_fixup = radeon_legacy_mode_fixup,
1287         .prepare = radeon_legacy_tv_dac_prepare,
1288         .mode_set = radeon_legacy_tv_dac_mode_set,
1289         .commit = radeon_legacy_tv_dac_commit,
1290         .detect = radeon_legacy_tv_dac_detect,
1291         .disable = radeon_legacy_encoder_disable,
1292 };
1293
1294
1295 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1296         .destroy = radeon_enc_destroy,
1297 };
1298
1299
1300 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1301 {
1302         struct drm_device *dev = encoder->base.dev;
1303         struct radeon_device *rdev = dev->dev_private;
1304         struct radeon_encoder_int_tmds *tmds = NULL;
1305         bool ret;
1306
1307         tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1308
1309         if (!tmds)
1310                 return NULL;
1311
1312         if (rdev->is_atom_bios)
1313                 ret = radeon_atombios_get_tmds_info(encoder, tmds);
1314         else
1315                 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1316
1317         if (ret == false)
1318                 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1319
1320         return tmds;
1321 }
1322
1323 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1324 {
1325         struct drm_device *dev = encoder->base.dev;
1326         struct radeon_device *rdev = dev->dev_private;
1327         struct radeon_encoder_ext_tmds *tmds = NULL;
1328         bool ret;
1329
1330         if (rdev->is_atom_bios)
1331                 return NULL;
1332
1333         tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1334
1335         if (!tmds)
1336                 return NULL;
1337
1338         ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1339
1340         if (ret == false)
1341                 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1342
1343         return tmds;
1344 }
1345
1346 void
1347 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1348 {
1349         struct radeon_device *rdev = dev->dev_private;
1350         struct drm_encoder *encoder;
1351         struct radeon_encoder *radeon_encoder;
1352
1353         /* see if we already added it */
1354         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1355                 radeon_encoder = to_radeon_encoder(encoder);
1356                 if (radeon_encoder->encoder_id == encoder_id) {
1357                         radeon_encoder->devices |= supported_device;
1358                         return;
1359                 }
1360
1361         }
1362
1363         /* add a new one */
1364         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1365         if (!radeon_encoder)
1366                 return;
1367
1368         encoder = &radeon_encoder->base;
1369         if (rdev->flags & RADEON_SINGLE_CRTC)
1370                 encoder->possible_crtcs = 0x1;
1371         else
1372                 encoder->possible_crtcs = 0x3;
1373
1374         radeon_encoder->enc_priv = NULL;
1375
1376         radeon_encoder->encoder_id = encoder_id;
1377         radeon_encoder->devices = supported_device;
1378         radeon_encoder->rmx_type = RMX_OFF;
1379
1380         switch (radeon_encoder->encoder_id) {
1381         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1382                 encoder->possible_crtcs = 0x1;
1383                 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
1384                 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1385                 if (rdev->is_atom_bios)
1386                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1387                 else
1388                         radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1389                 radeon_encoder->rmx_type = RMX_FULL;
1390                 break;
1391         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1392                 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
1393                 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1394                 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1395                 break;
1396         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1397                 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
1398                 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1399                 if (rdev->is_atom_bios)
1400                         radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1401                 else
1402                         radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1403                 break;
1404         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1405                 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1406                 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1407                 if (rdev->is_atom_bios)
1408                         radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1409                 else
1410                         radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1411                 break;
1412         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1413                 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
1414                 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1415                 if (!rdev->is_atom_bios)
1416                         radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
1417                 break;
1418         }
1419 }