drivers/gpu/drm/radeon/radeon_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include "drmP.h"
  29 #include "drm_sarea.h"
  30 #include "radeon.h"
  31 #include "radeon_drm.h"
  32
  33 #include <linux/vga_switcheroo.h>
  34 #include <linux/slab.h>
  35
  36 int radeon_driver_unload_kms(struct drm_device *dev)
  37 {
  38         struct radeon_device *rdev = dev->dev_private;
  39
  40         if (rdev == NULL)
  41                 return 0;
  42         radeon_modeset_fini(rdev);
  43         radeon_device_fini(rdev);
  44         kfree(rdev);
  45         dev->dev_private = NULL;
  46         return 0;
  47 }
  48
  49 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
  50 {
  51         struct radeon_device *rdev;
  52         int r;
  53
  54         rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
  55         if (rdev == NULL) {
  56                 return -ENOMEM;
  57         }
  58         dev->dev_private = (void *)rdev;
  59
  60         /* update BUS flag */
  61         if (drm_device_is_agp(dev)) {
  62                 flags |= RADEON_IS_AGP;
  63         } else if (drm_device_is_pcie(dev)) {
  64                 flags |= RADEON_IS_PCIE;
  65         } else {
  66                 flags |= RADEON_IS_PCI;
  67         }
  68
  69         /* radeon_device_init should report only fatal error
  70          * like memory allocation failure or iomapping failure,
  71          * or memory manager initialization failure, it must
  72          * properly initialize the GPU MC controller and permit
  73          * VRAM allocation
  74          */
  75         r = radeon_device_init(rdev, dev, dev->pdev, flags);
  76         if (r) {
  77                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
  78                 goto out;
  79         }
  80         /* Again modeset_init should fail only on fatal error
  81          * otherwise it should provide enough functionalities
  82          * for shadowfb to run
  83          */
  84         r = radeon_modeset_init(rdev);
  85         if (r)
  86                 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
  87 out:
  88         if (r)
  89                 radeon_driver_unload_kms(dev);
  90         return r;
  91 }
  92
  93
  94 /*
  95  * Userspace get informations ioctl
  96  */
  97 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
  98 {
  99         struct radeon_device *rdev = dev->dev_private;
 100         struct drm_radeon_info *info;
 101         uint32_t *value_ptr;
 102         uint32_t value;
 103
 104         info = data;
 105         value_ptr = (uint32_t *)((unsigned long)info->value);
 106         switch (info->request) {
 107         case RADEON_INFO_DEVICE_ID:
 108                 value = dev->pci_device;
 109                 break;
 110         case RADEON_INFO_NUM_GB_PIPES:
 111                 value = rdev->num_gb_pipes;
 112                 break;
 113         case RADEON_INFO_NUM_Z_PIPES:
 114                 value = rdev->num_z_pipes;
 115                 break;
 116         case RADEON_INFO_ACCEL_WORKING:
 117                 value = rdev->accel_working;
 118                 break;
 119         default:
 120                 DRM_DEBUG("Invalid request %d\n", info->request);
 121                 return -EINVAL;
 122         }
 123         if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
 124                 DRM_ERROR("copy_to_user\n");
 125                 return -EFAULT;
 126         }
 127         return 0;
 128 }
 129
 130
 131 /*
 132  * Outdated mess for old drm with Xorg being in charge (void function now).
 133  */
 134 int radeon_driver_firstopen_kms(struct drm_device *dev)
 135 {
 136         return 0;
 137 }
 138
 139
 140 void radeon_driver_lastclose_kms(struct drm_device *dev)
 141 {
 142         vga_switcheroo_process_delayed_switch();
 143 }
 144
 145 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 146 {
 147         return 0;
 148 }
 149
 150 void radeon_driver_postclose_kms(struct drm_device *dev,
 151                                  struct drm_file *file_priv)
 152 {
 153 }
 154
 155 void radeon_driver_preclose_kms(struct drm_device *dev,
 156                                 struct drm_file *file_priv)
 157 {
 158 }
 159
 160
 161 /*
 162  * VBlank related functions.
 163  */
 164 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
 165 {
 166         struct radeon_device *rdev = dev->dev_private;
 167
 168         if (crtc < 0 || crtc > 1) {
 169                 DRM_ERROR("Invalid crtc %d\n", crtc);
 170                 return -EINVAL;
 171         }
 172
 173         return radeon_get_vblank_counter(rdev, crtc);
 174 }
 175
 176 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
 177 {
 178         struct radeon_device *rdev = dev->dev_private;
 179
 180         if (crtc < 0 || crtc > 1) {
 181                 DRM_ERROR("Invalid crtc %d\n", crtc);
 182                 return -EINVAL;
 183         }
 184
 185         rdev->irq.crtc_vblank_int[crtc] = true;
 186
 187         return radeon_irq_set(rdev);
 188 }
 189
 190 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
 191 {
 192         struct radeon_device *rdev = dev->dev_private;
 193
 194         if (crtc < 0 || crtc > 1) {
 195                 DRM_ERROR("Invalid crtc %d\n", crtc);
 196                 return;
 197         }
 198
 199         rdev->irq.crtc_vblank_int[crtc] = false;
 200
 201         radeon_irq_set(rdev);
 202 }
 203
 204
 205 /*
 206  * IOCTL.
 207  */
 208 int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
 209                          struct drm_file *file_priv)
 210 {
 211         /* Not valid in KMS. */
 212         return -EINVAL;
 213 }
 214
 215 #define KMS_INVALID_IOCTL(name)                                         \
 216 int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
 217 {                                                                       \
 218         DRM_ERROR("invalid ioctl with kms %s\n", __func__);             \
 219         return -EINVAL;                                                 \
 220 }
 221
 222 /*
 223  * All these ioctls are invalid in kms world.
 224  */
 225 KMS_INVALID_IOCTL(radeon_cp_init_kms)
 226 KMS_INVALID_IOCTL(radeon_cp_start_kms)
 227 KMS_INVALID_IOCTL(radeon_cp_stop_kms)
 228 KMS_INVALID_IOCTL(radeon_cp_reset_kms)
 229 KMS_INVALID_IOCTL(radeon_cp_idle_kms)
 230 KMS_INVALID_IOCTL(radeon_cp_resume_kms)
 231 KMS_INVALID_IOCTL(radeon_engine_reset_kms)
 232 KMS_INVALID_IOCTL(radeon_fullscreen_kms)
 233 KMS_INVALID_IOCTL(radeon_cp_swap_kms)
 234 KMS_INVALID_IOCTL(radeon_cp_clear_kms)
 235 KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
 236 KMS_INVALID_IOCTL(radeon_cp_indices_kms)
 237 KMS_INVALID_IOCTL(radeon_cp_texture_kms)
 238 KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
 239 KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
 240 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
 241 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
 242 KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
 243 KMS_INVALID_IOCTL(radeon_cp_flip_kms)
 244 KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
 245 KMS_INVALID_IOCTL(radeon_mem_free_kms)
 246 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
 247 KMS_INVALID_IOCTL(radeon_irq_emit_kms)
 248 KMS_INVALID_IOCTL(radeon_irq_wait_kms)
 249 KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
 250 KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
 251 KMS_INVALID_IOCTL(radeon_surface_free_kms)
 252
 253
 254 struct drm_ioctl_desc radeon_ioctls_kms[] = {
 255         DRM_IOCTL_DEF(DRM_RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 256         DRM_IOCTL_DEF(DRM_RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 257         DRM_IOCTL_DEF(DRM_RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 258         DRM_IOCTL_DEF(DRM_RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 259         DRM_IOCTL_DEF(DRM_RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
 260         DRM_IOCTL_DEF(DRM_RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
 261         DRM_IOCTL_DEF(DRM_RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
 262         DRM_IOCTL_DEF(DRM_RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
 263         DRM_IOCTL_DEF(DRM_RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
 264         DRM_IOCTL_DEF(DRM_RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
 265         DRM_IOCTL_DEF(DRM_RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
 266         DRM_IOCTL_DEF(DRM_RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
 267         DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
 268         DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
 269         DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 270         DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
 271         DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
 272         DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
 273         DRM_IOCTL_DEF(DRM_RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
 274         DRM_IOCTL_DEF(DRM_RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
 275         DRM_IOCTL_DEF(DRM_RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
 276         DRM_IOCTL_DEF(DRM_RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 277         DRM_IOCTL_DEF(DRM_RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
 278         DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
 279         DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
 280         DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
 281         DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
 282         /* KMS */
 283         DRM_IOCTL_DEF(DRM_RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
 284         DRM_IOCTL_DEF(DRM_RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
 285         DRM_IOCTL_DEF(DRM_RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
 286         DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
 287         DRM_IOCTL_DEF(DRM_RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
 288         DRM_IOCTL_DEF(DRM_RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
 289         DRM_IOCTL_DEF(DRM_RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
 290         DRM_IOCTL_DEF(DRM_RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
 291         DRM_IOCTL_DEF(DRM_RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
 292         DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
 293         DRM_IOCTL_DEF(DRM_RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
 294         DRM_IOCTL_DEF(DRM_RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
 295 };
 296 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);