Merge branches 'einj', 'intel_idle', 'misc', 'srat' and 'turbostat-ivb' into release
[sfrench/cifs-2.6.git] / drivers / gpu / drm / radeon / radeon_gart.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include "drmP.h"
29 #include "radeon_drm.h"
30 #include "radeon.h"
31 #include "radeon_reg.h"
32
33 /*
34  * Common GART table functions.
35  */
36 int radeon_gart_table_ram_alloc(struct radeon_device *rdev)
37 {
38         void *ptr;
39
40         ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size,
41                                    &rdev->gart.table_addr);
42         if (ptr == NULL) {
43                 return -ENOMEM;
44         }
45 #ifdef CONFIG_X86
46         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
47             rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
48                 set_memory_uc((unsigned long)ptr,
49                               rdev->gart.table_size >> PAGE_SHIFT);
50         }
51 #endif
52         rdev->gart.ptr = ptr;
53         memset((void *)rdev->gart.ptr, 0, rdev->gart.table_size);
54         return 0;
55 }
56
57 void radeon_gart_table_ram_free(struct radeon_device *rdev)
58 {
59         if (rdev->gart.ptr == NULL) {
60                 return;
61         }
62 #ifdef CONFIG_X86
63         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
64             rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
65                 set_memory_wb((unsigned long)rdev->gart.ptr,
66                               rdev->gart.table_size >> PAGE_SHIFT);
67         }
68 #endif
69         pci_free_consistent(rdev->pdev, rdev->gart.table_size,
70                             (void *)rdev->gart.ptr,
71                             rdev->gart.table_addr);
72         rdev->gart.ptr = NULL;
73         rdev->gart.table_addr = 0;
74 }
75
76 int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
77 {
78         int r;
79
80         if (rdev->gart.robj == NULL) {
81                 r = radeon_bo_create(rdev, rdev->gart.table_size,
82                                      PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
83                                      &rdev->gart.robj);
84                 if (r) {
85                         return r;
86                 }
87         }
88         return 0;
89 }
90
91 int radeon_gart_table_vram_pin(struct radeon_device *rdev)
92 {
93         uint64_t gpu_addr;
94         int r;
95
96         r = radeon_bo_reserve(rdev->gart.robj, false);
97         if (unlikely(r != 0))
98                 return r;
99         r = radeon_bo_pin(rdev->gart.robj,
100                                 RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
101         if (r) {
102                 radeon_bo_unreserve(rdev->gart.robj);
103                 return r;
104         }
105         r = radeon_bo_kmap(rdev->gart.robj, &rdev->gart.ptr);
106         if (r)
107                 radeon_bo_unpin(rdev->gart.robj);
108         radeon_bo_unreserve(rdev->gart.robj);
109         rdev->gart.table_addr = gpu_addr;
110         return r;
111 }
112
113 void radeon_gart_table_vram_unpin(struct radeon_device *rdev)
114 {
115         int r;
116
117         if (rdev->gart.robj == NULL) {
118                 return;
119         }
120         r = radeon_bo_reserve(rdev->gart.robj, false);
121         if (likely(r == 0)) {
122                 radeon_bo_kunmap(rdev->gart.robj);
123                 radeon_bo_unpin(rdev->gart.robj);
124                 radeon_bo_unreserve(rdev->gart.robj);
125                 rdev->gart.ptr = NULL;
126         }
127 }
128
129 void radeon_gart_table_vram_free(struct radeon_device *rdev)
130 {
131         if (rdev->gart.robj == NULL) {
132                 return;
133         }
134         radeon_gart_table_vram_unpin(rdev);
135         radeon_bo_unref(&rdev->gart.robj);
136 }
137
138
139
140
141 /*
142  * Common gart functions.
143  */
144 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
145                         int pages)
146 {
147         unsigned t;
148         unsigned p;
149         int i, j;
150         u64 page_base;
151
152         if (!rdev->gart.ready) {
153                 WARN(1, "trying to unbind memory from uninitialized GART !\n");
154                 return;
155         }
156         t = offset / RADEON_GPU_PAGE_SIZE;
157         p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
158         for (i = 0; i < pages; i++, p++) {
159                 if (rdev->gart.pages[p]) {
160                         if (!rdev->gart.ttm_alloced[p])
161                                 pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p],
162                                                 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
163                         rdev->gart.pages[p] = NULL;
164                         rdev->gart.pages_addr[p] = rdev->dummy_page.addr;
165                         page_base = rdev->gart.pages_addr[p];
166                         for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
167                                 if (rdev->gart.ptr) {
168                                         radeon_gart_set_page(rdev, t, page_base);
169                                 }
170                                 page_base += RADEON_GPU_PAGE_SIZE;
171                         }
172                 }
173         }
174         mb();
175         radeon_gart_tlb_flush(rdev);
176 }
177
178 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
179                      int pages, struct page **pagelist, dma_addr_t *dma_addr)
180 {
181         unsigned t;
182         unsigned p;
183         uint64_t page_base;
184         int i, j;
185
186         if (!rdev->gart.ready) {
187                 WARN(1, "trying to bind memory to uninitialized GART !\n");
188                 return -EINVAL;
189         }
190         t = offset / RADEON_GPU_PAGE_SIZE;
191         p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
192
193         for (i = 0; i < pages; i++, p++) {
194                 /* we reverted the patch using dma_addr in TTM for now but this
195                  * code stops building on alpha so just comment it out for now */
196                 if (0) { /*dma_addr[i] != DMA_ERROR_CODE) */
197                         rdev->gart.ttm_alloced[p] = true;
198                         rdev->gart.pages_addr[p] = dma_addr[i];
199                 } else {
200                         /* we need to support large memory configurations */
201                         /* assume that unbind have already been call on the range */
202                         rdev->gart.pages_addr[p] = pci_map_page(rdev->pdev, pagelist[i],
203                                                         0, PAGE_SIZE,
204                                                         PCI_DMA_BIDIRECTIONAL);
205                         if (pci_dma_mapping_error(rdev->pdev, rdev->gart.pages_addr[p])) {
206                                 /* FIXME: failed to map page (return -ENOMEM?) */
207                                 radeon_gart_unbind(rdev, offset, pages);
208                                 return -ENOMEM;
209                         }
210                 }
211                 rdev->gart.pages[p] = pagelist[i];
212                 if (rdev->gart.ptr) {
213                         page_base = rdev->gart.pages_addr[p];
214                         for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
215                                 radeon_gart_set_page(rdev, t, page_base);
216                                 page_base += RADEON_GPU_PAGE_SIZE;
217                         }
218                 }
219         }
220         mb();
221         radeon_gart_tlb_flush(rdev);
222         return 0;
223 }
224
225 void radeon_gart_restore(struct radeon_device *rdev)
226 {
227         int i, j, t;
228         u64 page_base;
229
230         if (!rdev->gart.ptr) {
231                 return;
232         }
233         for (i = 0, t = 0; i < rdev->gart.num_cpu_pages; i++) {
234                 page_base = rdev->gart.pages_addr[i];
235                 for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
236                         radeon_gart_set_page(rdev, t, page_base);
237                         page_base += RADEON_GPU_PAGE_SIZE;
238                 }
239         }
240         mb();
241         radeon_gart_tlb_flush(rdev);
242 }
243
244 int radeon_gart_init(struct radeon_device *rdev)
245 {
246         int r, i;
247
248         if (rdev->gart.pages) {
249                 return 0;
250         }
251         /* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */
252         if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) {
253                 DRM_ERROR("Page size is smaller than GPU page size!\n");
254                 return -EINVAL;
255         }
256         r = radeon_dummy_page_init(rdev);
257         if (r)
258                 return r;
259         /* Compute table size */
260         rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE;
261         rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE;
262         DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
263                  rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages);
264         /* Allocate pages table */
265         rdev->gart.pages = kzalloc(sizeof(void *) * rdev->gart.num_cpu_pages,
266                                    GFP_KERNEL);
267         if (rdev->gart.pages == NULL) {
268                 radeon_gart_fini(rdev);
269                 return -ENOMEM;
270         }
271         rdev->gart.pages_addr = kzalloc(sizeof(dma_addr_t) *
272                                         rdev->gart.num_cpu_pages, GFP_KERNEL);
273         if (rdev->gart.pages_addr == NULL) {
274                 radeon_gart_fini(rdev);
275                 return -ENOMEM;
276         }
277         rdev->gart.ttm_alloced = kzalloc(sizeof(bool) *
278                                          rdev->gart.num_cpu_pages, GFP_KERNEL);
279         if (rdev->gart.ttm_alloced == NULL) {
280                 radeon_gart_fini(rdev);
281                 return -ENOMEM;
282         }
283         /* set GART entry to point to the dummy page by default */
284         for (i = 0; i < rdev->gart.num_cpu_pages; i++) {
285                 rdev->gart.pages_addr[i] = rdev->dummy_page.addr;
286         }
287         return 0;
288 }
289
290 void radeon_gart_fini(struct radeon_device *rdev)
291 {
292         if (rdev->gart.pages && rdev->gart.pages_addr && rdev->gart.ready) {
293                 /* unbind pages */
294                 radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages);
295         }
296         rdev->gart.ready = false;
297         kfree(rdev->gart.pages);
298         kfree(rdev->gart.pages_addr);
299         kfree(rdev->gart.ttm_alloced);
300         rdev->gart.pages = NULL;
301         rdev->gart.pages_addr = NULL;
302         rdev->gart.ttm_alloced = NULL;
303
304         radeon_dummy_page_fini(rdev);
305 }