drivers/gpu/drm/radeon/radeon_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 extern int atom_debug;
  33
  34 /* evil but including atombios.h is much worse */
  35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  36                                 struct drm_display_mode *mode);
  37
  38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
  39 {
  40         struct drm_device *dev = encoder->dev;
  41         struct radeon_device *rdev = dev->dev_private;
  42         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  43         struct drm_encoder *clone_encoder;
  44         uint32_t index_mask = 0;
  45         int count;
  46
  47         /* DIG routing gets problematic */
  48         if (rdev->family >= CHIP_R600)
  49                 return index_mask;
  50         /* LVDS/TV are too wacky */
  51         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
  52                 return index_mask;
  53         /* DVO requires 2x ppll clocks depending on tmds chip */
  54         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
  55                 return index_mask;
  56
  57         count = -1;
  58         list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
  59                 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
  60                 count++;
  61
  62                 if (clone_encoder == encoder)
  63                         continue;
  64                 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
  65                         continue;
  66                 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
  67                         continue;
  68                 else
  69                         index_mask |= (1 << count);
  70         }
  71         return index_mask;
  72 }
  73
  74 void radeon_setup_encoder_clones(struct drm_device *dev)
  75 {
  76         struct drm_encoder *encoder;
  77
  78         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  79                 encoder->possible_clones = radeon_encoder_clones(encoder);
  80         }
  81 }
  82
  83 uint32_t
  84 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
  85 {
  86         struct radeon_device *rdev = dev->dev_private;
  87         uint32_t ret = 0;
  88
  89         switch (supported_device) {
  90         case ATOM_DEVICE_CRT1_SUPPORT:
  91         case ATOM_DEVICE_TV1_SUPPORT:
  92         case ATOM_DEVICE_TV2_SUPPORT:
  93         case ATOM_DEVICE_CRT2_SUPPORT:
  94         case ATOM_DEVICE_CV_SUPPORT:
  95                 switch (dac) {
  96                 case 1: /* dac a */
  97                         if ((rdev->family == CHIP_RS300) ||
  98                             (rdev->family == CHIP_RS400) ||
  99                             (rdev->family == CHIP_RS480))
 100                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
 101                         else if (ASIC_IS_AVIVO(rdev))
 102                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
 103                         else
 104                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
 105                         break;
 106                 case 2: /* dac b */
 107                         if (ASIC_IS_AVIVO(rdev))
 108                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
 109                         else {
 110                                 /*if (rdev->family == CHIP_R200)
 111                                   ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 112                                   else*/
 113                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
 114                         }
 115                         break;
 116                 case 3: /* external dac */
 117                         if (ASIC_IS_AVIVO(rdev))
 118                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 119                         else
 120                                 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 121                         break;
 122                 }
 123                 break;
 124         case ATOM_DEVICE_LCD1_SUPPORT:
 125                 if (ASIC_IS_AVIVO(rdev))
 126                         ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 127                 else
 128                         ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
 129                 break;
 130         case ATOM_DEVICE_DFP1_SUPPORT:
 131                 if ((rdev->family == CHIP_RS300) ||
 132                     (rdev->family == CHIP_RS400) ||
 133                     (rdev->family == CHIP_RS480))
 134                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 135                 else if (ASIC_IS_AVIVO(rdev))
 136                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
 137                 else
 138                         ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
 139                 break;
 140         case ATOM_DEVICE_LCD2_SUPPORT:
 141         case ATOM_DEVICE_DFP2_SUPPORT:
 142                 if ((rdev->family == CHIP_RS600) ||
 143                     (rdev->family == CHIP_RS690) ||
 144                     (rdev->family == CHIP_RS740))
 145                         ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
 146                 else if (ASIC_IS_AVIVO(rdev))
 147                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 148                 else
 149                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 150                 break;
 151         case ATOM_DEVICE_DFP3_SUPPORT:
 152                 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 153                 break;
 154         }
 155
 156         return ret;
 157 }
 158
 159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
 160 {
 161         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 162         switch (radeon_encoder->encoder_id) {
 163         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 164         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 165         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 166         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 167         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 168         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 169         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 170         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 171         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 172         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 173         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 174                 return true;
 175         default:
 176                 return false;
 177         }
 178 }
 179 void
 180 radeon_link_encoder_connector(struct drm_device *dev)
 181 {
 182         struct drm_connector *connector;
 183         struct radeon_connector *radeon_connector;
 184         struct drm_encoder *encoder;
 185         struct radeon_encoder *radeon_encoder;
 186
 187         /* walk the list and link encoders to connectors */
 188         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 189                 radeon_connector = to_radeon_connector(connector);
 190                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 191                         radeon_encoder = to_radeon_encoder(encoder);
 192                         if (radeon_encoder->devices & radeon_connector->devices)
 193                                 drm_mode_connector_attach_encoder(connector, encoder);
 194                 }
 195         }
 196 }
 197
 198 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
 199 {
 200         struct drm_device *dev = encoder->dev;
 201         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 202         struct drm_connector *connector;
 203
 204         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 205                 if (connector->encoder == encoder) {
 206                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 207                         radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
 208                         DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
 209                                   radeon_encoder->active_device, radeon_encoder->devices,
 210                                   radeon_connector->devices, encoder->encoder_type);
 211                 }
 212         }
 213 }
 214
 215 static struct drm_connector *
 216 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
 217 {
 218         struct drm_device *dev = encoder->dev;
 219         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 220         struct drm_connector *connector;
 221         struct radeon_connector *radeon_connector;
 222
 223         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 224                 radeon_connector = to_radeon_connector(connector);
 225                 if (radeon_encoder->active_device & radeon_connector->devices)
 226                         return connector;
 227         }
 228         return NULL;
 229 }
 230
 231 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 232                                    struct drm_display_mode *mode,
 233                                    struct drm_display_mode *adjusted_mode)
 234 {
 235         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 236         struct drm_device *dev = encoder->dev;
 237         struct radeon_device *rdev = dev->dev_private;
 238
 239         /* set the active encoder to connector routing */
 240         radeon_encoder_set_active_device(encoder);
 241         drm_mode_set_crtcinfo(adjusted_mode, 0);
 242
 243         /* hw bug */
 244         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 245             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 246                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 247
 248         /* get the native mode for LVDS */
 249         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 250                 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
 251                 int mode_id = adjusted_mode->base.id;
 252                 *adjusted_mode = *native_mode;
 253                 if (!ASIC_IS_AVIVO(rdev)) {
 254                         adjusted_mode->hdisplay = mode->hdisplay;
 255                         adjusted_mode->vdisplay = mode->vdisplay;
 256                         adjusted_mode->crtc_hdisplay = mode->hdisplay;
 257                         adjusted_mode->crtc_vdisplay = mode->vdisplay;
 258                 }
 259                 adjusted_mode->base.id = mode_id;
 260         }
 261
 262         /* get the native mode for TV */
 263         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 264                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 265                 if (tv_dac) {
 266                         if (tv_dac->tv_std == TV_STD_NTSC ||
 267                             tv_dac->tv_std == TV_STD_NTSC_J ||
 268                             tv_dac->tv_std == TV_STD_PAL_M)
 269                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 270                         else
 271                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 272                 }
 273         }
 274
 275         if (ASIC_IS_DCE3(rdev) &&
 276             (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT))) {
 277                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 278                 radeon_dp_set_link_config(connector, mode);
 279         }
 280
 281         return true;
 282 }
 283
 284 static void
 285 atombios_dac_setup(struct drm_encoder *encoder, int action)
 286 {
 287         struct drm_device *dev = encoder->dev;
 288         struct radeon_device *rdev = dev->dev_private;
 289         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 290         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 291         int index = 0, num = 0;
 292         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 293         enum radeon_tv_std tv_std = TV_STD_NTSC;
 294
 295         if (dac_info->tv_std)
 296                 tv_std = dac_info->tv_std;
 297
 298         memset(&args, 0, sizeof(args));
 299
 300         switch (radeon_encoder->encoder_id) {
 301         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 302         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 303                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 304                 num = 1;
 305                 break;
 306         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 307         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 308                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 309                 num = 2;
 310                 break;
 311         }
 312
 313         args.ucAction = action;
 314
 315         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 316                 args.ucDacStandard = ATOM_DAC1_PS2;
 317         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 318                 args.ucDacStandard = ATOM_DAC1_CV;
 319         else {
 320                 switch (tv_std) {
 321                 case TV_STD_PAL:
 322                 case TV_STD_PAL_M:
 323                 case TV_STD_SCART_PAL:
 324                 case TV_STD_SECAM:
 325                 case TV_STD_PAL_CN:
 326                         args.ucDacStandard = ATOM_DAC1_PAL;
 327                         break;
 328                 case TV_STD_NTSC:
 329                 case TV_STD_NTSC_J:
 330                 case TV_STD_PAL_60:
 331                 default:
 332                         args.ucDacStandard = ATOM_DAC1_NTSC;
 333                         break;
 334                 }
 335         }
 336         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 337
 338         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 339
 340 }
 341
 342 static void
 343 atombios_tv_setup(struct drm_encoder *encoder, int action)
 344 {
 345         struct drm_device *dev = encoder->dev;
 346         struct radeon_device *rdev = dev->dev_private;
 347         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 348         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 349         int index = 0;
 350         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 351         enum radeon_tv_std tv_std = TV_STD_NTSC;
 352
 353         if (dac_info->tv_std)
 354                 tv_std = dac_info->tv_std;
 355
 356         memset(&args, 0, sizeof(args));
 357
 358         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 359
 360         args.sTVEncoder.ucAction = action;
 361
 362         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 363                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 364         else {
 365                 switch (tv_std) {
 366                 case TV_STD_NTSC:
 367                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 368                         break;
 369                 case TV_STD_PAL:
 370                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 371                         break;
 372                 case TV_STD_PAL_M:
 373                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 374                         break;
 375                 case TV_STD_PAL_60:
 376                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 377                         break;
 378                 case TV_STD_NTSC_J:
 379                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 380                         break;
 381                 case TV_STD_SCART_PAL:
 382                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 383                         break;
 384                 case TV_STD_SECAM:
 385                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 386                         break;
 387                 case TV_STD_PAL_CN:
 388                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 389                         break;
 390                 default:
 391                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 392                         break;
 393                 }
 394         }
 395
 396         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 397
 398         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 399
 400 }
 401
 402 void
 403 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
 404 {
 405         struct drm_device *dev = encoder->dev;
 406         struct radeon_device *rdev = dev->dev_private;
 407         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 408         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
 409         int index = 0;
 410
 411         memset(&args, 0, sizeof(args));
 412
 413         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 414
 415         args.sXTmdsEncoder.ucEnable = action;
 416
 417         if (radeon_encoder->pixel_clock > 165000)
 418                 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
 419
 420         /*if (pScrn->rgbBits == 8)*/
 421         args.sXTmdsEncoder.ucMisc |= (1 << 1);
 422
 423         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 424
 425 }
 426
 427 static void
 428 atombios_ddia_setup(struct drm_encoder *encoder, int action)
 429 {
 430         struct drm_device *dev = encoder->dev;
 431         struct radeon_device *rdev = dev->dev_private;
 432         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 433         DVO_ENCODER_CONTROL_PS_ALLOCATION args;
 434         int index = 0;
 435
 436         memset(&args, 0, sizeof(args));
 437
 438         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 439
 440         args.sDVOEncoder.ucAction = action;
 441         args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 442
 443         if (radeon_encoder->pixel_clock > 165000)
 444                 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
 445
 446         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 447
 448 }
 449
 450 union lvds_encoder_control {
 451         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 452         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 453 };
 454
 455 void
 456 atombios_digital_setup(struct drm_encoder *encoder, int action)
 457 {
 458         struct drm_device *dev = encoder->dev;
 459         struct radeon_device *rdev = dev->dev_private;
 460         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 461         union lvds_encoder_control args;
 462         int index = 0;
 463         int hdmi_detected = 0;
 464         uint8_t frev, crev;
 465         struct radeon_encoder_atom_dig *dig;
 466         struct drm_connector *connector;
 467         struct radeon_connector *radeon_connector;
 468         struct radeon_connector_atom_dig *dig_connector;
 469
 470         connector = radeon_get_connector_for_encoder(encoder);
 471         if (!connector)
 472                 return;
 473
 474         radeon_connector = to_radeon_connector(connector);
 475
 476         if (!radeon_encoder->enc_priv)
 477                 return;
 478
 479         dig = radeon_encoder->enc_priv;
 480
 481         if (!radeon_connector->con_priv)
 482                 return;
 483
 484         if (drm_detect_hdmi_monitor(radeon_connector->edid))
 485                 hdmi_detected = 1;
 486
 487         dig_connector = radeon_connector->con_priv;
 488
 489         memset(&args, 0, sizeof(args));
 490
 491         switch (radeon_encoder->encoder_id) {
 492         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 493                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 494                 break;
 495         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 496         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 497                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 498                 break;
 499         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 500                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 501                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 502                 else
 503                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 504                 break;
 505         }
 506
 507         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 508
 509         switch (frev) {
 510         case 1:
 511         case 2:
 512                 switch (crev) {
 513                 case 1:
 514                         args.v1.ucMisc = 0;
 515                         args.v1.ucAction = action;
 516                         if (hdmi_detected)
 517                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 518                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 519                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 520                                 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
 521                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 522                                 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
 523                                         args.v1.ucMisc |= (1 << 1);
 524                         } else {
 525                                 if (dig_connector->linkb)
 526                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 527                                 if (radeon_encoder->pixel_clock > 165000)
 528                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 529                                 /*if (pScrn->rgbBits == 8) */
 530                                 args.v1.ucMisc |= (1 << 1);
 531                         }
 532                         break;
 533                 case 2:
 534                 case 3:
 535                         args.v2.ucMisc = 0;
 536                         args.v2.ucAction = action;
 537                         if (crev == 3) {
 538                                 if (dig->coherent_mode)
 539                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 540                         }
 541                         if (hdmi_detected)
 542                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 543                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 544                         args.v2.ucTruncate = 0;
 545                         args.v2.ucSpatial = 0;
 546                         args.v2.ucTemporal = 0;
 547                         args.v2.ucFRC = 0;
 548                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 549                                 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
 550                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 551                                 if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
 552                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 553                                         if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
 554                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 555                                 }
 556                                 if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
 557                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 558                                         if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
 559                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 560                                         if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 561                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 562                                 }
 563                         } else {
 564                                 if (dig_connector->linkb)
 565                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 566                                 if (radeon_encoder->pixel_clock > 165000)
 567                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 568                         }
 569                         break;
 570                 default:
 571                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 572                         break;
 573                 }
 574                 break;
 575         default:
 576                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 577                 break;
 578         }
 579
 580         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 581         r600_hdmi_enable(encoder, hdmi_detected);
 582 }
 583
 584 int
 585 atombios_get_encoder_mode(struct drm_encoder *encoder)
 586 {
 587         struct drm_connector *connector;
 588         struct radeon_connector *radeon_connector;
 589         struct radeon_connector_atom_dig *radeon_dig_connector;
 590
 591         connector = radeon_get_connector_for_encoder(encoder);
 592         if (!connector)
 593                 return 0;
 594
 595         radeon_connector = to_radeon_connector(connector);
 596
 597         switch (connector->connector_type) {
 598         case DRM_MODE_CONNECTOR_DVII:
 599         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 600                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 601                         return ATOM_ENCODER_MODE_HDMI;
 602                 else if (radeon_connector->use_digital)
 603                         return ATOM_ENCODER_MODE_DVI;
 604                 else
 605                         return ATOM_ENCODER_MODE_CRT;
 606                 break;
 607         case DRM_MODE_CONNECTOR_DVID:
 608         case DRM_MODE_CONNECTOR_HDMIA:
 609         default:
 610                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 611                         return ATOM_ENCODER_MODE_HDMI;
 612                 else
 613                         return ATOM_ENCODER_MODE_DVI;
 614                 break;
 615         case DRM_MODE_CONNECTOR_LVDS:
 616                 return ATOM_ENCODER_MODE_LVDS;
 617                 break;
 618         case DRM_MODE_CONNECTOR_DisplayPort:
 619         case DRM_MODE_CONNECTOR_eDP:
 620                 radeon_dig_connector = radeon_connector->con_priv;
 621                 if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 622                     (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
 623                         return ATOM_ENCODER_MODE_DP;
 624                 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
 625                         return ATOM_ENCODER_MODE_HDMI;
 626                 else
 627                         return ATOM_ENCODER_MODE_DVI;
 628                 break;
 629         case DRM_MODE_CONNECTOR_DVIA:
 630         case DRM_MODE_CONNECTOR_VGA:
 631                 return ATOM_ENCODER_MODE_CRT;
 632                 break;
 633         case DRM_MODE_CONNECTOR_Composite:
 634         case DRM_MODE_CONNECTOR_SVIDEO:
 635         case DRM_MODE_CONNECTOR_9PinDIN:
 636                 /* fix me */
 637                 return ATOM_ENCODER_MODE_TV;
 638                 /*return ATOM_ENCODER_MODE_CV;*/
 639                 break;
 640         }
 641 }
 642
 643 /*
 644  * DIG Encoder/Transmitter Setup
 645  *
 646  * DCE 3.0/3.1
 647  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 648  * Supports up to 3 digital outputs
 649  * - 2 DIG encoder blocks.
 650  * DIG1 can drive UNIPHY link A or link B
 651  * DIG2 can drive UNIPHY link B or LVTMA
 652  *
 653  * DCE 3.2
 654  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 655  * Supports up to 5 digital outputs
 656  * - 2 DIG encoder blocks.
 657  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 658  *
 659  * Routing
 660  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 661  * Examples:
 662  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 663  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 664  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 665  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 666  */
 667 static void
 668 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
 669 {
 670         struct drm_device *dev = encoder->dev;
 671         struct radeon_device *rdev = dev->dev_private;
 672         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 673         DIG_ENCODER_CONTROL_PS_ALLOCATION args;
 674         int index = 0, num = 0;
 675         uint8_t frev, crev;
 676         struct radeon_encoder_atom_dig *dig;
 677         struct drm_connector *connector;
 678         struct radeon_connector *radeon_connector;
 679         struct radeon_connector_atom_dig *dig_connector;
 680
 681         connector = radeon_get_connector_for_encoder(encoder);
 682         if (!connector)
 683                 return;
 684
 685         radeon_connector = to_radeon_connector(connector);
 686
 687         if (!radeon_connector->con_priv)
 688                 return;
 689
 690         dig_connector = radeon_connector->con_priv;
 691
 692         if (!radeon_encoder->enc_priv)
 693                 return;
 694
 695         dig = radeon_encoder->enc_priv;
 696
 697         memset(&args, 0, sizeof(args));
 698
 699         if (dig->dig_encoder)
 700                 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 701         else
 702                 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 703         num = dig->dig_encoder + 1;
 704
 705         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 706
 707         args.ucAction = action;
 708         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 709
 710         if (ASIC_IS_DCE32(rdev)) {
 711                 switch (radeon_encoder->encoder_id) {
 712                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 713                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 714                         break;
 715                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 716                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 717                         break;
 718                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 719                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 720                         break;
 721                 }
 722         } else {
 723                 switch (radeon_encoder->encoder_id) {
 724                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 725                         args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1;
 726                         break;
 727                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 728                         args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2;
 729                         break;
 730                 }
 731         }
 732
 733         args.ucEncoderMode = atombios_get_encoder_mode(encoder);
 734
 735         if (args.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
 736                 if (dig_connector->dp_clock == 270000)
 737                         args.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 738                 args.ucLaneNum = dig_connector->dp_lane_count;
 739         } else if (radeon_encoder->pixel_clock > 165000)
 740                 args.ucLaneNum = 8;
 741         else
 742                 args.ucLaneNum = 4;
 743
 744         if (dig_connector->linkb)
 745                 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 746         else
 747                 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 748
 749         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 750
 751 }
 752
 753 union dig_transmitter_control {
 754         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 755         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 756 };
 757
 758 void
 759 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 760 {
 761         struct drm_device *dev = encoder->dev;
 762         struct radeon_device *rdev = dev->dev_private;
 763         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 764         union dig_transmitter_control args;
 765         int index = 0, num = 0;
 766         uint8_t frev, crev;
 767         struct radeon_encoder_atom_dig *dig;
 768         struct drm_connector *connector;
 769         struct radeon_connector *radeon_connector;
 770         struct radeon_connector_atom_dig *dig_connector;
 771         bool is_dp = false;
 772
 773         connector = radeon_get_connector_for_encoder(encoder);
 774         if (!connector)
 775                 return;
 776
 777         radeon_connector = to_radeon_connector(connector);
 778
 779         if (!radeon_encoder->enc_priv)
 780                 return;
 781
 782         dig = radeon_encoder->enc_priv;
 783
 784         if (!radeon_connector->con_priv)
 785                 return;
 786
 787         dig_connector = radeon_connector->con_priv;
 788
 789         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
 790                 is_dp = true;
 791
 792         memset(&args, 0, sizeof(args));
 793
 794         if (ASIC_IS_DCE32(rdev))
 795                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 796         else {
 797                 switch (radeon_encoder->encoder_id) {
 798                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 799                         index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
 800                         break;
 801                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 802                         index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
 803                         break;
 804                 }
 805         }
 806
 807         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 808
 809         args.v1.ucAction = action;
 810         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 811                 args.v1.usInitInfo = radeon_connector->connector_object_id;
 812         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 813                 args.v1.asMode.ucLaneSel = lane_num;
 814                 args.v1.asMode.ucLaneSet = lane_set;
 815         } else {
 816                 if (is_dp)
 817                         args.v1.usPixelClock =
 818                                 cpu_to_le16(dig_connector->dp_clock / 10);
 819                 else if (radeon_encoder->pixel_clock > 165000)
 820                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 821                 else
 822                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 823         }
 824         if (ASIC_IS_DCE32(rdev)) {
 825                 if (dig->dig_encoder == 1)
 826                         args.v2.acConfig.ucEncoderSel = 1;
 827                 if (dig_connector->linkb)
 828                         args.v2.acConfig.ucLinkSel = 1;
 829
 830                 switch (radeon_encoder->encoder_id) {
 831                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 832                         args.v2.acConfig.ucTransmitterSel = 0;
 833                         num = 0;
 834                         break;
 835                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 836                         args.v2.acConfig.ucTransmitterSel = 1;
 837                         num = 1;
 838                         break;
 839                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 840                         args.v2.acConfig.ucTransmitterSel = 2;
 841                         num = 2;
 842                         break;
 843                 }
 844
 845                 if (is_dp)
 846                         args.v2.acConfig.fCoherentMode = 1;
 847                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 848                         if (dig->coherent_mode)
 849                                 args.v2.acConfig.fCoherentMode = 1;
 850                 }
 851         } else {
 852
 853                 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 854
 855                 if (dig->dig_encoder)
 856                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 857                 else
 858                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
 859
 860                 switch (radeon_encoder->encoder_id) {
 861                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 862                         if (rdev->flags & RADEON_IS_IGP) {
 863                                 if (radeon_encoder->pixel_clock > 165000) {
 864                                         if (dig_connector->igp_lane_info & 0x3)
 865                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
 866                                         else if (dig_connector->igp_lane_info & 0xc)
 867                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
 868                                 } else {
 869                                         if (dig_connector->igp_lane_info & 0x1)
 870                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 871                                         else if (dig_connector->igp_lane_info & 0x2)
 872                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
 873                                         else if (dig_connector->igp_lane_info & 0x4)
 874                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
 875                                         else if (dig_connector->igp_lane_info & 0x8)
 876                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
 877                                 }
 878                         }
 879                         break;
 880                 }
 881
 882                 if (radeon_encoder->pixel_clock > 165000)
 883                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
 884
 885                 if (dig_connector->linkb)
 886                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
 887                 else
 888                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
 889
 890                 if (is_dp)
 891                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 892                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 893                         if (dig->coherent_mode)
 894                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 895                 }
 896         }
 897
 898         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 899 }
 900
 901 static void
 902 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
 903 {
 904         struct drm_device *dev = encoder->dev;
 905         struct radeon_device *rdev = dev->dev_private;
 906         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 907         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 908         ENABLE_YUV_PS_ALLOCATION args;
 909         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
 910         uint32_t temp, reg;
 911
 912         memset(&args, 0, sizeof(args));
 913
 914         if (rdev->family >= CHIP_R600)
 915                 reg = R600_BIOS_3_SCRATCH;
 916         else
 917                 reg = RADEON_BIOS_3_SCRATCH;
 918
 919         /* XXX: fix up scratch reg handling */
 920         temp = RREG32(reg);
 921         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 922                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
 923                              (radeon_crtc->crtc_id << 18)));
 924         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 925                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
 926         else
 927                 WREG32(reg, 0);
 928
 929         if (enable)
 930                 args.ucEnable = ATOM_ENABLE;
 931         args.ucCRTC = radeon_crtc->crtc_id;
 932
 933         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 934
 935         WREG32(reg, temp);
 936 }
 937
 938 static void
 939 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
 940 {
 941         struct drm_device *dev = encoder->dev;
 942         struct radeon_device *rdev = dev->dev_private;
 943         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 944         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
 945         int index = 0;
 946         bool is_dig = false;
 947
 948         memset(&args, 0, sizeof(args));
 949
 950         DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
 951                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
 952                   radeon_encoder->active_device);
 953         switch (radeon_encoder->encoder_id) {
 954         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 955         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 956                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
 957                 break;
 958         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 959         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 960         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 961         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 962                 is_dig = true;
 963                 break;
 964         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 965         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 966         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 967                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
 968                 break;
 969         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 970                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 971                 break;
 972         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 973                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 974                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 975                 else
 976                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
 977                 break;
 978         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 979         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 980                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 981                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
 982                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 983                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
 984                 else
 985                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
 986                 break;
 987         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 988         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 989                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 990                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
 991                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 992                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
 993                 else
 994                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
 995                 break;
 996         }
 997
 998         if (is_dig) {
 999                 switch (mode) {
1000                 case DRM_MODE_DPMS_ON:
1001                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1002                         {
1003                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1004                                 dp_link_train(encoder, connector);
1005                         }
1006                         break;
1007                 case DRM_MODE_DPMS_STANDBY:
1008                 case DRM_MODE_DPMS_SUSPEND:
1009                 case DRM_MODE_DPMS_OFF:
1010                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1011                         break;
1012                 }
1013         } else {
1014                 switch (mode) {
1015                 case DRM_MODE_DPMS_ON:
1016                         args.ucAction = ATOM_ENABLE;
1017                         break;
1018                 case DRM_MODE_DPMS_STANDBY:
1019                 case DRM_MODE_DPMS_SUSPEND:
1020                 case DRM_MODE_DPMS_OFF:
1021                         args.ucAction = ATOM_DISABLE;
1022                         break;
1023                 }
1024                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1025         }
1026         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1027 }
1028
1029 union crtc_sourc_param {
1030         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1031         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1032 };
1033
1034 static void
1035 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1036 {
1037         struct drm_device *dev = encoder->dev;
1038         struct radeon_device *rdev = dev->dev_private;
1039         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1040         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1041         union crtc_sourc_param args;
1042         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1043         uint8_t frev, crev;
1044         struct radeon_encoder_atom_dig *dig;
1045
1046         memset(&args, 0, sizeof(args));
1047
1048         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1049
1050         switch (frev) {
1051         case 1:
1052                 switch (crev) {
1053                 case 1:
1054                 default:
1055                         if (ASIC_IS_AVIVO(rdev))
1056                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1057                         else {
1058                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1059                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1060                                 } else {
1061                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1062                                 }
1063                         }
1064                         switch (radeon_encoder->encoder_id) {
1065                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1066                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1067                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1068                                 break;
1069                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1070                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1071                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1072                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1073                                 else
1074                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1075                                 break;
1076                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1077                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1078                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1079                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1080                                 break;
1081                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1082                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1083                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1084                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1085                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1086                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1087                                 else
1088                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1089                                 break;
1090                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1091                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1092                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1093                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1094                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1095                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1096                                 else
1097                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1098                                 break;
1099                         }
1100                         break;
1101                 case 2:
1102                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1103                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1104                         switch (radeon_encoder->encoder_id) {
1105                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1106                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1107                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1108                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1109                                 dig = radeon_encoder->enc_priv;
1110                                 if (dig->dig_encoder)
1111                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1112                                 else
1113                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1114                                 break;
1115                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1116                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1117                                 break;
1118                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1119                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1120                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1121                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1122                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1123                                 else
1124                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1125                                 break;
1126                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1127                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1128                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1129                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1130                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1131                                 else
1132                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1133                                 break;
1134                         }
1135                         break;
1136                 }
1137                 break;
1138         default:
1139                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1140                 break;
1141         }
1142
1143         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1144 }
1145
1146 static void
1147 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1148                               struct drm_display_mode *mode)
1149 {
1150         struct drm_device *dev = encoder->dev;
1151         struct radeon_device *rdev = dev->dev_private;
1152         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1153         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1154
1155         /* Funky macbooks */
1156         if ((dev->pdev->device == 0x71C5) &&
1157             (dev->pdev->subsystem_vendor == 0x106b) &&
1158             (dev->pdev->subsystem_device == 0x0080)) {
1159                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1160                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1161
1162                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1163                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1164
1165                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1166                 }
1167         }
1168
1169         /* set scaler clears this on some chips */
1170         if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1171                 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1172                         WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1173                                AVIVO_D1MODE_INTERLEAVE_EN);
1174         }
1175 }
1176
1177 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1178 {
1179         struct drm_device *dev = encoder->dev;
1180         struct radeon_device *rdev = dev->dev_private;
1181         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1182         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1183         struct drm_encoder *test_encoder;
1184         struct radeon_encoder_atom_dig *dig;
1185         uint32_t dig_enc_in_use = 0;
1186         /* on DCE32 and encoder can driver any block so just crtc id */
1187         if (ASIC_IS_DCE32(rdev)) {
1188                 return radeon_crtc->crtc_id;
1189         }
1190
1191         /* on DCE3 - LVTMA can only be driven by DIGB */
1192         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1193                 struct radeon_encoder *radeon_test_encoder;
1194
1195                 if (encoder == test_encoder)
1196                         continue;
1197
1198                 if (!radeon_encoder_is_digital(test_encoder))
1199                         continue;
1200
1201                 radeon_test_encoder = to_radeon_encoder(test_encoder);
1202                 dig = radeon_test_encoder->enc_priv;
1203
1204                 if (dig->dig_encoder >= 0)
1205                         dig_enc_in_use |= (1 << dig->dig_encoder);
1206         }
1207
1208         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1209                 if (dig_enc_in_use & 0x2)
1210                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1211                 return 1;
1212         }
1213         if (!(dig_enc_in_use & 1))
1214                 return 0;
1215         return 1;
1216 }
1217
1218 static void
1219 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1220                              struct drm_display_mode *mode,
1221                              struct drm_display_mode *adjusted_mode)
1222 {
1223         struct drm_device *dev = encoder->dev;
1224         struct radeon_device *rdev = dev->dev_private;
1225         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1226         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1227
1228         if (radeon_encoder->active_device &
1229             (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1230                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1231                 if (dig)
1232                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1233         }
1234         radeon_encoder->pixel_clock = adjusted_mode->clock;
1235
1236         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1237         atombios_set_encoder_crtc_source(encoder);
1238
1239         if (ASIC_IS_AVIVO(rdev)) {
1240                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1241                         atombios_yuv_setup(encoder, true);
1242                 else
1243                         atombios_yuv_setup(encoder, false);
1244         }
1245
1246         switch (radeon_encoder->encoder_id) {
1247         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1248         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1249         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1250         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1251                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1252                 break;
1253         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1254         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1255         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1256         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1257                 /* disable the encoder and transmitter */
1258                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1259                 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1260
1261                 /* setup and enable the encoder and transmitter */
1262                 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1263                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1264                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1265                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1266                 break;
1267         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1268                 atombios_ddia_setup(encoder, ATOM_ENABLE);
1269                 break;
1270         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1271         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1272                 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1273                 break;
1274         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1275         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1276         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1277         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1278                 atombios_dac_setup(encoder, ATOM_ENABLE);
1279                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1280                         atombios_tv_setup(encoder, ATOM_ENABLE);
1281                 break;
1282         }
1283         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1284
1285         r600_hdmi_setmode(encoder, adjusted_mode);
1286 }
1287
1288 static bool
1289 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1290 {
1291         struct drm_device *dev = encoder->dev;
1292         struct radeon_device *rdev = dev->dev_private;
1293         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1294         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1295
1296         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1297                                        ATOM_DEVICE_CV_SUPPORT |
1298                                        ATOM_DEVICE_CRT_SUPPORT)) {
1299                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1300                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1301                 uint8_t frev, crev;
1302
1303                 memset(&args, 0, sizeof(args));
1304
1305                 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1306
1307                 args.sDacload.ucMisc = 0;
1308
1309                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1310                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1311                         args.sDacload.ucDacType = ATOM_DAC_A;
1312                 else
1313                         args.sDacload.ucDacType = ATOM_DAC_B;
1314
1315                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1316                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1317                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1318                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1319                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1320                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1321                         if (crev >= 3)
1322                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1323                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1324                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1325                         if (crev >= 3)
1326                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1327                 }
1328
1329                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1330
1331                 return true;
1332         } else
1333                 return false;
1334 }
1335
1336 static enum drm_connector_status
1337 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1338 {
1339         struct drm_device *dev = encoder->dev;
1340         struct radeon_device *rdev = dev->dev_private;
1341         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1342         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1343         uint32_t bios_0_scratch;
1344
1345         if (!atombios_dac_load_detect(encoder, connector)) {
1346                 DRM_DEBUG("detect returned false \n");
1347                 return connector_status_unknown;
1348         }
1349
1350         if (rdev->family >= CHIP_R600)
1351                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1352         else
1353                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1354
1355         DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1356         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1357                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1358                         return connector_status_connected;
1359         }
1360         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1361                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1362                         return connector_status_connected;
1363         }
1364         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1365                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1366                         return connector_status_connected;
1367         }
1368         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1369                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1370                         return connector_status_connected; /* CTV */
1371                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1372                         return connector_status_connected; /* STV */
1373         }
1374         return connector_status_disconnected;
1375 }
1376
1377 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1378 {
1379         radeon_atom_output_lock(encoder, true);
1380         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1381 }
1382
1383 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1384 {
1385         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1386         radeon_atom_output_lock(encoder, false);
1387 }
1388
1389 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1390 {
1391         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1392         struct radeon_encoder_atom_dig *dig;
1393         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1394
1395         if (radeon_encoder_is_digital(encoder)) {
1396                 dig = radeon_encoder->enc_priv;
1397                 dig->dig_encoder = -1;
1398         }
1399         radeon_encoder->active_device = 0;
1400 }
1401
1402 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1403         .dpms = radeon_atom_encoder_dpms,
1404         .mode_fixup = radeon_atom_mode_fixup,
1405         .prepare = radeon_atom_encoder_prepare,
1406         .mode_set = radeon_atom_encoder_mode_set,
1407         .commit = radeon_atom_encoder_commit,
1408         .disable = radeon_atom_encoder_disable,
1409         /* no detect for TMDS/LVDS yet */
1410 };
1411
1412 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1413         .dpms = radeon_atom_encoder_dpms,
1414         .mode_fixup = radeon_atom_mode_fixup,
1415         .prepare = radeon_atom_encoder_prepare,
1416         .mode_set = radeon_atom_encoder_mode_set,
1417         .commit = radeon_atom_encoder_commit,
1418         .detect = radeon_atom_dac_detect,
1419 };
1420
1421 void radeon_enc_destroy(struct drm_encoder *encoder)
1422 {
1423         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1424         kfree(radeon_encoder->enc_priv);
1425         drm_encoder_cleanup(encoder);
1426         kfree(radeon_encoder);
1427 }
1428
1429 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1430         .destroy = radeon_enc_destroy,
1431 };
1432
1433 struct radeon_encoder_atom_dac *
1434 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1435 {
1436         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1437
1438         if (!dac)
1439                 return NULL;
1440
1441         dac->tv_std = TV_STD_NTSC;
1442         return dac;
1443 }
1444
1445 struct radeon_encoder_atom_dig *
1446 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1447 {
1448         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1449
1450         if (!dig)
1451                 return NULL;
1452
1453         /* coherent mode by default */
1454         dig->coherent_mode = true;
1455         dig->dig_encoder = -1;
1456
1457         return dig;
1458 }
1459
1460 void
1461 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1462 {
1463         struct radeon_device *rdev = dev->dev_private;
1464         struct drm_encoder *encoder;
1465         struct radeon_encoder *radeon_encoder;
1466
1467         /* see if we already added it */
1468         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1469                 radeon_encoder = to_radeon_encoder(encoder);
1470                 if (radeon_encoder->encoder_id == encoder_id) {
1471                         radeon_encoder->devices |= supported_device;
1472                         return;
1473                 }
1474
1475         }
1476
1477         /* add a new one */
1478         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1479         if (!radeon_encoder)
1480                 return;
1481
1482         encoder = &radeon_encoder->base;
1483         if (rdev->flags & RADEON_SINGLE_CRTC)
1484                 encoder->possible_crtcs = 0x1;
1485         else
1486                 encoder->possible_crtcs = 0x3;
1487
1488         radeon_encoder->enc_priv = NULL;
1489
1490         radeon_encoder->encoder_id = encoder_id;
1491         radeon_encoder->devices = supported_device;
1492         radeon_encoder->rmx_type = RMX_OFF;
1493
1494         switch (radeon_encoder->encoder_id) {
1495         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1496         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1497         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1498         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1499                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1500                         radeon_encoder->rmx_type = RMX_FULL;
1501                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1502                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1503                 } else {
1504                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1505                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1506                 }
1507                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1508                 break;
1509         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1510                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1511                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1512                 break;
1513         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1514         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1515         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1516                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1517                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1518                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1519                 break;
1520         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1521         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1522         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1523         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1524         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1525         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1526         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1527                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1528                         radeon_encoder->rmx_type = RMX_FULL;
1529                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1530                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1531                 } else {
1532                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1533                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1534                 }
1535                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1536                 break;
1537         }
1538
1539         r600_hdmi_init(encoder);
1540 }