drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/radeon_drm.h>
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include <linux/pm_runtime.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_edid.h>
  36
  37 #include <linux/gcd.h>
  38
  39 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  40 {
  41         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  42         struct drm_device *dev = crtc->dev;
  43         struct radeon_device *rdev = dev->dev_private;
  44         int i;
  45
  46         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  47         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  48
  49         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  50         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  51         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  52
  53         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  54         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  55         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  56
  57         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  58         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  59         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  60
  61         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  62         for (i = 0; i < 256; i++) {
  63                 WREG32(AVIVO_DC_LUT_30_COLOR,
  64                              (radeon_crtc->lut_r[i] << 20) |
  65                              (radeon_crtc->lut_g[i] << 10) |
  66                              (radeon_crtc->lut_b[i] << 0));
  67         }
  68
  69         WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
  70 }
  71
  72 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
  73 {
  74         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  75         struct drm_device *dev = crtc->dev;
  76         struct radeon_device *rdev = dev->dev_private;
  77         int i;
  78
  79         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  80         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  81
  82         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  83         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  84         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  85
  86         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  87         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  88         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  89
  90         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  91         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  92
  93         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
  94         for (i = 0; i < 256; i++) {
  95                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
  96                        (radeon_crtc->lut_r[i] << 20) |
  97                        (radeon_crtc->lut_g[i] << 10) |
  98                        (radeon_crtc->lut_b[i] << 0));
  99         }
 100 }
 101
 102 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 103 {
 104         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 105         struct drm_device *dev = crtc->dev;
 106         struct radeon_device *rdev = dev->dev_private;
 107         int i;
 108
 109         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 110
 111         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 112                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 113                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 114         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 115                NI_GRPH_PRESCALE_BYPASS);
 116         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 117                NI_OVL_PRESCALE_BYPASS);
 118         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 119                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 120                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 121
 122         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 123
 124         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 125         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 126         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 127
 128         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 129         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 130         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 131
 132         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 133         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 134
 135         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 136         for (i = 0; i < 256; i++) {
 137                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 138                        (radeon_crtc->lut_r[i] << 20) |
 139                        (radeon_crtc->lut_g[i] << 10) |
 140                        (radeon_crtc->lut_b[i] << 0));
 141         }
 142
 143         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 144                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 145                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 146                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 147                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 148         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 149                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 150                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 151         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 152                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 153                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 154         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 155                (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
 156                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 157         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
 158         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 159         if (ASIC_IS_DCE8(rdev)) {
 160                 /* XXX this only needs to be programmed once per crtc at startup,
 161                  * not sure where the best place for it is
 162                  */
 163                 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
 164                        CIK_CURSOR_ALPHA_BLND_ENA);
 165         }
 166 }
 167
 168 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 169 {
 170         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 171         struct drm_device *dev = crtc->dev;
 172         struct radeon_device *rdev = dev->dev_private;
 173         int i;
 174         uint32_t dac2_cntl;
 175
 176         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 177         if (radeon_crtc->crtc_id == 0)
 178                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 179         else
 180                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 181         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 182
 183         WREG8(RADEON_PALETTE_INDEX, 0);
 184         for (i = 0; i < 256; i++) {
 185                 WREG32(RADEON_PALETTE_30_DATA,
 186                              (radeon_crtc->lut_r[i] << 20) |
 187                              (radeon_crtc->lut_g[i] << 10) |
 188                              (radeon_crtc->lut_b[i] << 0));
 189         }
 190 }
 191
 192 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 193 {
 194         struct drm_device *dev = crtc->dev;
 195         struct radeon_device *rdev = dev->dev_private;
 196
 197         if (!crtc->enabled)
 198                 return;
 199
 200         if (ASIC_IS_DCE5(rdev))
 201                 dce5_crtc_load_lut(crtc);
 202         else if (ASIC_IS_DCE4(rdev))
 203                 dce4_crtc_load_lut(crtc);
 204         else if (ASIC_IS_AVIVO(rdev))
 205                 avivo_crtc_load_lut(crtc);
 206         else
 207                 legacy_crtc_load_lut(crtc);
 208 }
 209
 210 /** Sets the color ramps on behalf of fbcon */
 211 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 212                               u16 blue, int regno)
 213 {
 214         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 215
 216         radeon_crtc->lut_r[regno] = red >> 6;
 217         radeon_crtc->lut_g[regno] = green >> 6;
 218         radeon_crtc->lut_b[regno] = blue >> 6;
 219 }
 220
 221 /** Gets the color ramps on behalf of fbcon */
 222 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 223                               u16 *blue, int regno)
 224 {
 225         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 226
 227         *red = radeon_crtc->lut_r[regno] << 6;
 228         *green = radeon_crtc->lut_g[regno] << 6;
 229         *blue = radeon_crtc->lut_b[regno] << 6;
 230 }
 231
 232 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 233                                   u16 *blue, uint32_t start, uint32_t size)
 234 {
 235         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 236         int end = (start + size > 256) ? 256 : start + size, i;
 237
 238         /* userspace palettes are always correct as is */
 239         for (i = start; i < end; i++) {
 240                 radeon_crtc->lut_r[i] = red[i] >> 6;
 241                 radeon_crtc->lut_g[i] = green[i] >> 6;
 242                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 243         }
 244         radeon_crtc_load_lut(crtc);
 245 }
 246
 247 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 248 {
 249         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 250
 251         drm_crtc_cleanup(crtc);
 252         kfree(radeon_crtc);
 253 }
 254
 255 /*
 256  * Handle unpin events outside the interrupt handler proper.
 257  */
 258 static void radeon_unpin_work_func(struct work_struct *__work)
 259 {
 260         struct radeon_unpin_work *work =
 261                 container_of(__work, struct radeon_unpin_work, work);
 262         int r;
 263
 264         /* unpin of the old buffer */
 265         r = radeon_bo_reserve(work->old_rbo, false);
 266         if (likely(r == 0)) {
 267                 r = radeon_bo_unpin(work->old_rbo);
 268                 if (unlikely(r != 0)) {
 269                         DRM_ERROR("failed to unpin buffer after flip\n");
 270                 }
 271                 radeon_bo_unreserve(work->old_rbo);
 272         } else
 273                 DRM_ERROR("failed to reserve buffer after flip\n");
 274
 275         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 276         kfree(work);
 277 }
 278
 279 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 280 {
 281         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 282         struct radeon_unpin_work *work;
 283         unsigned long flags;
 284         u32 update_pending;
 285         int vpos, hpos;
 286
 287         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 288         work = radeon_crtc->unpin_work;
 289         if (work == NULL ||
 290             (work->fence && !radeon_fence_signaled(work->fence))) {
 291                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 292                 return;
 293         }
 294         /* New pageflip, or just completion of a previous one? */
 295         if (!radeon_crtc->deferred_flip_completion) {
 296                 /* do the flip (mmio) */
 297                 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
 298         } else {
 299                 /* This is just a completion of a flip queued in crtc
 300                  * at last invocation. Make sure we go directly to
 301                  * completion routine.
 302                  */
 303                 update_pending = 0;
 304                 radeon_crtc->deferred_flip_completion = 0;
 305         }
 306
 307         /* Has the pageflip already completed in crtc, or is it certain
 308          * to complete in this vblank?
 309          */
 310         if (update_pending &&
 311             (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
 312                                                                &vpos, &hpos, NULL, NULL)) &&
 313             ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
 314              (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
 315                 /* crtc didn't flip in this target vblank interval,
 316                  * but flip is pending in crtc. Based on the current
 317                  * scanout position we know that the current frame is
 318                  * (nearly) complete and the flip will (likely)
 319                  * complete before the start of the next frame.
 320                  */
 321                 update_pending = 0;
 322         }
 323         if (update_pending) {
 324                 /* crtc didn't flip in this target vblank interval,
 325                  * but flip is pending in crtc. It will complete it
 326                  * in next vblank interval, so complete the flip at
 327                  * next vblank irq.
 328                  */
 329                 radeon_crtc->deferred_flip_completion = 1;
 330                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 331                 return;
 332         }
 333
 334         /* Pageflip (will be) certainly completed in this vblank. Clean up. */
 335         radeon_crtc->unpin_work = NULL;
 336
 337         /* wakeup userspace */
 338         if (work->event)
 339                 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
 340
 341         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 342
 343         drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
 344         radeon_fence_unref(&work->fence);
 345         radeon_post_page_flip(work->rdev, work->crtc_id);
 346         schedule_work(&work->work);
 347 }
 348
 349 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
 350                                  struct drm_framebuffer *fb,
 351                                  struct drm_pending_vblank_event *event,
 352                                  uint32_t page_flip_flags)
 353 {
 354         struct drm_device *dev = crtc->dev;
 355         struct radeon_device *rdev = dev->dev_private;
 356         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 357         struct radeon_framebuffer *old_radeon_fb;
 358         struct radeon_framebuffer *new_radeon_fb;
 359         struct drm_gem_object *obj;
 360         struct radeon_bo *rbo;
 361         struct radeon_unpin_work *work;
 362         unsigned long flags;
 363         u32 tiling_flags, pitch_pixels;
 364         u64 base;
 365         int r;
 366
 367         work = kzalloc(sizeof *work, GFP_KERNEL);
 368         if (work == NULL)
 369                 return -ENOMEM;
 370
 371         work->event = event;
 372         work->rdev = rdev;
 373         work->crtc_id = radeon_crtc->crtc_id;
 374         old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
 375         new_radeon_fb = to_radeon_framebuffer(fb);
 376         /* schedule unpin of the old buffer */
 377         obj = old_radeon_fb->obj;
 378         /* take a reference to the old object */
 379         drm_gem_object_reference(obj);
 380         rbo = gem_to_radeon_bo(obj);
 381         work->old_rbo = rbo;
 382         obj = new_radeon_fb->obj;
 383         rbo = gem_to_radeon_bo(obj);
 384
 385         spin_lock(&rbo->tbo.bdev->fence_lock);
 386         if (rbo->tbo.sync_obj)
 387                 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
 388         spin_unlock(&rbo->tbo.bdev->fence_lock);
 389
 390         INIT_WORK(&work->work, radeon_unpin_work_func);
 391
 392         /* We borrow the event spin lock for protecting unpin_work */
 393         spin_lock_irqsave(&dev->event_lock, flags);
 394         if (radeon_crtc->unpin_work) {
 395                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 396                 r = -EBUSY;
 397                 goto unlock_free;
 398         }
 399         radeon_crtc->unpin_work = work;
 400         radeon_crtc->deferred_flip_completion = 0;
 401         spin_unlock_irqrestore(&dev->event_lock, flags);
 402
 403         /* pin the new buffer */
 404         DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
 405                          work->old_rbo, rbo);
 406
 407         r = radeon_bo_reserve(rbo, false);
 408         if (unlikely(r != 0)) {
 409                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 410                 goto pflip_cleanup;
 411         }
 412         /* Only 27 bit offset for legacy CRTC */
 413         r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
 414                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
 415         if (unlikely(r != 0)) {
 416                 radeon_bo_unreserve(rbo);
 417                 r = -EINVAL;
 418                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 419                 goto pflip_cleanup;
 420         }
 421         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 422         radeon_bo_unreserve(rbo);
 423
 424         if (!ASIC_IS_AVIVO(rdev)) {
 425                 /* crtc offset is from display base addr not FB location */
 426                 base -= radeon_crtc->legacy_display_base_addr;
 427                 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
 428
 429                 if (tiling_flags & RADEON_TILING_MACRO) {
 430                         if (ASIC_IS_R300(rdev)) {
 431                                 base &= ~0x7ff;
 432                         } else {
 433                                 int byteshift = fb->bits_per_pixel >> 4;
 434                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 435                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 436                         }
 437                 } else {
 438                         int offset = crtc->y * pitch_pixels + crtc->x;
 439                         switch (fb->bits_per_pixel) {
 440                         case 8:
 441                         default:
 442                                 offset *= 1;
 443                                 break;
 444                         case 15:
 445                         case 16:
 446                                 offset *= 2;
 447                                 break;
 448                         case 24:
 449                                 offset *= 3;
 450                                 break;
 451                         case 32:
 452                                 offset *= 4;
 453                                 break;
 454                         }
 455                         base += offset;
 456                 }
 457                 base &= ~7;
 458         }
 459
 460         spin_lock_irqsave(&dev->event_lock, flags);
 461         work->new_crtc_base = base;
 462         spin_unlock_irqrestore(&dev->event_lock, flags);
 463
 464         /* update crtc fb */
 465         crtc->primary->fb = fb;
 466
 467         r = drm_vblank_get(dev, radeon_crtc->crtc_id);
 468         if (r) {
 469                 DRM_ERROR("failed to get vblank before flip\n");
 470                 goto pflip_cleanup1;
 471         }
 472
 473         /* set the proper interrupt */
 474         radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
 475
 476         return 0;
 477
 478 pflip_cleanup1:
 479         if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
 480                 DRM_ERROR("failed to reserve new rbo in error path\n");
 481                 goto pflip_cleanup;
 482         }
 483         if (unlikely(radeon_bo_unpin(rbo) != 0)) {
 484                 DRM_ERROR("failed to unpin new rbo in error path\n");
 485         }
 486         radeon_bo_unreserve(rbo);
 487
 488 pflip_cleanup:
 489         spin_lock_irqsave(&dev->event_lock, flags);
 490         radeon_crtc->unpin_work = NULL;
 491 unlock_free:
 492         spin_unlock_irqrestore(&dev->event_lock, flags);
 493         drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
 494         radeon_fence_unref(&work->fence);
 495         kfree(work);
 496
 497         return r;
 498 }
 499
 500 static int
 501 radeon_crtc_set_config(struct drm_mode_set *set)
 502 {
 503         struct drm_device *dev;
 504         struct radeon_device *rdev;
 505         struct drm_crtc *crtc;
 506         bool active = false;
 507         int ret;
 508
 509         if (!set || !set->crtc)
 510                 return -EINVAL;
 511
 512         dev = set->crtc->dev;
 513
 514         ret = pm_runtime_get_sync(dev->dev);
 515         if (ret < 0)
 516                 return ret;
 517
 518         ret = drm_crtc_helper_set_config(set);
 519
 520         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 521                 if (crtc->enabled)
 522                         active = true;
 523
 524         pm_runtime_mark_last_busy(dev->dev);
 525
 526         rdev = dev->dev_private;
 527         /* if we have active crtcs and we don't have a power ref,
 528            take the current one */
 529         if (active && !rdev->have_disp_power_ref) {
 530                 rdev->have_disp_power_ref = true;
 531                 return ret;
 532         }
 533         /* if we have no active crtcs, then drop the power ref
 534            we got before */
 535         if (!active && rdev->have_disp_power_ref) {
 536                 pm_runtime_put_autosuspend(dev->dev);
 537                 rdev->have_disp_power_ref = false;
 538         }
 539
 540         /* drop the power reference we got coming in here */
 541         pm_runtime_put_autosuspend(dev->dev);
 542         return ret;
 543 }
 544 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 545         .cursor_set = radeon_crtc_cursor_set,
 546         .cursor_move = radeon_crtc_cursor_move,
 547         .gamma_set = radeon_crtc_gamma_set,
 548         .set_config = radeon_crtc_set_config,
 549         .destroy = radeon_crtc_destroy,
 550         .page_flip = radeon_crtc_page_flip,
 551 };
 552
 553 static void radeon_crtc_init(struct drm_device *dev, int index)
 554 {
 555         struct radeon_device *rdev = dev->dev_private;
 556         struct radeon_crtc *radeon_crtc;
 557         int i;
 558
 559         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 560         if (radeon_crtc == NULL)
 561                 return;
 562
 563         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 564
 565         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 566         radeon_crtc->crtc_id = index;
 567         rdev->mode_info.crtcs[index] = radeon_crtc;
 568
 569         if (rdev->family >= CHIP_BONAIRE) {
 570                 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
 571                 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
 572         } else {
 573                 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
 574                 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
 575         }
 576         dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
 577         dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
 578
 579 #if 0
 580         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 581         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 582         radeon_crtc->mode_set.num_connectors = 0;
 583 #endif
 584
 585         for (i = 0; i < 256; i++) {
 586                 radeon_crtc->lut_r[i] = i << 2;
 587                 radeon_crtc->lut_g[i] = i << 2;
 588                 radeon_crtc->lut_b[i] = i << 2;
 589         }
 590
 591         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 592                 radeon_atombios_init_crtc(dev, radeon_crtc);
 593         else
 594                 radeon_legacy_init_crtc(dev, radeon_crtc);
 595 }
 596
 597 static const char *encoder_names[38] = {
 598         "NONE",
 599         "INTERNAL_LVDS",
 600         "INTERNAL_TMDS1",
 601         "INTERNAL_TMDS2",
 602         "INTERNAL_DAC1",
 603         "INTERNAL_DAC2",
 604         "INTERNAL_SDVOA",
 605         "INTERNAL_SDVOB",
 606         "SI170B",
 607         "CH7303",
 608         "CH7301",
 609         "INTERNAL_DVO1",
 610         "EXTERNAL_SDVOA",
 611         "EXTERNAL_SDVOB",
 612         "TITFP513",
 613         "INTERNAL_LVTM1",
 614         "VT1623",
 615         "HDMI_SI1930",
 616         "HDMI_INTERNAL",
 617         "INTERNAL_KLDSCP_TMDS1",
 618         "INTERNAL_KLDSCP_DVO1",
 619         "INTERNAL_KLDSCP_DAC1",
 620         "INTERNAL_KLDSCP_DAC2",
 621         "SI178",
 622         "MVPU_FPGA",
 623         "INTERNAL_DDI",
 624         "VT1625",
 625         "HDMI_SI1932",
 626         "DP_AN9801",
 627         "DP_DP501",
 628         "INTERNAL_UNIPHY",
 629         "INTERNAL_KLDSCP_LVTMA",
 630         "INTERNAL_UNIPHY1",
 631         "INTERNAL_UNIPHY2",
 632         "NUTMEG",
 633         "TRAVIS",
 634         "INTERNAL_VCE",
 635         "INTERNAL_UNIPHY3",
 636 };
 637
 638 static const char *hpd_names[6] = {
 639         "HPD1",
 640         "HPD2",
 641         "HPD3",
 642         "HPD4",
 643         "HPD5",
 644         "HPD6",
 645 };
 646
 647 static void radeon_print_display_setup(struct drm_device *dev)
 648 {
 649         struct drm_connector *connector;
 650         struct radeon_connector *radeon_connector;
 651         struct drm_encoder *encoder;
 652         struct radeon_encoder *radeon_encoder;
 653         uint32_t devices;
 654         int i = 0;
 655
 656         DRM_INFO("Radeon Display Connectors\n");
 657         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 658                 radeon_connector = to_radeon_connector(connector);
 659                 DRM_INFO("Connector %d:\n", i);
 660                 DRM_INFO("  %s\n", drm_get_connector_name(connector));
 661                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 662                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 663                 if (radeon_connector->ddc_bus) {
 664                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 665                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 666                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 667                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 668                                  radeon_connector->ddc_bus->rec.a_data_reg,
 669                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 670                                  radeon_connector->ddc_bus->rec.en_data_reg,
 671                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 672                                  radeon_connector->ddc_bus->rec.y_data_reg);
 673                         if (radeon_connector->router.ddc_valid)
 674                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 675                                          radeon_connector->router.ddc_mux_control_pin,
 676                                          radeon_connector->router.ddc_mux_state);
 677                         if (radeon_connector->router.cd_valid)
 678                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 679                                          radeon_connector->router.cd_mux_control_pin,
 680                                          radeon_connector->router.cd_mux_state);
 681                 } else {
 682                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 683                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 684                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 685                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 686                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 687                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 688                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 689                 }
 690                 DRM_INFO("  Encoders:\n");
 691                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 692                         radeon_encoder = to_radeon_encoder(encoder);
 693                         devices = radeon_encoder->devices & radeon_connector->devices;
 694                         if (devices) {
 695                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 696                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 697                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 698                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 699                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 700                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 701                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 702                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 703                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 704                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 705                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 706                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 707                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 708                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 709                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 710                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 711                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 712                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 713                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 714                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 715                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 716                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 717                         }
 718                 }
 719                 i++;
 720         }
 721 }
 722
 723 static bool radeon_setup_enc_conn(struct drm_device *dev)
 724 {
 725         struct radeon_device *rdev = dev->dev_private;
 726         bool ret = false;
 727
 728         if (rdev->bios) {
 729                 if (rdev->is_atom_bios) {
 730                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 731                         if (ret == false)
 732                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 733                 } else {
 734                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 735                         if (ret == false)
 736                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 737                 }
 738         } else {
 739                 if (!ASIC_IS_AVIVO(rdev))
 740                         ret = radeon_get_legacy_connector_info_from_table(dev);
 741         }
 742         if (ret) {
 743                 radeon_setup_encoder_clones(dev);
 744                 radeon_print_display_setup(dev);
 745         }
 746
 747         return ret;
 748 }
 749
 750 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 751 {
 752         struct drm_device *dev = radeon_connector->base.dev;
 753         struct radeon_device *rdev = dev->dev_private;
 754         int ret = 0;
 755
 756         /* on hw with routers, select right port */
 757         if (radeon_connector->router.ddc_valid)
 758                 radeon_router_select_ddc_port(radeon_connector);
 759
 760         if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
 761             ENCODER_OBJECT_ID_NONE) {
 762                 if (radeon_connector->ddc_bus->has_aux)
 763                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 764                                                               &radeon_connector->ddc_bus->aux.ddc);
 765         } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 766                    (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
 767                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 768
 769                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 770                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
 771                     radeon_connector->ddc_bus->has_aux)
 772                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 773                                                               &radeon_connector->ddc_bus->aux.ddc);
 774                 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
 775                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 776                                                               &radeon_connector->ddc_bus->adapter);
 777         } else {
 778                 if (radeon_connector->ddc_bus && !radeon_connector->edid)
 779                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 780                                                               &radeon_connector->ddc_bus->adapter);
 781         }
 782
 783         if (!radeon_connector->edid) {
 784                 if (rdev->is_atom_bios) {
 785                         /* some laptops provide a hardcoded edid in rom for LCDs */
 786                         if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 787                              (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
 788                                 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 789                 } else
 790                         /* some servers provide a hardcoded edid in rom for KVMs */
 791                         radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 792         }
 793         if (radeon_connector->edid) {
 794                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 795                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 796                 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
 797                 return ret;
 798         }
 799         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 800         return 0;
 801 }
 802
 803 /* avivo */
 804
 805 /**
 806  * avivo_reduce_ratio - fractional number reduction
 807  *
 808  * @nom: nominator
 809  * @den: denominator
 810  * @nom_min: minimum value for nominator
 811  * @den_min: minimum value for denominator
 812  *
 813  * Find the greatest common divisor and apply it on both nominator and
 814  * denominator, but make nominator and denominator are at least as large
 815  * as their minimum values.
 816  */
 817 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
 818                                unsigned nom_min, unsigned den_min)
 819 {
 820         unsigned tmp;
 821
 822         /* reduce the numbers to a simpler ratio */
 823         tmp = gcd(*nom, *den);
 824         *nom /= tmp;
 825         *den /= tmp;
 826
 827         /* make sure nominator is large enough */
 828         if (*nom < nom_min) {
 829                 tmp = (nom_min + *nom - 1) / *nom;
 830                 *nom *= tmp;
 831                 *den *= tmp;
 832         }
 833
 834         /* make sure the denominator is large enough */
 835         if (*den < den_min) {
 836                 tmp = (den_min + *den - 1) / *den;
 837                 *nom *= tmp;
 838                 *den *= tmp;
 839         }
 840 }
 841
 842 /**
 843  * radeon_compute_pll_avivo - compute PLL paramaters
 844  *
 845  * @pll: information about the PLL
 846  * @dot_clock_p: resulting pixel clock
 847  * fb_div_p: resulting feedback divider
 848  * frac_fb_div_p: fractional part of the feedback divider
 849  * ref_div_p: resulting reference divider
 850  * post_div_p: resulting reference divider
 851  *
 852  * Try to calculate the PLL parameters to generate the given frequency:
 853  * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
 854  */
 855 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 856                               u32 freq,
 857                               u32 *dot_clock_p,
 858                               u32 *fb_div_p,
 859                               u32 *frac_fb_div_p,
 860                               u32 *ref_div_p,
 861                               u32 *post_div_p)
 862 {
 863         unsigned fb_div_min, fb_div_max, fb_div;
 864         unsigned post_div_min, post_div_max, post_div;
 865         unsigned ref_div_min, ref_div_max, ref_div;
 866         unsigned post_div_best, diff_best;
 867         unsigned nom, den, tmp;
 868
 869         /* determine allowed feedback divider range */
 870         fb_div_min = pll->min_feedback_div;
 871         fb_div_max = pll->max_feedback_div;
 872
 873         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 874                 fb_div_min *= 10;
 875                 fb_div_max *= 10;
 876         }
 877
 878         /* determine allowed ref divider range */
 879         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 880                 ref_div_min = pll->reference_div;
 881         else
 882                 ref_div_min = pll->min_ref_div;
 883         ref_div_max = pll->max_ref_div;
 884
 885         /* determine allowed post divider range */
 886         if (pll->flags & RADEON_PLL_USE_POST_DIV) {
 887                 post_div_min = pll->post_div;
 888                 post_div_max = pll->post_div;
 889         } else {
 890                 unsigned target_clock = freq / 10;
 891                 unsigned vco_min, vco_max;
 892
 893                 if (pll->flags & RADEON_PLL_IS_LCD) {
 894                         vco_min = pll->lcd_pll_out_min;
 895                         vco_max = pll->lcd_pll_out_max;
 896                 } else {
 897                         vco_min = pll->pll_out_min;
 898                         vco_max = pll->pll_out_max;
 899                 }
 900
 901                 post_div_min = vco_min / target_clock;
 902                 if ((target_clock * post_div_min) < vco_min)
 903                         ++post_div_min;
 904                 if (post_div_min < pll->min_post_div)
 905                         post_div_min = pll->min_post_div;
 906
 907                 post_div_max = vco_max / target_clock;
 908                 if ((target_clock * post_div_max) > vco_max)
 909                         --post_div_max;
 910                 if (post_div_max > pll->max_post_div)
 911                         post_div_max = pll->max_post_div;
 912         }
 913
 914         /* represent the searched ratio as fractional number */
 915         nom = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? freq : freq / 10;
 916         den = pll->reference_freq;
 917
 918         /* reduce the numbers to a simpler ratio */
 919         avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
 920
 921         /* now search for a post divider */
 922         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
 923                 post_div_best = post_div_min;
 924         else
 925                 post_div_best = post_div_max;
 926         diff_best = ~0;
 927
 928         for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
 929                 unsigned diff = abs(den - den / post_div * post_div);
 930                 if (diff < diff_best || (diff == diff_best &&
 931                     !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
 932
 933                         post_div_best = post_div;
 934                         diff_best = diff;
 935                 }
 936         }
 937         post_div = post_div_best;
 938
 939         /* get matching reference and feedback divider */
 940         ref_div = max(den / post_div, 1u);
 941         fb_div = nom;
 942
 943         /* we're almost done, but reference and feedback
 944            divider might be to large now */
 945
 946         tmp = ref_div;
 947
 948         if (fb_div > fb_div_max) {
 949                 ref_div = ref_div * fb_div_max / fb_div;
 950                 fb_div = fb_div_max;
 951         }
 952
 953         if (ref_div > ref_div_max) {
 954                 ref_div = ref_div_max;
 955                 fb_div = nom * ref_div_max / tmp;
 956         }
 957
 958         /* reduce the numbers to a simpler ratio once more */
 959         /* this also makes sure that the reference divider is large enough */
 960         avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
 961
 962         /* and finally save the result */
 963         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 964                 *fb_div_p = fb_div / 10;
 965                 *frac_fb_div_p = fb_div % 10;
 966         } else {
 967                 *fb_div_p = fb_div;
 968                 *frac_fb_div_p = 0;
 969         }
 970
 971         *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
 972                         (pll->reference_freq * *frac_fb_div_p)) /
 973                        (ref_div * post_div * 10);
 974         *ref_div_p = ref_div;
 975         *post_div_p = post_div;
 976
 977         DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
 978                       freq, *dot_clock_p, *fb_div_p, *frac_fb_div_p,
 979                       ref_div, post_div);
 980 }
 981
 982 /* pre-avivo */
 983 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
 984 {
 985         uint64_t mod;
 986
 987         n += d / 2;
 988
 989         mod = do_div(n, d);
 990         return n;
 991 }
 992
 993 void radeon_compute_pll_legacy(struct radeon_pll *pll,
 994                                uint64_t freq,
 995                                uint32_t *dot_clock_p,
 996                                uint32_t *fb_div_p,
 997                                uint32_t *frac_fb_div_p,
 998                                uint32_t *ref_div_p,
 999                                uint32_t *post_div_p)
1000 {
1001         uint32_t min_ref_div = pll->min_ref_div;
1002         uint32_t max_ref_div = pll->max_ref_div;
1003         uint32_t min_post_div = pll->min_post_div;
1004         uint32_t max_post_div = pll->max_post_div;
1005         uint32_t min_fractional_feed_div = 0;
1006         uint32_t max_fractional_feed_div = 0;
1007         uint32_t best_vco = pll->best_vco;
1008         uint32_t best_post_div = 1;
1009         uint32_t best_ref_div = 1;
1010         uint32_t best_feedback_div = 1;
1011         uint32_t best_frac_feedback_div = 0;
1012         uint32_t best_freq = -1;
1013         uint32_t best_error = 0xffffffff;
1014         uint32_t best_vco_diff = 1;
1015         uint32_t post_div;
1016         u32 pll_out_min, pll_out_max;
1017
1018         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1019         freq = freq * 1000;
1020
1021         if (pll->flags & RADEON_PLL_IS_LCD) {
1022                 pll_out_min = pll->lcd_pll_out_min;
1023                 pll_out_max = pll->lcd_pll_out_max;
1024         } else {
1025                 pll_out_min = pll->pll_out_min;
1026                 pll_out_max = pll->pll_out_max;
1027         }
1028
1029         if (pll_out_min > 64800)
1030                 pll_out_min = 64800;
1031
1032         if (pll->flags & RADEON_PLL_USE_REF_DIV)
1033                 min_ref_div = max_ref_div = pll->reference_div;
1034         else {
1035                 while (min_ref_div < max_ref_div-1) {
1036                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
1037                         uint32_t pll_in = pll->reference_freq / mid;
1038                         if (pll_in < pll->pll_in_min)
1039                                 max_ref_div = mid;
1040                         else if (pll_in > pll->pll_in_max)
1041                                 min_ref_div = mid;
1042                         else
1043                                 break;
1044                 }
1045         }
1046
1047         if (pll->flags & RADEON_PLL_USE_POST_DIV)
1048                 min_post_div = max_post_div = pll->post_div;
1049
1050         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1051                 min_fractional_feed_div = pll->min_frac_feedback_div;
1052                 max_fractional_feed_div = pll->max_frac_feedback_div;
1053         }
1054
1055         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1056                 uint32_t ref_div;
1057
1058                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1059                         continue;
1060
1061                 /* legacy radeons only have a few post_divs */
1062                 if (pll->flags & RADEON_PLL_LEGACY) {
1063                         if ((post_div == 5) ||
1064                             (post_div == 7) ||
1065                             (post_div == 9) ||
1066                             (post_div == 10) ||
1067                             (post_div == 11) ||
1068                             (post_div == 13) ||
1069                             (post_div == 14) ||
1070                             (post_div == 15))
1071                                 continue;
1072                 }
1073
1074                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1075                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
1076                         uint32_t pll_in = pll->reference_freq / ref_div;
1077                         uint32_t min_feed_div = pll->min_feedback_div;
1078                         uint32_t max_feed_div = pll->max_feedback_div + 1;
1079
1080                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1081                                 continue;
1082
1083                         while (min_feed_div < max_feed_div) {
1084                                 uint32_t vco;
1085                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
1086                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1087                                 uint32_t frac_feedback_div;
1088                                 uint64_t tmp;
1089
1090                                 feedback_div = (min_feed_div + max_feed_div) / 2;
1091
1092                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
1093                                 vco = radeon_div(tmp, ref_div);
1094
1095                                 if (vco < pll_out_min) {
1096                                         min_feed_div = feedback_div + 1;
1097                                         continue;
1098                                 } else if (vco > pll_out_max) {
1099                                         max_feed_div = feedback_div;
1100                                         continue;
1101                                 }
1102
1103                                 while (min_frac_feed_div < max_frac_feed_div) {
1104                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1105                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1106                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1107                                         current_freq = radeon_div(tmp, ref_div * post_div);
1108
1109                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1110                                                 if (freq < current_freq)
1111                                                         error = 0xffffffff;
1112                                                 else
1113                                                         error = freq - current_freq;
1114                                         } else
1115                                                 error = abs(current_freq - freq);
1116                                         vco_diff = abs(vco - best_vco);
1117
1118                                         if ((best_vco == 0 && error < best_error) ||
1119                                             (best_vco != 0 &&
1120                                              ((best_error > 100 && error < best_error - 100) ||
1121                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1122                                                 best_post_div = post_div;
1123                                                 best_ref_div = ref_div;
1124                                                 best_feedback_div = feedback_div;
1125                                                 best_frac_feedback_div = frac_feedback_div;
1126                                                 best_freq = current_freq;
1127                                                 best_error = error;
1128                                                 best_vco_diff = vco_diff;
1129                                         } else if (current_freq == freq) {
1130                                                 if (best_freq == -1) {
1131                                                         best_post_div = post_div;
1132                                                         best_ref_div = ref_div;
1133                                                         best_feedback_div = feedback_div;
1134                                                         best_frac_feedback_div = frac_feedback_div;
1135                                                         best_freq = current_freq;
1136                                                         best_error = error;
1137                                                         best_vco_diff = vco_diff;
1138                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1139                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1140                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1141                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1142                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1143                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1144                                                         best_post_div = post_div;
1145                                                         best_ref_div = ref_div;
1146                                                         best_feedback_div = feedback_div;
1147                                                         best_frac_feedback_div = frac_feedback_div;
1148                                                         best_freq = current_freq;
1149                                                         best_error = error;
1150                                                         best_vco_diff = vco_diff;
1151                                                 }
1152                                         }
1153                                         if (current_freq < freq)
1154                                                 min_frac_feed_div = frac_feedback_div + 1;
1155                                         else
1156                                                 max_frac_feed_div = frac_feedback_div;
1157                                 }
1158                                 if (current_freq < freq)
1159                                         min_feed_div = feedback_div + 1;
1160                                 else
1161                                         max_feed_div = feedback_div;
1162                         }
1163                 }
1164         }
1165
1166         *dot_clock_p = best_freq / 10000;
1167         *fb_div_p = best_feedback_div;
1168         *frac_fb_div_p = best_frac_feedback_div;
1169         *ref_div_p = best_ref_div;
1170         *post_div_p = best_post_div;
1171         DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1172                       (long long)freq,
1173                       best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1174                       best_ref_div, best_post_div);
1175
1176 }
1177
1178 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1179 {
1180         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1181
1182         if (radeon_fb->obj) {
1183                 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1184         }
1185         drm_framebuffer_cleanup(fb);
1186         kfree(radeon_fb);
1187 }
1188
1189 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1190                                                   struct drm_file *file_priv,
1191                                                   unsigned int *handle)
1192 {
1193         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1194
1195         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1196 }
1197
1198 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1199         .destroy = radeon_user_framebuffer_destroy,
1200         .create_handle = radeon_user_framebuffer_create_handle,
1201 };
1202
1203 int
1204 radeon_framebuffer_init(struct drm_device *dev,
1205                         struct radeon_framebuffer *rfb,
1206                         struct drm_mode_fb_cmd2 *mode_cmd,
1207                         struct drm_gem_object *obj)
1208 {
1209         int ret;
1210         rfb->obj = obj;
1211         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1212         ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1213         if (ret) {
1214                 rfb->obj = NULL;
1215                 return ret;
1216         }
1217         return 0;
1218 }
1219
1220 static struct drm_framebuffer *
1221 radeon_user_framebuffer_create(struct drm_device *dev,
1222                                struct drm_file *file_priv,
1223                                struct drm_mode_fb_cmd2 *mode_cmd)
1224 {
1225         struct drm_gem_object *obj;
1226         struct radeon_framebuffer *radeon_fb;
1227         int ret;
1228
1229         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1230         if (obj ==  NULL) {
1231                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1232                         "can't create framebuffer\n", mode_cmd->handles[0]);
1233                 return ERR_PTR(-ENOENT);
1234         }
1235
1236         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1237         if (radeon_fb == NULL) {
1238                 drm_gem_object_unreference_unlocked(obj);
1239                 return ERR_PTR(-ENOMEM);
1240         }
1241
1242         ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1243         if (ret) {
1244                 kfree(radeon_fb);
1245                 drm_gem_object_unreference_unlocked(obj);
1246                 return ERR_PTR(ret);
1247         }
1248
1249         return &radeon_fb->base;
1250 }
1251
1252 static void radeon_output_poll_changed(struct drm_device *dev)
1253 {
1254         struct radeon_device *rdev = dev->dev_private;
1255         radeon_fb_output_poll_changed(rdev);
1256 }
1257
1258 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1259         .fb_create = radeon_user_framebuffer_create,
1260         .output_poll_changed = radeon_output_poll_changed
1261 };
1262
1263 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1264 {       { 0, "driver" },
1265         { 1, "bios" },
1266 };
1267
1268 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1269 {       { TV_STD_NTSC, "ntsc" },
1270         { TV_STD_PAL, "pal" },
1271         { TV_STD_PAL_M, "pal-m" },
1272         { TV_STD_PAL_60, "pal-60" },
1273         { TV_STD_NTSC_J, "ntsc-j" },
1274         { TV_STD_SCART_PAL, "scart-pal" },
1275         { TV_STD_PAL_CN, "pal-cn" },
1276         { TV_STD_SECAM, "secam" },
1277 };
1278
1279 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1280 {       { UNDERSCAN_OFF, "off" },
1281         { UNDERSCAN_ON, "on" },
1282         { UNDERSCAN_AUTO, "auto" },
1283 };
1284
1285 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1286 {       { RADEON_AUDIO_DISABLE, "off" },
1287         { RADEON_AUDIO_ENABLE, "on" },
1288         { RADEON_AUDIO_AUTO, "auto" },
1289 };
1290
1291 /* XXX support different dither options? spatial, temporal, both, etc. */
1292 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1293 {       { RADEON_FMT_DITHER_DISABLE, "off" },
1294         { RADEON_FMT_DITHER_ENABLE, "on" },
1295 };
1296
1297 static int radeon_modeset_create_props(struct radeon_device *rdev)
1298 {
1299         int sz;
1300
1301         if (rdev->is_atom_bios) {
1302                 rdev->mode_info.coherent_mode_property =
1303                         drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1304                 if (!rdev->mode_info.coherent_mode_property)
1305                         return -ENOMEM;
1306         }
1307
1308         if (!ASIC_IS_AVIVO(rdev)) {
1309                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1310                 rdev->mode_info.tmds_pll_property =
1311                         drm_property_create_enum(rdev->ddev, 0,
1312                                             "tmds_pll",
1313                                             radeon_tmds_pll_enum_list, sz);
1314         }
1315
1316         rdev->mode_info.load_detect_property =
1317                 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1318         if (!rdev->mode_info.load_detect_property)
1319                 return -ENOMEM;
1320
1321         drm_mode_create_scaling_mode_property(rdev->ddev);
1322
1323         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1324         rdev->mode_info.tv_std_property =
1325                 drm_property_create_enum(rdev->ddev, 0,
1326                                     "tv standard",
1327                                     radeon_tv_std_enum_list, sz);
1328
1329         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1330         rdev->mode_info.underscan_property =
1331                 drm_property_create_enum(rdev->ddev, 0,
1332                                     "underscan",
1333                                     radeon_underscan_enum_list, sz);
1334
1335         rdev->mode_info.underscan_hborder_property =
1336                 drm_property_create_range(rdev->ddev, 0,
1337                                         "underscan hborder", 0, 128);
1338         if (!rdev->mode_info.underscan_hborder_property)
1339                 return -ENOMEM;
1340
1341         rdev->mode_info.underscan_vborder_property =
1342                 drm_property_create_range(rdev->ddev, 0,
1343                                         "underscan vborder", 0, 128);
1344         if (!rdev->mode_info.underscan_vborder_property)
1345                 return -ENOMEM;
1346
1347         sz = ARRAY_SIZE(radeon_audio_enum_list);
1348         rdev->mode_info.audio_property =
1349                 drm_property_create_enum(rdev->ddev, 0,
1350                                          "audio",
1351                                          radeon_audio_enum_list, sz);
1352
1353         sz = ARRAY_SIZE(radeon_dither_enum_list);
1354         rdev->mode_info.dither_property =
1355                 drm_property_create_enum(rdev->ddev, 0,
1356                                          "dither",
1357                                          radeon_dither_enum_list, sz);
1358
1359         return 0;
1360 }
1361
1362 void radeon_update_display_priority(struct radeon_device *rdev)
1363 {
1364         /* adjustment options for the display watermarks */
1365         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1366                 /* set display priority to high for r3xx, rv515 chips
1367                  * this avoids flickering due to underflow to the
1368                  * display controllers during heavy acceleration.
1369                  * Don't force high on rs4xx igp chips as it seems to
1370                  * affect the sound card.  See kernel bug 15982.
1371                  */
1372                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1373                     !(rdev->flags & RADEON_IS_IGP))
1374                         rdev->disp_priority = 2;
1375                 else
1376                         rdev->disp_priority = 0;
1377         } else
1378                 rdev->disp_priority = radeon_disp_priority;
1379
1380 }
1381
1382 /*
1383  * Allocate hdmi structs and determine register offsets
1384  */
1385 static void radeon_afmt_init(struct radeon_device *rdev)
1386 {
1387         int i;
1388
1389         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1390                 rdev->mode_info.afmt[i] = NULL;
1391
1392         if (ASIC_IS_NODCE(rdev)) {
1393                 /* nothing to do */
1394         } else if (ASIC_IS_DCE4(rdev)) {
1395                 static uint32_t eg_offsets[] = {
1396                         EVERGREEN_CRTC0_REGISTER_OFFSET,
1397                         EVERGREEN_CRTC1_REGISTER_OFFSET,
1398                         EVERGREEN_CRTC2_REGISTER_OFFSET,
1399                         EVERGREEN_CRTC3_REGISTER_OFFSET,
1400                         EVERGREEN_CRTC4_REGISTER_OFFSET,
1401                         EVERGREEN_CRTC5_REGISTER_OFFSET,
1402                         0x13830 - 0x7030,
1403                 };
1404                 int num_afmt;
1405
1406                 /* DCE8 has 7 audio blocks tied to DIG encoders */
1407                 /* DCE6 has 6 audio blocks tied to DIG encoders */
1408                 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1409                 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1410                 if (ASIC_IS_DCE8(rdev))
1411                         num_afmt = 7;
1412                 else if (ASIC_IS_DCE6(rdev))
1413                         num_afmt = 6;
1414                 else if (ASIC_IS_DCE5(rdev))
1415                         num_afmt = 6;
1416                 else if (ASIC_IS_DCE41(rdev))
1417                         num_afmt = 2;
1418                 else /* DCE4 */
1419                         num_afmt = 6;
1420
1421                 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1422                 for (i = 0; i < num_afmt; i++) {
1423                         rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1424                         if (rdev->mode_info.afmt[i]) {
1425                                 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1426                                 rdev->mode_info.afmt[i]->id = i;
1427                         }
1428                 }
1429         } else if (ASIC_IS_DCE3(rdev)) {
1430                 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1431                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1432                 if (rdev->mode_info.afmt[0]) {
1433                         rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1434                         rdev->mode_info.afmt[0]->id = 0;
1435                 }
1436                 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1437                 if (rdev->mode_info.afmt[1]) {
1438                         rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1439                         rdev->mode_info.afmt[1]->id = 1;
1440                 }
1441         } else if (ASIC_IS_DCE2(rdev)) {
1442                 /* DCE2 has at least 1 routable audio block */
1443                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1444                 if (rdev->mode_info.afmt[0]) {
1445                         rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1446                         rdev->mode_info.afmt[0]->id = 0;
1447                 }
1448                 /* r6xx has 2 routable audio blocks */
1449                 if (rdev->family >= CHIP_R600) {
1450                         rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1451                         if (rdev->mode_info.afmt[1]) {
1452                                 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1453                                 rdev->mode_info.afmt[1]->id = 1;
1454                         }
1455                 }
1456         }
1457 }
1458
1459 static void radeon_afmt_fini(struct radeon_device *rdev)
1460 {
1461         int i;
1462
1463         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1464                 kfree(rdev->mode_info.afmt[i]);
1465                 rdev->mode_info.afmt[i] = NULL;
1466         }
1467 }
1468
1469 int radeon_modeset_init(struct radeon_device *rdev)
1470 {
1471         int i;
1472         int ret;
1473
1474         drm_mode_config_init(rdev->ddev);
1475         rdev->mode_info.mode_config_initialized = true;
1476
1477         rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1478
1479         if (ASIC_IS_DCE5(rdev)) {
1480                 rdev->ddev->mode_config.max_width = 16384;
1481                 rdev->ddev->mode_config.max_height = 16384;
1482         } else if (ASIC_IS_AVIVO(rdev)) {
1483                 rdev->ddev->mode_config.max_width = 8192;
1484                 rdev->ddev->mode_config.max_height = 8192;
1485         } else {
1486                 rdev->ddev->mode_config.max_width = 4096;
1487                 rdev->ddev->mode_config.max_height = 4096;
1488         }
1489
1490         rdev->ddev->mode_config.preferred_depth = 24;
1491         rdev->ddev->mode_config.prefer_shadow = 1;
1492
1493         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1494
1495         ret = radeon_modeset_create_props(rdev);
1496         if (ret) {
1497                 return ret;
1498         }
1499
1500         /* init i2c buses */
1501         radeon_i2c_init(rdev);
1502
1503         /* check combios for a valid hardcoded EDID - Sun servers */
1504         if (!rdev->is_atom_bios) {
1505                 /* check for hardcoded EDID in BIOS */
1506                 radeon_combios_check_hardcoded_edid(rdev);
1507         }
1508
1509         /* allocate crtcs */
1510         for (i = 0; i < rdev->num_crtc; i++) {
1511                 radeon_crtc_init(rdev->ddev, i);
1512         }
1513
1514         /* okay we should have all the bios connectors */
1515         ret = radeon_setup_enc_conn(rdev->ddev);
1516         if (!ret) {
1517                 return ret;
1518         }
1519
1520         /* init dig PHYs, disp eng pll */
1521         if (rdev->is_atom_bios) {
1522                 radeon_atom_encoder_init(rdev);
1523                 radeon_atom_disp_eng_pll_init(rdev);
1524         }
1525
1526         /* initialize hpd */
1527         radeon_hpd_init(rdev);
1528
1529         /* setup afmt */
1530         radeon_afmt_init(rdev);
1531
1532         radeon_fbdev_init(rdev);
1533         drm_kms_helper_poll_init(rdev->ddev);
1534
1535         if (rdev->pm.dpm_enabled) {
1536                 /* do dpm late init */
1537                 ret = radeon_pm_late_init(rdev);
1538                 if (ret) {
1539                         rdev->pm.dpm_enabled = false;
1540                         DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1541                 }
1542                 /* set the dpm state for PX since there won't be
1543                  * a modeset to call this.
1544                  */
1545                 radeon_pm_compute_clocks(rdev);
1546         }
1547
1548         return 0;
1549 }
1550
1551 void radeon_modeset_fini(struct radeon_device *rdev)
1552 {
1553         radeon_fbdev_fini(rdev);
1554         kfree(rdev->mode_info.bios_hardcoded_edid);
1555
1556         if (rdev->mode_info.mode_config_initialized) {
1557                 radeon_afmt_fini(rdev);
1558                 drm_kms_helper_poll_fini(rdev->ddev);
1559                 radeon_hpd_fini(rdev);
1560                 drm_mode_config_cleanup(rdev->ddev);
1561                 rdev->mode_info.mode_config_initialized = false;
1562         }
1563         /* free i2c buses */
1564         radeon_i2c_fini(rdev);
1565 }
1566
1567 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1568 {
1569         /* try and guess if this is a tv or a monitor */
1570         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1571             (mode->vdisplay == 576) || /* 576p */
1572             (mode->vdisplay == 720) || /* 720p */
1573             (mode->vdisplay == 1080)) /* 1080p */
1574                 return true;
1575         else
1576                 return false;
1577 }
1578
1579 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1580                                 const struct drm_display_mode *mode,
1581                                 struct drm_display_mode *adjusted_mode)
1582 {
1583         struct drm_device *dev = crtc->dev;
1584         struct radeon_device *rdev = dev->dev_private;
1585         struct drm_encoder *encoder;
1586         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1587         struct radeon_encoder *radeon_encoder;
1588         struct drm_connector *connector;
1589         struct radeon_connector *radeon_connector;
1590         bool first = true;
1591         u32 src_v = 1, dst_v = 1;
1592         u32 src_h = 1, dst_h = 1;
1593
1594         radeon_crtc->h_border = 0;
1595         radeon_crtc->v_border = 0;
1596
1597         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1598                 if (encoder->crtc != crtc)
1599                         continue;
1600                 radeon_encoder = to_radeon_encoder(encoder);
1601                 connector = radeon_get_connector_for_encoder(encoder);
1602                 radeon_connector = to_radeon_connector(connector);
1603
1604                 if (first) {
1605                         /* set scaling */
1606                         if (radeon_encoder->rmx_type == RMX_OFF)
1607                                 radeon_crtc->rmx_type = RMX_OFF;
1608                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1609                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1610                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1611                         else
1612                                 radeon_crtc->rmx_type = RMX_OFF;
1613                         /* copy native mode */
1614                         memcpy(&radeon_crtc->native_mode,
1615                                &radeon_encoder->native_mode,
1616                                 sizeof(struct drm_display_mode));
1617                         src_v = crtc->mode.vdisplay;
1618                         dst_v = radeon_crtc->native_mode.vdisplay;
1619                         src_h = crtc->mode.hdisplay;
1620                         dst_h = radeon_crtc->native_mode.hdisplay;
1621
1622                         /* fix up for overscan on hdmi */
1623                         if (ASIC_IS_AVIVO(rdev) &&
1624                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1625                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1626                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1627                               drm_detect_hdmi_monitor(radeon_connector->edid) &&
1628                               is_hdtv_mode(mode)))) {
1629                                 if (radeon_encoder->underscan_hborder != 0)
1630                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1631                                 else
1632                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1633                                 if (radeon_encoder->underscan_vborder != 0)
1634                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1635                                 else
1636                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1637                                 radeon_crtc->rmx_type = RMX_FULL;
1638                                 src_v = crtc->mode.vdisplay;
1639                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1640                                 src_h = crtc->mode.hdisplay;
1641                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1642                         }
1643                         first = false;
1644                 } else {
1645                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1646                                 /* WARNING: Right now this can't happen but
1647                                  * in the future we need to check that scaling
1648                                  * are consistent across different encoder
1649                                  * (ie all encoder can work with the same
1650                                  *  scaling).
1651                                  */
1652                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1653                                 return false;
1654                         }
1655                 }
1656         }
1657         if (radeon_crtc->rmx_type != RMX_OFF) {
1658                 fixed20_12 a, b;
1659                 a.full = dfixed_const(src_v);
1660                 b.full = dfixed_const(dst_v);
1661                 radeon_crtc->vsc.full = dfixed_div(a, b);
1662                 a.full = dfixed_const(src_h);
1663                 b.full = dfixed_const(dst_h);
1664                 radeon_crtc->hsc.full = dfixed_div(a, b);
1665         } else {
1666                 radeon_crtc->vsc.full = dfixed_const(1);
1667                 radeon_crtc->hsc.full = dfixed_const(1);
1668         }
1669         return true;
1670 }
1671
1672 /*
1673  * Retrieve current video scanout position of crtc on a given gpu, and
1674  * an optional accurate timestamp of when query happened.
1675  *
1676  * \param dev Device to query.
1677  * \param crtc Crtc to query.
1678  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1679  * \param *vpos Location where vertical scanout position should be stored.
1680  * \param *hpos Location where horizontal scanout position should go.
1681  * \param *stime Target location for timestamp taken immediately before
1682  *               scanout position query. Can be NULL to skip timestamp.
1683  * \param *etime Target location for timestamp taken immediately after
1684  *               scanout position query. Can be NULL to skip timestamp.
1685  *
1686  * Returns vpos as a positive number while in active scanout area.
1687  * Returns vpos as a negative number inside vblank, counting the number
1688  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1689  * until start of active scanout / end of vblank."
1690  *
1691  * \return Flags, or'ed together as follows:
1692  *
1693  * DRM_SCANOUTPOS_VALID = Query successful.
1694  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1695  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1696  * this flag means that returned position may be offset by a constant but
1697  * unknown small number of scanlines wrt. real scanout position.
1698  *
1699  */
1700 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
1701                                int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
1702 {
1703         u32 stat_crtc = 0, vbl = 0, position = 0;
1704         int vbl_start, vbl_end, vtotal, ret = 0;
1705         bool in_vbl = true;
1706
1707         struct radeon_device *rdev = dev->dev_private;
1708
1709         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1710
1711         /* Get optional system timestamp before query. */
1712         if (stime)
1713                 *stime = ktime_get();
1714
1715         if (ASIC_IS_DCE4(rdev)) {
1716                 if (crtc == 0) {
1717                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1718                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1719                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1720                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1721                         ret |= DRM_SCANOUTPOS_VALID;
1722                 }
1723                 if (crtc == 1) {
1724                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1725                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1726                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1727                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1728                         ret |= DRM_SCANOUTPOS_VALID;
1729                 }
1730                 if (crtc == 2) {
1731                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1732                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1733                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1734                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1735                         ret |= DRM_SCANOUTPOS_VALID;
1736                 }
1737                 if (crtc == 3) {
1738                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1739                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1740                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1741                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1742                         ret |= DRM_SCANOUTPOS_VALID;
1743                 }
1744                 if (crtc == 4) {
1745                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1746                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1747                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1748                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1749                         ret |= DRM_SCANOUTPOS_VALID;
1750                 }
1751                 if (crtc == 5) {
1752                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1753                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1754                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1755                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1756                         ret |= DRM_SCANOUTPOS_VALID;
1757                 }
1758         } else if (ASIC_IS_AVIVO(rdev)) {
1759                 if (crtc == 0) {
1760                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1761                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1762                         ret |= DRM_SCANOUTPOS_VALID;
1763                 }
1764                 if (crtc == 1) {
1765                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1766                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1767                         ret |= DRM_SCANOUTPOS_VALID;
1768                 }
1769         } else {
1770                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1771                 if (crtc == 0) {
1772                         /* Assume vbl_end == 0, get vbl_start from
1773                          * upper 16 bits.
1774                          */
1775                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1776                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1777                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1778                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1779                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1780                         if (!(stat_crtc & 1))
1781                                 in_vbl = false;
1782
1783                         ret |= DRM_SCANOUTPOS_VALID;
1784                 }
1785                 if (crtc == 1) {
1786                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1787                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1788                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1789                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1790                         if (!(stat_crtc & 1))
1791                                 in_vbl = false;
1792
1793                         ret |= DRM_SCANOUTPOS_VALID;
1794                 }
1795         }
1796
1797         /* Get optional system timestamp after query. */
1798         if (etime)
1799                 *etime = ktime_get();
1800
1801         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1802
1803         /* Decode into vertical and horizontal scanout position. */
1804         *vpos = position & 0x1fff;
1805         *hpos = (position >> 16) & 0x1fff;
1806
1807         /* Valid vblank area boundaries from gpu retrieved? */
1808         if (vbl > 0) {
1809                 /* Yes: Decode. */
1810                 ret |= DRM_SCANOUTPOS_ACCURATE;
1811                 vbl_start = vbl & 0x1fff;
1812                 vbl_end = (vbl >> 16) & 0x1fff;
1813         }
1814         else {
1815                 /* No: Fake something reasonable which gives at least ok results. */
1816                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1817                 vbl_end = 0;
1818         }
1819
1820         /* Test scanout position against vblank region. */
1821         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1822                 in_vbl = false;
1823
1824         /* Check if inside vblank area and apply corrective offsets:
1825          * vpos will then be >=0 in video scanout area, but negative
1826          * within vblank area, counting down the number of lines until
1827          * start of scanout.
1828          */
1829
1830         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1831         if (in_vbl && (*vpos >= vbl_start)) {
1832                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1833                 *vpos = *vpos - vtotal;
1834         }
1835
1836         /* Correct for shifted end of vbl at vbl_end. */
1837         *vpos = *vpos - vbl_end;
1838
1839         /* In vblank? */
1840         if (in_vbl)
1841                 ret |= DRM_SCANOUTPOS_INVBL;
1842
1843         /* Is vpos outside nominal vblank area, but less than
1844          * 1/100 of a frame height away from start of vblank?
1845          * If so, assume this isn't a massively delayed vblank
1846          * interrupt, but a vblank interrupt that fired a few
1847          * microseconds before true start of vblank. Compensate
1848          * by adding a full frame duration to the final timestamp.
1849          * Happens, e.g., on ATI R500, R600.
1850          *
1851          * We only do this if DRM_CALLED_FROM_VBLIRQ.
1852          */
1853         if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1854                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1855                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1856
1857                 if (vbl_start - *vpos < vtotal / 100) {
1858                         *vpos -= vtotal;
1859
1860                         /* Signal this correction as "applied". */
1861                         ret |= 0x8;
1862                 }
1863         }
1864
1865         return ret;
1866 }