drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/platform_device.h>
  32 #include "drmP.h"
  33 #include "radeon_drm.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "radeon_mode.h"
  37 #include "r600d.h"
  38 #include "atom.h"
  39 #include "avivod.h"
  40
  41 #define PFP_UCODE_SIZE 576
  42 #define PM4_UCODE_SIZE 1792
  43 #define RLC_UCODE_SIZE 768
  44 #define R700_PFP_UCODE_SIZE 848
  45 #define R700_PM4_UCODE_SIZE 1360
  46 #define R700_RLC_UCODE_SIZE 1024
  47 #define EVERGREEN_PFP_UCODE_SIZE 1120
  48 #define EVERGREEN_PM4_UCODE_SIZE 1376
  49 #define EVERGREEN_RLC_UCODE_SIZE 768
  50
  51 /* Firmware Names */
  52 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  53 MODULE_FIRMWARE("radeon/R600_me.bin");
  54 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  55 MODULE_FIRMWARE("radeon/RV610_me.bin");
  56 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  57 MODULE_FIRMWARE("radeon/RV630_me.bin");
  58 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  59 MODULE_FIRMWARE("radeon/RV620_me.bin");
  60 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  61 MODULE_FIRMWARE("radeon/RV635_me.bin");
  62 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  63 MODULE_FIRMWARE("radeon/RV670_me.bin");
  64 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  65 MODULE_FIRMWARE("radeon/RS780_me.bin");
  66 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  67 MODULE_FIRMWARE("radeon/RV770_me.bin");
  68 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  69 MODULE_FIRMWARE("radeon/RV730_me.bin");
  70 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  71 MODULE_FIRMWARE("radeon/RV710_me.bin");
  72 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  73 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  74 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  75 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  76 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  77 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  78 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  79 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  80 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  81 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  82 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  83 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  84 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  85 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  86
  87 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  88
  89 /* r600,rv610,rv630,rv620,rv635,rv670 */
  90 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  91 void r600_gpu_init(struct radeon_device *rdev);
  92 void r600_fini(struct radeon_device *rdev);
  93 void r600_irq_disable(struct radeon_device *rdev);
  94
  95 /* get temperature in millidegrees */
  96 u32 rv6xx_get_temp(struct radeon_device *rdev)
  97 {
  98         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
  99                 ASIC_T_SHIFT;
 100         u32 actual_temp = 0;
 101
 102         if ((temp >> 7) & 1)
 103                 actual_temp = 0;
 104         else
 105                 actual_temp = (temp >> 1) & 0xff;
 106
 107         return actual_temp * 1000;
 108 }
 109
 110 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 111 {
 112         int i;
 113
 114         rdev->pm.dynpm_can_upclock = true;
 115         rdev->pm.dynpm_can_downclock = true;
 116
 117         /* power state array is low to high, default is first */
 118         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 119                 int min_power_state_index = 0;
 120
 121                 if (rdev->pm.num_power_states > 2)
 122                         min_power_state_index = 1;
 123
 124                 switch (rdev->pm.dynpm_planned_action) {
 125                 case DYNPM_ACTION_MINIMUM:
 126                         rdev->pm.requested_power_state_index = min_power_state_index;
 127                         rdev->pm.requested_clock_mode_index = 0;
 128                         rdev->pm.dynpm_can_downclock = false;
 129                         break;
 130                 case DYNPM_ACTION_DOWNCLOCK:
 131                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 132                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 133                                 rdev->pm.dynpm_can_downclock = false;
 134                         } else {
 135                                 if (rdev->pm.active_crtc_count > 1) {
 136                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 137                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 138                                                         continue;
 139                                                 else if (i >= rdev->pm.current_power_state_index) {
 140                                                         rdev->pm.requested_power_state_index =
 141                                                                 rdev->pm.current_power_state_index;
 142                                                         break;
 143                                                 } else {
 144                                                         rdev->pm.requested_power_state_index = i;
 145                                                         break;
 146                                                 }
 147                                         }
 148                                 } else {
 149                                         if (rdev->pm.current_power_state_index == 0)
 150                                                 rdev->pm.requested_power_state_index =
 151                                                         rdev->pm.num_power_states - 1;
 152                                         else
 153                                                 rdev->pm.requested_power_state_index =
 154                                                         rdev->pm.current_power_state_index - 1;
 155                                 }
 156                         }
 157                         rdev->pm.requested_clock_mode_index = 0;
 158                         /* don't use the power state if crtcs are active and no display flag is set */
 159                         if ((rdev->pm.active_crtc_count > 0) &&
 160                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 161                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 162                              RADEON_PM_MODE_NO_DISPLAY)) {
 163                                 rdev->pm.requested_power_state_index++;
 164                         }
 165                         break;
 166                 case DYNPM_ACTION_UPCLOCK:
 167                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 168                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 169                                 rdev->pm.dynpm_can_upclock = false;
 170                         } else {
 171                                 if (rdev->pm.active_crtc_count > 1) {
 172                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 173                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 174                                                         continue;
 175                                                 else if (i <= rdev->pm.current_power_state_index) {
 176                                                         rdev->pm.requested_power_state_index =
 177                                                                 rdev->pm.current_power_state_index;
 178                                                         break;
 179                                                 } else {
 180                                                         rdev->pm.requested_power_state_index = i;
 181                                                         break;
 182                                                 }
 183                                         }
 184                                 } else
 185                                         rdev->pm.requested_power_state_index =
 186                                                 rdev->pm.current_power_state_index + 1;
 187                         }
 188                         rdev->pm.requested_clock_mode_index = 0;
 189                         break;
 190                 case DYNPM_ACTION_DEFAULT:
 191                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 192                         rdev->pm.requested_clock_mode_index = 0;
 193                         rdev->pm.dynpm_can_upclock = false;
 194                         break;
 195                 case DYNPM_ACTION_NONE:
 196                 default:
 197                         DRM_ERROR("Requested mode for not defined action\n");
 198                         return;
 199                 }
 200         } else {
 201                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 202                 /* for now just select the first power state and switch between clock modes */
 203                 /* power state array is low to high, default is first (0) */
 204                 if (rdev->pm.active_crtc_count > 1) {
 205                         rdev->pm.requested_power_state_index = -1;
 206                         /* start at 1 as we don't want the default mode */
 207                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 208                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 209                                         continue;
 210                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 211                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 212                                         rdev->pm.requested_power_state_index = i;
 213                                         break;
 214                                 }
 215                         }
 216                         /* if nothing selected, grab the default state. */
 217                         if (rdev->pm.requested_power_state_index == -1)
 218                                 rdev->pm.requested_power_state_index = 0;
 219                 } else
 220                         rdev->pm.requested_power_state_index = 1;
 221
 222                 switch (rdev->pm.dynpm_planned_action) {
 223                 case DYNPM_ACTION_MINIMUM:
 224                         rdev->pm.requested_clock_mode_index = 0;
 225                         rdev->pm.dynpm_can_downclock = false;
 226                         break;
 227                 case DYNPM_ACTION_DOWNCLOCK:
 228                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 229                                 if (rdev->pm.current_clock_mode_index == 0) {
 230                                         rdev->pm.requested_clock_mode_index = 0;
 231                                         rdev->pm.dynpm_can_downclock = false;
 232                                 } else
 233                                         rdev->pm.requested_clock_mode_index =
 234                                                 rdev->pm.current_clock_mode_index - 1;
 235                         } else {
 236                                 rdev->pm.requested_clock_mode_index = 0;
 237                                 rdev->pm.dynpm_can_downclock = false;
 238                         }
 239                         /* don't use the power state if crtcs are active and no display flag is set */
 240                         if ((rdev->pm.active_crtc_count > 0) &&
 241                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 242                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 243                              RADEON_PM_MODE_NO_DISPLAY)) {
 244                                 rdev->pm.requested_clock_mode_index++;
 245                         }
 246                         break;
 247                 case DYNPM_ACTION_UPCLOCK:
 248                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 249                                 if (rdev->pm.current_clock_mode_index ==
 250                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 251                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 252                                         rdev->pm.dynpm_can_upclock = false;
 253                                 } else
 254                                         rdev->pm.requested_clock_mode_index =
 255                                                 rdev->pm.current_clock_mode_index + 1;
 256                         } else {
 257                                 rdev->pm.requested_clock_mode_index =
 258                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 259                                 rdev->pm.dynpm_can_upclock = false;
 260                         }
 261                         break;
 262                 case DYNPM_ACTION_DEFAULT:
 263                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 264                         rdev->pm.requested_clock_mode_index = 0;
 265                         rdev->pm.dynpm_can_upclock = false;
 266                         break;
 267                 case DYNPM_ACTION_NONE:
 268                 default:
 269                         DRM_ERROR("Requested mode for not defined action\n");
 270                         return;
 271                 }
 272         }
 273
 274         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 275                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 276                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 277                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 278                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 279                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 280                   pcie_lanes);
 281 }
 282
 283 static int r600_pm_get_type_index(struct radeon_device *rdev,
 284                                   enum radeon_pm_state_type ps_type,
 285                                   int instance)
 286 {
 287         int i;
 288         int found_instance = -1;
 289
 290         for (i = 0; i < rdev->pm.num_power_states; i++) {
 291                 if (rdev->pm.power_state[i].type == ps_type) {
 292                         found_instance++;
 293                         if (found_instance == instance)
 294                                 return i;
 295                 }
 296         }
 297         /* return default if no match */
 298         return rdev->pm.default_power_state_index;
 299 }
 300
 301 void rs780_pm_init_profile(struct radeon_device *rdev)
 302 {
 303         if (rdev->pm.num_power_states == 2) {
 304                 /* default */
 305                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 306                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 307                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 308                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 309                 /* low sh */
 310                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 311                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 312                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 313                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 314                 /* mid sh */
 315                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 316                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 317                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 318                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 319                 /* high sh */
 320                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 321                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 322                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 323                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 324                 /* low mh */
 325                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 326                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 327                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 328                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 329                 /* mid mh */
 330                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 331                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 332                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 333                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 334                 /* high mh */
 335                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 336                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 337                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 338                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 339         } else if (rdev->pm.num_power_states == 3) {
 340                 /* default */
 341                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 342                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 343                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 344                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 345                 /* low sh */
 346                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 347                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 348                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 349                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 350                 /* mid sh */
 351                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 352                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 353                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 354                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 355                 /* high sh */
 356                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 357                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 358                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 359                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 360                 /* low mh */
 361                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 362                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 363                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 364                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 365                 /* mid mh */
 366                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 367                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 368                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 369                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 370                 /* high mh */
 371                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 372                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 373                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 374                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 375         } else {
 376                 /* default */
 377                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 378                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 379                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 380                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 381                 /* low sh */
 382                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 383                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 384                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 385                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 386                 /* mid sh */
 387                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 388                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 389                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 390                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 391                 /* high sh */
 392                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 393                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 394                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 395                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 396                 /* low mh */
 397                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 398                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 399                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 400                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 401                 /* mid mh */
 402                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 403                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 404                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 405                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 406                 /* high mh */
 407                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 408                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 409                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 410                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 411         }
 412 }
 413
 414 void r600_pm_init_profile(struct radeon_device *rdev)
 415 {
 416         if (rdev->family == CHIP_R600) {
 417                 /* XXX */
 418                 /* default */
 419                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 420                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 421                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 422                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 423                 /* low sh */
 424                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 425                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 426                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 427                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 428                 /* mid sh */
 429                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 430                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 431                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 432                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 433                 /* high sh */
 434                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 435                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 436                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 437                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 438                 /* low mh */
 439                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 440                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 441                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 442                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 443                 /* mid mh */
 444                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 445                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 446                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 447                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 448                 /* high mh */
 449                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 450                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 451                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 452                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 453         } else {
 454                 if (rdev->pm.num_power_states < 4) {
 455                         /* default */
 456                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 457                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 458                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 459                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 460                         /* low sh */
 461                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 462                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 463                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 464                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 465                         /* mid sh */
 466                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 467                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 468                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 469                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 470                         /* high sh */
 471                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 472                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 473                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 474                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 475                         /* low mh */
 476                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 477                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 478                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 479                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 480                         /* low mh */
 481                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 482                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 483                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 484                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 485                         /* high mh */
 486                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 487                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 488                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 489                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 490                 } else {
 491                         /* default */
 492                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 493                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 494                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 495                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 496                         /* low sh */
 497                         if (rdev->flags & RADEON_IS_MOBILITY) {
 498                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 499                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 500                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 501                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 502                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 503                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 504                         } else {
 505                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 506                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 507                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 508                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 509                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 510                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 511                         }
 512                         /* mid sh */
 513                         if (rdev->flags & RADEON_IS_MOBILITY) {
 514                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 515                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 516                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 517                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 518                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 519                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 520                         } else {
 521                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 522                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 523                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 524                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 525                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 526                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 527                         }
 528                         /* high sh */
 529                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
 530                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 531                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
 532                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 533                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 534                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 535                         /* low mh */
 536                         if (rdev->flags & RADEON_IS_MOBILITY) {
 537                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 538                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 539                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 540                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 541                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 542                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 543                         } else {
 544                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 545                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 546                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 547                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 548                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 549                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 550                         }
 551                         /* mid mh */
 552                         if (rdev->flags & RADEON_IS_MOBILITY) {
 553                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 554                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 555                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 556                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 557                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 558                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 559                         } else {
 560                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 561                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 562                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 563                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 564                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 565                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 566                         }
 567                         /* high mh */
 568                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
 569                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 570                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
 571                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 572                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 573                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 574                 }
 575         }
 576 }
 577
 578 void r600_pm_misc(struct radeon_device *rdev)
 579 {
 580         int req_ps_idx = rdev->pm.requested_power_state_index;
 581         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 582         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 583         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 584
 585         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 586                 if (voltage->voltage != rdev->pm.current_vddc) {
 587                         radeon_atom_set_voltage(rdev, voltage->voltage);
 588                         rdev->pm.current_vddc = voltage->voltage;
 589                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 590                 }
 591         }
 592 }
 593
 594 bool r600_gui_idle(struct radeon_device *rdev)
 595 {
 596         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 597                 return false;
 598         else
 599                 return true;
 600 }
 601
 602 /* hpd for digital panel detect/disconnect */
 603 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 604 {
 605         bool connected = false;
 606
 607         if (ASIC_IS_DCE3(rdev)) {
 608                 switch (hpd) {
 609                 case RADEON_HPD_1:
 610                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 611                                 connected = true;
 612                         break;
 613                 case RADEON_HPD_2:
 614                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 615                                 connected = true;
 616                         break;
 617                 case RADEON_HPD_3:
 618                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 619                                 connected = true;
 620                         break;
 621                 case RADEON_HPD_4:
 622                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 623                                 connected = true;
 624                         break;
 625                         /* DCE 3.2 */
 626                 case RADEON_HPD_5:
 627                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 628                                 connected = true;
 629                         break;
 630                 case RADEON_HPD_6:
 631                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 632                                 connected = true;
 633                         break;
 634                 default:
 635                         break;
 636                 }
 637         } else {
 638                 switch (hpd) {
 639                 case RADEON_HPD_1:
 640                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 641                                 connected = true;
 642                         break;
 643                 case RADEON_HPD_2:
 644                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 645                                 connected = true;
 646                         break;
 647                 case RADEON_HPD_3:
 648                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 649                                 connected = true;
 650                         break;
 651                 default:
 652                         break;
 653                 }
 654         }
 655         return connected;
 656 }
 657
 658 void r600_hpd_set_polarity(struct radeon_device *rdev,
 659                            enum radeon_hpd_id hpd)
 660 {
 661         u32 tmp;
 662         bool connected = r600_hpd_sense(rdev, hpd);
 663
 664         if (ASIC_IS_DCE3(rdev)) {
 665                 switch (hpd) {
 666                 case RADEON_HPD_1:
 667                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 668                         if (connected)
 669                                 tmp &= ~DC_HPDx_INT_POLARITY;
 670                         else
 671                                 tmp |= DC_HPDx_INT_POLARITY;
 672                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 673                         break;
 674                 case RADEON_HPD_2:
 675                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 676                         if (connected)
 677                                 tmp &= ~DC_HPDx_INT_POLARITY;
 678                         else
 679                                 tmp |= DC_HPDx_INT_POLARITY;
 680                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 681                         break;
 682                 case RADEON_HPD_3:
 683                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 684                         if (connected)
 685                                 tmp &= ~DC_HPDx_INT_POLARITY;
 686                         else
 687                                 tmp |= DC_HPDx_INT_POLARITY;
 688                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 689                         break;
 690                 case RADEON_HPD_4:
 691                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 692                         if (connected)
 693                                 tmp &= ~DC_HPDx_INT_POLARITY;
 694                         else
 695                                 tmp |= DC_HPDx_INT_POLARITY;
 696                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 697                         break;
 698                 case RADEON_HPD_5:
 699                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 700                         if (connected)
 701                                 tmp &= ~DC_HPDx_INT_POLARITY;
 702                         else
 703                                 tmp |= DC_HPDx_INT_POLARITY;
 704                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 705                         break;
 706                         /* DCE 3.2 */
 707                 case RADEON_HPD_6:
 708                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 709                         if (connected)
 710                                 tmp &= ~DC_HPDx_INT_POLARITY;
 711                         else
 712                                 tmp |= DC_HPDx_INT_POLARITY;
 713                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 714                         break;
 715                 default:
 716                         break;
 717                 }
 718         } else {
 719                 switch (hpd) {
 720                 case RADEON_HPD_1:
 721                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 722                         if (connected)
 723                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 724                         else
 725                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 726                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 727                         break;
 728                 case RADEON_HPD_2:
 729                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 730                         if (connected)
 731                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 732                         else
 733                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 734                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 735                         break;
 736                 case RADEON_HPD_3:
 737                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 738                         if (connected)
 739                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 740                         else
 741                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 742                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 743                         break;
 744                 default:
 745                         break;
 746                 }
 747         }
 748 }
 749
 750 void r600_hpd_init(struct radeon_device *rdev)
 751 {
 752         struct drm_device *dev = rdev->ddev;
 753         struct drm_connector *connector;
 754
 755         if (ASIC_IS_DCE3(rdev)) {
 756                 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 757                 if (ASIC_IS_DCE32(rdev))
 758                         tmp |= DC_HPDx_EN;
 759
 760                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 761                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 762                         switch (radeon_connector->hpd.hpd) {
 763                         case RADEON_HPD_1:
 764                                 WREG32(DC_HPD1_CONTROL, tmp);
 765                                 rdev->irq.hpd[0] = true;
 766                                 break;
 767                         case RADEON_HPD_2:
 768                                 WREG32(DC_HPD2_CONTROL, tmp);
 769                                 rdev->irq.hpd[1] = true;
 770                                 break;
 771                         case RADEON_HPD_3:
 772                                 WREG32(DC_HPD3_CONTROL, tmp);
 773                                 rdev->irq.hpd[2] = true;
 774                                 break;
 775                         case RADEON_HPD_4:
 776                                 WREG32(DC_HPD4_CONTROL, tmp);
 777                                 rdev->irq.hpd[3] = true;
 778                                 break;
 779                                 /* DCE 3.2 */
 780                         case RADEON_HPD_5:
 781                                 WREG32(DC_HPD5_CONTROL, tmp);
 782                                 rdev->irq.hpd[4] = true;
 783                                 break;
 784                         case RADEON_HPD_6:
 785                                 WREG32(DC_HPD6_CONTROL, tmp);
 786                                 rdev->irq.hpd[5] = true;
 787                                 break;
 788                         default:
 789                                 break;
 790                         }
 791                 }
 792         } else {
 793                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 794                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 795                         switch (radeon_connector->hpd.hpd) {
 796                         case RADEON_HPD_1:
 797                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 798                                 rdev->irq.hpd[0] = true;
 799                                 break;
 800                         case RADEON_HPD_2:
 801                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 802                                 rdev->irq.hpd[1] = true;
 803                                 break;
 804                         case RADEON_HPD_3:
 805                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 806                                 rdev->irq.hpd[2] = true;
 807                                 break;
 808                         default:
 809                                 break;
 810                         }
 811                 }
 812         }
 813         if (rdev->irq.installed)
 814                 r600_irq_set(rdev);
 815 }
 816
 817 void r600_hpd_fini(struct radeon_device *rdev)
 818 {
 819         struct drm_device *dev = rdev->ddev;
 820         struct drm_connector *connector;
 821
 822         if (ASIC_IS_DCE3(rdev)) {
 823                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 824                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 825                         switch (radeon_connector->hpd.hpd) {
 826                         case RADEON_HPD_1:
 827                                 WREG32(DC_HPD1_CONTROL, 0);
 828                                 rdev->irq.hpd[0] = false;
 829                                 break;
 830                         case RADEON_HPD_2:
 831                                 WREG32(DC_HPD2_CONTROL, 0);
 832                                 rdev->irq.hpd[1] = false;
 833                                 break;
 834                         case RADEON_HPD_3:
 835                                 WREG32(DC_HPD3_CONTROL, 0);
 836                                 rdev->irq.hpd[2] = false;
 837                                 break;
 838                         case RADEON_HPD_4:
 839                                 WREG32(DC_HPD4_CONTROL, 0);
 840                                 rdev->irq.hpd[3] = false;
 841                                 break;
 842                                 /* DCE 3.2 */
 843                         case RADEON_HPD_5:
 844                                 WREG32(DC_HPD5_CONTROL, 0);
 845                                 rdev->irq.hpd[4] = false;
 846                                 break;
 847                         case RADEON_HPD_6:
 848                                 WREG32(DC_HPD6_CONTROL, 0);
 849                                 rdev->irq.hpd[5] = false;
 850                                 break;
 851                         default:
 852                                 break;
 853                         }
 854                 }
 855         } else {
 856                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 857                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 858                         switch (radeon_connector->hpd.hpd) {
 859                         case RADEON_HPD_1:
 860                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 861                                 rdev->irq.hpd[0] = false;
 862                                 break;
 863                         case RADEON_HPD_2:
 864                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 865                                 rdev->irq.hpd[1] = false;
 866                                 break;
 867                         case RADEON_HPD_3:
 868                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 869                                 rdev->irq.hpd[2] = false;
 870                                 break;
 871                         default:
 872                                 break;
 873                         }
 874                 }
 875         }
 876 }
 877
 878 /*
 879  * R600 PCIE GART
 880  */
 881 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 882 {
 883         unsigned i;
 884         u32 tmp;
 885
 886         /* flush hdp cache so updates hit vram */
 887         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) {
 888                 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
 889                 u32 tmp;
 890
 891                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
 892                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
 893                  */
 894                 WREG32(HDP_DEBUG1, 0);
 895                 tmp = readl((void __iomem *)ptr);
 896         } else
 897                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 898
 899         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 900         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 901         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 902         for (i = 0; i < rdev->usec_timeout; i++) {
 903                 /* read MC_STATUS */
 904                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 905                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 906                 if (tmp == 2) {
 907                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 908                         return;
 909                 }
 910                 if (tmp) {
 911                         return;
 912                 }
 913                 udelay(1);
 914         }
 915 }
 916
 917 int r600_pcie_gart_init(struct radeon_device *rdev)
 918 {
 919         int r;
 920
 921         if (rdev->gart.table.vram.robj) {
 922                 WARN(1, "R600 PCIE GART already initialized.\n");
 923                 return 0;
 924         }
 925         /* Initialize common gart structure */
 926         r = radeon_gart_init(rdev);
 927         if (r)
 928                 return r;
 929         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 930         return radeon_gart_table_vram_alloc(rdev);
 931 }
 932
 933 int r600_pcie_gart_enable(struct radeon_device *rdev)
 934 {
 935         u32 tmp;
 936         int r, i;
 937
 938         if (rdev->gart.table.vram.robj == NULL) {
 939                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 940                 return -EINVAL;
 941         }
 942         r = radeon_gart_table_vram_pin(rdev);
 943         if (r)
 944                 return r;
 945         radeon_gart_restore(rdev);
 946
 947         /* Setup L2 cache */
 948         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 949                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 950                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 951         WREG32(VM_L2_CNTL2, 0);
 952         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 953         /* Setup TLB control */
 954         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 955                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 956                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 957                 ENABLE_WAIT_L2_QUERY;
 958         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 959         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 960         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 961         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 962         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 963         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 964         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 965         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 966         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 967         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 968         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 969         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 970         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 971         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 972         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 973         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 974         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 975         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 976                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 977         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 978                         (u32)(rdev->dummy_page.addr >> 12));
 979         for (i = 1; i < 7; i++)
 980                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 981
 982         r600_pcie_gart_tlb_flush(rdev);
 983         rdev->gart.ready = true;
 984         return 0;
 985 }
 986
 987 void r600_pcie_gart_disable(struct radeon_device *rdev)
 988 {
 989         u32 tmp;
 990         int i, r;
 991
 992         /* Disable all tables */
 993         for (i = 0; i < 7; i++)
 994                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 995
 996         /* Disable L2 cache */
 997         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 998                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 999         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1000         /* Setup L1 TLB control */
1001         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1002                 ENABLE_WAIT_L2_QUERY;
1003         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1004         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1005         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1006         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1007         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1008         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1009         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1010         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1011         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1012         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1013         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1014         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1015         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1016         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1017         if (rdev->gart.table.vram.robj) {
1018                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1019                 if (likely(r == 0)) {
1020                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
1021                         radeon_bo_unpin(rdev->gart.table.vram.robj);
1022                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
1023                 }
1024         }
1025 }
1026
1027 void r600_pcie_gart_fini(struct radeon_device *rdev)
1028 {
1029         radeon_gart_fini(rdev);
1030         r600_pcie_gart_disable(rdev);
1031         radeon_gart_table_vram_free(rdev);
1032 }
1033
1034 void r600_agp_enable(struct radeon_device *rdev)
1035 {
1036         u32 tmp;
1037         int i;
1038
1039         /* Setup L2 cache */
1040         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1041                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1042                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1043         WREG32(VM_L2_CNTL2, 0);
1044         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1045         /* Setup TLB control */
1046         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1047                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1048                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1049                 ENABLE_WAIT_L2_QUERY;
1050         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1051         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1052         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1053         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1054         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1055         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1056         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1057         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1058         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1059         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1060         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1061         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1062         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1063         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1064         for (i = 0; i < 7; i++)
1065                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1066 }
1067
1068 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1069 {
1070         unsigned i;
1071         u32 tmp;
1072
1073         for (i = 0; i < rdev->usec_timeout; i++) {
1074                 /* read MC_STATUS */
1075                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1076                 if (!tmp)
1077                         return 0;
1078                 udelay(1);
1079         }
1080         return -1;
1081 }
1082
1083 static void r600_mc_program(struct radeon_device *rdev)
1084 {
1085         struct rv515_mc_save save;
1086         u32 tmp;
1087         int i, j;
1088
1089         /* Initialize HDP */
1090         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1091                 WREG32((0x2c14 + j), 0x00000000);
1092                 WREG32((0x2c18 + j), 0x00000000);
1093                 WREG32((0x2c1c + j), 0x00000000);
1094                 WREG32((0x2c20 + j), 0x00000000);
1095                 WREG32((0x2c24 + j), 0x00000000);
1096         }
1097         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1098
1099         rv515_mc_stop(rdev, &save);
1100         if (r600_mc_wait_for_idle(rdev)) {
1101                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1102         }
1103         /* Lockout access through VGA aperture (doesn't exist before R600) */
1104         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1105         /* Update configuration */
1106         if (rdev->flags & RADEON_IS_AGP) {
1107                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1108                         /* VRAM before AGP */
1109                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1110                                 rdev->mc.vram_start >> 12);
1111                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1112                                 rdev->mc.gtt_end >> 12);
1113                 } else {
1114                         /* VRAM after AGP */
1115                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1116                                 rdev->mc.gtt_start >> 12);
1117                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1118                                 rdev->mc.vram_end >> 12);
1119                 }
1120         } else {
1121                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1122                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1123         }
1124         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1125         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1126         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1127         WREG32(MC_VM_FB_LOCATION, tmp);
1128         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1129         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1130         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1131         if (rdev->flags & RADEON_IS_AGP) {
1132                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1133                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1134                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1135         } else {
1136                 WREG32(MC_VM_AGP_BASE, 0);
1137                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1138                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1139         }
1140         if (r600_mc_wait_for_idle(rdev)) {
1141                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1142         }
1143         rv515_mc_resume(rdev, &save);
1144         /* we need to own VRAM, so turn off the VGA renderer here
1145          * to stop it overwriting our objects */
1146         rv515_vga_render_disable(rdev);
1147 }
1148
1149 /**
1150  * r600_vram_gtt_location - try to find VRAM & GTT location
1151  * @rdev: radeon device structure holding all necessary informations
1152  * @mc: memory controller structure holding memory informations
1153  *
1154  * Function will place try to place VRAM at same place as in CPU (PCI)
1155  * address space as some GPU seems to have issue when we reprogram at
1156  * different address space.
1157  *
1158  * If there is not enough space to fit the unvisible VRAM after the
1159  * aperture then we limit the VRAM size to the aperture.
1160  *
1161  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1162  * them to be in one from GPU point of view so that we can program GPU to
1163  * catch access outside them (weird GPU policy see ??).
1164  *
1165  * This function will never fails, worst case are limiting VRAM or GTT.
1166  *
1167  * Note: GTT start, end, size should be initialized before calling this
1168  * function on AGP platform.
1169  */
1170 void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1171 {
1172         u64 size_bf, size_af;
1173
1174         if (mc->mc_vram_size > 0xE0000000) {
1175                 /* leave room for at least 512M GTT */
1176                 dev_warn(rdev->dev, "limiting VRAM\n");
1177                 mc->real_vram_size = 0xE0000000;
1178                 mc->mc_vram_size = 0xE0000000;
1179         }
1180         if (rdev->flags & RADEON_IS_AGP) {
1181                 size_bf = mc->gtt_start;
1182                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1183                 if (size_bf > size_af) {
1184                         if (mc->mc_vram_size > size_bf) {
1185                                 dev_warn(rdev->dev, "limiting VRAM\n");
1186                                 mc->real_vram_size = size_bf;
1187                                 mc->mc_vram_size = size_bf;
1188                         }
1189                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1190                 } else {
1191                         if (mc->mc_vram_size > size_af) {
1192                                 dev_warn(rdev->dev, "limiting VRAM\n");
1193                                 mc->real_vram_size = size_af;
1194                                 mc->mc_vram_size = size_af;
1195                         }
1196                         mc->vram_start = mc->gtt_end;
1197                 }
1198                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1199                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1200                                 mc->mc_vram_size >> 20, mc->vram_start,
1201                                 mc->vram_end, mc->real_vram_size >> 20);
1202         } else {
1203                 u64 base = 0;
1204                 if (rdev->flags & RADEON_IS_IGP)
1205                         base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
1206                 radeon_vram_location(rdev, &rdev->mc, base);
1207                 rdev->mc.gtt_base_align = 0;
1208                 radeon_gtt_location(rdev, mc);
1209         }
1210 }
1211
1212 int r600_mc_init(struct radeon_device *rdev)
1213 {
1214         u32 tmp;
1215         int chansize, numchan;
1216
1217         /* Get VRAM informations */
1218         rdev->mc.vram_is_ddr = true;
1219         tmp = RREG32(RAMCFG);
1220         if (tmp & CHANSIZE_OVERRIDE) {
1221                 chansize = 16;
1222         } else if (tmp & CHANSIZE_MASK) {
1223                 chansize = 64;
1224         } else {
1225                 chansize = 32;
1226         }
1227         tmp = RREG32(CHMAP);
1228         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1229         case 0:
1230         default:
1231                 numchan = 1;
1232                 break;
1233         case 1:
1234                 numchan = 2;
1235                 break;
1236         case 2:
1237                 numchan = 4;
1238                 break;
1239         case 3:
1240                 numchan = 8;
1241                 break;
1242         }
1243         rdev->mc.vram_width = numchan * chansize;
1244         /* Could aper size report 0 ? */
1245         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1246         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1247         /* Setup GPU memory space */
1248         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1249         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1250         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1251         r600_vram_gtt_location(rdev, &rdev->mc);
1252
1253         if (rdev->flags & RADEON_IS_IGP) {
1254                 rs690_pm_info(rdev);
1255                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1256         }
1257         radeon_update_bandwidth_info(rdev);
1258         return 0;
1259 }
1260
1261 /* We doesn't check that the GPU really needs a reset we simply do the
1262  * reset, it's up to the caller to determine if the GPU needs one. We
1263  * might add an helper function to check that.
1264  */
1265 int r600_gpu_soft_reset(struct radeon_device *rdev)
1266 {
1267         struct rv515_mc_save save;
1268         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1269                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1270                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1271                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1272                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1273                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1274                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1275                                 S_008010_GUI_ACTIVE(1);
1276         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1277                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1278                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1279                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1280                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1281                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1282                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1283                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1284         u32 tmp;
1285
1286         dev_info(rdev->dev, "GPU softreset \n");
1287         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1288                 RREG32(R_008010_GRBM_STATUS));
1289         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1290                 RREG32(R_008014_GRBM_STATUS2));
1291         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1292                 RREG32(R_000E50_SRBM_STATUS));
1293         rv515_mc_stop(rdev, &save);
1294         if (r600_mc_wait_for_idle(rdev)) {
1295                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1296         }
1297         /* Disable CP parsing/prefetching */
1298         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1299         /* Check if any of the rendering block is busy and reset it */
1300         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1301             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1302                 tmp = S_008020_SOFT_RESET_CR(1) |
1303                         S_008020_SOFT_RESET_DB(1) |
1304                         S_008020_SOFT_RESET_CB(1) |
1305                         S_008020_SOFT_RESET_PA(1) |
1306                         S_008020_SOFT_RESET_SC(1) |
1307                         S_008020_SOFT_RESET_SMX(1) |
1308                         S_008020_SOFT_RESET_SPI(1) |
1309                         S_008020_SOFT_RESET_SX(1) |
1310                         S_008020_SOFT_RESET_SH(1) |
1311                         S_008020_SOFT_RESET_TC(1) |
1312                         S_008020_SOFT_RESET_TA(1) |
1313                         S_008020_SOFT_RESET_VC(1) |
1314                         S_008020_SOFT_RESET_VGT(1);
1315                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1316                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1317                 RREG32(R_008020_GRBM_SOFT_RESET);
1318                 mdelay(15);
1319                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1320         }
1321         /* Reset CP (we always reset CP) */
1322         tmp = S_008020_SOFT_RESET_CP(1);
1323         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1324         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1325         RREG32(R_008020_GRBM_SOFT_RESET);
1326         mdelay(15);
1327         WREG32(R_008020_GRBM_SOFT_RESET, 0);
1328         /* Wait a little for things to settle down */
1329         mdelay(1);
1330         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1331                 RREG32(R_008010_GRBM_STATUS));
1332         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1333                 RREG32(R_008014_GRBM_STATUS2));
1334         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1335                 RREG32(R_000E50_SRBM_STATUS));
1336         rv515_mc_resume(rdev, &save);
1337         return 0;
1338 }
1339
1340 bool r600_gpu_is_lockup(struct radeon_device *rdev)
1341 {
1342         u32 srbm_status;
1343         u32 grbm_status;
1344         u32 grbm_status2;
1345         int r;
1346
1347         srbm_status = RREG32(R_000E50_SRBM_STATUS);
1348         grbm_status = RREG32(R_008010_GRBM_STATUS);
1349         grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1350         if (!G_008010_GUI_ACTIVE(grbm_status)) {
1351                 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
1352                 return false;
1353         }
1354         /* force CP activities */
1355         r = radeon_ring_lock(rdev, 2);
1356         if (!r) {
1357                 /* PACKET2 NOP */
1358                 radeon_ring_write(rdev, 0x80000000);
1359                 radeon_ring_write(rdev, 0x80000000);
1360                 radeon_ring_unlock_commit(rdev);
1361         }
1362         rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1363         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
1364 }
1365
1366 int r600_asic_reset(struct radeon_device *rdev)
1367 {
1368         return r600_gpu_soft_reset(rdev);
1369 }
1370
1371 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1372                                              u32 num_backends,
1373                                              u32 backend_disable_mask)
1374 {
1375         u32 backend_map = 0;
1376         u32 enabled_backends_mask;
1377         u32 enabled_backends_count;
1378         u32 cur_pipe;
1379         u32 swizzle_pipe[R6XX_MAX_PIPES];
1380         u32 cur_backend;
1381         u32 i;
1382
1383         if (num_tile_pipes > R6XX_MAX_PIPES)
1384                 num_tile_pipes = R6XX_MAX_PIPES;
1385         if (num_tile_pipes < 1)
1386                 num_tile_pipes = 1;
1387         if (num_backends > R6XX_MAX_BACKENDS)
1388                 num_backends = R6XX_MAX_BACKENDS;
1389         if (num_backends < 1)
1390                 num_backends = 1;
1391
1392         enabled_backends_mask = 0;
1393         enabled_backends_count = 0;
1394         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1395                 if (((backend_disable_mask >> i) & 1) == 0) {
1396                         enabled_backends_mask |= (1 << i);
1397                         ++enabled_backends_count;
1398                 }
1399                 if (enabled_backends_count == num_backends)
1400                         break;
1401         }
1402
1403         if (enabled_backends_count == 0) {
1404                 enabled_backends_mask = 1;
1405                 enabled_backends_count = 1;
1406         }
1407
1408         if (enabled_backends_count != num_backends)
1409                 num_backends = enabled_backends_count;
1410
1411         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1412         switch (num_tile_pipes) {
1413         case 1:
1414                 swizzle_pipe[0] = 0;
1415                 break;
1416         case 2:
1417                 swizzle_pipe[0] = 0;
1418                 swizzle_pipe[1] = 1;
1419                 break;
1420         case 3:
1421                 swizzle_pipe[0] = 0;
1422                 swizzle_pipe[1] = 1;
1423                 swizzle_pipe[2] = 2;
1424                 break;
1425         case 4:
1426                 swizzle_pipe[0] = 0;
1427                 swizzle_pipe[1] = 1;
1428                 swizzle_pipe[2] = 2;
1429                 swizzle_pipe[3] = 3;
1430                 break;
1431         case 5:
1432                 swizzle_pipe[0] = 0;
1433                 swizzle_pipe[1] = 1;
1434                 swizzle_pipe[2] = 2;
1435                 swizzle_pipe[3] = 3;
1436                 swizzle_pipe[4] = 4;
1437                 break;
1438         case 6:
1439                 swizzle_pipe[0] = 0;
1440                 swizzle_pipe[1] = 2;
1441                 swizzle_pipe[2] = 4;
1442                 swizzle_pipe[3] = 5;
1443                 swizzle_pipe[4] = 1;
1444                 swizzle_pipe[5] = 3;
1445                 break;
1446         case 7:
1447                 swizzle_pipe[0] = 0;
1448                 swizzle_pipe[1] = 2;
1449                 swizzle_pipe[2] = 4;
1450                 swizzle_pipe[3] = 6;
1451                 swizzle_pipe[4] = 1;
1452                 swizzle_pipe[5] = 3;
1453                 swizzle_pipe[6] = 5;
1454                 break;
1455         case 8:
1456                 swizzle_pipe[0] = 0;
1457                 swizzle_pipe[1] = 2;
1458                 swizzle_pipe[2] = 4;
1459                 swizzle_pipe[3] = 6;
1460                 swizzle_pipe[4] = 1;
1461                 swizzle_pipe[5] = 3;
1462                 swizzle_pipe[6] = 5;
1463                 swizzle_pipe[7] = 7;
1464                 break;
1465         }
1466
1467         cur_backend = 0;
1468         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1469                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1470                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1471
1472                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1473
1474                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1475         }
1476
1477         return backend_map;
1478 }
1479
1480 int r600_count_pipe_bits(uint32_t val)
1481 {
1482         int i, ret = 0;
1483
1484         for (i = 0; i < 32; i++) {
1485                 ret += val & 1;
1486                 val >>= 1;
1487         }
1488         return ret;
1489 }
1490
1491 void r600_gpu_init(struct radeon_device *rdev)
1492 {
1493         u32 tiling_config;
1494         u32 ramcfg;
1495         u32 backend_map;
1496         u32 cc_rb_backend_disable;
1497         u32 cc_gc_shader_pipe_config;
1498         u32 tmp;
1499         int i, j;
1500         u32 sq_config;
1501         u32 sq_gpr_resource_mgmt_1 = 0;
1502         u32 sq_gpr_resource_mgmt_2 = 0;
1503         u32 sq_thread_resource_mgmt = 0;
1504         u32 sq_stack_resource_mgmt_1 = 0;
1505         u32 sq_stack_resource_mgmt_2 = 0;
1506
1507         /* FIXME: implement */
1508         switch (rdev->family) {
1509         case CHIP_R600:
1510                 rdev->config.r600.max_pipes = 4;
1511                 rdev->config.r600.max_tile_pipes = 8;
1512                 rdev->config.r600.max_simds = 4;
1513                 rdev->config.r600.max_backends = 4;
1514                 rdev->config.r600.max_gprs = 256;
1515                 rdev->config.r600.max_threads = 192;
1516                 rdev->config.r600.max_stack_entries = 256;
1517                 rdev->config.r600.max_hw_contexts = 8;
1518                 rdev->config.r600.max_gs_threads = 16;
1519                 rdev->config.r600.sx_max_export_size = 128;
1520                 rdev->config.r600.sx_max_export_pos_size = 16;
1521                 rdev->config.r600.sx_max_export_smx_size = 128;
1522                 rdev->config.r600.sq_num_cf_insts = 2;
1523                 break;
1524         case CHIP_RV630:
1525         case CHIP_RV635:
1526                 rdev->config.r600.max_pipes = 2;
1527                 rdev->config.r600.max_tile_pipes = 2;
1528                 rdev->config.r600.max_simds = 3;
1529                 rdev->config.r600.max_backends = 1;
1530                 rdev->config.r600.max_gprs = 128;
1531                 rdev->config.r600.max_threads = 192;
1532                 rdev->config.r600.max_stack_entries = 128;
1533                 rdev->config.r600.max_hw_contexts = 8;
1534                 rdev->config.r600.max_gs_threads = 4;
1535                 rdev->config.r600.sx_max_export_size = 128;
1536                 rdev->config.r600.sx_max_export_pos_size = 16;
1537                 rdev->config.r600.sx_max_export_smx_size = 128;
1538                 rdev->config.r600.sq_num_cf_insts = 2;
1539                 break;
1540         case CHIP_RV610:
1541         case CHIP_RV620:
1542         case CHIP_RS780:
1543         case CHIP_RS880:
1544                 rdev->config.r600.max_pipes = 1;
1545                 rdev->config.r600.max_tile_pipes = 1;
1546                 rdev->config.r600.max_simds = 2;
1547                 rdev->config.r600.max_backends = 1;
1548                 rdev->config.r600.max_gprs = 128;
1549                 rdev->config.r600.max_threads = 192;
1550                 rdev->config.r600.max_stack_entries = 128;
1551                 rdev->config.r600.max_hw_contexts = 4;
1552                 rdev->config.r600.max_gs_threads = 4;
1553                 rdev->config.r600.sx_max_export_size = 128;
1554                 rdev->config.r600.sx_max_export_pos_size = 16;
1555                 rdev->config.r600.sx_max_export_smx_size = 128;
1556                 rdev->config.r600.sq_num_cf_insts = 1;
1557                 break;
1558         case CHIP_RV670:
1559                 rdev->config.r600.max_pipes = 4;
1560                 rdev->config.r600.max_tile_pipes = 4;
1561                 rdev->config.r600.max_simds = 4;
1562                 rdev->config.r600.max_backends = 4;
1563                 rdev->config.r600.max_gprs = 192;
1564                 rdev->config.r600.max_threads = 192;
1565                 rdev->config.r600.max_stack_entries = 256;
1566                 rdev->config.r600.max_hw_contexts = 8;
1567                 rdev->config.r600.max_gs_threads = 16;
1568                 rdev->config.r600.sx_max_export_size = 128;
1569                 rdev->config.r600.sx_max_export_pos_size = 16;
1570                 rdev->config.r600.sx_max_export_smx_size = 128;
1571                 rdev->config.r600.sq_num_cf_insts = 2;
1572                 break;
1573         default:
1574                 break;
1575         }
1576
1577         /* Initialize HDP */
1578         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1579                 WREG32((0x2c14 + j), 0x00000000);
1580                 WREG32((0x2c18 + j), 0x00000000);
1581                 WREG32((0x2c1c + j), 0x00000000);
1582                 WREG32((0x2c20 + j), 0x00000000);
1583                 WREG32((0x2c24 + j), 0x00000000);
1584         }
1585
1586         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1587
1588         /* Setup tiling */
1589         tiling_config = 0;
1590         ramcfg = RREG32(RAMCFG);
1591         switch (rdev->config.r600.max_tile_pipes) {
1592         case 1:
1593                 tiling_config |= PIPE_TILING(0);
1594                 break;
1595         case 2:
1596                 tiling_config |= PIPE_TILING(1);
1597                 break;
1598         case 4:
1599                 tiling_config |= PIPE_TILING(2);
1600                 break;
1601         case 8:
1602                 tiling_config |= PIPE_TILING(3);
1603                 break;
1604         default:
1605                 break;
1606         }
1607         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1608         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1609         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1610         tiling_config |= GROUP_SIZE(0);
1611         rdev->config.r600.tiling_group_size = 256;
1612         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1613         if (tmp > 3) {
1614                 tiling_config |= ROW_TILING(3);
1615                 tiling_config |= SAMPLE_SPLIT(3);
1616         } else {
1617                 tiling_config |= ROW_TILING(tmp);
1618                 tiling_config |= SAMPLE_SPLIT(tmp);
1619         }
1620         tiling_config |= BANK_SWAPS(1);
1621
1622         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1623         cc_rb_backend_disable |=
1624                 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1625
1626         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1627         cc_gc_shader_pipe_config |=
1628                 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1629         cc_gc_shader_pipe_config |=
1630                 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1631
1632         backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1633                                                         (R6XX_MAX_BACKENDS -
1634                                                          r600_count_pipe_bits((cc_rb_backend_disable &
1635                                                                                R6XX_MAX_BACKENDS_MASK) >> 16)),
1636                                                         (cc_rb_backend_disable >> 16));
1637         rdev->config.r600.tile_config = tiling_config;
1638         tiling_config |= BACKEND_MAP(backend_map);
1639         WREG32(GB_TILING_CONFIG, tiling_config);
1640         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1641         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1642
1643         /* Setup pipes */
1644         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1645         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1646         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1647
1648         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1649         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1650         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1651
1652         /* Setup some CP states */
1653         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1654         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1655
1656         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1657                              SYNC_WALKER | SYNC_ALIGNER));
1658         /* Setup various GPU states */
1659         if (rdev->family == CHIP_RV670)
1660                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1661
1662         tmp = RREG32(SX_DEBUG_1);
1663         tmp |= SMX_EVENT_RELEASE;
1664         if ((rdev->family > CHIP_R600))
1665                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1666         WREG32(SX_DEBUG_1, tmp);
1667
1668         if (((rdev->family) == CHIP_R600) ||
1669             ((rdev->family) == CHIP_RV630) ||
1670             ((rdev->family) == CHIP_RV610) ||
1671             ((rdev->family) == CHIP_RV620) ||
1672             ((rdev->family) == CHIP_RS780) ||
1673             ((rdev->family) == CHIP_RS880)) {
1674                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1675         } else {
1676                 WREG32(DB_DEBUG, 0);
1677         }
1678         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1679                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1680
1681         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1682         WREG32(VGT_NUM_INSTANCES, 0);
1683
1684         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1685         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1686
1687         tmp = RREG32(SQ_MS_FIFO_SIZES);
1688         if (((rdev->family) == CHIP_RV610) ||
1689             ((rdev->family) == CHIP_RV620) ||
1690             ((rdev->family) == CHIP_RS780) ||
1691             ((rdev->family) == CHIP_RS880)) {
1692                 tmp = (CACHE_FIFO_SIZE(0xa) |
1693                        FETCH_FIFO_HIWATER(0xa) |
1694                        DONE_FIFO_HIWATER(0xe0) |
1695                        ALU_UPDATE_FIFO_HIWATER(0x8));
1696         } else if (((rdev->family) == CHIP_R600) ||
1697                    ((rdev->family) == CHIP_RV630)) {
1698                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1699                 tmp |= DONE_FIFO_HIWATER(0x4);
1700         }
1701         WREG32(SQ_MS_FIFO_SIZES, tmp);
1702
1703         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1704          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1705          */
1706         sq_config = RREG32(SQ_CONFIG);
1707         sq_config &= ~(PS_PRIO(3) |
1708                        VS_PRIO(3) |
1709                        GS_PRIO(3) |
1710                        ES_PRIO(3));
1711         sq_config |= (DX9_CONSTS |
1712                       VC_ENABLE |
1713                       PS_PRIO(0) |
1714                       VS_PRIO(1) |
1715                       GS_PRIO(2) |
1716                       ES_PRIO(3));
1717
1718         if ((rdev->family) == CHIP_R600) {
1719                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1720                                           NUM_VS_GPRS(124) |
1721                                           NUM_CLAUSE_TEMP_GPRS(4));
1722                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1723                                           NUM_ES_GPRS(0));
1724                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1725                                            NUM_VS_THREADS(48) |
1726                                            NUM_GS_THREADS(4) |
1727                                            NUM_ES_THREADS(4));
1728                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1729                                             NUM_VS_STACK_ENTRIES(128));
1730                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1731                                             NUM_ES_STACK_ENTRIES(0));
1732         } else if (((rdev->family) == CHIP_RV610) ||
1733                    ((rdev->family) == CHIP_RV620) ||
1734                    ((rdev->family) == CHIP_RS780) ||
1735                    ((rdev->family) == CHIP_RS880)) {
1736                 /* no vertex cache */
1737                 sq_config &= ~VC_ENABLE;
1738
1739                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1740                                           NUM_VS_GPRS(44) |
1741                                           NUM_CLAUSE_TEMP_GPRS(2));
1742                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1743                                           NUM_ES_GPRS(17));
1744                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1745                                            NUM_VS_THREADS(78) |
1746                                            NUM_GS_THREADS(4) |
1747                                            NUM_ES_THREADS(31));
1748                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1749                                             NUM_VS_STACK_ENTRIES(40));
1750                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1751                                             NUM_ES_STACK_ENTRIES(16));
1752         } else if (((rdev->family) == CHIP_RV630) ||
1753                    ((rdev->family) == CHIP_RV635)) {
1754                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1755                                           NUM_VS_GPRS(44) |
1756                                           NUM_CLAUSE_TEMP_GPRS(2));
1757                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1758                                           NUM_ES_GPRS(18));
1759                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1760                                            NUM_VS_THREADS(78) |
1761                                            NUM_GS_THREADS(4) |
1762                                            NUM_ES_THREADS(31));
1763                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1764                                             NUM_VS_STACK_ENTRIES(40));
1765                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1766                                             NUM_ES_STACK_ENTRIES(16));
1767         } else if ((rdev->family) == CHIP_RV670) {
1768                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1769                                           NUM_VS_GPRS(44) |
1770                                           NUM_CLAUSE_TEMP_GPRS(2));
1771                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1772                                           NUM_ES_GPRS(17));
1773                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1774                                            NUM_VS_THREADS(78) |
1775                                            NUM_GS_THREADS(4) |
1776                                            NUM_ES_THREADS(31));
1777                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1778                                             NUM_VS_STACK_ENTRIES(64));
1779                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1780                                             NUM_ES_STACK_ENTRIES(64));
1781         }
1782
1783         WREG32(SQ_CONFIG, sq_config);
1784         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1785         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1786         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1787         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1788         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1789
1790         if (((rdev->family) == CHIP_RV610) ||
1791             ((rdev->family) == CHIP_RV620) ||
1792             ((rdev->family) == CHIP_RS780) ||
1793             ((rdev->family) == CHIP_RS880)) {
1794                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1795         } else {
1796                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1797         }
1798
1799         /* More default values. 2D/3D driver should adjust as needed */
1800         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1801                                          S1_X(0x4) | S1_Y(0xc)));
1802         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1803                                          S1_X(0x2) | S1_Y(0x2) |
1804                                          S2_X(0xa) | S2_Y(0x6) |
1805                                          S3_X(0x6) | S3_Y(0xa)));
1806         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1807                                              S1_X(0x4) | S1_Y(0xc) |
1808                                              S2_X(0x1) | S2_Y(0x6) |
1809                                              S3_X(0xa) | S3_Y(0xe)));
1810         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1811                                              S5_X(0x0) | S5_Y(0x0) |
1812                                              S6_X(0xb) | S6_Y(0x4) |
1813                                              S7_X(0x7) | S7_Y(0x8)));
1814
1815         WREG32(VGT_STRMOUT_EN, 0);
1816         tmp = rdev->config.r600.max_pipes * 16;
1817         switch (rdev->family) {
1818         case CHIP_RV610:
1819         case CHIP_RV620:
1820         case CHIP_RS780:
1821         case CHIP_RS880:
1822                 tmp += 32;
1823                 break;
1824         case CHIP_RV670:
1825                 tmp += 128;
1826                 break;
1827         default:
1828                 break;
1829         }
1830         if (tmp > 256) {
1831                 tmp = 256;
1832         }
1833         WREG32(VGT_ES_PER_GS, 128);
1834         WREG32(VGT_GS_PER_ES, tmp);
1835         WREG32(VGT_GS_PER_VS, 2);
1836         WREG32(VGT_GS_VERTEX_REUSE, 16);
1837
1838         /* more default values. 2D/3D driver should adjust as needed */
1839         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1840         WREG32(VGT_STRMOUT_EN, 0);
1841         WREG32(SX_MISC, 0);
1842         WREG32(PA_SC_MODE_CNTL, 0);
1843         WREG32(PA_SC_AA_CONFIG, 0);
1844         WREG32(PA_SC_LINE_STIPPLE, 0);
1845         WREG32(SPI_INPUT_Z, 0);
1846         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1847         WREG32(CB_COLOR7_FRAG, 0);
1848
1849         /* Clear render buffer base addresses */
1850         WREG32(CB_COLOR0_BASE, 0);
1851         WREG32(CB_COLOR1_BASE, 0);
1852         WREG32(CB_COLOR2_BASE, 0);
1853         WREG32(CB_COLOR3_BASE, 0);
1854         WREG32(CB_COLOR4_BASE, 0);
1855         WREG32(CB_COLOR5_BASE, 0);
1856         WREG32(CB_COLOR6_BASE, 0);
1857         WREG32(CB_COLOR7_BASE, 0);
1858         WREG32(CB_COLOR7_FRAG, 0);
1859
1860         switch (rdev->family) {
1861         case CHIP_RV610:
1862         case CHIP_RV620:
1863         case CHIP_RS780:
1864         case CHIP_RS880:
1865                 tmp = TC_L2_SIZE(8);
1866                 break;
1867         case CHIP_RV630:
1868         case CHIP_RV635:
1869                 tmp = TC_L2_SIZE(4);
1870                 break;
1871         case CHIP_R600:
1872                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1873                 break;
1874         default:
1875                 tmp = TC_L2_SIZE(0);
1876                 break;
1877         }
1878         WREG32(TC_CNTL, tmp);
1879
1880         tmp = RREG32(HDP_HOST_PATH_CNTL);
1881         WREG32(HDP_HOST_PATH_CNTL, tmp);
1882
1883         tmp = RREG32(ARB_POP);
1884         tmp |= ENABLE_TC128;
1885         WREG32(ARB_POP, tmp);
1886
1887         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1888         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1889                                NUM_CLIP_SEQ(3)));
1890         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1891 }
1892
1893
1894 /*
1895  * Indirect registers accessor
1896  */
1897 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1898 {
1899         u32 r;
1900
1901         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1902         (void)RREG32(PCIE_PORT_INDEX);
1903         r = RREG32(PCIE_PORT_DATA);
1904         return r;
1905 }
1906
1907 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1908 {
1909         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1910         (void)RREG32(PCIE_PORT_INDEX);
1911         WREG32(PCIE_PORT_DATA, (v));
1912         (void)RREG32(PCIE_PORT_DATA);
1913 }
1914
1915 /*
1916  * CP & Ring
1917  */
1918 void r600_cp_stop(struct radeon_device *rdev)
1919 {
1920         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1921 }
1922
1923 int r600_init_microcode(struct radeon_device *rdev)
1924 {
1925         struct platform_device *pdev;
1926         const char *chip_name;
1927         const char *rlc_chip_name;
1928         size_t pfp_req_size, me_req_size, rlc_req_size;
1929         char fw_name[30];
1930         int err;
1931
1932         DRM_DEBUG("\n");
1933
1934         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1935         err = IS_ERR(pdev);
1936         if (err) {
1937                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1938                 return -EINVAL;
1939         }
1940
1941         switch (rdev->family) {
1942         case CHIP_R600:
1943                 chip_name = "R600";
1944                 rlc_chip_name = "R600";
1945                 break;
1946         case CHIP_RV610:
1947                 chip_name = "RV610";
1948                 rlc_chip_name = "R600";
1949                 break;
1950         case CHIP_RV630:
1951                 chip_name = "RV630";
1952                 rlc_chip_name = "R600";
1953                 break;
1954         case CHIP_RV620:
1955                 chip_name = "RV620";
1956                 rlc_chip_name = "R600";
1957                 break;
1958         case CHIP_RV635:
1959                 chip_name = "RV635";
1960                 rlc_chip_name = "R600";
1961                 break;
1962         case CHIP_RV670:
1963                 chip_name = "RV670";
1964                 rlc_chip_name = "R600";
1965                 break;
1966         case CHIP_RS780:
1967         case CHIP_RS880:
1968                 chip_name = "RS780";
1969                 rlc_chip_name = "R600";
1970                 break;
1971         case CHIP_RV770:
1972                 chip_name = "RV770";
1973                 rlc_chip_name = "R700";
1974                 break;
1975         case CHIP_RV730:
1976         case CHIP_RV740:
1977                 chip_name = "RV730";
1978                 rlc_chip_name = "R700";
1979                 break;
1980         case CHIP_RV710:
1981                 chip_name = "RV710";
1982                 rlc_chip_name = "R700";
1983                 break;
1984         case CHIP_CEDAR:
1985                 chip_name = "CEDAR";
1986                 rlc_chip_name = "CEDAR";
1987                 break;
1988         case CHIP_REDWOOD:
1989                 chip_name = "REDWOOD";
1990                 rlc_chip_name = "REDWOOD";
1991                 break;
1992         case CHIP_JUNIPER:
1993                 chip_name = "JUNIPER";
1994                 rlc_chip_name = "JUNIPER";
1995                 break;
1996         case CHIP_CYPRESS:
1997         case CHIP_HEMLOCK:
1998                 chip_name = "CYPRESS";
1999                 rlc_chip_name = "CYPRESS";
2000                 break;
2001         default: BUG();
2002         }
2003
2004         if (rdev->family >= CHIP_CEDAR) {
2005                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2006                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2007                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2008         } else if (rdev->family >= CHIP_RV770) {
2009                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2010                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2011                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2012         } else {
2013                 pfp_req_size = PFP_UCODE_SIZE * 4;
2014                 me_req_size = PM4_UCODE_SIZE * 12;
2015                 rlc_req_size = RLC_UCODE_SIZE * 4;
2016         }
2017
2018         DRM_INFO("Loading %s Microcode\n", chip_name);
2019
2020         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2021         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2022         if (err)
2023                 goto out;
2024         if (rdev->pfp_fw->size != pfp_req_size) {
2025                 printk(KERN_ERR
2026                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2027                        rdev->pfp_fw->size, fw_name);
2028                 err = -EINVAL;
2029                 goto out;
2030         }
2031
2032         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2033         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2034         if (err)
2035                 goto out;
2036         if (rdev->me_fw->size != me_req_size) {
2037                 printk(KERN_ERR
2038                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2039                        rdev->me_fw->size, fw_name);
2040                 err = -EINVAL;
2041         }
2042
2043         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2044         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2045         if (err)
2046                 goto out;
2047         if (rdev->rlc_fw->size != rlc_req_size) {
2048                 printk(KERN_ERR
2049                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2050                        rdev->rlc_fw->size, fw_name);
2051                 err = -EINVAL;
2052         }
2053
2054 out:
2055         platform_device_unregister(pdev);
2056
2057         if (err) {
2058                 if (err != -EINVAL)
2059                         printk(KERN_ERR
2060                                "r600_cp: Failed to load firmware \"%s\"\n",
2061                                fw_name);
2062                 release_firmware(rdev->pfp_fw);
2063                 rdev->pfp_fw = NULL;
2064                 release_firmware(rdev->me_fw);
2065                 rdev->me_fw = NULL;
2066                 release_firmware(rdev->rlc_fw);
2067                 rdev->rlc_fw = NULL;
2068         }
2069         return err;
2070 }
2071
2072 static int r600_cp_load_microcode(struct radeon_device *rdev)
2073 {
2074         const __be32 *fw_data;
2075         int i;
2076
2077         if (!rdev->me_fw || !rdev->pfp_fw)
2078                 return -EINVAL;
2079
2080         r600_cp_stop(rdev);
2081
2082         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2083
2084         /* Reset cp */
2085         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2086         RREG32(GRBM_SOFT_RESET);
2087         mdelay(15);
2088         WREG32(GRBM_SOFT_RESET, 0);
2089
2090         WREG32(CP_ME_RAM_WADDR, 0);
2091
2092         fw_data = (const __be32 *)rdev->me_fw->data;
2093         WREG32(CP_ME_RAM_WADDR, 0);
2094         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2095                 WREG32(CP_ME_RAM_DATA,
2096                        be32_to_cpup(fw_data++));
2097
2098         fw_data = (const __be32 *)rdev->pfp_fw->data;
2099         WREG32(CP_PFP_UCODE_ADDR, 0);
2100         for (i = 0; i < PFP_UCODE_SIZE; i++)
2101                 WREG32(CP_PFP_UCODE_DATA,
2102                        be32_to_cpup(fw_data++));
2103
2104         WREG32(CP_PFP_UCODE_ADDR, 0);
2105         WREG32(CP_ME_RAM_WADDR, 0);
2106         WREG32(CP_ME_RAM_RADDR, 0);
2107         return 0;
2108 }
2109
2110 int r600_cp_start(struct radeon_device *rdev)
2111 {
2112         int r;
2113         uint32_t cp_me;
2114
2115         r = radeon_ring_lock(rdev, 7);
2116         if (r) {
2117                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2118                 return r;
2119         }
2120         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2121         radeon_ring_write(rdev, 0x1);
2122         if (rdev->family >= CHIP_CEDAR) {
2123                 radeon_ring_write(rdev, 0x0);
2124                 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
2125         } else if (rdev->family >= CHIP_RV770) {
2126                 radeon_ring_write(rdev, 0x0);
2127                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
2128         } else {
2129                 radeon_ring_write(rdev, 0x3);
2130                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
2131         }
2132         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2133         radeon_ring_write(rdev, 0);
2134         radeon_ring_write(rdev, 0);
2135         radeon_ring_unlock_commit(rdev);
2136
2137         cp_me = 0xff;
2138         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2139         return 0;
2140 }
2141
2142 int r600_cp_resume(struct radeon_device *rdev)
2143 {
2144         u32 tmp;
2145         u32 rb_bufsz;
2146         int r;
2147
2148         /* Reset cp */
2149         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2150         RREG32(GRBM_SOFT_RESET);
2151         mdelay(15);
2152         WREG32(GRBM_SOFT_RESET, 0);
2153
2154         /* Set ring buffer size */
2155         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
2156         tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2157 #ifdef __BIG_ENDIAN
2158         tmp |= BUF_SWAP_32BIT;
2159 #endif
2160         WREG32(CP_RB_CNTL, tmp);
2161         WREG32(CP_SEM_WAIT_TIMER, 0x4);
2162
2163         /* Set the write pointer delay */
2164         WREG32(CP_RB_WPTR_DELAY, 0);
2165
2166         /* Initialize the ring buffer's read and write pointers */
2167         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2168         WREG32(CP_RB_RPTR_WR, 0);
2169         WREG32(CP_RB_WPTR, 0);
2170         WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
2171         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
2172         mdelay(1);
2173         WREG32(CP_RB_CNTL, tmp);
2174
2175         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2176         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2177
2178         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2179         rdev->cp.wptr = RREG32(CP_RB_WPTR);
2180
2181         r600_cp_start(rdev);
2182         rdev->cp.ready = true;
2183         r = radeon_ring_test(rdev);
2184         if (r) {
2185                 rdev->cp.ready = false;
2186                 return r;
2187         }
2188         return 0;
2189 }
2190
2191 void r600_cp_commit(struct radeon_device *rdev)
2192 {
2193         WREG32(CP_RB_WPTR, rdev->cp.wptr);
2194         (void)RREG32(CP_RB_WPTR);
2195 }
2196
2197 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2198 {
2199         u32 rb_bufsz;
2200
2201         /* Align ring size */
2202         rb_bufsz = drm_order(ring_size / 8);
2203         ring_size = (1 << (rb_bufsz + 1)) * 4;
2204         rdev->cp.ring_size = ring_size;
2205         rdev->cp.align_mask = 16 - 1;
2206 }
2207
2208 void r600_cp_fini(struct radeon_device *rdev)
2209 {
2210         r600_cp_stop(rdev);
2211         radeon_ring_fini(rdev);
2212 }
2213
2214
2215 /*
2216  * GPU scratch registers helpers function.
2217  */
2218 void r600_scratch_init(struct radeon_device *rdev)
2219 {
2220         int i;
2221
2222         rdev->scratch.num_reg = 7;
2223         for (i = 0; i < rdev->scratch.num_reg; i++) {
2224                 rdev->scratch.free[i] = true;
2225                 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
2226         }
2227 }
2228
2229 int r600_ring_test(struct radeon_device *rdev)
2230 {
2231         uint32_t scratch;
2232         uint32_t tmp = 0;
2233         unsigned i;
2234         int r;
2235
2236         r = radeon_scratch_get(rdev, &scratch);
2237         if (r) {
2238                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2239                 return r;
2240         }
2241         WREG32(scratch, 0xCAFEDEAD);
2242         r = radeon_ring_lock(rdev, 3);
2243         if (r) {
2244                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2245                 radeon_scratch_free(rdev, scratch);
2246                 return r;
2247         }
2248         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2249         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2250         radeon_ring_write(rdev, 0xDEADBEEF);
2251         radeon_ring_unlock_commit(rdev);
2252         for (i = 0; i < rdev->usec_timeout; i++) {
2253                 tmp = RREG32(scratch);
2254                 if (tmp == 0xDEADBEEF)
2255                         break;
2256                 DRM_UDELAY(1);
2257         }
2258         if (i < rdev->usec_timeout) {
2259                 DRM_INFO("ring test succeeded in %d usecs\n", i);
2260         } else {
2261                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2262                           scratch, tmp);
2263                 r = -EINVAL;
2264         }
2265         radeon_scratch_free(rdev, scratch);
2266         return r;
2267 }
2268
2269 void r600_wb_disable(struct radeon_device *rdev)
2270 {
2271         int r;
2272
2273         WREG32(SCRATCH_UMSK, 0);
2274         if (rdev->wb.wb_obj) {
2275                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
2276                 if (unlikely(r != 0))
2277                         return;
2278                 radeon_bo_kunmap(rdev->wb.wb_obj);
2279                 radeon_bo_unpin(rdev->wb.wb_obj);
2280                 radeon_bo_unreserve(rdev->wb.wb_obj);
2281         }
2282 }
2283
2284 void r600_wb_fini(struct radeon_device *rdev)
2285 {
2286         r600_wb_disable(rdev);
2287         if (rdev->wb.wb_obj) {
2288                 radeon_bo_unref(&rdev->wb.wb_obj);
2289                 rdev->wb.wb = NULL;
2290                 rdev->wb.wb_obj = NULL;
2291         }
2292 }
2293
2294 int r600_wb_enable(struct radeon_device *rdev)
2295 {
2296         int r;
2297
2298         if (rdev->wb.wb_obj == NULL) {
2299                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
2300                                 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
2301                 if (r) {
2302                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
2303                         return r;
2304                 }
2305                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
2306                 if (unlikely(r != 0)) {
2307                         r600_wb_fini(rdev);
2308                         return r;
2309                 }
2310                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
2311                                 &rdev->wb.gpu_addr);
2312                 if (r) {
2313                         radeon_bo_unreserve(rdev->wb.wb_obj);
2314                         dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
2315                         r600_wb_fini(rdev);
2316                         return r;
2317                 }
2318                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
2319                 radeon_bo_unreserve(rdev->wb.wb_obj);
2320                 if (r) {
2321                         dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
2322                         r600_wb_fini(rdev);
2323                         return r;
2324                 }
2325         }
2326         WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
2327         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
2328         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
2329         WREG32(SCRATCH_UMSK, 0xff);
2330         return 0;
2331 }
2332
2333 void r600_fence_ring_emit(struct radeon_device *rdev,
2334                           struct radeon_fence *fence)
2335 {
2336         /* Also consider EVENT_WRITE_EOP.  it handles the interrupts + timestamps + events */
2337
2338         radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2339         radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
2340         /* wait for 3D idle clean */
2341         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2342         radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2343         radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2344         /* Emit fence sequence & fire IRQ */
2345         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2346         radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2347         radeon_ring_write(rdev, fence->seq);
2348         /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2349         radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2350         radeon_ring_write(rdev, RB_INT_STAT);
2351 }
2352
2353 int r600_copy_blit(struct radeon_device *rdev,
2354                    uint64_t src_offset, uint64_t dst_offset,
2355                    unsigned num_pages, struct radeon_fence *fence)
2356 {
2357         int r;
2358
2359         mutex_lock(&rdev->r600_blit.mutex);
2360         rdev->r600_blit.vb_ib = NULL;
2361         r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2362         if (r) {
2363                 if (rdev->r600_blit.vb_ib)
2364                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2365                 mutex_unlock(&rdev->r600_blit.mutex);
2366                 return r;
2367         }
2368         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2369         r600_blit_done_copy(rdev, fence);
2370         mutex_unlock(&rdev->r600_blit.mutex);
2371         return 0;
2372 }
2373
2374 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2375                          uint32_t tiling_flags, uint32_t pitch,
2376                          uint32_t offset, uint32_t obj_size)
2377 {
2378         /* FIXME: implement */
2379         return 0;
2380 }
2381
2382 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2383 {
2384         /* FIXME: implement */
2385 }
2386
2387
2388 bool r600_card_posted(struct radeon_device *rdev)
2389 {
2390         uint32_t reg;
2391
2392         /* first check CRTCs */
2393         reg = RREG32(D1CRTC_CONTROL) |
2394                 RREG32(D2CRTC_CONTROL);
2395         if (reg & CRTC_EN)
2396                 return true;
2397
2398         /* then check MEM_SIZE, in case the crtcs are off */
2399         if (RREG32(CONFIG_MEMSIZE))
2400                 return true;
2401
2402         return false;
2403 }
2404
2405 int r600_startup(struct radeon_device *rdev)
2406 {
2407         int r;
2408
2409         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2410                 r = r600_init_microcode(rdev);
2411                 if (r) {
2412                         DRM_ERROR("Failed to load firmware!\n");
2413                         return r;
2414                 }
2415         }
2416
2417         r600_mc_program(rdev);
2418         if (rdev->flags & RADEON_IS_AGP) {
2419                 r600_agp_enable(rdev);
2420         } else {
2421                 r = r600_pcie_gart_enable(rdev);
2422                 if (r)
2423                         return r;
2424         }
2425         r600_gpu_init(rdev);
2426         r = r600_blit_init(rdev);
2427         if (r) {
2428                 r600_blit_fini(rdev);
2429                 rdev->asic->copy = NULL;
2430                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2431         }
2432         /* pin copy shader into vram */
2433         if (rdev->r600_blit.shader_obj) {
2434                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2435                 if (unlikely(r != 0))
2436                         return r;
2437                 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
2438                                 &rdev->r600_blit.shader_gpu_addr);
2439                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2440                 if (r) {
2441                         dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
2442                         return r;
2443                 }
2444         }
2445         /* Enable IRQ */
2446         r = r600_irq_init(rdev);
2447         if (r) {
2448                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2449                 radeon_irq_kms_fini(rdev);
2450                 return r;
2451         }
2452         r600_irq_set(rdev);
2453
2454         r = radeon_ring_init(rdev, rdev->cp.ring_size);
2455         if (r)
2456                 return r;
2457         r = r600_cp_load_microcode(rdev);
2458         if (r)
2459                 return r;
2460         r = r600_cp_resume(rdev);
2461         if (r)
2462                 return r;
2463         /* write back buffer are not vital so don't worry about failure */
2464         r600_wb_enable(rdev);
2465         return 0;
2466 }
2467
2468 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2469 {
2470         uint32_t temp;
2471
2472         temp = RREG32(CONFIG_CNTL);
2473         if (state == false) {
2474                 temp &= ~(1<<0);
2475                 temp |= (1<<1);
2476         } else {
2477                 temp &= ~(1<<1);
2478         }
2479         WREG32(CONFIG_CNTL, temp);
2480 }
2481
2482 int r600_resume(struct radeon_device *rdev)
2483 {
2484         int r;
2485
2486         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2487          * posting will perform necessary task to bring back GPU into good
2488          * shape.
2489          */
2490         /* post card */
2491         atom_asic_init(rdev->mode_info.atom_context);
2492         /* Initialize clocks */
2493         r = radeon_clocks_init(rdev);
2494         if (r) {
2495                 return r;
2496         }
2497
2498         r = r600_startup(rdev);
2499         if (r) {
2500                 DRM_ERROR("r600 startup failed on resume\n");
2501                 return r;
2502         }
2503
2504         r = r600_ib_test(rdev);
2505         if (r) {
2506                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2507                 return r;
2508         }
2509
2510         r = r600_audio_init(rdev);
2511         if (r) {
2512                 DRM_ERROR("radeon: audio resume failed\n");
2513                 return r;
2514         }
2515
2516         return r;
2517 }
2518
2519 int r600_suspend(struct radeon_device *rdev)
2520 {
2521         int r;
2522
2523         r600_audio_fini(rdev);
2524         /* FIXME: we should wait for ring to be empty */
2525         r600_cp_stop(rdev);
2526         rdev->cp.ready = false;
2527         r600_irq_suspend(rdev);
2528         r600_wb_disable(rdev);
2529         r600_pcie_gart_disable(rdev);
2530         /* unpin shaders bo */
2531         if (rdev->r600_blit.shader_obj) {
2532                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2533                 if (!r) {
2534                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
2535                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2536                 }
2537         }
2538         return 0;
2539 }
2540
2541 /* Plan is to move initialization in that function and use
2542  * helper function so that radeon_device_init pretty much
2543  * do nothing more than calling asic specific function. This
2544  * should also allow to remove a bunch of callback function
2545  * like vram_info.
2546  */
2547 int r600_init(struct radeon_device *rdev)
2548 {
2549         int r;
2550
2551         r = radeon_dummy_page_init(rdev);
2552         if (r)
2553                 return r;
2554         if (r600_debugfs_mc_info_init(rdev)) {
2555                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2556         }
2557         /* This don't do much */
2558         r = radeon_gem_init(rdev);
2559         if (r)
2560                 return r;
2561         /* Read BIOS */
2562         if (!radeon_get_bios(rdev)) {
2563                 if (ASIC_IS_AVIVO(rdev))
2564                         return -EINVAL;
2565         }
2566         /* Must be an ATOMBIOS */
2567         if (!rdev->is_atom_bios) {
2568                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2569                 return -EINVAL;
2570         }
2571         r = radeon_atombios_init(rdev);
2572         if (r)
2573                 return r;
2574         /* Post card if necessary */
2575         if (!r600_card_posted(rdev)) {
2576                 if (!rdev->bios) {
2577                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2578                         return -EINVAL;
2579                 }
2580                 DRM_INFO("GPU not posted. posting now...\n");
2581                 atom_asic_init(rdev->mode_info.atom_context);
2582         }
2583         /* Initialize scratch registers */
2584         r600_scratch_init(rdev);
2585         /* Initialize surface registers */
2586         radeon_surface_init(rdev);
2587         /* Initialize clocks */
2588         radeon_get_clock_info(rdev->ddev);
2589         r = radeon_clocks_init(rdev);
2590         if (r)
2591                 return r;
2592         /* Fence driver */
2593         r = radeon_fence_driver_init(rdev);
2594         if (r)
2595                 return r;
2596         if (rdev->flags & RADEON_IS_AGP) {
2597                 r = radeon_agp_init(rdev);
2598                 if (r)
2599                         radeon_agp_disable(rdev);
2600         }
2601         r = r600_mc_init(rdev);
2602         if (r)
2603                 return r;
2604         /* Memory manager */
2605         r = radeon_bo_init(rdev);
2606         if (r)
2607                 return r;
2608
2609         r = radeon_irq_kms_init(rdev);
2610         if (r)
2611                 return r;
2612
2613         rdev->cp.ring_obj = NULL;
2614         r600_ring_init(rdev, 1024 * 1024);
2615
2616         rdev->ih.ring_obj = NULL;
2617         r600_ih_ring_init(rdev, 64 * 1024);
2618
2619         r = r600_pcie_gart_init(rdev);
2620         if (r)
2621                 return r;
2622
2623         rdev->accel_working = true;
2624         r = r600_startup(rdev);
2625         if (r) {
2626                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2627                 r600_cp_fini(rdev);
2628                 r600_wb_fini(rdev);
2629                 r600_irq_fini(rdev);
2630                 radeon_irq_kms_fini(rdev);
2631                 r600_pcie_gart_fini(rdev);
2632                 rdev->accel_working = false;
2633         }
2634         if (rdev->accel_working) {
2635                 r = radeon_ib_pool_init(rdev);
2636                 if (r) {
2637                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2638                         rdev->accel_working = false;
2639                 } else {
2640                         r = r600_ib_test(rdev);
2641                         if (r) {
2642                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2643                                 rdev->accel_working = false;
2644                         }
2645                 }
2646         }
2647
2648         r = r600_audio_init(rdev);
2649         if (r)
2650                 return r; /* TODO error handling */
2651         return 0;
2652 }
2653
2654 void r600_fini(struct radeon_device *rdev)
2655 {
2656         r600_audio_fini(rdev);
2657         r600_blit_fini(rdev);
2658         r600_cp_fini(rdev);
2659         r600_wb_fini(rdev);
2660         r600_irq_fini(rdev);
2661         radeon_irq_kms_fini(rdev);
2662         r600_pcie_gart_fini(rdev);
2663         radeon_agp_fini(rdev);
2664         radeon_gem_fini(rdev);
2665         radeon_fence_driver_fini(rdev);
2666         radeon_clocks_fini(rdev);
2667         radeon_bo_fini(rdev);
2668         radeon_atombios_fini(rdev);
2669         kfree(rdev->bios);
2670         rdev->bios = NULL;
2671         radeon_dummy_page_fini(rdev);
2672 }
2673
2674
2675 /*
2676  * CS stuff
2677  */
2678 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2679 {
2680         /* FIXME: implement */
2681         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2682         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2683         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2684         radeon_ring_write(rdev, ib->length_dw);
2685 }
2686
2687 int r600_ib_test(struct radeon_device *rdev)
2688 {
2689         struct radeon_ib *ib;
2690         uint32_t scratch;
2691         uint32_t tmp = 0;
2692         unsigned i;
2693         int r;
2694
2695         r = radeon_scratch_get(rdev, &scratch);
2696         if (r) {
2697                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2698                 return r;
2699         }
2700         WREG32(scratch, 0xCAFEDEAD);
2701         r = radeon_ib_get(rdev, &ib);
2702         if (r) {
2703                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2704                 return r;
2705         }
2706         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2707         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2708         ib->ptr[2] = 0xDEADBEEF;
2709         ib->ptr[3] = PACKET2(0);
2710         ib->ptr[4] = PACKET2(0);
2711         ib->ptr[5] = PACKET2(0);
2712         ib->ptr[6] = PACKET2(0);
2713         ib->ptr[7] = PACKET2(0);
2714         ib->ptr[8] = PACKET2(0);
2715         ib->ptr[9] = PACKET2(0);
2716         ib->ptr[10] = PACKET2(0);
2717         ib->ptr[11] = PACKET2(0);
2718         ib->ptr[12] = PACKET2(0);
2719         ib->ptr[13] = PACKET2(0);
2720         ib->ptr[14] = PACKET2(0);
2721         ib->ptr[15] = PACKET2(0);
2722         ib->length_dw = 16;
2723         r = radeon_ib_schedule(rdev, ib);
2724         if (r) {
2725                 radeon_scratch_free(rdev, scratch);
2726                 radeon_ib_free(rdev, &ib);
2727                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2728                 return r;
2729         }
2730         r = radeon_fence_wait(ib->fence, false);
2731         if (r) {
2732                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2733                 return r;
2734         }
2735         for (i = 0; i < rdev->usec_timeout; i++) {
2736                 tmp = RREG32(scratch);
2737                 if (tmp == 0xDEADBEEF)
2738                         break;
2739                 DRM_UDELAY(1);
2740         }
2741         if (i < rdev->usec_timeout) {
2742                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2743         } else {
2744                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2745                           scratch, tmp);
2746                 r = -EINVAL;
2747         }
2748         radeon_scratch_free(rdev, scratch);
2749         radeon_ib_free(rdev, &ib);
2750         return r;
2751 }
2752
2753 /*
2754  * Interrupts
2755  *
2756  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2757  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2758  * writing to the ring and the GPU consuming, the GPU writes to the ring
2759  * and host consumes.  As the host irq handler processes interrupts, it
2760  * increments the rptr.  When the rptr catches up with the wptr, all the
2761  * current interrupts have been processed.
2762  */
2763
2764 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2765 {
2766         u32 rb_bufsz;
2767
2768         /* Align ring size */
2769         rb_bufsz = drm_order(ring_size / 4);
2770         ring_size = (1 << rb_bufsz) * 4;
2771         rdev->ih.ring_size = ring_size;
2772         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2773         rdev->ih.rptr = 0;
2774 }
2775
2776 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2777 {
2778         int r;
2779
2780         /* Allocate ring buffer */
2781         if (rdev->ih.ring_obj == NULL) {
2782                 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2783                                      true,
2784                                      RADEON_GEM_DOMAIN_GTT,
2785                                      &rdev->ih.ring_obj);
2786                 if (r) {
2787                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2788                         return r;
2789                 }
2790                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2791                 if (unlikely(r != 0))
2792                         return r;
2793                 r = radeon_bo_pin(rdev->ih.ring_obj,
2794                                   RADEON_GEM_DOMAIN_GTT,
2795                                   &rdev->ih.gpu_addr);
2796                 if (r) {
2797                         radeon_bo_unreserve(rdev->ih.ring_obj);
2798                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2799                         return r;
2800                 }
2801                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2802                                    (void **)&rdev->ih.ring);
2803                 radeon_bo_unreserve(rdev->ih.ring_obj);
2804                 if (r) {
2805                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2806                         return r;
2807                 }
2808         }
2809         return 0;
2810 }
2811
2812 static void r600_ih_ring_fini(struct radeon_device *rdev)
2813 {
2814         int r;
2815         if (rdev->ih.ring_obj) {
2816                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2817                 if (likely(r == 0)) {
2818                         radeon_bo_kunmap(rdev->ih.ring_obj);
2819                         radeon_bo_unpin(rdev->ih.ring_obj);
2820                         radeon_bo_unreserve(rdev->ih.ring_obj);
2821                 }
2822                 radeon_bo_unref(&rdev->ih.ring_obj);
2823                 rdev->ih.ring = NULL;
2824                 rdev->ih.ring_obj = NULL;
2825         }
2826 }
2827
2828 void r600_rlc_stop(struct radeon_device *rdev)
2829 {
2830
2831         if ((rdev->family >= CHIP_RV770) &&
2832             (rdev->family <= CHIP_RV740)) {
2833                 /* r7xx asics need to soft reset RLC before halting */
2834                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2835                 RREG32(SRBM_SOFT_RESET);
2836                 udelay(15000);
2837                 WREG32(SRBM_SOFT_RESET, 0);
2838                 RREG32(SRBM_SOFT_RESET);
2839         }
2840
2841         WREG32(RLC_CNTL, 0);
2842 }
2843
2844 static void r600_rlc_start(struct radeon_device *rdev)
2845 {
2846         WREG32(RLC_CNTL, RLC_ENABLE);
2847 }
2848
2849 static int r600_rlc_init(struct radeon_device *rdev)
2850 {
2851         u32 i;
2852         const __be32 *fw_data;
2853
2854         if (!rdev->rlc_fw)
2855                 return -EINVAL;
2856
2857         r600_rlc_stop(rdev);
2858
2859         WREG32(RLC_HB_BASE, 0);
2860         WREG32(RLC_HB_CNTL, 0);
2861         WREG32(RLC_HB_RPTR, 0);
2862         WREG32(RLC_HB_WPTR, 0);
2863         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2864         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2865         WREG32(RLC_MC_CNTL, 0);
2866         WREG32(RLC_UCODE_CNTL, 0);
2867
2868         fw_data = (const __be32 *)rdev->rlc_fw->data;
2869         if (rdev->family >= CHIP_CEDAR) {
2870                 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2871                         WREG32(RLC_UCODE_ADDR, i);
2872                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2873                 }
2874         } else if (rdev->family >= CHIP_RV770) {
2875                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2876                         WREG32(RLC_UCODE_ADDR, i);
2877                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2878                 }
2879         } else {
2880                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2881                         WREG32(RLC_UCODE_ADDR, i);
2882                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2883                 }
2884         }
2885         WREG32(RLC_UCODE_ADDR, 0);
2886
2887         r600_rlc_start(rdev);
2888
2889         return 0;
2890 }
2891
2892 static void r600_enable_interrupts(struct radeon_device *rdev)
2893 {
2894         u32 ih_cntl = RREG32(IH_CNTL);
2895         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2896
2897         ih_cntl |= ENABLE_INTR;
2898         ih_rb_cntl |= IH_RB_ENABLE;
2899         WREG32(IH_CNTL, ih_cntl);
2900         WREG32(IH_RB_CNTL, ih_rb_cntl);
2901         rdev->ih.enabled = true;
2902 }
2903
2904 void r600_disable_interrupts(struct radeon_device *rdev)
2905 {
2906         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2907         u32 ih_cntl = RREG32(IH_CNTL);
2908
2909         ih_rb_cntl &= ~IH_RB_ENABLE;
2910         ih_cntl &= ~ENABLE_INTR;
2911         WREG32(IH_RB_CNTL, ih_rb_cntl);
2912         WREG32(IH_CNTL, ih_cntl);
2913         /* set rptr, wptr to 0 */
2914         WREG32(IH_RB_RPTR, 0);
2915         WREG32(IH_RB_WPTR, 0);
2916         rdev->ih.enabled = false;
2917         rdev->ih.wptr = 0;
2918         rdev->ih.rptr = 0;
2919 }
2920
2921 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2922 {
2923         u32 tmp;
2924
2925         WREG32(CP_INT_CNTL, 0);
2926         WREG32(GRBM_INT_CNTL, 0);
2927         WREG32(DxMODE_INT_MASK, 0);
2928         if (ASIC_IS_DCE3(rdev)) {
2929                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2930                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2931                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2932                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2933                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2934                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2935                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2936                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2937                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2938                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2939                 if (ASIC_IS_DCE32(rdev)) {
2940                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2941                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2942                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2943                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2944                 }
2945         } else {
2946                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2947                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2948                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2949                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2950                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2951                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2952                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2953                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2954         }
2955 }
2956
2957 int r600_irq_init(struct radeon_device *rdev)
2958 {
2959         int ret = 0;
2960         int rb_bufsz;
2961         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2962
2963         /* allocate ring */
2964         ret = r600_ih_ring_alloc(rdev);
2965         if (ret)
2966                 return ret;
2967
2968         /* disable irqs */
2969         r600_disable_interrupts(rdev);
2970
2971         /* init rlc */
2972         ret = r600_rlc_init(rdev);
2973         if (ret) {
2974                 r600_ih_ring_fini(rdev);
2975                 return ret;
2976         }
2977
2978         /* setup interrupt control */
2979         /* set dummy read address to ring address */
2980         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2981         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2982         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2983          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2984          */
2985         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2986         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2987         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2988         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2989
2990         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2991         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2992
2993         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2994                       IH_WPTR_OVERFLOW_CLEAR |
2995                       (rb_bufsz << 1));
2996         /* WPTR writeback, not yet */
2997         /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2998         WREG32(IH_RB_WPTR_ADDR_LO, 0);
2999         WREG32(IH_RB_WPTR_ADDR_HI, 0);
3000
3001         WREG32(IH_RB_CNTL, ih_rb_cntl);
3002
3003         /* set rptr, wptr to 0 */
3004         WREG32(IH_RB_RPTR, 0);
3005         WREG32(IH_RB_WPTR, 0);
3006
3007         /* Default settings for IH_CNTL (disabled at first) */
3008         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3009         /* RPTR_REARM only works if msi's are enabled */
3010         if (rdev->msi_enabled)
3011                 ih_cntl |= RPTR_REARM;
3012
3013 #ifdef __BIG_ENDIAN
3014         ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
3015 #endif
3016         WREG32(IH_CNTL, ih_cntl);
3017
3018         /* force the active interrupt state to all disabled */
3019         if (rdev->family >= CHIP_CEDAR)
3020                 evergreen_disable_interrupt_state(rdev);
3021         else
3022                 r600_disable_interrupt_state(rdev);
3023
3024         /* enable irqs */
3025         r600_enable_interrupts(rdev);
3026
3027         return ret;
3028 }
3029
3030 void r600_irq_suspend(struct radeon_device *rdev)
3031 {
3032         r600_irq_disable(rdev);
3033         r600_rlc_stop(rdev);
3034 }
3035
3036 void r600_irq_fini(struct radeon_device *rdev)
3037 {
3038         r600_irq_suspend(rdev);
3039         r600_ih_ring_fini(rdev);
3040 }
3041
3042 int r600_irq_set(struct radeon_device *rdev)
3043 {
3044         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3045         u32 mode_int = 0;
3046         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3047         u32 grbm_int_cntl = 0;
3048         u32 hdmi1, hdmi2;
3049
3050         if (!rdev->irq.installed) {
3051                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
3052                 return -EINVAL;
3053         }
3054         /* don't enable anything if the ih is disabled */
3055         if (!rdev->ih.enabled) {
3056                 r600_disable_interrupts(rdev);
3057                 /* force the active interrupt state to all disabled */
3058                 r600_disable_interrupt_state(rdev);
3059                 return 0;
3060         }
3061
3062         hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3063         if (ASIC_IS_DCE3(rdev)) {
3064                 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3065                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3066                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3067                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3068                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3069                 if (ASIC_IS_DCE32(rdev)) {
3070                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3071                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3072                 }
3073         } else {
3074                 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3075                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3076                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3077                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3078         }
3079
3080         if (rdev->irq.sw_int) {
3081                 DRM_DEBUG("r600_irq_set: sw int\n");
3082                 cp_int_cntl |= RB_INT_ENABLE;
3083         }
3084         if (rdev->irq.crtc_vblank_int[0]) {
3085                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3086                 mode_int |= D1MODE_VBLANK_INT_MASK;
3087         }
3088         if (rdev->irq.crtc_vblank_int[1]) {
3089                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3090                 mode_int |= D2MODE_VBLANK_INT_MASK;
3091         }
3092         if (rdev->irq.hpd[0]) {
3093                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3094                 hpd1 |= DC_HPDx_INT_EN;
3095         }
3096         if (rdev->irq.hpd[1]) {
3097                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3098                 hpd2 |= DC_HPDx_INT_EN;
3099         }
3100         if (rdev->irq.hpd[2]) {
3101                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3102                 hpd3 |= DC_HPDx_INT_EN;
3103         }
3104         if (rdev->irq.hpd[3]) {
3105                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3106                 hpd4 |= DC_HPDx_INT_EN;
3107         }
3108         if (rdev->irq.hpd[4]) {
3109                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3110                 hpd5 |= DC_HPDx_INT_EN;
3111         }
3112         if (rdev->irq.hpd[5]) {
3113                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3114                 hpd6 |= DC_HPDx_INT_EN;
3115         }
3116         if (rdev->irq.hdmi[0]) {
3117                 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3118                 hdmi1 |= R600_HDMI_INT_EN;
3119         }
3120         if (rdev->irq.hdmi[1]) {
3121                 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3122                 hdmi2 |= R600_HDMI_INT_EN;
3123         }
3124         if (rdev->irq.gui_idle) {
3125                 DRM_DEBUG("gui idle\n");
3126                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3127         }
3128
3129         WREG32(CP_INT_CNTL, cp_int_cntl);
3130         WREG32(DxMODE_INT_MASK, mode_int);
3131         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3132         WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
3133         if (ASIC_IS_DCE3(rdev)) {
3134                 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
3135                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3136                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3137                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3138                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3139                 if (ASIC_IS_DCE32(rdev)) {
3140                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3141                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3142                 }
3143         } else {
3144                 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
3145                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3146                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3147                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3148         }
3149
3150         return 0;
3151 }
3152
3153 static inline void r600_irq_ack(struct radeon_device *rdev,
3154                                 u32 *disp_int,
3155                                 u32 *disp_int_cont,
3156                                 u32 *disp_int_cont2)
3157 {
3158         u32 tmp;
3159
3160         if (ASIC_IS_DCE3(rdev)) {
3161                 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3162                 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3163                 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3164         } else {
3165                 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
3166                 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3167                 *disp_int_cont2 = 0;
3168         }
3169
3170         if (*disp_int & LB_D1_VBLANK_INTERRUPT)
3171                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3172         if (*disp_int & LB_D1_VLINE_INTERRUPT)
3173                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3174         if (*disp_int & LB_D2_VBLANK_INTERRUPT)
3175                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3176         if (*disp_int & LB_D2_VLINE_INTERRUPT)
3177                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3178         if (*disp_int & DC_HPD1_INTERRUPT) {
3179                 if (ASIC_IS_DCE3(rdev)) {
3180                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3181                         tmp |= DC_HPDx_INT_ACK;
3182                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3183                 } else {
3184                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3185                         tmp |= DC_HPDx_INT_ACK;
3186                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3187                 }
3188         }
3189         if (*disp_int & DC_HPD2_INTERRUPT) {
3190                 if (ASIC_IS_DCE3(rdev)) {
3191                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3192                         tmp |= DC_HPDx_INT_ACK;
3193                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3194                 } else {
3195                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3196                         tmp |= DC_HPDx_INT_ACK;
3197                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3198                 }
3199         }
3200         if (*disp_int_cont & DC_HPD3_INTERRUPT) {
3201                 if (ASIC_IS_DCE3(rdev)) {
3202                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3203                         tmp |= DC_HPDx_INT_ACK;
3204                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3205                 } else {
3206                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3207                         tmp |= DC_HPDx_INT_ACK;
3208                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3209                 }
3210         }
3211         if (*disp_int_cont & DC_HPD4_INTERRUPT) {
3212                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3213                 tmp |= DC_HPDx_INT_ACK;
3214                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3215         }
3216         if (ASIC_IS_DCE32(rdev)) {
3217                 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
3218                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3219                         tmp |= DC_HPDx_INT_ACK;
3220                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3221                 }
3222                 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
3223                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3224                         tmp |= DC_HPDx_INT_ACK;
3225                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3226                 }
3227         }
3228         if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3229                 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3230         }
3231         if (ASIC_IS_DCE3(rdev)) {
3232                 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3233                         WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3234                 }
3235         } else {
3236                 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3237                         WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3238                 }
3239         }
3240 }
3241
3242 void r600_irq_disable(struct radeon_device *rdev)
3243 {
3244         u32 disp_int, disp_int_cont, disp_int_cont2;
3245
3246         r600_disable_interrupts(rdev);
3247         /* Wait and acknowledge irq */
3248         mdelay(1);
3249         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3250         r600_disable_interrupt_state(rdev);
3251 }
3252
3253 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3254 {
3255         u32 wptr, tmp;
3256
3257         /* XXX use writeback */
3258         wptr = RREG32(IH_RB_WPTR);
3259
3260         if (wptr & RB_OVERFLOW) {
3261                 /* When a ring buffer overflow happen start parsing interrupt
3262                  * from the last not overwritten vector (wptr + 16). Hopefully
3263                  * this should allow us to catchup.
3264                  */
3265                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3266                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3267                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3268                 tmp = RREG32(IH_RB_CNTL);
3269                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3270                 WREG32(IH_RB_CNTL, tmp);
3271         }
3272         return (wptr & rdev->ih.ptr_mask);
3273 }
3274
3275 /*        r600 IV Ring
3276  * Each IV ring entry is 128 bits:
3277  * [7:0]    - interrupt source id
3278  * [31:8]   - reserved
3279  * [59:32]  - interrupt source data
3280  * [127:60]  - reserved
3281  *
3282  * The basic interrupt vector entries
3283  * are decoded as follows:
3284  * src_id  src_data  description
3285  *      1         0  D1 Vblank
3286  *      1         1  D1 Vline
3287  *      5         0  D2 Vblank
3288  *      5         1  D2 Vline
3289  *     19         0  FP Hot plug detection A
3290  *     19         1  FP Hot plug detection B
3291  *     19         2  DAC A auto-detection
3292  *     19         3  DAC B auto-detection
3293  *     21         4  HDMI block A
3294  *     21         5  HDMI block B
3295  *    176         -  CP_INT RB
3296  *    177         -  CP_INT IB1
3297  *    178         -  CP_INT IB2
3298  *    181         -  EOP Interrupt
3299  *    233         -  GUI Idle
3300  *
3301  * Note, these are based on r600 and may need to be
3302  * adjusted or added to on newer asics
3303  */
3304
3305 int r600_irq_process(struct radeon_device *rdev)
3306 {
3307         u32 wptr = r600_get_ih_wptr(rdev);
3308         u32 rptr = rdev->ih.rptr;
3309         u32 src_id, src_data;
3310         u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
3311         unsigned long flags;
3312         bool queue_hotplug = false;
3313
3314         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3315         if (!rdev->ih.enabled)
3316                 return IRQ_NONE;
3317
3318         spin_lock_irqsave(&rdev->ih.lock, flags);
3319
3320         if (rptr == wptr) {
3321                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3322                 return IRQ_NONE;
3323         }
3324         if (rdev->shutdown) {
3325                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3326                 return IRQ_NONE;
3327         }
3328
3329 restart_ih:
3330         /* display interrupts */
3331         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3332
3333         rdev->ih.wptr = wptr;
3334         while (rptr != wptr) {
3335                 /* wptr/rptr are in bytes! */
3336                 ring_index = rptr / 4;
3337                 src_id =  rdev->ih.ring[ring_index] & 0xff;
3338                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3339
3340                 switch (src_id) {
3341                 case 1: /* D1 vblank/vline */
3342                         switch (src_data) {
3343                         case 0: /* D1 vblank */
3344                                 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
3345                                         drm_handle_vblank(rdev->ddev, 0);
3346                                         rdev->pm.vblank_sync = true;
3347                                         wake_up(&rdev->irq.vblank_queue);
3348                                         disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3349                                         DRM_DEBUG("IH: D1 vblank\n");
3350                                 }
3351                                 break;
3352                         case 1: /* D1 vline */
3353                                 if (disp_int & LB_D1_VLINE_INTERRUPT) {
3354                                         disp_int &= ~LB_D1_VLINE_INTERRUPT;
3355                                         DRM_DEBUG("IH: D1 vline\n");
3356                                 }
3357                                 break;
3358                         default:
3359                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3360                                 break;
3361                         }
3362                         break;
3363                 case 5: /* D2 vblank/vline */
3364                         switch (src_data) {
3365                         case 0: /* D2 vblank */
3366                                 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
3367                                         drm_handle_vblank(rdev->ddev, 1);
3368                                         rdev->pm.vblank_sync = true;
3369                                         wake_up(&rdev->irq.vblank_queue);
3370                                         disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3371                                         DRM_DEBUG("IH: D2 vblank\n");
3372                                 }
3373                                 break;
3374                         case 1: /* D1 vline */
3375                                 if (disp_int & LB_D2_VLINE_INTERRUPT) {
3376                                         disp_int &= ~LB_D2_VLINE_INTERRUPT;
3377                                         DRM_DEBUG("IH: D2 vline\n");
3378                                 }
3379                                 break;
3380                         default:
3381                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3382                                 break;
3383                         }
3384                         break;
3385                 case 19: /* HPD/DAC hotplug */
3386                         switch (src_data) {
3387                         case 0:
3388                                 if (disp_int & DC_HPD1_INTERRUPT) {
3389                                         disp_int &= ~DC_HPD1_INTERRUPT;
3390                                         queue_hotplug = true;
3391                                         DRM_DEBUG("IH: HPD1\n");
3392                                 }
3393                                 break;
3394                         case 1:
3395                                 if (disp_int & DC_HPD2_INTERRUPT) {
3396                                         disp_int &= ~DC_HPD2_INTERRUPT;
3397                                         queue_hotplug = true;
3398                                         DRM_DEBUG("IH: HPD2\n");
3399                                 }
3400                                 break;
3401                         case 4:
3402                                 if (disp_int_cont & DC_HPD3_INTERRUPT) {
3403                                         disp_int_cont &= ~DC_HPD3_INTERRUPT;
3404                                         queue_hotplug = true;
3405                                         DRM_DEBUG("IH: HPD3\n");
3406                                 }
3407                                 break;
3408                         case 5:
3409                                 if (disp_int_cont & DC_HPD4_INTERRUPT) {
3410                                         disp_int_cont &= ~DC_HPD4_INTERRUPT;
3411                                         queue_hotplug = true;
3412                                         DRM_DEBUG("IH: HPD4\n");
3413                                 }
3414                                 break;
3415                         case 10:
3416                                 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
3417                                         disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3418                                         queue_hotplug = true;
3419                                         DRM_DEBUG("IH: HPD5\n");
3420                                 }
3421                                 break;
3422                         case 12:
3423                                 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
3424                                         disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3425                                         queue_hotplug = true;
3426                                         DRM_DEBUG("IH: HPD6\n");
3427                                 }
3428                                 break;
3429                         default:
3430                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3431                                 break;
3432                         }
3433                         break;
3434                 case 21: /* HDMI */
3435                         DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3436                         r600_audio_schedule_polling(rdev);
3437                         break;
3438                 case 176: /* CP_INT in ring buffer */
3439                 case 177: /* CP_INT in IB1 */
3440                 case 178: /* CP_INT in IB2 */
3441                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3442                         radeon_fence_process(rdev);
3443                         break;
3444                 case 181: /* CP EOP event */
3445                         DRM_DEBUG("IH: CP EOP\n");
3446                         break;
3447                 case 233: /* GUI IDLE */
3448                         DRM_DEBUG("IH: CP EOP\n");
3449                         rdev->pm.gui_idle = true;
3450                         wake_up(&rdev->irq.idle_queue);
3451                         break;
3452                 default:
3453                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3454                         break;
3455                 }
3456
3457                 /* wptr/rptr are in bytes! */
3458                 rptr += 16;
3459                 rptr &= rdev->ih.ptr_mask;
3460         }
3461         /* make sure wptr hasn't changed while processing */
3462         wptr = r600_get_ih_wptr(rdev);
3463         if (wptr != rdev->ih.wptr)
3464                 goto restart_ih;
3465         if (queue_hotplug)
3466                 queue_work(rdev->wq, &rdev->hotplug_work);
3467         rdev->ih.rptr = rptr;
3468         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3469         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3470         return IRQ_HANDLED;
3471 }
3472
3473 /*
3474  * Debugfs info
3475  */
3476 #if defined(CONFIG_DEBUG_FS)
3477
3478 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
3479 {
3480         struct drm_info_node *node = (struct drm_info_node *) m->private;
3481         struct drm_device *dev = node->minor->dev;
3482         struct radeon_device *rdev = dev->dev_private;
3483         unsigned count, i, j;
3484
3485         radeon_ring_free_size(rdev);
3486         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3487         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
3488         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3489         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3490         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3491         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3492         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3493         seq_printf(m, "%u dwords in ring\n", count);
3494         i = rdev->cp.rptr;
3495         for (j = 0; j <= count; j++) {
3496                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
3497                 i = (i + 1) & rdev->cp.ptr_mask;
3498         }
3499         return 0;
3500 }
3501
3502 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3503 {
3504         struct drm_info_node *node = (struct drm_info_node *) m->private;
3505         struct drm_device *dev = node->minor->dev;
3506         struct radeon_device *rdev = dev->dev_private;
3507
3508         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3509         DREG32_SYS(m, rdev, VM_L2_STATUS);
3510         return 0;
3511 }
3512
3513 static struct drm_info_list r600_mc_info_list[] = {
3514         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3515         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3516 };
3517 #endif
3518
3519 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3520 {
3521 #if defined(CONFIG_DEBUG_FS)
3522         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3523 #else
3524         return 0;
3525 #endif
3526 }
3527
3528 /**
3529  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3530  * rdev: radeon device structure
3531  * bo: buffer object struct which userspace is waiting for idle
3532  *
3533  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3534  * through ring buffer, this leads to corruption in rendering, see
3535  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3536  * directly perform HDP flush by writing register through MMIO.
3537  */
3538 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3539 {
3540         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
3541          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
3542          */
3543         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) {
3544                 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
3545                 u32 tmp;
3546
3547                 WREG32(HDP_DEBUG1, 0);
3548                 tmp = readl((void __iomem *)ptr);
3549         } else
3550                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3551 }