drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "radeon_drm.h"
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "r100d.h"
  37 #include "rs100d.h"
  38 #include "rv200d.h"
  39 #include "rv250d.h"
  40 #include "atom.h"
  41
  42 #include <linux/firmware.h>
  43 #include <linux/platform_device.h>
  44
  45 #include "r100_reg_safe.h"
  46 #include "rn50_reg_safe.h"
  47
  48 /* Firmware Names */
  49 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  50 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  51 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  52 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  53 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  54 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  55 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  56
  57 MODULE_FIRMWARE(FIRMWARE_R100);
  58 MODULE_FIRMWARE(FIRMWARE_R200);
  59 MODULE_FIRMWARE(FIRMWARE_R300);
  60 MODULE_FIRMWARE(FIRMWARE_R420);
  61 MODULE_FIRMWARE(FIRMWARE_RS690);
  62 MODULE_FIRMWARE(FIRMWARE_RS600);
  63 MODULE_FIRMWARE(FIRMWARE_R520);
  64
  65 #include "r100_track.h"
  66
  67 /* This files gather functions specifics to:
  68  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  69  */
  70
  71 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
  72 {
  73         int i;
  74         rdev->pm.dynpm_can_upclock = true;
  75         rdev->pm.dynpm_can_downclock = true;
  76
  77         switch (rdev->pm.dynpm_planned_action) {
  78         case DYNPM_ACTION_MINIMUM:
  79                 rdev->pm.requested_power_state_index = 0;
  80                 rdev->pm.dynpm_can_downclock = false;
  81                 break;
  82         case DYNPM_ACTION_DOWNCLOCK:
  83                 if (rdev->pm.current_power_state_index == 0) {
  84                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
  85                         rdev->pm.dynpm_can_downclock = false;
  86                 } else {
  87                         if (rdev->pm.active_crtc_count > 1) {
  88                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
  89                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
  90                                                 continue;
  91                                         else if (i >= rdev->pm.current_power_state_index) {
  92                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
  93                                                 break;
  94                                         } else {
  95                                                 rdev->pm.requested_power_state_index = i;
  96                                                 break;
  97                                         }
  98                                 }
  99                         } else
 100                                 rdev->pm.requested_power_state_index =
 101                                         rdev->pm.current_power_state_index - 1;
 102                 }
 103                 /* don't use the power state if crtcs are active and no display flag is set */
 104                 if ((rdev->pm.active_crtc_count > 0) &&
 105                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
 106                      RADEON_PM_MODE_NO_DISPLAY)) {
 107                         rdev->pm.requested_power_state_index++;
 108                 }
 109                 break;
 110         case DYNPM_ACTION_UPCLOCK:
 111                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 112                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 113                         rdev->pm.dynpm_can_upclock = false;
 114                 } else {
 115                         if (rdev->pm.active_crtc_count > 1) {
 116                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 117                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 118                                                 continue;
 119                                         else if (i <= rdev->pm.current_power_state_index) {
 120                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 121                                                 break;
 122                                         } else {
 123                                                 rdev->pm.requested_power_state_index = i;
 124                                                 break;
 125                                         }
 126                                 }
 127                         } else
 128                                 rdev->pm.requested_power_state_index =
 129                                         rdev->pm.current_power_state_index + 1;
 130                 }
 131                 break;
 132         case DYNPM_ACTION_DEFAULT:
 133                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 134                 rdev->pm.dynpm_can_upclock = false;
 135                 break;
 136         case DYNPM_ACTION_NONE:
 137         default:
 138                 DRM_ERROR("Requested mode for not defined action\n");
 139                 return;
 140         }
 141         /* only one clock mode per power state */
 142         rdev->pm.requested_clock_mode_index = 0;
 143
 144         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 145                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 146                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 147                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 148                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 149                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 150                   pcie_lanes);
 151 }
 152
 153 void r100_pm_init_profile(struct radeon_device *rdev)
 154 {
 155         /* default */
 156         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 157         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 158         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 159         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 160         /* low sh */
 161         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 162         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 163         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 164         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 165         /* mid sh */
 166         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 167         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 168         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 169         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 170         /* high sh */
 171         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 172         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 173         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 174         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 175         /* low mh */
 176         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 177         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 178         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 179         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 180         /* mid mh */
 181         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 182         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 183         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 184         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 185         /* high mh */
 186         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 187         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 188         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 189         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 190 }
 191
 192 void r100_pm_misc(struct radeon_device *rdev)
 193 {
 194         int requested_index = rdev->pm.requested_power_state_index;
 195         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 196         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 197         u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
 198
 199         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 200                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 201                         tmp = RREG32(voltage->gpio.reg);
 202                         if (voltage->active_high)
 203                                 tmp |= voltage->gpio.mask;
 204                         else
 205                                 tmp &= ~(voltage->gpio.mask);
 206                         WREG32(voltage->gpio.reg, tmp);
 207                         if (voltage->delay)
 208                                 udelay(voltage->delay);
 209                 } else {
 210                         tmp = RREG32(voltage->gpio.reg);
 211                         if (voltage->active_high)
 212                                 tmp &= ~voltage->gpio.mask;
 213                         else
 214                                 tmp |= voltage->gpio.mask;
 215                         WREG32(voltage->gpio.reg, tmp);
 216                         if (voltage->delay)
 217                                 udelay(voltage->delay);
 218                 }
 219         }
 220
 221         sclk_cntl = RREG32_PLL(SCLK_CNTL);
 222         sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
 223         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
 224         sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
 225         sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
 226         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 227                 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
 228                 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
 229                         sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
 230                 else
 231                         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
 232                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
 233                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
 234                 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
 235                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
 236         } else
 237                 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
 238
 239         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 240                 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
 241                 if (voltage->delay) {
 242                         sclk_more_cntl |= VOLTAGE_DROP_SYNC;
 243                         switch (voltage->delay) {
 244                         case 33:
 245                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
 246                                 break;
 247                         case 66:
 248                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
 249                                 break;
 250                         case 99:
 251                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
 252                                 break;
 253                         case 132:
 254                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
 255                                 break;
 256                         }
 257                 } else
 258                         sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
 259         } else
 260                 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
 261
 262         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 263                 sclk_cntl &= ~FORCE_HDP;
 264         else
 265                 sclk_cntl |= FORCE_HDP;
 266
 267         WREG32_PLL(SCLK_CNTL, sclk_cntl);
 268         WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
 269         WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
 270
 271         /* set pcie lanes */
 272         if ((rdev->flags & RADEON_IS_PCIE) &&
 273             !(rdev->flags & RADEON_IS_IGP) &&
 274             rdev->asic->set_pcie_lanes &&
 275             (ps->pcie_lanes !=
 276              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 277                 radeon_set_pcie_lanes(rdev,
 278                                       ps->pcie_lanes);
 279                 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
 280         }
 281 }
 282
 283 void r100_pm_prepare(struct radeon_device *rdev)
 284 {
 285         struct drm_device *ddev = rdev->ddev;
 286         struct drm_crtc *crtc;
 287         struct radeon_crtc *radeon_crtc;
 288         u32 tmp;
 289
 290         /* disable any active CRTCs */
 291         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 292                 radeon_crtc = to_radeon_crtc(crtc);
 293                 if (radeon_crtc->enabled) {
 294                         if (radeon_crtc->crtc_id) {
 295                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 296                                 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
 297                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 298                         } else {
 299                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 300                                 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
 301                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 302                         }
 303                 }
 304         }
 305 }
 306
 307 void r100_pm_finish(struct radeon_device *rdev)
 308 {
 309         struct drm_device *ddev = rdev->ddev;
 310         struct drm_crtc *crtc;
 311         struct radeon_crtc *radeon_crtc;
 312         u32 tmp;
 313
 314         /* enable any active CRTCs */
 315         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 316                 radeon_crtc = to_radeon_crtc(crtc);
 317                 if (radeon_crtc->enabled) {
 318                         if (radeon_crtc->crtc_id) {
 319                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 320                                 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
 321                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 322                         } else {
 323                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 324                                 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
 325                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 326                         }
 327                 }
 328         }
 329 }
 330
 331 bool r100_gui_idle(struct radeon_device *rdev)
 332 {
 333         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
 334                 return false;
 335         else
 336                 return true;
 337 }
 338
 339 /* hpd for digital panel detect/disconnect */
 340 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 341 {
 342         bool connected = false;
 343
 344         switch (hpd) {
 345         case RADEON_HPD_1:
 346                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
 347                         connected = true;
 348                 break;
 349         case RADEON_HPD_2:
 350                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
 351                         connected = true;
 352                 break;
 353         default:
 354                 break;
 355         }
 356         return connected;
 357 }
 358
 359 void r100_hpd_set_polarity(struct radeon_device *rdev,
 360                            enum radeon_hpd_id hpd)
 361 {
 362         u32 tmp;
 363         bool connected = r100_hpd_sense(rdev, hpd);
 364
 365         switch (hpd) {
 366         case RADEON_HPD_1:
 367                 tmp = RREG32(RADEON_FP_GEN_CNTL);
 368                 if (connected)
 369                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 370                 else
 371                         tmp |= RADEON_FP_DETECT_INT_POL;
 372                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 373                 break;
 374         case RADEON_HPD_2:
 375                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 376                 if (connected)
 377                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 378                 else
 379                         tmp |= RADEON_FP2_DETECT_INT_POL;
 380                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 381                 break;
 382         default:
 383                 break;
 384         }
 385 }
 386
 387 void r100_hpd_init(struct radeon_device *rdev)
 388 {
 389         struct drm_device *dev = rdev->ddev;
 390         struct drm_connector *connector;
 391
 392         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 393                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 394                 switch (radeon_connector->hpd.hpd) {
 395                 case RADEON_HPD_1:
 396                         rdev->irq.hpd[0] = true;
 397                         break;
 398                 case RADEON_HPD_2:
 399                         rdev->irq.hpd[1] = true;
 400                         break;
 401                 default:
 402                         break;
 403                 }
 404         }
 405         if (rdev->irq.installed)
 406                 r100_irq_set(rdev);
 407 }
 408
 409 void r100_hpd_fini(struct radeon_device *rdev)
 410 {
 411         struct drm_device *dev = rdev->ddev;
 412         struct drm_connector *connector;
 413
 414         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 415                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 416                 switch (radeon_connector->hpd.hpd) {
 417                 case RADEON_HPD_1:
 418                         rdev->irq.hpd[0] = false;
 419                         break;
 420                 case RADEON_HPD_2:
 421                         rdev->irq.hpd[1] = false;
 422                         break;
 423                 default:
 424                         break;
 425                 }
 426         }
 427 }
 428
 429 /*
 430  * PCI GART
 431  */
 432 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 433 {
 434         /* TODO: can we do somethings here ? */
 435         /* It seems hw only cache one entry so we should discard this
 436          * entry otherwise if first GPU GART read hit this entry it
 437          * could end up in wrong address. */
 438 }
 439
 440 int r100_pci_gart_init(struct radeon_device *rdev)
 441 {
 442         int r;
 443
 444         if (rdev->gart.table.ram.ptr) {
 445                 WARN(1, "R100 PCI GART already initialized.\n");
 446                 return 0;
 447         }
 448         /* Initialize common gart structure */
 449         r = radeon_gart_init(rdev);
 450         if (r)
 451                 return r;
 452         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 453         rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 454         rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 455         return radeon_gart_table_ram_alloc(rdev);
 456 }
 457
 458 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 459 void r100_enable_bm(struct radeon_device *rdev)
 460 {
 461         uint32_t tmp;
 462         /* Enable bus mastering */
 463         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 464         WREG32(RADEON_BUS_CNTL, tmp);
 465 }
 466
 467 int r100_pci_gart_enable(struct radeon_device *rdev)
 468 {
 469         uint32_t tmp;
 470
 471         radeon_gart_restore(rdev);
 472         /* discard memory request outside of configured range */
 473         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 474         WREG32(RADEON_AIC_CNTL, tmp);
 475         /* set address range for PCI address translate */
 476         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 477         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 478         /* set PCI GART page-table base address */
 479         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 480         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 481         WREG32(RADEON_AIC_CNTL, tmp);
 482         r100_pci_gart_tlb_flush(rdev);
 483         rdev->gart.ready = true;
 484         return 0;
 485 }
 486
 487 void r100_pci_gart_disable(struct radeon_device *rdev)
 488 {
 489         uint32_t tmp;
 490
 491         /* discard memory request outside of configured range */
 492         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 493         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 494         WREG32(RADEON_AIC_LO_ADDR, 0);
 495         WREG32(RADEON_AIC_HI_ADDR, 0);
 496 }
 497
 498 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 499 {
 500         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 501                 return -EINVAL;
 502         }
 503         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
 504         return 0;
 505 }
 506
 507 void r100_pci_gart_fini(struct radeon_device *rdev)
 508 {
 509         radeon_gart_fini(rdev);
 510         r100_pci_gart_disable(rdev);
 511         radeon_gart_table_ram_free(rdev);
 512 }
 513
 514 int r100_irq_set(struct radeon_device *rdev)
 515 {
 516         uint32_t tmp = 0;
 517
 518         if (!rdev->irq.installed) {
 519                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
 520                 WREG32(R_000040_GEN_INT_CNTL, 0);
 521                 return -EINVAL;
 522         }
 523         if (rdev->irq.sw_int) {
 524                 tmp |= RADEON_SW_INT_ENABLE;
 525         }
 526         if (rdev->irq.gui_idle) {
 527                 tmp |= RADEON_GUI_IDLE_MASK;
 528         }
 529         if (rdev->irq.crtc_vblank_int[0]) {
 530                 tmp |= RADEON_CRTC_VBLANK_MASK;
 531         }
 532         if (rdev->irq.crtc_vblank_int[1]) {
 533                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 534         }
 535         if (rdev->irq.hpd[0]) {
 536                 tmp |= RADEON_FP_DETECT_MASK;
 537         }
 538         if (rdev->irq.hpd[1]) {
 539                 tmp |= RADEON_FP2_DETECT_MASK;
 540         }
 541         WREG32(RADEON_GEN_INT_CNTL, tmp);
 542         return 0;
 543 }
 544
 545 void r100_irq_disable(struct radeon_device *rdev)
 546 {
 547         u32 tmp;
 548
 549         WREG32(R_000040_GEN_INT_CNTL, 0);
 550         /* Wait and acknowledge irq */
 551         mdelay(1);
 552         tmp = RREG32(R_000044_GEN_INT_STATUS);
 553         WREG32(R_000044_GEN_INT_STATUS, tmp);
 554 }
 555
 556 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
 557 {
 558         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 559         uint32_t irq_mask = RADEON_SW_INT_TEST |
 560                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 561                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 562
 563         /* the interrupt works, but the status bit is permanently asserted */
 564         if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
 565                 if (!rdev->irq.gui_idle_acked)
 566                         irq_mask |= RADEON_GUI_IDLE_STAT;
 567         }
 568
 569         if (irqs) {
 570                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 571         }
 572         return irqs & irq_mask;
 573 }
 574
 575 int r100_irq_process(struct radeon_device *rdev)
 576 {
 577         uint32_t status, msi_rearm;
 578         bool queue_hotplug = false;
 579
 580         /* reset gui idle ack.  the status bit is broken */
 581         rdev->irq.gui_idle_acked = false;
 582
 583         status = r100_irq_ack(rdev);
 584         if (!status) {
 585                 return IRQ_NONE;
 586         }
 587         if (rdev->shutdown) {
 588                 return IRQ_NONE;
 589         }
 590         while (status) {
 591                 /* SW interrupt */
 592                 if (status & RADEON_SW_INT_TEST) {
 593                         radeon_fence_process(rdev);
 594                 }
 595                 /* gui idle interrupt */
 596                 if (status & RADEON_GUI_IDLE_STAT) {
 597                         rdev->irq.gui_idle_acked = true;
 598                         rdev->pm.gui_idle = true;
 599                         wake_up(&rdev->irq.idle_queue);
 600                 }
 601                 /* Vertical blank interrupts */
 602                 if (status & RADEON_CRTC_VBLANK_STAT) {
 603                         drm_handle_vblank(rdev->ddev, 0);
 604                         rdev->pm.vblank_sync = true;
 605                         wake_up(&rdev->irq.vblank_queue);
 606                 }
 607                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 608                         drm_handle_vblank(rdev->ddev, 1);
 609                         rdev->pm.vblank_sync = true;
 610                         wake_up(&rdev->irq.vblank_queue);
 611                 }
 612                 if (status & RADEON_FP_DETECT_STAT) {
 613                         queue_hotplug = true;
 614                         DRM_DEBUG("HPD1\n");
 615                 }
 616                 if (status & RADEON_FP2_DETECT_STAT) {
 617                         queue_hotplug = true;
 618                         DRM_DEBUG("HPD2\n");
 619                 }
 620                 status = r100_irq_ack(rdev);
 621         }
 622         /* reset gui idle ack.  the status bit is broken */
 623         rdev->irq.gui_idle_acked = false;
 624         if (queue_hotplug)
 625                 queue_work(rdev->wq, &rdev->hotplug_work);
 626         if (rdev->msi_enabled) {
 627                 switch (rdev->family) {
 628                 case CHIP_RS400:
 629                 case CHIP_RS480:
 630                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 631                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 632                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 633                         break;
 634                 default:
 635                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
 636                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
 637                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
 638                         break;
 639                 }
 640         }
 641         return IRQ_HANDLED;
 642 }
 643
 644 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 645 {
 646         if (crtc == 0)
 647                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 648         else
 649                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 650 }
 651
 652 /* Who ever call radeon_fence_emit should call ring_lock and ask
 653  * for enough space (today caller are ib schedule and buffer move) */
 654 void r100_fence_ring_emit(struct radeon_device *rdev,
 655                           struct radeon_fence *fence)
 656 {
 657         /* We have to make sure that caches are flushed before
 658          * CPU might read something from VRAM. */
 659         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 660         radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
 661         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 662         radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
 663         /* Wait until IDLE & CLEAN */
 664         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 665         radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 666         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 667         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
 668                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 669         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 670         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
 671         /* Emit fence sequence & fire IRQ */
 672         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 673         radeon_ring_write(rdev, fence->seq);
 674         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 675         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 676 }
 677
 678 int r100_wb_init(struct radeon_device *rdev)
 679 {
 680         int r;
 681
 682         if (rdev->wb.wb_obj == NULL) {
 683                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
 684                                         RADEON_GEM_DOMAIN_GTT,
 685                                         &rdev->wb.wb_obj);
 686                 if (r) {
 687                         dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
 688                         return r;
 689                 }
 690                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 691                 if (unlikely(r != 0))
 692                         return r;
 693                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
 694                                         &rdev->wb.gpu_addr);
 695                 if (r) {
 696                         dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
 697                         radeon_bo_unreserve(rdev->wb.wb_obj);
 698                         return r;
 699                 }
 700                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 701                 radeon_bo_unreserve(rdev->wb.wb_obj);
 702                 if (r) {
 703                         dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
 704                         return r;
 705                 }
 706         }
 707         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
 708         WREG32(R_00070C_CP_RB_RPTR_ADDR,
 709                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
 710         WREG32(R_000770_SCRATCH_UMSK, 0xff);
 711         return 0;
 712 }
 713
 714 void r100_wb_disable(struct radeon_device *rdev)
 715 {
 716         WREG32(R_000770_SCRATCH_UMSK, 0);
 717 }
 718
 719 void r100_wb_fini(struct radeon_device *rdev)
 720 {
 721         int r;
 722
 723         r100_wb_disable(rdev);
 724         if (rdev->wb.wb_obj) {
 725                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 726                 if (unlikely(r != 0)) {
 727                         dev_err(rdev->dev, "(%d) can't finish WB\n", r);
 728                         return;
 729                 }
 730                 radeon_bo_kunmap(rdev->wb.wb_obj);
 731                 radeon_bo_unpin(rdev->wb.wb_obj);
 732                 radeon_bo_unreserve(rdev->wb.wb_obj);
 733                 radeon_bo_unref(&rdev->wb.wb_obj);
 734                 rdev->wb.wb = NULL;
 735                 rdev->wb.wb_obj = NULL;
 736         }
 737 }
 738
 739 int r100_copy_blit(struct radeon_device *rdev,
 740                    uint64_t src_offset,
 741                    uint64_t dst_offset,
 742                    unsigned num_pages,
 743                    struct radeon_fence *fence)
 744 {
 745         uint32_t cur_pages;
 746         uint32_t stride_bytes = PAGE_SIZE;
 747         uint32_t pitch;
 748         uint32_t stride_pixels;
 749         unsigned ndw;
 750         int num_loops;
 751         int r = 0;
 752
 753         /* radeon limited to 16k stride */
 754         stride_bytes &= 0x3fff;
 755         /* radeon pitch is /64 */
 756         pitch = stride_bytes / 64;
 757         stride_pixels = stride_bytes / 4;
 758         num_loops = DIV_ROUND_UP(num_pages, 8191);
 759
 760         /* Ask for enough room for blit + flush + fence */
 761         ndw = 64 + (10 * num_loops);
 762         r = radeon_ring_lock(rdev, ndw);
 763         if (r) {
 764                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 765                 return -EINVAL;
 766         }
 767         while (num_pages > 0) {
 768                 cur_pages = num_pages;
 769                 if (cur_pages > 8191) {
 770                         cur_pages = 8191;
 771                 }
 772                 num_pages -= cur_pages;
 773
 774                 /* pages are in Y direction - height
 775                    page width in X direction - width */
 776                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
 777                 radeon_ring_write(rdev,
 778                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 779                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 780                                   RADEON_GMC_SRC_CLIPPING |
 781                                   RADEON_GMC_DST_CLIPPING |
 782                                   RADEON_GMC_BRUSH_NONE |
 783                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 784                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 785                                   RADEON_ROP3_S |
 786                                   RADEON_DP_SRC_SOURCE_MEMORY |
 787                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 788                                   RADEON_GMC_WR_MSK_DIS);
 789                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
 790                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
 791                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 792                 radeon_ring_write(rdev, 0);
 793                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 794                 radeon_ring_write(rdev, num_pages);
 795                 radeon_ring_write(rdev, num_pages);
 796                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
 797         }
 798         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 799         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
 800         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 801         radeon_ring_write(rdev,
 802                           RADEON_WAIT_2D_IDLECLEAN |
 803                           RADEON_WAIT_HOST_IDLECLEAN |
 804                           RADEON_WAIT_DMA_GUI_IDLE);
 805         if (fence) {
 806                 r = radeon_fence_emit(rdev, fence);
 807         }
 808         radeon_ring_unlock_commit(rdev);
 809         return r;
 810 }
 811
 812 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 813 {
 814         unsigned i;
 815         u32 tmp;
 816
 817         for (i = 0; i < rdev->usec_timeout; i++) {
 818                 tmp = RREG32(R_000E40_RBBM_STATUS);
 819                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 820                         return 0;
 821                 }
 822                 udelay(1);
 823         }
 824         return -1;
 825 }
 826
 827 void r100_ring_start(struct radeon_device *rdev)
 828 {
 829         int r;
 830
 831         r = radeon_ring_lock(rdev, 2);
 832         if (r) {
 833                 return;
 834         }
 835         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 836         radeon_ring_write(rdev,
 837                           RADEON_ISYNC_ANY2D_IDLE3D |
 838                           RADEON_ISYNC_ANY3D_IDLE2D |
 839                           RADEON_ISYNC_WAIT_IDLEGUI |
 840                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 841         radeon_ring_unlock_commit(rdev);
 842 }
 843
 844
 845 /* Load the microcode for the CP */
 846 static int r100_cp_init_microcode(struct radeon_device *rdev)
 847 {
 848         struct platform_device *pdev;
 849         const char *fw_name = NULL;
 850         int err;
 851
 852         DRM_DEBUG_KMS("\n");
 853
 854         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 855         err = IS_ERR(pdev);
 856         if (err) {
 857                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 858                 return -EINVAL;
 859         }
 860         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 861             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 862             (rdev->family == CHIP_RS200)) {
 863                 DRM_INFO("Loading R100 Microcode\n");
 864                 fw_name = FIRMWARE_R100;
 865         } else if ((rdev->family == CHIP_R200) ||
 866                    (rdev->family == CHIP_RV250) ||
 867                    (rdev->family == CHIP_RV280) ||
 868                    (rdev->family == CHIP_RS300)) {
 869                 DRM_INFO("Loading R200 Microcode\n");
 870                 fw_name = FIRMWARE_R200;
 871         } else if ((rdev->family == CHIP_R300) ||
 872                    (rdev->family == CHIP_R350) ||
 873                    (rdev->family == CHIP_RV350) ||
 874                    (rdev->family == CHIP_RV380) ||
 875                    (rdev->family == CHIP_RS400) ||
 876                    (rdev->family == CHIP_RS480)) {
 877                 DRM_INFO("Loading R300 Microcode\n");
 878                 fw_name = FIRMWARE_R300;
 879         } else if ((rdev->family == CHIP_R420) ||
 880                    (rdev->family == CHIP_R423) ||
 881                    (rdev->family == CHIP_RV410)) {
 882                 DRM_INFO("Loading R400 Microcode\n");
 883                 fw_name = FIRMWARE_R420;
 884         } else if ((rdev->family == CHIP_RS690) ||
 885                    (rdev->family == CHIP_RS740)) {
 886                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 887                 fw_name = FIRMWARE_RS690;
 888         } else if (rdev->family == CHIP_RS600) {
 889                 DRM_INFO("Loading RS600 Microcode\n");
 890                 fw_name = FIRMWARE_RS600;
 891         } else if ((rdev->family == CHIP_RV515) ||
 892                    (rdev->family == CHIP_R520) ||
 893                    (rdev->family == CHIP_RV530) ||
 894                    (rdev->family == CHIP_R580) ||
 895                    (rdev->family == CHIP_RV560) ||
 896                    (rdev->family == CHIP_RV570)) {
 897                 DRM_INFO("Loading R500 Microcode\n");
 898                 fw_name = FIRMWARE_R520;
 899         }
 900
 901         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 902         platform_device_unregister(pdev);
 903         if (err) {
 904                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
 905                        fw_name);
 906         } else if (rdev->me_fw->size % 8) {
 907                 printk(KERN_ERR
 908                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 909                        rdev->me_fw->size, fw_name);
 910                 err = -EINVAL;
 911                 release_firmware(rdev->me_fw);
 912                 rdev->me_fw = NULL;
 913         }
 914         return err;
 915 }
 916
 917 static void r100_cp_load_microcode(struct radeon_device *rdev)
 918 {
 919         const __be32 *fw_data;
 920         int i, size;
 921
 922         if (r100_gui_wait_for_idle(rdev)) {
 923                 printk(KERN_WARNING "Failed to wait GUI idle while "
 924                        "programming pipes. Bad things might happen.\n");
 925         }
 926
 927         if (rdev->me_fw) {
 928                 size = rdev->me_fw->size / 4;
 929                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
 930                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
 931                 for (i = 0; i < size; i += 2) {
 932                         WREG32(RADEON_CP_ME_RAM_DATAH,
 933                                be32_to_cpup(&fw_data[i]));
 934                         WREG32(RADEON_CP_ME_RAM_DATAL,
 935                                be32_to_cpup(&fw_data[i + 1]));
 936                 }
 937         }
 938 }
 939
 940 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 941 {
 942         unsigned rb_bufsz;
 943         unsigned rb_blksz;
 944         unsigned max_fetch;
 945         unsigned pre_write_timer;
 946         unsigned pre_write_limit;
 947         unsigned indirect2_start;
 948         unsigned indirect1_start;
 949         uint32_t tmp;
 950         int r;
 951
 952         if (r100_debugfs_cp_init(rdev)) {
 953                 DRM_ERROR("Failed to register debugfs file for CP !\n");
 954         }
 955         if (!rdev->me_fw) {
 956                 r = r100_cp_init_microcode(rdev);
 957                 if (r) {
 958                         DRM_ERROR("Failed to load firmware!\n");
 959                         return r;
 960                 }
 961         }
 962
 963         /* Align ring size */
 964         rb_bufsz = drm_order(ring_size / 8);
 965         ring_size = (1 << (rb_bufsz + 1)) * 4;
 966         r100_cp_load_microcode(rdev);
 967         r = radeon_ring_init(rdev, ring_size);
 968         if (r) {
 969                 return r;
 970         }
 971         /* Each time the cp read 1024 bytes (16 dword/quadword) update
 972          * the rptr copy in system ram */
 973         rb_blksz = 9;
 974         /* cp will read 128bytes at a time (4 dwords) */
 975         max_fetch = 1;
 976         rdev->cp.align_mask = 16 - 1;
 977         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
 978         pre_write_timer = 64;
 979         /* Force CP_RB_WPTR write if written more than one time before the
 980          * delay expire
 981          */
 982         pre_write_limit = 0;
 983         /* Setup the cp cache like this (cache size is 96 dwords) :
 984          *      RING            0  to 15
 985          *      INDIRECT1       16 to 79
 986          *      INDIRECT2       80 to 95
 987          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 988          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
 989          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 990          * Idea being that most of the gpu cmd will be through indirect1 buffer
 991          * so it gets the bigger cache.
 992          */
 993         indirect2_start = 80;
 994         indirect1_start = 16;
 995         /* cp setup */
 996         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
 997         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
 998                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
 999                REG_SET(RADEON_MAX_FETCH, max_fetch) |
1000                RADEON_RB_NO_UPDATE);
1001 #ifdef __BIG_ENDIAN
1002         tmp |= RADEON_BUF_SWAP_32BIT;
1003 #endif
1004         WREG32(RADEON_CP_RB_CNTL, tmp);
1005
1006         /* Set ring address */
1007         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
1008         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
1009         /* Force read & write ptr to 0 */
1010         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
1011         WREG32(RADEON_CP_RB_RPTR_WR, 0);
1012         WREG32(RADEON_CP_RB_WPTR, 0);
1013         WREG32(RADEON_CP_RB_CNTL, tmp);
1014         udelay(10);
1015         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1016         rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
1017         /* protect against crazy HW on resume */
1018         rdev->cp.wptr &= rdev->cp.ptr_mask;
1019         /* Set cp mode to bus mastering & enable cp*/
1020         WREG32(RADEON_CP_CSQ_MODE,
1021                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1022                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1023         WREG32(0x718, 0);
1024         WREG32(0x744, 0x00004D4D);
1025         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1026         radeon_ring_start(rdev);
1027         r = radeon_ring_test(rdev);
1028         if (r) {
1029                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1030                 return r;
1031         }
1032         rdev->cp.ready = true;
1033         return 0;
1034 }
1035
1036 void r100_cp_fini(struct radeon_device *rdev)
1037 {
1038         if (r100_cp_wait_for_idle(rdev)) {
1039                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1040         }
1041         /* Disable ring */
1042         r100_cp_disable(rdev);
1043         radeon_ring_fini(rdev);
1044         DRM_INFO("radeon: cp finalized\n");
1045 }
1046
1047 void r100_cp_disable(struct radeon_device *rdev)
1048 {
1049         /* Disable ring */
1050         rdev->cp.ready = false;
1051         WREG32(RADEON_CP_CSQ_MODE, 0);
1052         WREG32(RADEON_CP_CSQ_CNTL, 0);
1053         if (r100_gui_wait_for_idle(rdev)) {
1054                 printk(KERN_WARNING "Failed to wait GUI idle while "
1055                        "programming pipes. Bad things might happen.\n");
1056         }
1057 }
1058
1059 void r100_cp_commit(struct radeon_device *rdev)
1060 {
1061         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1062         (void)RREG32(RADEON_CP_RB_WPTR);
1063 }
1064
1065
1066 /*
1067  * CS functions
1068  */
1069 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1070                           struct radeon_cs_packet *pkt,
1071                           const unsigned *auth, unsigned n,
1072                           radeon_packet0_check_t check)
1073 {
1074         unsigned reg;
1075         unsigned i, j, m;
1076         unsigned idx;
1077         int r;
1078
1079         idx = pkt->idx + 1;
1080         reg = pkt->reg;
1081         /* Check that register fall into register range
1082          * determined by the number of entry (n) in the
1083          * safe register bitmap.
1084          */
1085         if (pkt->one_reg_wr) {
1086                 if ((reg >> 7) > n) {
1087                         return -EINVAL;
1088                 }
1089         } else {
1090                 if (((reg + (pkt->count << 2)) >> 7) > n) {
1091                         return -EINVAL;
1092                 }
1093         }
1094         for (i = 0; i <= pkt->count; i++, idx++) {
1095                 j = (reg >> 7);
1096                 m = 1 << ((reg >> 2) & 31);
1097                 if (auth[j] & m) {
1098                         r = check(p, pkt, idx, reg);
1099                         if (r) {
1100                                 return r;
1101                         }
1102                 }
1103                 if (pkt->one_reg_wr) {
1104                         if (!(auth[j] & m)) {
1105                                 break;
1106                         }
1107                 } else {
1108                         reg += 4;
1109                 }
1110         }
1111         return 0;
1112 }
1113
1114 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1115                          struct radeon_cs_packet *pkt)
1116 {
1117         volatile uint32_t *ib;
1118         unsigned i;
1119         unsigned idx;
1120
1121         ib = p->ib->ptr;
1122         idx = pkt->idx;
1123         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1124                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1125         }
1126 }
1127
1128 /**
1129  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1130  * @parser:     parser structure holding parsing context.
1131  * @pkt:        where to store packet informations
1132  *
1133  * Assume that chunk_ib_index is properly set. Will return -EINVAL
1134  * if packet is bigger than remaining ib size. or if packets is unknown.
1135  **/
1136 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1137                          struct radeon_cs_packet *pkt,
1138                          unsigned idx)
1139 {
1140         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1141         uint32_t header;
1142
1143         if (idx >= ib_chunk->length_dw) {
1144                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1145                           idx, ib_chunk->length_dw);
1146                 return -EINVAL;
1147         }
1148         header = radeon_get_ib_value(p, idx);
1149         pkt->idx = idx;
1150         pkt->type = CP_PACKET_GET_TYPE(header);
1151         pkt->count = CP_PACKET_GET_COUNT(header);
1152         switch (pkt->type) {
1153         case PACKET_TYPE0:
1154                 pkt->reg = CP_PACKET0_GET_REG(header);
1155                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1156                 break;
1157         case PACKET_TYPE3:
1158                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1159                 break;
1160         case PACKET_TYPE2:
1161                 pkt->count = -1;
1162                 break;
1163         default:
1164                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1165                 return -EINVAL;
1166         }
1167         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1168                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1169                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1170                 return -EINVAL;
1171         }
1172         return 0;
1173 }
1174
1175 /**
1176  * r100_cs_packet_next_vline() - parse userspace VLINE packet
1177  * @parser:             parser structure holding parsing context.
1178  *
1179  * Userspace sends a special sequence for VLINE waits.
1180  * PACKET0 - VLINE_START_END + value
1181  * PACKET0 - WAIT_UNTIL +_value
1182  * RELOC (P3) - crtc_id in reloc.
1183  *
1184  * This function parses this and relocates the VLINE START END
1185  * and WAIT UNTIL packets to the correct crtc.
1186  * It also detects a switched off crtc and nulls out the
1187  * wait in that case.
1188  */
1189 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1190 {
1191         struct drm_mode_object *obj;
1192         struct drm_crtc *crtc;
1193         struct radeon_crtc *radeon_crtc;
1194         struct radeon_cs_packet p3reloc, waitreloc;
1195         int crtc_id;
1196         int r;
1197         uint32_t header, h_idx, reg;
1198         volatile uint32_t *ib;
1199
1200         ib = p->ib->ptr;
1201
1202         /* parse the wait until */
1203         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1204         if (r)
1205                 return r;
1206
1207         /* check its a wait until and only 1 count */
1208         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1209             waitreloc.count != 0) {
1210                 DRM_ERROR("vline wait had illegal wait until segment\n");
1211                 r = -EINVAL;
1212                 return r;
1213         }
1214
1215         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1216                 DRM_ERROR("vline wait had illegal wait until\n");
1217                 r = -EINVAL;
1218                 return r;
1219         }
1220
1221         /* jump over the NOP */
1222         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1223         if (r)
1224                 return r;
1225
1226         h_idx = p->idx - 2;
1227         p->idx += waitreloc.count + 2;
1228         p->idx += p3reloc.count + 2;
1229
1230         header = radeon_get_ib_value(p, h_idx);
1231         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1232         reg = CP_PACKET0_GET_REG(header);
1233         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1234         if (!obj) {
1235                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1236                 r = -EINVAL;
1237                 goto out;
1238         }
1239         crtc = obj_to_crtc(obj);
1240         radeon_crtc = to_radeon_crtc(crtc);
1241         crtc_id = radeon_crtc->crtc_id;
1242
1243         if (!crtc->enabled) {
1244                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1245                 ib[h_idx + 2] = PACKET2(0);
1246                 ib[h_idx + 3] = PACKET2(0);
1247         } else if (crtc_id == 1) {
1248                 switch (reg) {
1249                 case AVIVO_D1MODE_VLINE_START_END:
1250                         header &= ~R300_CP_PACKET0_REG_MASK;
1251                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1252                         break;
1253                 case RADEON_CRTC_GUI_TRIG_VLINE:
1254                         header &= ~R300_CP_PACKET0_REG_MASK;
1255                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1256                         break;
1257                 default:
1258                         DRM_ERROR("unknown crtc reloc\n");
1259                         r = -EINVAL;
1260                         goto out;
1261                 }
1262                 ib[h_idx] = header;
1263                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1264         }
1265 out:
1266         return r;
1267 }
1268
1269 /**
1270  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1271  * @parser:             parser structure holding parsing context.
1272  * @data:               pointer to relocation data
1273  * @offset_start:       starting offset
1274  * @offset_mask:        offset mask (to align start offset on)
1275  * @reloc:              reloc informations
1276  *
1277  * Check next packet is relocation packet3, do bo validation and compute
1278  * GPU offset using the provided start.
1279  **/
1280 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1281                               struct radeon_cs_reloc **cs_reloc)
1282 {
1283         struct radeon_cs_chunk *relocs_chunk;
1284         struct radeon_cs_packet p3reloc;
1285         unsigned idx;
1286         int r;
1287
1288         if (p->chunk_relocs_idx == -1) {
1289                 DRM_ERROR("No relocation chunk !\n");
1290                 return -EINVAL;
1291         }
1292         *cs_reloc = NULL;
1293         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1294         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1295         if (r) {
1296                 return r;
1297         }
1298         p->idx += p3reloc.count + 2;
1299         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1300                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1301                           p3reloc.idx);
1302                 r100_cs_dump_packet(p, &p3reloc);
1303                 return -EINVAL;
1304         }
1305         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1306         if (idx >= relocs_chunk->length_dw) {
1307                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1308                           idx, relocs_chunk->length_dw);
1309                 r100_cs_dump_packet(p, &p3reloc);
1310                 return -EINVAL;
1311         }
1312         /* FIXME: we assume reloc size is 4 dwords */
1313         *cs_reloc = p->relocs_ptr[(idx / 4)];
1314         return 0;
1315 }
1316
1317 static int r100_get_vtx_size(uint32_t vtx_fmt)
1318 {
1319         int vtx_size;
1320         vtx_size = 2;
1321         /* ordered according to bits in spec */
1322         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1323                 vtx_size++;
1324         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1325                 vtx_size += 3;
1326         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1327                 vtx_size++;
1328         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1329                 vtx_size++;
1330         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1331                 vtx_size += 3;
1332         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1333                 vtx_size++;
1334         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1335                 vtx_size++;
1336         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1337                 vtx_size += 2;
1338         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1339                 vtx_size += 2;
1340         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1341                 vtx_size++;
1342         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1343                 vtx_size += 2;
1344         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1345                 vtx_size++;
1346         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1347                 vtx_size += 2;
1348         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1349                 vtx_size++;
1350         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1351                 vtx_size++;
1352         /* blend weight */
1353         if (vtx_fmt & (0x7 << 15))
1354                 vtx_size += (vtx_fmt >> 15) & 0x7;
1355         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1356                 vtx_size += 3;
1357         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1358                 vtx_size += 2;
1359         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1360                 vtx_size++;
1361         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1362                 vtx_size++;
1363         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1364                 vtx_size++;
1365         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1366                 vtx_size++;
1367         return vtx_size;
1368 }
1369
1370 static int r100_packet0_check(struct radeon_cs_parser *p,
1371                               struct radeon_cs_packet *pkt,
1372                               unsigned idx, unsigned reg)
1373 {
1374         struct radeon_cs_reloc *reloc;
1375         struct r100_cs_track *track;
1376         volatile uint32_t *ib;
1377         uint32_t tmp;
1378         int r;
1379         int i, face;
1380         u32 tile_flags = 0;
1381         u32 idx_value;
1382
1383         ib = p->ib->ptr;
1384         track = (struct r100_cs_track *)p->track;
1385
1386         idx_value = radeon_get_ib_value(p, idx);
1387
1388         switch (reg) {
1389         case RADEON_CRTC_GUI_TRIG_VLINE:
1390                 r = r100_cs_packet_parse_vline(p);
1391                 if (r) {
1392                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1393                                   idx, reg);
1394                         r100_cs_dump_packet(p, pkt);
1395                         return r;
1396                 }
1397                 break;
1398                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1399                  * range access */
1400         case RADEON_DST_PITCH_OFFSET:
1401         case RADEON_SRC_PITCH_OFFSET:
1402                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1403                 if (r)
1404                         return r;
1405                 break;
1406         case RADEON_RB3D_DEPTHOFFSET:
1407                 r = r100_cs_packet_next_reloc(p, &reloc);
1408                 if (r) {
1409                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1410                                   idx, reg);
1411                         r100_cs_dump_packet(p, pkt);
1412                         return r;
1413                 }
1414                 track->zb.robj = reloc->robj;
1415                 track->zb.offset = idx_value;
1416                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1417                 break;
1418         case RADEON_RB3D_COLOROFFSET:
1419                 r = r100_cs_packet_next_reloc(p, &reloc);
1420                 if (r) {
1421                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1422                                   idx, reg);
1423                         r100_cs_dump_packet(p, pkt);
1424                         return r;
1425                 }
1426                 track->cb[0].robj = reloc->robj;
1427                 track->cb[0].offset = idx_value;
1428                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1429                 break;
1430         case RADEON_PP_TXOFFSET_0:
1431         case RADEON_PP_TXOFFSET_1:
1432         case RADEON_PP_TXOFFSET_2:
1433                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1434                 r = r100_cs_packet_next_reloc(p, &reloc);
1435                 if (r) {
1436                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1437                                   idx, reg);
1438                         r100_cs_dump_packet(p, pkt);
1439                         return r;
1440                 }
1441                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1442                 track->textures[i].robj = reloc->robj;
1443                 break;
1444         case RADEON_PP_CUBIC_OFFSET_T0_0:
1445         case RADEON_PP_CUBIC_OFFSET_T0_1:
1446         case RADEON_PP_CUBIC_OFFSET_T0_2:
1447         case RADEON_PP_CUBIC_OFFSET_T0_3:
1448         case RADEON_PP_CUBIC_OFFSET_T0_4:
1449                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1450                 r = r100_cs_packet_next_reloc(p, &reloc);
1451                 if (r) {
1452                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1453                                   idx, reg);
1454                         r100_cs_dump_packet(p, pkt);
1455                         return r;
1456                 }
1457                 track->textures[0].cube_info[i].offset = idx_value;
1458                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1459                 track->textures[0].cube_info[i].robj = reloc->robj;
1460                 break;
1461         case RADEON_PP_CUBIC_OFFSET_T1_0:
1462         case RADEON_PP_CUBIC_OFFSET_T1_1:
1463         case RADEON_PP_CUBIC_OFFSET_T1_2:
1464         case RADEON_PP_CUBIC_OFFSET_T1_3:
1465         case RADEON_PP_CUBIC_OFFSET_T1_4:
1466                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1467                 r = r100_cs_packet_next_reloc(p, &reloc);
1468                 if (r) {
1469                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1470                                   idx, reg);
1471                         r100_cs_dump_packet(p, pkt);
1472                         return r;
1473                 }
1474                 track->textures[1].cube_info[i].offset = idx_value;
1475                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1476                 track->textures[1].cube_info[i].robj = reloc->robj;
1477                 break;
1478         case RADEON_PP_CUBIC_OFFSET_T2_0:
1479         case RADEON_PP_CUBIC_OFFSET_T2_1:
1480         case RADEON_PP_CUBIC_OFFSET_T2_2:
1481         case RADEON_PP_CUBIC_OFFSET_T2_3:
1482         case RADEON_PP_CUBIC_OFFSET_T2_4:
1483                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1484                 r = r100_cs_packet_next_reloc(p, &reloc);
1485                 if (r) {
1486                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1487                                   idx, reg);
1488                         r100_cs_dump_packet(p, pkt);
1489                         return r;
1490                 }
1491                 track->textures[2].cube_info[i].offset = idx_value;
1492                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1493                 track->textures[2].cube_info[i].robj = reloc->robj;
1494                 break;
1495         case RADEON_RE_WIDTH_HEIGHT:
1496                 track->maxy = ((idx_value >> 16) & 0x7FF);
1497                 break;
1498         case RADEON_RB3D_COLORPITCH:
1499                 r = r100_cs_packet_next_reloc(p, &reloc);
1500                 if (r) {
1501                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1502                                   idx, reg);
1503                         r100_cs_dump_packet(p, pkt);
1504                         return r;
1505                 }
1506
1507                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1508                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
1509                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1510                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1511
1512                 tmp = idx_value & ~(0x7 << 16);
1513                 tmp |= tile_flags;
1514                 ib[idx] = tmp;
1515
1516                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1517                 break;
1518         case RADEON_RB3D_DEPTHPITCH:
1519                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1520                 break;
1521         case RADEON_RB3D_CNTL:
1522                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1523                 case 7:
1524                 case 8:
1525                 case 9:
1526                 case 11:
1527                 case 12:
1528                         track->cb[0].cpp = 1;
1529                         break;
1530                 case 3:
1531                 case 4:
1532                 case 15:
1533                         track->cb[0].cpp = 2;
1534                         break;
1535                 case 6:
1536                         track->cb[0].cpp = 4;
1537                         break;
1538                 default:
1539                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1540                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1541                         return -EINVAL;
1542                 }
1543                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1544                 break;
1545         case RADEON_RB3D_ZSTENCILCNTL:
1546                 switch (idx_value & 0xf) {
1547                 case 0:
1548                         track->zb.cpp = 2;
1549                         break;
1550                 case 2:
1551                 case 3:
1552                 case 4:
1553                 case 5:
1554                 case 9:
1555                 case 11:
1556                         track->zb.cpp = 4;
1557                         break;
1558                 default:
1559                         break;
1560                 }
1561                 break;
1562         case RADEON_RB3D_ZPASS_ADDR:
1563                 r = r100_cs_packet_next_reloc(p, &reloc);
1564                 if (r) {
1565                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1566                                   idx, reg);
1567                         r100_cs_dump_packet(p, pkt);
1568                         return r;
1569                 }
1570                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1571                 break;
1572         case RADEON_PP_CNTL:
1573                 {
1574                         uint32_t temp = idx_value >> 4;
1575                         for (i = 0; i < track->num_texture; i++)
1576                                 track->textures[i].enabled = !!(temp & (1 << i));
1577                 }
1578                 break;
1579         case RADEON_SE_VF_CNTL:
1580                 track->vap_vf_cntl = idx_value;
1581                 break;
1582         case RADEON_SE_VTX_FMT:
1583                 track->vtx_size = r100_get_vtx_size(idx_value);
1584                 break;
1585         case RADEON_PP_TEX_SIZE_0:
1586         case RADEON_PP_TEX_SIZE_1:
1587         case RADEON_PP_TEX_SIZE_2:
1588                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1589                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1590                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1591                 break;
1592         case RADEON_PP_TEX_PITCH_0:
1593         case RADEON_PP_TEX_PITCH_1:
1594         case RADEON_PP_TEX_PITCH_2:
1595                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1596                 track->textures[i].pitch = idx_value + 32;
1597                 break;
1598         case RADEON_PP_TXFILTER_0:
1599         case RADEON_PP_TXFILTER_1:
1600         case RADEON_PP_TXFILTER_2:
1601                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1602                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1603                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1604                 tmp = (idx_value >> 23) & 0x7;
1605                 if (tmp == 2 || tmp == 6)
1606                         track->textures[i].roundup_w = false;
1607                 tmp = (idx_value >> 27) & 0x7;
1608                 if (tmp == 2 || tmp == 6)
1609                         track->textures[i].roundup_h = false;
1610                 break;
1611         case RADEON_PP_TXFORMAT_0:
1612         case RADEON_PP_TXFORMAT_1:
1613         case RADEON_PP_TXFORMAT_2:
1614                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1615                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1616                         track->textures[i].use_pitch = 1;
1617                 } else {
1618                         track->textures[i].use_pitch = 0;
1619                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1620                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1621                 }
1622                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1623                         track->textures[i].tex_coord_type = 2;
1624                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1625                 case RADEON_TXFORMAT_I8:
1626                 case RADEON_TXFORMAT_RGB332:
1627                 case RADEON_TXFORMAT_Y8:
1628                         track->textures[i].cpp = 1;
1629                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1630                         break;
1631                 case RADEON_TXFORMAT_AI88:
1632                 case RADEON_TXFORMAT_ARGB1555:
1633                 case RADEON_TXFORMAT_RGB565:
1634                 case RADEON_TXFORMAT_ARGB4444:
1635                 case RADEON_TXFORMAT_VYUY422:
1636                 case RADEON_TXFORMAT_YVYU422:
1637                 case RADEON_TXFORMAT_SHADOW16:
1638                 case RADEON_TXFORMAT_LDUDV655:
1639                 case RADEON_TXFORMAT_DUDV88:
1640                         track->textures[i].cpp = 2;
1641                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1642                         break;
1643                 case RADEON_TXFORMAT_ARGB8888:
1644                 case RADEON_TXFORMAT_RGBA8888:
1645                 case RADEON_TXFORMAT_SHADOW32:
1646                 case RADEON_TXFORMAT_LDUDUV8888:
1647                         track->textures[i].cpp = 4;
1648                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1649                         break;
1650                 case RADEON_TXFORMAT_DXT1:
1651                         track->textures[i].cpp = 1;
1652                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1653                         break;
1654                 case RADEON_TXFORMAT_DXT23:
1655                 case RADEON_TXFORMAT_DXT45:
1656                         track->textures[i].cpp = 1;
1657                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1658                         break;
1659                 }
1660                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1661                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1662                 break;
1663         case RADEON_PP_CUBIC_FACES_0:
1664         case RADEON_PP_CUBIC_FACES_1:
1665         case RADEON_PP_CUBIC_FACES_2:
1666                 tmp = idx_value;
1667                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1668                 for (face = 0; face < 4; face++) {
1669                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1670                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1671                 }
1672                 break;
1673         default:
1674                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1675                        reg, idx);
1676                 return -EINVAL;
1677         }
1678         return 0;
1679 }
1680
1681 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1682                                          struct radeon_cs_packet *pkt,
1683                                          struct radeon_bo *robj)
1684 {
1685         unsigned idx;
1686         u32 value;
1687         idx = pkt->idx + 1;
1688         value = radeon_get_ib_value(p, idx + 2);
1689         if ((value + 1) > radeon_bo_size(robj)) {
1690                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1691                           "(need %u have %lu) !\n",
1692                           value + 1,
1693                           radeon_bo_size(robj));
1694                 return -EINVAL;
1695         }
1696         return 0;
1697 }
1698
1699 static int r100_packet3_check(struct radeon_cs_parser *p,
1700                               struct radeon_cs_packet *pkt)
1701 {
1702         struct radeon_cs_reloc *reloc;
1703         struct r100_cs_track *track;
1704         unsigned idx;
1705         volatile uint32_t *ib;
1706         int r;
1707
1708         ib = p->ib->ptr;
1709         idx = pkt->idx + 1;
1710         track = (struct r100_cs_track *)p->track;
1711         switch (pkt->opcode) {
1712         case PACKET3_3D_LOAD_VBPNTR:
1713                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1714                 if (r)
1715                         return r;
1716                 break;
1717         case PACKET3_INDX_BUFFER:
1718                 r = r100_cs_packet_next_reloc(p, &reloc);
1719                 if (r) {
1720                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1721                         r100_cs_dump_packet(p, pkt);
1722                         return r;
1723                 }
1724                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1725                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1726                 if (r) {
1727                         return r;
1728                 }
1729                 break;
1730         case 0x23:
1731                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1732                 r = r100_cs_packet_next_reloc(p, &reloc);
1733                 if (r) {
1734                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1735                         r100_cs_dump_packet(p, pkt);
1736                         return r;
1737                 }
1738                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1739                 track->num_arrays = 1;
1740                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1741
1742                 track->arrays[0].robj = reloc->robj;
1743                 track->arrays[0].esize = track->vtx_size;
1744
1745                 track->max_indx = radeon_get_ib_value(p, idx+1);
1746
1747                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1748                 track->immd_dwords = pkt->count - 1;
1749                 r = r100_cs_track_check(p->rdev, track);
1750                 if (r)
1751                         return r;
1752                 break;
1753         case PACKET3_3D_DRAW_IMMD:
1754                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1755                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1756                         return -EINVAL;
1757                 }
1758                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1759                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1760                 track->immd_dwords = pkt->count - 1;
1761                 r = r100_cs_track_check(p->rdev, track);
1762                 if (r)
1763                         return r;
1764                 break;
1765                 /* triggers drawing using in-packet vertex data */
1766         case PACKET3_3D_DRAW_IMMD_2:
1767                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1768                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1769                         return -EINVAL;
1770                 }
1771                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1772                 track->immd_dwords = pkt->count;
1773                 r = r100_cs_track_check(p->rdev, track);
1774                 if (r)
1775                         return r;
1776                 break;
1777                 /* triggers drawing using in-packet vertex data */
1778         case PACKET3_3D_DRAW_VBUF_2:
1779                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1780                 r = r100_cs_track_check(p->rdev, track);
1781                 if (r)
1782                         return r;
1783                 break;
1784                 /* triggers drawing of vertex buffers setup elsewhere */
1785         case PACKET3_3D_DRAW_INDX_2:
1786                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1787                 r = r100_cs_track_check(p->rdev, track);
1788                 if (r)
1789                         return r;
1790                 break;
1791                 /* triggers drawing using indices to vertex buffer */
1792         case PACKET3_3D_DRAW_VBUF:
1793                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1794                 r = r100_cs_track_check(p->rdev, track);
1795                 if (r)
1796                         return r;
1797                 break;
1798                 /* triggers drawing of vertex buffers setup elsewhere */
1799         case PACKET3_3D_DRAW_INDX:
1800                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1801                 r = r100_cs_track_check(p->rdev, track);
1802                 if (r)
1803                         return r;
1804                 break;
1805                 /* triggers drawing using indices to vertex buffer */
1806         case PACKET3_3D_CLEAR_HIZ:
1807         case PACKET3_3D_CLEAR_ZMASK:
1808                 if (p->rdev->hyperz_filp != p->filp)
1809                         return -EINVAL;
1810                 break;
1811         case PACKET3_NOP:
1812                 break;
1813         default:
1814                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1815                 return -EINVAL;
1816         }
1817         return 0;
1818 }
1819
1820 int r100_cs_parse(struct radeon_cs_parser *p)
1821 {
1822         struct radeon_cs_packet pkt;
1823         struct r100_cs_track *track;
1824         int r;
1825
1826         track = kzalloc(sizeof(*track), GFP_KERNEL);
1827         r100_cs_track_clear(p->rdev, track);
1828         p->track = track;
1829         do {
1830                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1831                 if (r) {
1832                         return r;
1833                 }
1834                 p->idx += pkt.count + 2;
1835                 switch (pkt.type) {
1836                         case PACKET_TYPE0:
1837                                 if (p->rdev->family >= CHIP_R200)
1838                                         r = r100_cs_parse_packet0(p, &pkt,
1839                                                                   p->rdev->config.r100.reg_safe_bm,
1840                                                                   p->rdev->config.r100.reg_safe_bm_size,
1841                                                                   &r200_packet0_check);
1842                                 else
1843                                         r = r100_cs_parse_packet0(p, &pkt,
1844                                                                   p->rdev->config.r100.reg_safe_bm,
1845                                                                   p->rdev->config.r100.reg_safe_bm_size,
1846                                                                   &r100_packet0_check);
1847                                 break;
1848                         case PACKET_TYPE2:
1849                                 break;
1850                         case PACKET_TYPE3:
1851                                 r = r100_packet3_check(p, &pkt);
1852                                 break;
1853                         default:
1854                                 DRM_ERROR("Unknown packet type %d !\n",
1855                                           pkt.type);
1856                                 return -EINVAL;
1857                 }
1858                 if (r) {
1859                         return r;
1860                 }
1861         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1862         return 0;
1863 }
1864
1865
1866 /*
1867  * Global GPU functions
1868  */
1869 void r100_errata(struct radeon_device *rdev)
1870 {
1871         rdev->pll_errata = 0;
1872
1873         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1874                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1875         }
1876
1877         if (rdev->family == CHIP_RV100 ||
1878             rdev->family == CHIP_RS100 ||
1879             rdev->family == CHIP_RS200) {
1880                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1881         }
1882 }
1883
1884 /* Wait for vertical sync on primary CRTC */
1885 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1886 {
1887         uint32_t crtc_gen_cntl, tmp;
1888         int i;
1889
1890         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1891         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1892             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1893                 return;
1894         }
1895         /* Clear the CRTC_VBLANK_SAVE bit */
1896         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1897         for (i = 0; i < rdev->usec_timeout; i++) {
1898                 tmp = RREG32(RADEON_CRTC_STATUS);
1899                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1900                         return;
1901                 }
1902                 DRM_UDELAY(1);
1903         }
1904 }
1905
1906 /* Wait for vertical sync on secondary CRTC */
1907 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1908 {
1909         uint32_t crtc2_gen_cntl, tmp;
1910         int i;
1911
1912         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1913         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1914             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1915                 return;
1916
1917         /* Clear the CRTC_VBLANK_SAVE bit */
1918         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1919         for (i = 0; i < rdev->usec_timeout; i++) {
1920                 tmp = RREG32(RADEON_CRTC2_STATUS);
1921                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1922                         return;
1923                 }
1924                 DRM_UDELAY(1);
1925         }
1926 }
1927
1928 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1929 {
1930         unsigned i;
1931         uint32_t tmp;
1932
1933         for (i = 0; i < rdev->usec_timeout; i++) {
1934                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1935                 if (tmp >= n) {
1936                         return 0;
1937                 }
1938                 DRM_UDELAY(1);
1939         }
1940         return -1;
1941 }
1942
1943 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1944 {
1945         unsigned i;
1946         uint32_t tmp;
1947
1948         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1949                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1950                        " Bad things might happen.\n");
1951         }
1952         for (i = 0; i < rdev->usec_timeout; i++) {
1953                 tmp = RREG32(RADEON_RBBM_STATUS);
1954                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1955                         return 0;
1956                 }
1957                 DRM_UDELAY(1);
1958         }
1959         return -1;
1960 }
1961
1962 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1963 {
1964         unsigned i;
1965         uint32_t tmp;
1966
1967         for (i = 0; i < rdev->usec_timeout; i++) {
1968                 /* read MC_STATUS */
1969                 tmp = RREG32(RADEON_MC_STATUS);
1970                 if (tmp & RADEON_MC_IDLE) {
1971                         return 0;
1972                 }
1973                 DRM_UDELAY(1);
1974         }
1975         return -1;
1976 }
1977
1978 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
1979 {
1980         lockup->last_cp_rptr = cp->rptr;
1981         lockup->last_jiffies = jiffies;
1982 }
1983
1984 /**
1985  * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
1986  * @rdev:       radeon device structure
1987  * @lockup:     r100_gpu_lockup structure holding CP lockup tracking informations
1988  * @cp:         radeon_cp structure holding CP information
1989  *
1990  * We don't need to initialize the lockup tracking information as we will either
1991  * have CP rptr to a different value of jiffies wrap around which will force
1992  * initialization of the lockup tracking informations.
1993  *
1994  * A possible false positivie is if we get call after while and last_cp_rptr ==
1995  * the current CP rptr, even if it's unlikely it might happen. To avoid this
1996  * if the elapsed time since last call is bigger than 2 second than we return
1997  * false and update the tracking information. Due to this the caller must call
1998  * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
1999  * the fencing code should be cautious about that.
2000  *
2001  * Caller should write to the ring to force CP to do something so we don't get
2002  * false positive when CP is just gived nothing to do.
2003  *
2004  **/
2005 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2006 {
2007         unsigned long cjiffies, elapsed;
2008
2009         cjiffies = jiffies;
2010         if (!time_after(cjiffies, lockup->last_jiffies)) {
2011                 /* likely a wrap around */
2012                 lockup->last_cp_rptr = cp->rptr;
2013                 lockup->last_jiffies = jiffies;
2014                 return false;
2015         }
2016         if (cp->rptr != lockup->last_cp_rptr) {
2017                 /* CP is still working no lockup */
2018                 lockup->last_cp_rptr = cp->rptr;
2019                 lockup->last_jiffies = jiffies;
2020                 return false;
2021         }
2022         elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2023         if (elapsed >= 3000) {
2024                 /* very likely the improbable case where current
2025                  * rptr is equal to last recorded, a while ago, rptr
2026                  * this is more likely a false positive update tracking
2027                  * information which should force us to be recall at
2028                  * latter point
2029                  */
2030                 lockup->last_cp_rptr = cp->rptr;
2031                 lockup->last_jiffies = jiffies;
2032                 return false;
2033         }
2034         if (elapsed >= 1000) {
2035                 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2036                 return true;
2037         }
2038         /* give a chance to the GPU ... */
2039         return false;
2040 }
2041
2042 bool r100_gpu_is_lockup(struct radeon_device *rdev)
2043 {
2044         u32 rbbm_status;
2045         int r;
2046
2047         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2048         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2049                 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2050                 return false;
2051         }
2052         /* force CP activities */
2053         r = radeon_ring_lock(rdev, 2);
2054         if (!r) {
2055                 /* PACKET2 NOP */
2056                 radeon_ring_write(rdev, 0x80000000);
2057                 radeon_ring_write(rdev, 0x80000000);
2058                 radeon_ring_unlock_commit(rdev);
2059         }
2060         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2061         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
2062 }
2063
2064 void r100_bm_disable(struct radeon_device *rdev)
2065 {
2066         u32 tmp;
2067
2068         /* disable bus mastering */
2069         tmp = RREG32(R_000030_BUS_CNTL);
2070         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2071         mdelay(1);
2072         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2073         mdelay(1);
2074         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2075         tmp = RREG32(RADEON_BUS_CNTL);
2076         mdelay(1);
2077         pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2078         pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
2079         mdelay(1);
2080 }
2081
2082 int r100_asic_reset(struct radeon_device *rdev)
2083 {
2084         struct r100_mc_save save;
2085         u32 status, tmp;
2086
2087         r100_mc_stop(rdev, &save);
2088         status = RREG32(R_000E40_RBBM_STATUS);
2089         if (!G_000E40_GUI_ACTIVE(status)) {
2090                 return 0;
2091         }
2092         status = RREG32(R_000E40_RBBM_STATUS);
2093         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2094         /* stop CP */
2095         WREG32(RADEON_CP_CSQ_CNTL, 0);
2096         tmp = RREG32(RADEON_CP_RB_CNTL);
2097         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2098         WREG32(RADEON_CP_RB_RPTR_WR, 0);
2099         WREG32(RADEON_CP_RB_WPTR, 0);
2100         WREG32(RADEON_CP_RB_CNTL, tmp);
2101         /* save PCI state */
2102         pci_save_state(rdev->pdev);
2103         /* disable bus mastering */
2104         r100_bm_disable(rdev);
2105         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2106                                         S_0000F0_SOFT_RESET_RE(1) |
2107                                         S_0000F0_SOFT_RESET_PP(1) |
2108                                         S_0000F0_SOFT_RESET_RB(1));
2109         RREG32(R_0000F0_RBBM_SOFT_RESET);
2110         mdelay(500);
2111         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2112         mdelay(1);
2113         status = RREG32(R_000E40_RBBM_STATUS);
2114         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2115         /* reset CP */
2116         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2117         RREG32(R_0000F0_RBBM_SOFT_RESET);
2118         mdelay(500);
2119         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2120         mdelay(1);
2121         status = RREG32(R_000E40_RBBM_STATUS);
2122         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2123         /* restore PCI & busmastering */
2124         pci_restore_state(rdev->pdev);
2125         r100_enable_bm(rdev);
2126         /* Check if GPU is idle */
2127         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2128                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2129                 dev_err(rdev->dev, "failed to reset GPU\n");
2130                 rdev->gpu_lockup = true;
2131                 return -1;
2132         }
2133         r100_mc_resume(rdev, &save);
2134         dev_info(rdev->dev, "GPU reset succeed\n");
2135         return 0;
2136 }
2137
2138 void r100_set_common_regs(struct radeon_device *rdev)
2139 {
2140         struct drm_device *dev = rdev->ddev;
2141         bool force_dac2 = false;
2142         u32 tmp;
2143
2144         /* set these so they don't interfere with anything */
2145         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2146         WREG32(RADEON_SUBPIC_CNTL, 0);
2147         WREG32(RADEON_VIPH_CONTROL, 0);
2148         WREG32(RADEON_I2C_CNTL_1, 0);
2149         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2150         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2151         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2152
2153         /* always set up dac2 on rn50 and some rv100 as lots
2154          * of servers seem to wire it up to a VGA port but
2155          * don't report it in the bios connector
2156          * table.
2157          */
2158         switch (dev->pdev->device) {
2159                 /* RN50 */
2160         case 0x515e:
2161         case 0x5969:
2162                 force_dac2 = true;
2163                 break;
2164                 /* RV100*/
2165         case 0x5159:
2166         case 0x515a:
2167                 /* DELL triple head servers */
2168                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2169                     ((dev->pdev->subsystem_device == 0x016c) ||
2170                      (dev->pdev->subsystem_device == 0x016d) ||
2171                      (dev->pdev->subsystem_device == 0x016e) ||
2172                      (dev->pdev->subsystem_device == 0x016f) ||
2173                      (dev->pdev->subsystem_device == 0x0170) ||
2174                      (dev->pdev->subsystem_device == 0x017d) ||
2175                      (dev->pdev->subsystem_device == 0x017e) ||
2176                      (dev->pdev->subsystem_device == 0x0183) ||
2177                      (dev->pdev->subsystem_device == 0x018a) ||
2178                      (dev->pdev->subsystem_device == 0x019a)))
2179                         force_dac2 = true;
2180                 break;
2181         }
2182
2183         if (force_dac2) {
2184                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2185                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2186                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2187
2188                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2189                    enable it, even it's detected.
2190                 */
2191
2192                 /* force it to crtc0 */
2193                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2194                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2195                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2196
2197                 /* set up the TV DAC */
2198                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2199                                  RADEON_TV_DAC_STD_MASK |
2200                                  RADEON_TV_DAC_RDACPD |
2201                                  RADEON_TV_DAC_GDACPD |
2202                                  RADEON_TV_DAC_BDACPD |
2203                                  RADEON_TV_DAC_BGADJ_MASK |
2204                                  RADEON_TV_DAC_DACADJ_MASK);
2205                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2206                                 RADEON_TV_DAC_NHOLD |
2207                                 RADEON_TV_DAC_STD_PS2 |
2208                                 (0x58 << 16));
2209
2210                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2211                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2212                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2213         }
2214
2215         /* switch PM block to ACPI mode */
2216         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2217         tmp &= ~RADEON_PM_MODE_SEL;
2218         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2219
2220 }
2221
2222 /*
2223  * VRAM info
2224  */
2225 static void r100_vram_get_type(struct radeon_device *rdev)
2226 {
2227         uint32_t tmp;
2228
2229         rdev->mc.vram_is_ddr = false;
2230         if (rdev->flags & RADEON_IS_IGP)
2231                 rdev->mc.vram_is_ddr = true;
2232         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2233                 rdev->mc.vram_is_ddr = true;
2234         if ((rdev->family == CHIP_RV100) ||
2235             (rdev->family == CHIP_RS100) ||
2236             (rdev->family == CHIP_RS200)) {
2237                 tmp = RREG32(RADEON_MEM_CNTL);
2238                 if (tmp & RV100_HALF_MODE) {
2239                         rdev->mc.vram_width = 32;
2240                 } else {
2241                         rdev->mc.vram_width = 64;
2242                 }
2243                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2244                         rdev->mc.vram_width /= 4;
2245                         rdev->mc.vram_is_ddr = true;
2246                 }
2247         } else if (rdev->family <= CHIP_RV280) {
2248                 tmp = RREG32(RADEON_MEM_CNTL);
2249                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2250                         rdev->mc.vram_width = 128;
2251                 } else {
2252                         rdev->mc.vram_width = 64;
2253                 }
2254         } else {
2255                 /* newer IGPs */
2256                 rdev->mc.vram_width = 128;
2257         }
2258 }
2259
2260 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2261 {
2262         u32 aper_size;
2263         u8 byte;
2264
2265         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2266
2267         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2268          * that is has the 2nd generation multifunction PCI interface
2269          */
2270         if (rdev->family == CHIP_RV280 ||
2271             rdev->family >= CHIP_RV350) {
2272                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2273                        ~RADEON_HDP_APER_CNTL);
2274                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2275                 return aper_size * 2;
2276         }
2277
2278         /* Older cards have all sorts of funny issues to deal with. First
2279          * check if it's a multifunction card by reading the PCI config
2280          * header type... Limit those to one aperture size
2281          */
2282         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2283         if (byte & 0x80) {
2284                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2285                 DRM_INFO("Limiting VRAM to one aperture\n");
2286                 return aper_size;
2287         }
2288
2289         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2290          * have set it up. We don't write this as it's broken on some ASICs but
2291          * we expect the BIOS to have done the right thing (might be too optimistic...)
2292          */
2293         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2294                 return aper_size * 2;
2295         return aper_size;
2296 }
2297
2298 void r100_vram_init_sizes(struct radeon_device *rdev)
2299 {
2300         u64 config_aper_size;
2301
2302         /* work out accessible VRAM */
2303         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2304         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2305         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2306         /* FIXME we don't use the second aperture yet when we could use it */
2307         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2308                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2309         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2310         if (rdev->flags & RADEON_IS_IGP) {
2311                 uint32_t tom;
2312                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2313                 tom = RREG32(RADEON_NB_TOM);
2314                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2315                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2316                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2317         } else {
2318                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2319                 /* Some production boards of m6 will report 0
2320                  * if it's 8 MB
2321                  */
2322                 if (rdev->mc.real_vram_size == 0) {
2323                         rdev->mc.real_vram_size = 8192 * 1024;
2324                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2325                 }
2326                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2327                  * Novell bug 204882 + along with lots of ubuntu ones
2328                  */
2329                 if (config_aper_size > rdev->mc.real_vram_size)
2330                         rdev->mc.mc_vram_size = config_aper_size;
2331                 else
2332                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2333         }
2334 }
2335
2336 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2337 {
2338         uint32_t temp;
2339
2340         temp = RREG32(RADEON_CONFIG_CNTL);
2341         if (state == false) {
2342                 temp &= ~(1<<8);
2343                 temp |= (1<<9);
2344         } else {
2345                 temp &= ~(1<<9);
2346         }
2347         WREG32(RADEON_CONFIG_CNTL, temp);
2348 }
2349
2350 void r100_mc_init(struct radeon_device *rdev)
2351 {
2352         u64 base;
2353
2354         r100_vram_get_type(rdev);
2355         r100_vram_init_sizes(rdev);
2356         base = rdev->mc.aper_base;
2357         if (rdev->flags & RADEON_IS_IGP)
2358                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2359         radeon_vram_location(rdev, &rdev->mc, base);
2360         rdev->mc.gtt_base_align = 0;
2361         if (!(rdev->flags & RADEON_IS_AGP))
2362                 radeon_gtt_location(rdev, &rdev->mc);
2363         radeon_update_bandwidth_info(rdev);
2364 }
2365
2366
2367 /*
2368  * Indirect registers accessor
2369  */
2370 void r100_pll_errata_after_index(struct radeon_device *rdev)
2371 {
2372         if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2373                 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2374                 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2375         }
2376 }
2377
2378 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2379 {
2380         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2381          * or the chip could hang on a subsequent access
2382          */
2383         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2384                 udelay(5000);
2385         }
2386
2387         /* This function is required to workaround a hardware bug in some (all?)
2388          * revisions of the R300.  This workaround should be called after every
2389          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2390          * may not be correct.
2391          */
2392         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2393                 uint32_t save, tmp;
2394
2395                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2396                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2397                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2398                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2399                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2400         }
2401 }
2402
2403 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2404 {
2405         uint32_t data;
2406
2407         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2408         r100_pll_errata_after_index(rdev);
2409         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2410         r100_pll_errata_after_data(rdev);
2411         return data;
2412 }
2413
2414 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2415 {
2416         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2417         r100_pll_errata_after_index(rdev);
2418         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2419         r100_pll_errata_after_data(rdev);
2420 }
2421
2422 void r100_set_safe_registers(struct radeon_device *rdev)
2423 {
2424         if (ASIC_IS_RN50(rdev)) {
2425                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2426                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2427         } else if (rdev->family < CHIP_R200) {
2428                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2429                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2430         } else {
2431                 r200_set_safe_registers(rdev);
2432         }
2433 }
2434
2435 /*
2436  * Debugfs info
2437  */
2438 #if defined(CONFIG_DEBUG_FS)
2439 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2440 {
2441         struct drm_info_node *node = (struct drm_info_node *) m->private;
2442         struct drm_device *dev = node->minor->dev;
2443         struct radeon_device *rdev = dev->dev_private;
2444         uint32_t reg, value;
2445         unsigned i;
2446
2447         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2448         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2449         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2450         for (i = 0; i < 64; i++) {
2451                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2452                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2453                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2454                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2455                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2456         }
2457         return 0;
2458 }
2459
2460 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2461 {
2462         struct drm_info_node *node = (struct drm_info_node *) m->private;
2463         struct drm_device *dev = node->minor->dev;
2464         struct radeon_device *rdev = dev->dev_private;
2465         uint32_t rdp, wdp;
2466         unsigned count, i, j;
2467
2468         radeon_ring_free_size(rdev);
2469         rdp = RREG32(RADEON_CP_RB_RPTR);
2470         wdp = RREG32(RADEON_CP_RB_WPTR);
2471         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2472         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2473         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2474         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2475         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2476         seq_printf(m, "%u dwords in ring\n", count);
2477         for (j = 0; j <= count; j++) {
2478                 i = (rdp + j) & rdev->cp.ptr_mask;
2479                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2480         }
2481         return 0;
2482 }
2483
2484
2485 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2486 {
2487         struct drm_info_node *node = (struct drm_info_node *) m->private;
2488         struct drm_device *dev = node->minor->dev;
2489         struct radeon_device *rdev = dev->dev_private;
2490         uint32_t csq_stat, csq2_stat, tmp;
2491         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2492         unsigned i;
2493
2494         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2495         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2496         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2497         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2498         r_rptr = (csq_stat >> 0) & 0x3ff;
2499         r_wptr = (csq_stat >> 10) & 0x3ff;
2500         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2501         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2502         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2503         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2504         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2505         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2506         seq_printf(m, "Ring rptr %u\n", r_rptr);
2507         seq_printf(m, "Ring wptr %u\n", r_wptr);
2508         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2509         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2510         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2511         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2512         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2513          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2514         seq_printf(m, "Ring fifo:\n");
2515         for (i = 0; i < 256; i++) {
2516                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2517                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2518                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2519         }
2520         seq_printf(m, "Indirect1 fifo:\n");
2521         for (i = 256; i <= 512; i++) {
2522                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2523                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2524                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2525         }
2526         seq_printf(m, "Indirect2 fifo:\n");
2527         for (i = 640; i < ib1_wptr; i++) {
2528                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2529                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2530                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2531         }
2532         return 0;
2533 }
2534
2535 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2536 {
2537         struct drm_info_node *node = (struct drm_info_node *) m->private;
2538         struct drm_device *dev = node->minor->dev;
2539         struct radeon_device *rdev = dev->dev_private;
2540         uint32_t tmp;
2541
2542         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2543         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2544         tmp = RREG32(RADEON_MC_FB_LOCATION);
2545         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2546         tmp = RREG32(RADEON_BUS_CNTL);
2547         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2548         tmp = RREG32(RADEON_MC_AGP_LOCATION);
2549         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2550         tmp = RREG32(RADEON_AGP_BASE);
2551         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2552         tmp = RREG32(RADEON_HOST_PATH_CNTL);
2553         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2554         tmp = RREG32(0x01D0);
2555         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2556         tmp = RREG32(RADEON_AIC_LO_ADDR);
2557         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2558         tmp = RREG32(RADEON_AIC_HI_ADDR);
2559         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2560         tmp = RREG32(0x01E4);
2561         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2562         return 0;
2563 }
2564
2565 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2566         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2567 };
2568
2569 static struct drm_info_list r100_debugfs_cp_list[] = {
2570         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2571         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2572 };
2573
2574 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2575         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2576 };
2577 #endif
2578
2579 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2580 {
2581 #if defined(CONFIG_DEBUG_FS)
2582         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2583 #else
2584         return 0;
2585 #endif
2586 }
2587
2588 int r100_debugfs_cp_init(struct radeon_device *rdev)
2589 {
2590 #if defined(CONFIG_DEBUG_FS)
2591         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2592 #else
2593         return 0;
2594 #endif
2595 }
2596
2597 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2598 {
2599 #if defined(CONFIG_DEBUG_FS)
2600         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2601 #else
2602         return 0;
2603 #endif
2604 }
2605
2606 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2607                          uint32_t tiling_flags, uint32_t pitch,
2608                          uint32_t offset, uint32_t obj_size)
2609 {
2610         int surf_index = reg * 16;
2611         int flags = 0;
2612
2613         if (rdev->family <= CHIP_RS200) {
2614                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2615                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2616                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2617                 if (tiling_flags & RADEON_TILING_MACRO)
2618                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2619         } else if (rdev->family <= CHIP_RV280) {
2620                 if (tiling_flags & (RADEON_TILING_MACRO))
2621                         flags |= R200_SURF_TILE_COLOR_MACRO;
2622                 if (tiling_flags & RADEON_TILING_MICRO)
2623                         flags |= R200_SURF_TILE_COLOR_MICRO;
2624         } else {
2625                 if (tiling_flags & RADEON_TILING_MACRO)
2626                         flags |= R300_SURF_TILE_MACRO;
2627                 if (tiling_flags & RADEON_TILING_MICRO)
2628                         flags |= R300_SURF_TILE_MICRO;
2629         }
2630
2631         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2632                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2633         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2634                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2635
2636         /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2637         if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2638                 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2639                         if (ASIC_IS_RN50(rdev))
2640                                 pitch /= 16;
2641         }
2642
2643         /* r100/r200 divide by 16 */
2644         if (rdev->family < CHIP_R300)
2645                 flags |= pitch / 16;
2646         else
2647                 flags |= pitch / 8;
2648
2649
2650         DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2651         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2652         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2653         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2654         return 0;
2655 }
2656
2657 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2658 {
2659         int surf_index = reg * 16;
2660         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2661 }
2662
2663 void r100_bandwidth_update(struct radeon_device *rdev)
2664 {
2665         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2666         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2667         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2668         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2669         fixed20_12 memtcas_ff[8] = {
2670                 dfixed_init(1),
2671                 dfixed_init(2),
2672                 dfixed_init(3),
2673                 dfixed_init(0),
2674                 dfixed_init_half(1),
2675                 dfixed_init_half(2),
2676                 dfixed_init(0),
2677         };
2678         fixed20_12 memtcas_rs480_ff[8] = {
2679                 dfixed_init(0),
2680                 dfixed_init(1),
2681                 dfixed_init(2),
2682                 dfixed_init(3),
2683                 dfixed_init(0),
2684                 dfixed_init_half(1),
2685                 dfixed_init_half(2),
2686                 dfixed_init_half(3),
2687         };
2688         fixed20_12 memtcas2_ff[8] = {
2689                 dfixed_init(0),
2690                 dfixed_init(1),
2691                 dfixed_init(2),
2692                 dfixed_init(3),
2693                 dfixed_init(4),
2694                 dfixed_init(5),
2695                 dfixed_init(6),
2696                 dfixed_init(7),
2697         };
2698         fixed20_12 memtrbs[8] = {
2699                 dfixed_init(1),
2700                 dfixed_init_half(1),
2701                 dfixed_init(2),
2702                 dfixed_init_half(2),
2703                 dfixed_init(3),
2704                 dfixed_init_half(3),
2705                 dfixed_init(4),
2706                 dfixed_init_half(4)
2707         };
2708         fixed20_12 memtrbs_r4xx[8] = {
2709                 dfixed_init(4),
2710                 dfixed_init(5),
2711                 dfixed_init(6),
2712                 dfixed_init(7),
2713                 dfixed_init(8),
2714                 dfixed_init(9),
2715                 dfixed_init(10),
2716                 dfixed_init(11)
2717         };
2718         fixed20_12 min_mem_eff;
2719         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2720         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2721         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2722                 disp_drain_rate2, read_return_rate;
2723         fixed20_12 time_disp1_drop_priority;
2724         int c;
2725         int cur_size = 16;       /* in octawords */
2726         int critical_point = 0, critical_point2;
2727 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2728         int stop_req, max_stop_req;
2729         struct drm_display_mode *mode1 = NULL;
2730         struct drm_display_mode *mode2 = NULL;
2731         uint32_t pixel_bytes1 = 0;
2732         uint32_t pixel_bytes2 = 0;
2733
2734         radeon_update_display_priority(rdev);
2735
2736         if (rdev->mode_info.crtcs[0]->base.enabled) {
2737                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2738                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2739         }
2740         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2741                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2742                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2743                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2744                 }
2745         }
2746
2747         min_mem_eff.full = dfixed_const_8(0);
2748         /* get modes */
2749         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2750                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2751                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2752                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2753                 /* check crtc enables */
2754                 if (mode2)
2755                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2756                 if (mode1)
2757                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2758                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2759         }
2760
2761         /*
2762          * determine is there is enough bw for current mode
2763          */
2764         sclk_ff = rdev->pm.sclk;
2765         mclk_ff = rdev->pm.mclk;
2766
2767         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2768         temp_ff.full = dfixed_const(temp);
2769         mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
2770
2771         pix_clk.full = 0;
2772         pix_clk2.full = 0;
2773         peak_disp_bw.full = 0;
2774         if (mode1) {
2775                 temp_ff.full = dfixed_const(1000);
2776                 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2777                 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2778                 temp_ff.full = dfixed_const(pixel_bytes1);
2779                 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
2780         }
2781         if (mode2) {
2782                 temp_ff.full = dfixed_const(1000);
2783                 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2784                 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2785                 temp_ff.full = dfixed_const(pixel_bytes2);
2786                 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
2787         }
2788
2789         mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
2790         if (peak_disp_bw.full >= mem_bw.full) {
2791                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2792                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2793         }
2794
2795         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2796         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2797         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2798                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2799                 mem_trp  = ((temp & 0x3)) + 1;
2800                 mem_tras = ((temp & 0x70) >> 4) + 1;
2801         } else if (rdev->family == CHIP_R300 ||
2802                    rdev->family == CHIP_R350) { /* r300, r350 */
2803                 mem_trcd = (temp & 0x7) + 1;
2804                 mem_trp = ((temp >> 8) & 0x7) + 1;
2805                 mem_tras = ((temp >> 11) & 0xf) + 4;
2806         } else if (rdev->family == CHIP_RV350 ||
2807                    rdev->family <= CHIP_RV380) {
2808                 /* rv3x0 */
2809                 mem_trcd = (temp & 0x7) + 3;
2810                 mem_trp = ((temp >> 8) & 0x7) + 3;
2811                 mem_tras = ((temp >> 11) & 0xf) + 6;
2812         } else if (rdev->family == CHIP_R420 ||
2813                    rdev->family == CHIP_R423 ||
2814                    rdev->family == CHIP_RV410) {
2815                 /* r4xx */
2816                 mem_trcd = (temp & 0xf) + 3;
2817                 if (mem_trcd > 15)
2818                         mem_trcd = 15;
2819                 mem_trp = ((temp >> 8) & 0xf) + 3;
2820                 if (mem_trp > 15)
2821                         mem_trp = 15;
2822                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2823                 if (mem_tras > 31)
2824                         mem_tras = 31;
2825         } else { /* RV200, R200 */
2826                 mem_trcd = (temp & 0x7) + 1;
2827                 mem_trp = ((temp >> 8) & 0x7) + 1;
2828                 mem_tras = ((temp >> 12) & 0xf) + 4;
2829         }
2830         /* convert to FF */
2831         trcd_ff.full = dfixed_const(mem_trcd);
2832         trp_ff.full = dfixed_const(mem_trp);
2833         tras_ff.full = dfixed_const(mem_tras);
2834
2835         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2836         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2837         data = (temp & (7 << 20)) >> 20;
2838         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2839                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2840                         tcas_ff = memtcas_rs480_ff[data];
2841                 else
2842                         tcas_ff = memtcas_ff[data];
2843         } else
2844                 tcas_ff = memtcas2_ff[data];
2845
2846         if (rdev->family == CHIP_RS400 ||
2847             rdev->family == CHIP_RS480) {
2848                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2849                 data = (temp >> 23) & 0x7;
2850                 if (data < 5)
2851                         tcas_ff.full += dfixed_const(data);
2852         }
2853
2854         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2855                 /* on the R300, Tcas is included in Trbs.
2856                  */
2857                 temp = RREG32(RADEON_MEM_CNTL);
2858                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2859                 if (data == 1) {
2860                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2861                                 temp = RREG32(R300_MC_IND_INDEX);
2862                                 temp &= ~R300_MC_IND_ADDR_MASK;
2863                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2864                                 WREG32(R300_MC_IND_INDEX, temp);
2865                                 temp = RREG32(R300_MC_IND_DATA);
2866                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2867                         } else {
2868                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2869                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2870                         }
2871                 } else {
2872                         temp = RREG32(R300_MC_READ_CNTL_AB);
2873                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2874                 }
2875                 if (rdev->family == CHIP_RV410 ||
2876                     rdev->family == CHIP_R420 ||
2877                     rdev->family == CHIP_R423)
2878                         trbs_ff = memtrbs_r4xx[data];
2879                 else
2880                         trbs_ff = memtrbs[data];
2881                 tcas_ff.full += trbs_ff.full;
2882         }
2883
2884         sclk_eff_ff.full = sclk_ff.full;
2885
2886         if (rdev->flags & RADEON_IS_AGP) {
2887                 fixed20_12 agpmode_ff;
2888                 agpmode_ff.full = dfixed_const(radeon_agpmode);
2889                 temp_ff.full = dfixed_const_666(16);
2890                 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
2891         }
2892         /* TODO PCIE lanes may affect this - agpmode == 16?? */
2893
2894         if (ASIC_IS_R300(rdev)) {
2895                 sclk_delay_ff.full = dfixed_const(250);
2896         } else {
2897                 if ((rdev->family == CHIP_RV100) ||
2898                     rdev->flags & RADEON_IS_IGP) {
2899                         if (rdev->mc.vram_is_ddr)
2900                                 sclk_delay_ff.full = dfixed_const(41);
2901                         else
2902                                 sclk_delay_ff.full = dfixed_const(33);
2903                 } else {
2904                         if (rdev->mc.vram_width == 128)
2905                                 sclk_delay_ff.full = dfixed_const(57);
2906                         else
2907                                 sclk_delay_ff.full = dfixed_const(41);
2908                 }
2909         }
2910
2911         mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
2912
2913         if (rdev->mc.vram_is_ddr) {
2914                 if (rdev->mc.vram_width == 32) {
2915                         k1.full = dfixed_const(40);
2916                         c  = 3;
2917                 } else {
2918                         k1.full = dfixed_const(20);
2919                         c  = 1;
2920                 }
2921         } else {
2922                 k1.full = dfixed_const(40);
2923                 c  = 3;
2924         }
2925
2926         temp_ff.full = dfixed_const(2);
2927         mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
2928         temp_ff.full = dfixed_const(c);
2929         mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
2930         temp_ff.full = dfixed_const(4);
2931         mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
2932         mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
2933         mc_latency_mclk.full += k1.full;
2934
2935         mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
2936         mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
2937
2938         /*
2939           HW cursor time assuming worst case of full size colour cursor.
2940         */
2941         temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2942         temp_ff.full += trcd_ff.full;
2943         if (temp_ff.full < tras_ff.full)
2944                 temp_ff.full = tras_ff.full;
2945         cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
2946
2947         temp_ff.full = dfixed_const(cur_size);
2948         cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
2949         /*
2950           Find the total latency for the display data.
2951         */
2952         disp_latency_overhead.full = dfixed_const(8);
2953         disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
2954         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2955         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2956
2957         if (mc_latency_mclk.full > mc_latency_sclk.full)
2958                 disp_latency.full = mc_latency_mclk.full;
2959         else
2960                 disp_latency.full = mc_latency_sclk.full;
2961
2962         /* setup Max GRPH_STOP_REQ default value */
2963         if (ASIC_IS_RV100(rdev))
2964                 max_stop_req = 0x5c;
2965         else
2966                 max_stop_req = 0x7c;
2967
2968         if (mode1) {
2969                 /*  CRTC1
2970                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2971                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2972                 */
2973                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2974
2975                 if (stop_req > max_stop_req)
2976                         stop_req = max_stop_req;
2977
2978                 /*
2979                   Find the drain rate of the display buffer.
2980                 */
2981                 temp_ff.full = dfixed_const((16/pixel_bytes1));
2982                 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
2983
2984                 /*
2985                   Find the critical point of the display buffer.
2986                 */
2987                 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
2988                 crit_point_ff.full += dfixed_const_half(0);
2989
2990                 critical_point = dfixed_trunc(crit_point_ff);
2991
2992                 if (rdev->disp_priority == 2) {
2993                         critical_point = 0;
2994                 }
2995
2996                 /*
2997                   The critical point should never be above max_stop_req-4.  Setting
2998                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2999                 */
3000                 if (max_stop_req - critical_point < 4)
3001                         critical_point = 0;
3002
3003                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3004                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3005                         critical_point = 0x10;
3006                 }
3007
3008                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3009                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3010                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3011                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3012                 if ((rdev->family == CHIP_R350) &&
3013                     (stop_req > 0x15)) {
3014                         stop_req -= 0x10;
3015                 }
3016                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3017                 temp |= RADEON_GRPH_BUFFER_SIZE;
3018                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3019                           RADEON_GRPH_CRITICAL_AT_SOF |
3020                           RADEON_GRPH_STOP_CNTL);
3021                 /*
3022                   Write the result into the register.
3023                 */
3024                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3025                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3026
3027 #if 0
3028                 if ((rdev->family == CHIP_RS400) ||
3029                     (rdev->family == CHIP_RS480)) {
3030                         /* attempt to program RS400 disp regs correctly ??? */
3031                         temp = RREG32(RS400_DISP1_REG_CNTL);
3032                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3033                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
3034                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3035                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3036                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3037                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
3038                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3039                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3040                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3041                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3042                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3043                 }
3044 #endif
3045
3046                 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3047                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
3048                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3049         }
3050
3051         if (mode2) {
3052                 u32 grph2_cntl;
3053                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3054
3055                 if (stop_req > max_stop_req)
3056                         stop_req = max_stop_req;
3057
3058                 /*
3059                   Find the drain rate of the display buffer.
3060                 */
3061                 temp_ff.full = dfixed_const((16/pixel_bytes2));
3062                 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3063
3064                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3065                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3066                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3067                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3068                 if ((rdev->family == CHIP_R350) &&
3069                     (stop_req > 0x15)) {
3070                         stop_req -= 0x10;
3071                 }
3072                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3073                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3074                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3075                           RADEON_GRPH_CRITICAL_AT_SOF |
3076                           RADEON_GRPH_STOP_CNTL);
3077
3078                 if ((rdev->family == CHIP_RS100) ||
3079                     (rdev->family == CHIP_RS200))
3080                         critical_point2 = 0;
3081                 else {
3082                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3083                         temp_ff.full = dfixed_const(temp);
3084                         temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3085                         if (sclk_ff.full < temp_ff.full)
3086                                 temp_ff.full = sclk_ff.full;
3087
3088                         read_return_rate.full = temp_ff.full;
3089
3090                         if (mode1) {
3091                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3092                                 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3093                         } else {
3094                                 time_disp1_drop_priority.full = 0;
3095                         }
3096                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3097                         crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3098                         crit_point_ff.full += dfixed_const_half(0);
3099
3100                         critical_point2 = dfixed_trunc(crit_point_ff);
3101
3102                         if (rdev->disp_priority == 2) {
3103                                 critical_point2 = 0;
3104                         }
3105
3106                         if (max_stop_req - critical_point2 < 4)
3107                                 critical_point2 = 0;
3108
3109                 }
3110
3111                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3112                         /* some R300 cards have problem with this set to 0 */
3113                         critical_point2 = 0x10;
3114                 }
3115
3116                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3117                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3118
3119                 if ((rdev->family == CHIP_RS400) ||
3120                     (rdev->family == CHIP_RS480)) {
3121 #if 0
3122                         /* attempt to program RS400 disp2 regs correctly ??? */
3123                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
3124                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3125                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
3126                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3127                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3128                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3129                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
3130                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3131                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3132                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3133                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3134                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3135 #endif
3136                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3137                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3138                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
3139                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3140                 }
3141
3142                 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3143                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3144         }
3145 }
3146
3147 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3148 {
3149         DRM_ERROR("pitch                      %d\n", t->pitch);
3150         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
3151         DRM_ERROR("width                      %d\n", t->width);
3152         DRM_ERROR("width_11                   %d\n", t->width_11);
3153         DRM_ERROR("height                     %d\n", t->height);
3154         DRM_ERROR("height_11                  %d\n", t->height_11);
3155         DRM_ERROR("num levels                 %d\n", t->num_levels);
3156         DRM_ERROR("depth                      %d\n", t->txdepth);
3157         DRM_ERROR("bpp                        %d\n", t->cpp);
3158         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
3159         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
3160         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3161         DRM_ERROR("compress format            %d\n", t->compress_format);
3162 }
3163
3164 static int r100_track_compress_size(int compress_format, int w, int h)
3165 {
3166         int block_width, block_height, block_bytes;
3167         int wblocks, hblocks;
3168         int min_wblocks;
3169         int sz;
3170
3171         block_width = 4;
3172         block_height = 4;
3173
3174         switch (compress_format) {
3175         case R100_TRACK_COMP_DXT1:
3176                 block_bytes = 8;
3177                 min_wblocks = 4;
3178                 break;
3179         default:
3180         case R100_TRACK_COMP_DXT35:
3181                 block_bytes = 16;
3182                 min_wblocks = 2;
3183                 break;
3184         }
3185
3186         hblocks = (h + block_height - 1) / block_height;
3187         wblocks = (w + block_width - 1) / block_width;
3188         if (wblocks < min_wblocks)
3189                 wblocks = min_wblocks;
3190         sz = wblocks * hblocks * block_bytes;
3191         return sz;
3192 }
3193
3194 static int r100_cs_track_cube(struct radeon_device *rdev,
3195                               struct r100_cs_track *track, unsigned idx)
3196 {
3197         unsigned face, w, h;
3198         struct radeon_bo *cube_robj;
3199         unsigned long size;
3200         unsigned compress_format = track->textures[idx].compress_format;
3201
3202         for (face = 0; face < 5; face++) {
3203                 cube_robj = track->textures[idx].cube_info[face].robj;
3204                 w = track->textures[idx].cube_info[face].width;
3205                 h = track->textures[idx].cube_info[face].height;
3206
3207                 if (compress_format) {
3208                         size = r100_track_compress_size(compress_format, w, h);
3209                 } else
3210                         size = w * h;
3211                 size *= track->textures[idx].cpp;
3212
3213                 size += track->textures[idx].cube_info[face].offset;
3214
3215                 if (size > radeon_bo_size(cube_robj)) {
3216                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3217                                   size, radeon_bo_size(cube_robj));
3218                         r100_cs_track_texture_print(&track->textures[idx]);
3219                         return -1;
3220                 }
3221         }
3222         return 0;
3223 }
3224
3225 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3226                                        struct r100_cs_track *track)
3227 {
3228         struct radeon_bo *robj;
3229         unsigned long size;
3230         unsigned u, i, w, h, d;
3231         int ret;
3232
3233         for (u = 0; u < track->num_texture; u++) {
3234                 if (!track->textures[u].enabled)
3235                         continue;
3236                 robj = track->textures[u].robj;
3237                 if (robj == NULL) {
3238                         DRM_ERROR("No texture bound to unit %u\n", u);
3239                         return -EINVAL;
3240                 }
3241                 size = 0;
3242                 for (i = 0; i <= track->textures[u].num_levels; i++) {
3243                         if (track->textures[u].use_pitch) {
3244                                 if (rdev->family < CHIP_R300)
3245                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3246                                 else
3247                                         w = track->textures[u].pitch / (1 << i);
3248                         } else {
3249                                 w = track->textures[u].width;
3250                                 if (rdev->family >= CHIP_RV515)
3251                                         w |= track->textures[u].width_11;
3252                                 w = w / (1 << i);
3253                                 if (track->textures[u].roundup_w)
3254                                         w = roundup_pow_of_two(w);
3255                         }
3256                         h = track->textures[u].height;
3257                         if (rdev->family >= CHIP_RV515)
3258                                 h |= track->textures[u].height_11;
3259                         h = h / (1 << i);
3260                         if (track->textures[u].roundup_h)
3261                                 h = roundup_pow_of_two(h);
3262                         if (track->textures[u].tex_coord_type == 1) {
3263                                 d = (1 << track->textures[u].txdepth) / (1 << i);
3264                                 if (!d)
3265                                         d = 1;
3266                         } else {
3267                                 d = 1;
3268                         }
3269                         if (track->textures[u].compress_format) {
3270
3271                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3272                                 /* compressed textures are block based */
3273                         } else
3274                                 size += w * h * d;
3275                 }
3276                 size *= track->textures[u].cpp;
3277
3278                 switch (track->textures[u].tex_coord_type) {
3279                 case 0:
3280                 case 1:
3281                         break;
3282                 case 2:
3283                         if (track->separate_cube) {
3284                                 ret = r100_cs_track_cube(rdev, track, u);
3285                                 if (ret)
3286                                         return ret;
3287                         } else
3288                                 size *= 6;
3289                         break;
3290                 default:
3291                         DRM_ERROR("Invalid texture coordinate type %u for unit "
3292                                   "%u\n", track->textures[u].tex_coord_type, u);
3293                         return -EINVAL;
3294                 }
3295                 if (size > radeon_bo_size(robj)) {
3296                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3297                                   "%lu\n", u, size, radeon_bo_size(robj));
3298                         r100_cs_track_texture_print(&track->textures[u]);
3299                         return -EINVAL;
3300                 }
3301         }
3302         return 0;
3303 }
3304
3305 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3306 {
3307         unsigned i;
3308         unsigned long size;
3309         unsigned prim_walk;
3310         unsigned nverts;
3311
3312         for (i = 0; i < track->num_cb; i++) {
3313                 if (track->cb[i].robj == NULL) {
3314                         if (!(track->zb_cb_clear || track->color_channel_mask ||
3315                               track->blend_read_enable)) {
3316                                 continue;
3317                         }
3318                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3319                         return -EINVAL;
3320                 }
3321                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3322                 size += track->cb[i].offset;
3323                 if (size > radeon_bo_size(track->cb[i].robj)) {
3324                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
3325                                   "(need %lu have %lu) !\n", i, size,
3326                                   radeon_bo_size(track->cb[i].robj));
3327                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3328                                   i, track->cb[i].pitch, track->cb[i].cpp,
3329                                   track->cb[i].offset, track->maxy);
3330                         return -EINVAL;
3331                 }
3332         }
3333         if (track->z_enabled) {
3334                 if (track->zb.robj == NULL) {
3335                         DRM_ERROR("[drm] No buffer for z buffer !\n");
3336                         return -EINVAL;
3337                 }
3338                 size = track->zb.pitch * track->zb.cpp * track->maxy;
3339                 size += track->zb.offset;
3340                 if (size > radeon_bo_size(track->zb.robj)) {
3341                         DRM_ERROR("[drm] Buffer too small for z buffer "
3342                                   "(need %lu have %lu) !\n", size,
3343                                   radeon_bo_size(track->zb.robj));
3344                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3345                                   track->zb.pitch, track->zb.cpp,
3346                                   track->zb.offset, track->maxy);
3347                         return -EINVAL;
3348                 }
3349         }
3350         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3351         if (track->vap_vf_cntl & (1 << 14)) {
3352                 nverts = track->vap_alt_nverts;
3353         } else {
3354                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3355         }
3356         switch (prim_walk) {
3357         case 1:
3358                 for (i = 0; i < track->num_arrays; i++) {
3359                         size = track->arrays[i].esize * track->max_indx * 4;
3360                         if (track->arrays[i].robj == NULL) {
3361                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3362                                           "bound\n", prim_walk, i);
3363                                 return -EINVAL;
3364                         }
3365                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3366                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3367                                         "need %lu dwords have %lu dwords\n",
3368                                         prim_walk, i, size >> 2,
3369                                         radeon_bo_size(track->arrays[i].robj)
3370                                         >> 2);
3371                                 DRM_ERROR("Max indices %u\n", track->max_indx);
3372                                 return -EINVAL;
3373                         }
3374                 }
3375                 break;
3376         case 2:
3377                 for (i = 0; i < track->num_arrays; i++) {
3378                         size = track->arrays[i].esize * (nverts - 1) * 4;
3379                         if (track->arrays[i].robj == NULL) {
3380                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3381                                           "bound\n", prim_walk, i);
3382                                 return -EINVAL;
3383                         }
3384                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3385                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3386                                         "need %lu dwords have %lu dwords\n",
3387                                         prim_walk, i, size >> 2,
3388                                         radeon_bo_size(track->arrays[i].robj)
3389                                         >> 2);
3390                                 return -EINVAL;
3391                         }
3392                 }
3393                 break;
3394         case 3:
3395                 size = track->vtx_size * nverts;
3396                 if (size != track->immd_dwords) {
3397                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3398                                   track->immd_dwords, size);
3399                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3400                                   nverts, track->vtx_size);
3401                         return -EINVAL;
3402                 }
3403                 break;
3404         default:
3405                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3406                           prim_walk);
3407                 return -EINVAL;
3408         }
3409         return r100_cs_track_texture_check(rdev, track);
3410 }
3411
3412 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3413 {
3414         unsigned i, face;
3415
3416         if (rdev->family < CHIP_R300) {
3417                 track->num_cb = 1;
3418                 if (rdev->family <= CHIP_RS200)
3419                         track->num_texture = 3;
3420                 else
3421                         track->num_texture = 6;
3422                 track->maxy = 2048;
3423                 track->separate_cube = 1;
3424         } else {
3425                 track->num_cb = 4;
3426                 track->num_texture = 16;
3427                 track->maxy = 4096;
3428                 track->separate_cube = 0;
3429         }
3430
3431         for (i = 0; i < track->num_cb; i++) {
3432                 track->cb[i].robj = NULL;
3433                 track->cb[i].pitch = 8192;
3434                 track->cb[i].cpp = 16;
3435                 track->cb[i].offset = 0;
3436         }
3437         track->z_enabled = true;
3438         track->zb.robj = NULL;
3439         track->zb.pitch = 8192;
3440         track->zb.cpp = 4;
3441         track->zb.offset = 0;
3442         track->vtx_size = 0x7F;
3443         track->immd_dwords = 0xFFFFFFFFUL;
3444         track->num_arrays = 11;
3445         track->max_indx = 0x00FFFFFFUL;
3446         for (i = 0; i < track->num_arrays; i++) {
3447                 track->arrays[i].robj = NULL;
3448                 track->arrays[i].esize = 0x7F;
3449         }
3450         for (i = 0; i < track->num_texture; i++) {
3451                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3452                 track->textures[i].pitch = 16536;
3453                 track->textures[i].width = 16536;
3454                 track->textures[i].height = 16536;
3455                 track->textures[i].width_11 = 1 << 11;
3456                 track->textures[i].height_11 = 1 << 11;
3457                 track->textures[i].num_levels = 12;
3458                 if (rdev->family <= CHIP_RS200) {
3459                         track->textures[i].tex_coord_type = 0;
3460                         track->textures[i].txdepth = 0;
3461                 } else {
3462                         track->textures[i].txdepth = 16;
3463                         track->textures[i].tex_coord_type = 1;
3464                 }
3465                 track->textures[i].cpp = 64;
3466                 track->textures[i].robj = NULL;
3467                 /* CS IB emission code makes sure texture unit are disabled */
3468                 track->textures[i].enabled = false;
3469                 track->textures[i].roundup_w = true;
3470                 track->textures[i].roundup_h = true;
3471                 if (track->separate_cube)
3472                         for (face = 0; face < 5; face++) {
3473                                 track->textures[i].cube_info[face].robj = NULL;
3474                                 track->textures[i].cube_info[face].width = 16536;
3475                                 track->textures[i].cube_info[face].height = 16536;
3476                                 track->textures[i].cube_info[face].offset = 0;
3477                         }
3478         }
3479 }
3480
3481 int r100_ring_test(struct radeon_device *rdev)
3482 {
3483         uint32_t scratch;
3484         uint32_t tmp = 0;
3485         unsigned i;
3486         int r;
3487
3488         r = radeon_scratch_get(rdev, &scratch);
3489         if (r) {
3490                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3491                 return r;
3492         }
3493         WREG32(scratch, 0xCAFEDEAD);
3494         r = radeon_ring_lock(rdev, 2);
3495         if (r) {
3496                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3497                 radeon_scratch_free(rdev, scratch);
3498                 return r;
3499         }
3500         radeon_ring_write(rdev, PACKET0(scratch, 0));
3501         radeon_ring_write(rdev, 0xDEADBEEF);
3502         radeon_ring_unlock_commit(rdev);
3503         for (i = 0; i < rdev->usec_timeout; i++) {
3504                 tmp = RREG32(scratch);
3505                 if (tmp == 0xDEADBEEF) {
3506                         break;
3507                 }
3508                 DRM_UDELAY(1);
3509         }
3510         if (i < rdev->usec_timeout) {
3511                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3512         } else {
3513                 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3514                           scratch, tmp);
3515                 r = -EINVAL;
3516         }
3517         radeon_scratch_free(rdev, scratch);
3518         return r;
3519 }
3520
3521 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3522 {
3523         radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3524         radeon_ring_write(rdev, ib->gpu_addr);
3525         radeon_ring_write(rdev, ib->length_dw);
3526 }
3527
3528 int r100_ib_test(struct radeon_device *rdev)
3529 {
3530         struct radeon_ib *ib;
3531         uint32_t scratch;
3532         uint32_t tmp = 0;
3533         unsigned i;
3534         int r;
3535
3536         r = radeon_scratch_get(rdev, &scratch);
3537         if (r) {
3538                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3539                 return r;
3540         }
3541         WREG32(scratch, 0xCAFEDEAD);
3542         r = radeon_ib_get(rdev, &ib);
3543         if (r) {
3544                 return r;
3545         }
3546         ib->ptr[0] = PACKET0(scratch, 0);
3547         ib->ptr[1] = 0xDEADBEEF;
3548         ib->ptr[2] = PACKET2(0);
3549         ib->ptr[3] = PACKET2(0);
3550         ib->ptr[4] = PACKET2(0);
3551         ib->ptr[5] = PACKET2(0);
3552         ib->ptr[6] = PACKET2(0);
3553         ib->ptr[7] = PACKET2(0);
3554         ib->length_dw = 8;
3555         r = radeon_ib_schedule(rdev, ib);
3556         if (r) {
3557                 radeon_scratch_free(rdev, scratch);
3558                 radeon_ib_free(rdev, &ib);
3559                 return r;
3560         }
3561         r = radeon_fence_wait(ib->fence, false);
3562         if (r) {
3563                 return r;
3564         }
3565         for (i = 0; i < rdev->usec_timeout; i++) {
3566                 tmp = RREG32(scratch);
3567                 if (tmp == 0xDEADBEEF) {
3568                         break;
3569                 }
3570                 DRM_UDELAY(1);
3571         }
3572         if (i < rdev->usec_timeout) {
3573                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3574         } else {
3575                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3576                           scratch, tmp);
3577                 r = -EINVAL;
3578         }
3579         radeon_scratch_free(rdev, scratch);
3580         radeon_ib_free(rdev, &ib);
3581         return r;
3582 }
3583
3584 void r100_ib_fini(struct radeon_device *rdev)
3585 {
3586         radeon_ib_pool_fini(rdev);
3587 }
3588
3589 int r100_ib_init(struct radeon_device *rdev)
3590 {
3591         int r;
3592
3593         r = radeon_ib_pool_init(rdev);
3594         if (r) {
3595                 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3596                 r100_ib_fini(rdev);
3597                 return r;
3598         }
3599         r = r100_ib_test(rdev);
3600         if (r) {
3601                 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3602                 r100_ib_fini(rdev);
3603                 return r;
3604         }
3605         return 0;
3606 }
3607
3608 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3609 {
3610         /* Shutdown CP we shouldn't need to do that but better be safe than
3611          * sorry
3612          */
3613         rdev->cp.ready = false;
3614         WREG32(R_000740_CP_CSQ_CNTL, 0);
3615
3616         /* Save few CRTC registers */
3617         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3618         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3619         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3620         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3621         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3622                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3623                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3624         }
3625
3626         /* Disable VGA aperture access */
3627         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3628         /* Disable cursor, overlay, crtc */
3629         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3630         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3631                                         S_000054_CRTC_DISPLAY_DIS(1));
3632         WREG32(R_000050_CRTC_GEN_CNTL,
3633                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3634                         S_000050_CRTC_DISP_REQ_EN_B(1));
3635         WREG32(R_000420_OV0_SCALE_CNTL,
3636                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3637         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3638         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3639                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3640                                                 S_000360_CUR2_LOCK(1));
3641                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3642                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3643                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3644                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3645                 WREG32(R_000360_CUR2_OFFSET,
3646                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3647         }
3648 }
3649
3650 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3651 {
3652         /* Update base address for crtc */
3653         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3654         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3655                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3656         }
3657         /* Restore CRTC registers */
3658         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3659         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3660         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3661         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3662                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3663         }
3664 }
3665
3666 void r100_vga_render_disable(struct radeon_device *rdev)
3667 {
3668         u32 tmp;
3669
3670         tmp = RREG8(R_0003C2_GENMO_WT);
3671         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3672 }
3673
3674 static void r100_debugfs(struct radeon_device *rdev)
3675 {
3676         int r;
3677
3678         r = r100_debugfs_mc_info_init(rdev);
3679         if (r)
3680                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3681 }
3682
3683 static void r100_mc_program(struct radeon_device *rdev)
3684 {
3685         struct r100_mc_save save;
3686
3687         /* Stops all mc clients */
3688         r100_mc_stop(rdev, &save);
3689         if (rdev->flags & RADEON_IS_AGP) {
3690                 WREG32(R_00014C_MC_AGP_LOCATION,
3691                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3692                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3693                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3694                 if (rdev->family > CHIP_RV200)
3695                         WREG32(R_00015C_AGP_BASE_2,
3696                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3697         } else {
3698                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3699                 WREG32(R_000170_AGP_BASE, 0);
3700                 if (rdev->family > CHIP_RV200)
3701                         WREG32(R_00015C_AGP_BASE_2, 0);
3702         }
3703         /* Wait for mc idle */
3704         if (r100_mc_wait_for_idle(rdev))
3705                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3706         /* Program MC, should be a 32bits limited address space */
3707         WREG32(R_000148_MC_FB_LOCATION,
3708                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3709                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3710         r100_mc_resume(rdev, &save);
3711 }
3712
3713 void r100_clock_startup(struct radeon_device *rdev)
3714 {
3715         u32 tmp;
3716
3717         if (radeon_dynclks != -1 && radeon_dynclks)
3718                 radeon_legacy_set_clock_gating(rdev, 1);
3719         /* We need to force on some of the block */
3720         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3721         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3722         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3723                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3724         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3725 }
3726
3727 static int r100_startup(struct radeon_device *rdev)
3728 {
3729         int r;
3730
3731         /* set common regs */
3732         r100_set_common_regs(rdev);
3733         /* program mc */
3734         r100_mc_program(rdev);
3735         /* Resume clock */
3736         r100_clock_startup(rdev);
3737         /* Initialize GPU configuration (# pipes, ...) */
3738 //      r100_gpu_init(rdev);
3739         /* Initialize GART (initialize after TTM so we can allocate
3740          * memory through TTM but finalize after TTM) */
3741         r100_enable_bm(rdev);
3742         if (rdev->flags & RADEON_IS_PCI) {
3743                 r = r100_pci_gart_enable(rdev);
3744                 if (r)
3745                         return r;
3746         }
3747         /* Enable IRQ */
3748         r100_irq_set(rdev);
3749         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3750         /* 1M ring buffer */
3751         r = r100_cp_init(rdev, 1024 * 1024);
3752         if (r) {
3753                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3754                 return r;
3755         }
3756         r = r100_wb_init(rdev);
3757         if (r)
3758                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3759         r = r100_ib_init(rdev);
3760         if (r) {
3761                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3762                 return r;
3763         }
3764         return 0;
3765 }
3766
3767 int r100_resume(struct radeon_device *rdev)
3768 {
3769         /* Make sur GART are not working */
3770         if (rdev->flags & RADEON_IS_PCI)
3771                 r100_pci_gart_disable(rdev);
3772         /* Resume clock before doing reset */
3773         r100_clock_startup(rdev);
3774         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3775         if (radeon_asic_reset(rdev)) {
3776                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3777                         RREG32(R_000E40_RBBM_STATUS),
3778                         RREG32(R_0007C0_CP_STAT));
3779         }
3780         /* post */
3781         radeon_combios_asic_init(rdev->ddev);
3782         /* Resume clock after posting */
3783         r100_clock_startup(rdev);
3784         /* Initialize surface registers */
3785         radeon_surface_init(rdev);
3786         return r100_startup(rdev);
3787 }
3788
3789 int r100_suspend(struct radeon_device *rdev)
3790 {
3791         r100_cp_disable(rdev);
3792         r100_wb_disable(rdev);
3793         r100_irq_disable(rdev);
3794         if (rdev->flags & RADEON_IS_PCI)
3795                 r100_pci_gart_disable(rdev);
3796         return 0;
3797 }
3798
3799 void r100_fini(struct radeon_device *rdev)
3800 {
3801         r100_cp_fini(rdev);
3802         r100_wb_fini(rdev);
3803         r100_ib_fini(rdev);
3804         radeon_gem_fini(rdev);
3805         if (rdev->flags & RADEON_IS_PCI)
3806                 r100_pci_gart_fini(rdev);
3807         radeon_agp_fini(rdev);
3808         radeon_irq_kms_fini(rdev);
3809         radeon_fence_driver_fini(rdev);
3810         radeon_bo_fini(rdev);
3811         radeon_atombios_fini(rdev);
3812         kfree(rdev->bios);
3813         rdev->bios = NULL;
3814 }
3815
3816 /*
3817  * Due to how kexec works, it can leave the hw fully initialised when it
3818  * boots the new kernel. However doing our init sequence with the CP and
3819  * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3820  * do some quick sanity checks and restore sane values to avoid this
3821  * problem.
3822  */
3823 void r100_restore_sanity(struct radeon_device *rdev)
3824 {
3825         u32 tmp;
3826
3827         tmp = RREG32(RADEON_CP_CSQ_CNTL);
3828         if (tmp) {
3829                 WREG32(RADEON_CP_CSQ_CNTL, 0);
3830         }
3831         tmp = RREG32(RADEON_CP_RB_CNTL);
3832         if (tmp) {
3833                 WREG32(RADEON_CP_RB_CNTL, 0);
3834         }
3835         tmp = RREG32(RADEON_SCRATCH_UMSK);
3836         if (tmp) {
3837                 WREG32(RADEON_SCRATCH_UMSK, 0);
3838         }
3839 }
3840
3841 int r100_init(struct radeon_device *rdev)
3842 {
3843         int r;
3844
3845         /* Register debugfs file specific to this group of asics */
3846         r100_debugfs(rdev);
3847         /* Disable VGA */
3848         r100_vga_render_disable(rdev);
3849         /* Initialize scratch registers */
3850         radeon_scratch_init(rdev);
3851         /* Initialize surface registers */
3852         radeon_surface_init(rdev);
3853         /* sanity check some register to avoid hangs like after kexec */
3854         r100_restore_sanity(rdev);
3855         /* TODO: disable VGA need to use VGA request */
3856         /* BIOS*/
3857         if (!radeon_get_bios(rdev)) {
3858                 if (ASIC_IS_AVIVO(rdev))
3859                         return -EINVAL;
3860         }
3861         if (rdev->is_atom_bios) {
3862                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3863                 return -EINVAL;
3864         } else {
3865                 r = radeon_combios_init(rdev);
3866                 if (r)
3867                         return r;
3868         }
3869         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3870         if (radeon_asic_reset(rdev)) {
3871                 dev_warn(rdev->dev,
3872                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3873                         RREG32(R_000E40_RBBM_STATUS),
3874                         RREG32(R_0007C0_CP_STAT));
3875         }
3876         /* check if cards are posted or not */
3877         if (radeon_boot_test_post_card(rdev) == false)
3878                 return -EINVAL;
3879         /* Set asic errata */
3880         r100_errata(rdev);
3881         /* Initialize clocks */
3882         radeon_get_clock_info(rdev->ddev);
3883         /* initialize AGP */
3884         if (rdev->flags & RADEON_IS_AGP) {
3885                 r = radeon_agp_init(rdev);
3886                 if (r) {
3887                         radeon_agp_disable(rdev);
3888                 }
3889         }
3890         /* initialize VRAM */
3891         r100_mc_init(rdev);
3892         /* Fence driver */
3893         r = radeon_fence_driver_init(rdev);
3894         if (r)
3895                 return r;
3896         r = radeon_irq_kms_init(rdev);
3897         if (r)
3898                 return r;
3899         /* Memory manager */
3900         r = radeon_bo_init(rdev);
3901         if (r)
3902                 return r;
3903         if (rdev->flags & RADEON_IS_PCI) {
3904                 r = r100_pci_gart_init(rdev);
3905                 if (r)
3906                         return r;
3907         }
3908         r100_set_safe_registers(rdev);
3909         rdev->accel_working = true;
3910         r = r100_startup(rdev);
3911         if (r) {
3912                 /* Somethings want wront with the accel init stop accel */
3913                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3914                 r100_cp_fini(rdev);
3915                 r100_wb_fini(rdev);
3916                 r100_ib_fini(rdev);
3917                 radeon_irq_kms_fini(rdev);
3918                 if (rdev->flags & RADEON_IS_PCI)
3919                         r100_pci_gart_fini(rdev);
3920                 rdev->accel_working = false;
3921         }
3922         return 0;
3923 }