drm/radeon: Unbreak HPD handling for r600+
[sfrench/cifs-2.6.git] / drivers / gpu / drm / radeon / cik.c
1 /*
2  * Copyright 2012 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Alex Deucher
23  */
24 #include <linux/firmware.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
27 #include "drmP.h"
28 #include "radeon.h"
29 #include "radeon_asic.h"
30 #include "radeon_audio.h"
31 #include "cikd.h"
32 #include "atom.h"
33 #include "cik_blit_shaders.h"
34 #include "radeon_ucode.h"
35 #include "clearstate_ci.h"
36 #include "radeon_kfd.h"
37
38 #define SH_MEM_CONFIG_GFX_DEFAULT \
39         ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED)
40
41 MODULE_FIRMWARE("radeon/BONAIRE_pfp.bin");
42 MODULE_FIRMWARE("radeon/BONAIRE_me.bin");
43 MODULE_FIRMWARE("radeon/BONAIRE_ce.bin");
44 MODULE_FIRMWARE("radeon/BONAIRE_mec.bin");
45 MODULE_FIRMWARE("radeon/BONAIRE_mc.bin");
46 MODULE_FIRMWARE("radeon/BONAIRE_mc2.bin");
47 MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin");
48 MODULE_FIRMWARE("radeon/BONAIRE_sdma.bin");
49 MODULE_FIRMWARE("radeon/BONAIRE_smc.bin");
50
51 MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
52 MODULE_FIRMWARE("radeon/bonaire_me.bin");
53 MODULE_FIRMWARE("radeon/bonaire_ce.bin");
54 MODULE_FIRMWARE("radeon/bonaire_mec.bin");
55 MODULE_FIRMWARE("radeon/bonaire_mc.bin");
56 MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
57 MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
58 MODULE_FIRMWARE("radeon/bonaire_smc.bin");
59 MODULE_FIRMWARE("radeon/bonaire_k_smc.bin");
60
61 MODULE_FIRMWARE("radeon/HAWAII_pfp.bin");
62 MODULE_FIRMWARE("radeon/HAWAII_me.bin");
63 MODULE_FIRMWARE("radeon/HAWAII_ce.bin");
64 MODULE_FIRMWARE("radeon/HAWAII_mec.bin");
65 MODULE_FIRMWARE("radeon/HAWAII_mc.bin");
66 MODULE_FIRMWARE("radeon/HAWAII_mc2.bin");
67 MODULE_FIRMWARE("radeon/HAWAII_rlc.bin");
68 MODULE_FIRMWARE("radeon/HAWAII_sdma.bin");
69 MODULE_FIRMWARE("radeon/HAWAII_smc.bin");
70
71 MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
72 MODULE_FIRMWARE("radeon/hawaii_me.bin");
73 MODULE_FIRMWARE("radeon/hawaii_ce.bin");
74 MODULE_FIRMWARE("radeon/hawaii_mec.bin");
75 MODULE_FIRMWARE("radeon/hawaii_mc.bin");
76 MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
77 MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
78 MODULE_FIRMWARE("radeon/hawaii_smc.bin");
79 MODULE_FIRMWARE("radeon/hawaii_k_smc.bin");
80
81 MODULE_FIRMWARE("radeon/KAVERI_pfp.bin");
82 MODULE_FIRMWARE("radeon/KAVERI_me.bin");
83 MODULE_FIRMWARE("radeon/KAVERI_ce.bin");
84 MODULE_FIRMWARE("radeon/KAVERI_mec.bin");
85 MODULE_FIRMWARE("radeon/KAVERI_rlc.bin");
86 MODULE_FIRMWARE("radeon/KAVERI_sdma.bin");
87
88 MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
89 MODULE_FIRMWARE("radeon/kaveri_me.bin");
90 MODULE_FIRMWARE("radeon/kaveri_ce.bin");
91 MODULE_FIRMWARE("radeon/kaveri_mec.bin");
92 MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
93 MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
94 MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
95
96 MODULE_FIRMWARE("radeon/KABINI_pfp.bin");
97 MODULE_FIRMWARE("radeon/KABINI_me.bin");
98 MODULE_FIRMWARE("radeon/KABINI_ce.bin");
99 MODULE_FIRMWARE("radeon/KABINI_mec.bin");
100 MODULE_FIRMWARE("radeon/KABINI_rlc.bin");
101 MODULE_FIRMWARE("radeon/KABINI_sdma.bin");
102
103 MODULE_FIRMWARE("radeon/kabini_pfp.bin");
104 MODULE_FIRMWARE("radeon/kabini_me.bin");
105 MODULE_FIRMWARE("radeon/kabini_ce.bin");
106 MODULE_FIRMWARE("radeon/kabini_mec.bin");
107 MODULE_FIRMWARE("radeon/kabini_rlc.bin");
108 MODULE_FIRMWARE("radeon/kabini_sdma.bin");
109
110 MODULE_FIRMWARE("radeon/MULLINS_pfp.bin");
111 MODULE_FIRMWARE("radeon/MULLINS_me.bin");
112 MODULE_FIRMWARE("radeon/MULLINS_ce.bin");
113 MODULE_FIRMWARE("radeon/MULLINS_mec.bin");
114 MODULE_FIRMWARE("radeon/MULLINS_rlc.bin");
115 MODULE_FIRMWARE("radeon/MULLINS_sdma.bin");
116
117 MODULE_FIRMWARE("radeon/mullins_pfp.bin");
118 MODULE_FIRMWARE("radeon/mullins_me.bin");
119 MODULE_FIRMWARE("radeon/mullins_ce.bin");
120 MODULE_FIRMWARE("radeon/mullins_mec.bin");
121 MODULE_FIRMWARE("radeon/mullins_rlc.bin");
122 MODULE_FIRMWARE("radeon/mullins_sdma.bin");
123
124 extern int r600_ih_ring_alloc(struct radeon_device *rdev);
125 extern void r600_ih_ring_fini(struct radeon_device *rdev);
126 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
127 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
128 extern bool evergreen_is_display_hung(struct radeon_device *rdev);
129 extern void sumo_rlc_fini(struct radeon_device *rdev);
130 extern int sumo_rlc_init(struct radeon_device *rdev);
131 extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
132 extern void si_rlc_reset(struct radeon_device *rdev);
133 extern void si_init_uvd_internal_cg(struct radeon_device *rdev);
134 static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh);
135 extern int cik_sdma_resume(struct radeon_device *rdev);
136 extern void cik_sdma_enable(struct radeon_device *rdev, bool enable);
137 extern void cik_sdma_fini(struct radeon_device *rdev);
138 extern void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable);
139 static void cik_rlc_stop(struct radeon_device *rdev);
140 static void cik_pcie_gen3_enable(struct radeon_device *rdev);
141 static void cik_program_aspm(struct radeon_device *rdev);
142 static void cik_init_pg(struct radeon_device *rdev);
143 static void cik_init_cg(struct radeon_device *rdev);
144 static void cik_fini_pg(struct radeon_device *rdev);
145 static void cik_fini_cg(struct radeon_device *rdev);
146 static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
147                                           bool enable);
148
149 /**
150  * cik_get_allowed_info_register - fetch the register for the info ioctl
151  *
152  * @rdev: radeon_device pointer
153  * @reg: register offset in bytes
154  * @val: register value
155  *
156  * Returns 0 for success or -EINVAL for an invalid register
157  *
158  */
159 int cik_get_allowed_info_register(struct radeon_device *rdev,
160                                   u32 reg, u32 *val)
161 {
162         switch (reg) {
163         case GRBM_STATUS:
164         case GRBM_STATUS2:
165         case GRBM_STATUS_SE0:
166         case GRBM_STATUS_SE1:
167         case GRBM_STATUS_SE2:
168         case GRBM_STATUS_SE3:
169         case SRBM_STATUS:
170         case SRBM_STATUS2:
171         case (SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET):
172         case (SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET):
173         case UVD_STATUS:
174         /* TODO VCE */
175                 *val = RREG32(reg);
176                 return 0;
177         default:
178                 return -EINVAL;
179         }
180 }
181
182 /*
183  * Indirect registers accessor
184  */
185 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
186 {
187         unsigned long flags;
188         u32 r;
189
190         spin_lock_irqsave(&rdev->didt_idx_lock, flags);
191         WREG32(CIK_DIDT_IND_INDEX, (reg));
192         r = RREG32(CIK_DIDT_IND_DATA);
193         spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
194         return r;
195 }
196
197 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
198 {
199         unsigned long flags;
200
201         spin_lock_irqsave(&rdev->didt_idx_lock, flags);
202         WREG32(CIK_DIDT_IND_INDEX, (reg));
203         WREG32(CIK_DIDT_IND_DATA, (v));
204         spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
205 }
206
207 /* get temperature in millidegrees */
208 int ci_get_temp(struct radeon_device *rdev)
209 {
210         u32 temp;
211         int actual_temp = 0;
212
213         temp = (RREG32_SMC(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
214                 CTF_TEMP_SHIFT;
215
216         if (temp & 0x200)
217                 actual_temp = 255;
218         else
219                 actual_temp = temp & 0x1ff;
220
221         actual_temp = actual_temp * 1000;
222
223         return actual_temp;
224 }
225
226 /* get temperature in millidegrees */
227 int kv_get_temp(struct radeon_device *rdev)
228 {
229         u32 temp;
230         int actual_temp = 0;
231
232         temp = RREG32_SMC(0xC0300E0C);
233
234         if (temp)
235                 actual_temp = (temp / 8) - 49;
236         else
237                 actual_temp = 0;
238
239         actual_temp = actual_temp * 1000;
240
241         return actual_temp;
242 }
243
244 /*
245  * Indirect registers accessor
246  */
247 u32 cik_pciep_rreg(struct radeon_device *rdev, u32 reg)
248 {
249         unsigned long flags;
250         u32 r;
251
252         spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
253         WREG32(PCIE_INDEX, reg);
254         (void)RREG32(PCIE_INDEX);
255         r = RREG32(PCIE_DATA);
256         spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
257         return r;
258 }
259
260 void cik_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
261 {
262         unsigned long flags;
263
264         spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
265         WREG32(PCIE_INDEX, reg);
266         (void)RREG32(PCIE_INDEX);
267         WREG32(PCIE_DATA, v);
268         (void)RREG32(PCIE_DATA);
269         spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
270 }
271
272 static const u32 spectre_rlc_save_restore_register_list[] =
273 {
274         (0x0e00 << 16) | (0xc12c >> 2),
275         0x00000000,
276         (0x0e00 << 16) | (0xc140 >> 2),
277         0x00000000,
278         (0x0e00 << 16) | (0xc150 >> 2),
279         0x00000000,
280         (0x0e00 << 16) | (0xc15c >> 2),
281         0x00000000,
282         (0x0e00 << 16) | (0xc168 >> 2),
283         0x00000000,
284         (0x0e00 << 16) | (0xc170 >> 2),
285         0x00000000,
286         (0x0e00 << 16) | (0xc178 >> 2),
287         0x00000000,
288         (0x0e00 << 16) | (0xc204 >> 2),
289         0x00000000,
290         (0x0e00 << 16) | (0xc2b4 >> 2),
291         0x00000000,
292         (0x0e00 << 16) | (0xc2b8 >> 2),
293         0x00000000,
294         (0x0e00 << 16) | (0xc2bc >> 2),
295         0x00000000,
296         (0x0e00 << 16) | (0xc2c0 >> 2),
297         0x00000000,
298         (0x0e00 << 16) | (0x8228 >> 2),
299         0x00000000,
300         (0x0e00 << 16) | (0x829c >> 2),
301         0x00000000,
302         (0x0e00 << 16) | (0x869c >> 2),
303         0x00000000,
304         (0x0600 << 16) | (0x98f4 >> 2),
305         0x00000000,
306         (0x0e00 << 16) | (0x98f8 >> 2),
307         0x00000000,
308         (0x0e00 << 16) | (0x9900 >> 2),
309         0x00000000,
310         (0x0e00 << 16) | (0xc260 >> 2),
311         0x00000000,
312         (0x0e00 << 16) | (0x90e8 >> 2),
313         0x00000000,
314         (0x0e00 << 16) | (0x3c000 >> 2),
315         0x00000000,
316         (0x0e00 << 16) | (0x3c00c >> 2),
317         0x00000000,
318         (0x0e00 << 16) | (0x8c1c >> 2),
319         0x00000000,
320         (0x0e00 << 16) | (0x9700 >> 2),
321         0x00000000,
322         (0x0e00 << 16) | (0xcd20 >> 2),
323         0x00000000,
324         (0x4e00 << 16) | (0xcd20 >> 2),
325         0x00000000,
326         (0x5e00 << 16) | (0xcd20 >> 2),
327         0x00000000,
328         (0x6e00 << 16) | (0xcd20 >> 2),
329         0x00000000,
330         (0x7e00 << 16) | (0xcd20 >> 2),
331         0x00000000,
332         (0x8e00 << 16) | (0xcd20 >> 2),
333         0x00000000,
334         (0x9e00 << 16) | (0xcd20 >> 2),
335         0x00000000,
336         (0xae00 << 16) | (0xcd20 >> 2),
337         0x00000000,
338         (0xbe00 << 16) | (0xcd20 >> 2),
339         0x00000000,
340         (0x0e00 << 16) | (0x89bc >> 2),
341         0x00000000,
342         (0x0e00 << 16) | (0x8900 >> 2),
343         0x00000000,
344         0x3,
345         (0x0e00 << 16) | (0xc130 >> 2),
346         0x00000000,
347         (0x0e00 << 16) | (0xc134 >> 2),
348         0x00000000,
349         (0x0e00 << 16) | (0xc1fc >> 2),
350         0x00000000,
351         (0x0e00 << 16) | (0xc208 >> 2),
352         0x00000000,
353         (0x0e00 << 16) | (0xc264 >> 2),
354         0x00000000,
355         (0x0e00 << 16) | (0xc268 >> 2),
356         0x00000000,
357         (0x0e00 << 16) | (0xc26c >> 2),
358         0x00000000,
359         (0x0e00 << 16) | (0xc270 >> 2),
360         0x00000000,
361         (0x0e00 << 16) | (0xc274 >> 2),
362         0x00000000,
363         (0x0e00 << 16) | (0xc278 >> 2),
364         0x00000000,
365         (0x0e00 << 16) | (0xc27c >> 2),
366         0x00000000,
367         (0x0e00 << 16) | (0xc280 >> 2),
368         0x00000000,
369         (0x0e00 << 16) | (0xc284 >> 2),
370         0x00000000,
371         (0x0e00 << 16) | (0xc288 >> 2),
372         0x00000000,
373         (0x0e00 << 16) | (0xc28c >> 2),
374         0x00000000,
375         (0x0e00 << 16) | (0xc290 >> 2),
376         0x00000000,
377         (0x0e00 << 16) | (0xc294 >> 2),
378         0x00000000,
379         (0x0e00 << 16) | (0xc298 >> 2),
380         0x00000000,
381         (0x0e00 << 16) | (0xc29c >> 2),
382         0x00000000,
383         (0x0e00 << 16) | (0xc2a0 >> 2),
384         0x00000000,
385         (0x0e00 << 16) | (0xc2a4 >> 2),
386         0x00000000,
387         (0x0e00 << 16) | (0xc2a8 >> 2),
388         0x00000000,
389         (0x0e00 << 16) | (0xc2ac  >> 2),
390         0x00000000,
391         (0x0e00 << 16) | (0xc2b0 >> 2),
392         0x00000000,
393         (0x0e00 << 16) | (0x301d0 >> 2),
394         0x00000000,
395         (0x0e00 << 16) | (0x30238 >> 2),
396         0x00000000,
397         (0x0e00 << 16) | (0x30250 >> 2),
398         0x00000000,
399         (0x0e00 << 16) | (0x30254 >> 2),
400         0x00000000,
401         (0x0e00 << 16) | (0x30258 >> 2),
402         0x00000000,
403         (0x0e00 << 16) | (0x3025c >> 2),
404         0x00000000,
405         (0x4e00 << 16) | (0xc900 >> 2),
406         0x00000000,
407         (0x5e00 << 16) | (0xc900 >> 2),
408         0x00000000,
409         (0x6e00 << 16) | (0xc900 >> 2),
410         0x00000000,
411         (0x7e00 << 16) | (0xc900 >> 2),
412         0x00000000,
413         (0x8e00 << 16) | (0xc900 >> 2),
414         0x00000000,
415         (0x9e00 << 16) | (0xc900 >> 2),
416         0x00000000,
417         (0xae00 << 16) | (0xc900 >> 2),
418         0x00000000,
419         (0xbe00 << 16) | (0xc900 >> 2),
420         0x00000000,
421         (0x4e00 << 16) | (0xc904 >> 2),
422         0x00000000,
423         (0x5e00 << 16) | (0xc904 >> 2),
424         0x00000000,
425         (0x6e00 << 16) | (0xc904 >> 2),
426         0x00000000,
427         (0x7e00 << 16) | (0xc904 >> 2),
428         0x00000000,
429         (0x8e00 << 16) | (0xc904 >> 2),
430         0x00000000,
431         (0x9e00 << 16) | (0xc904 >> 2),
432         0x00000000,
433         (0xae00 << 16) | (0xc904 >> 2),
434         0x00000000,
435         (0xbe00 << 16) | (0xc904 >> 2),
436         0x00000000,
437         (0x4e00 << 16) | (0xc908 >> 2),
438         0x00000000,
439         (0x5e00 << 16) | (0xc908 >> 2),
440         0x00000000,
441         (0x6e00 << 16) | (0xc908 >> 2),
442         0x00000000,
443         (0x7e00 << 16) | (0xc908 >> 2),
444         0x00000000,
445         (0x8e00 << 16) | (0xc908 >> 2),
446         0x00000000,
447         (0x9e00 << 16) | (0xc908 >> 2),
448         0x00000000,
449         (0xae00 << 16) | (0xc908 >> 2),
450         0x00000000,
451         (0xbe00 << 16) | (0xc908 >> 2),
452         0x00000000,
453         (0x4e00 << 16) | (0xc90c >> 2),
454         0x00000000,
455         (0x5e00 << 16) | (0xc90c >> 2),
456         0x00000000,
457         (0x6e00 << 16) | (0xc90c >> 2),
458         0x00000000,
459         (0x7e00 << 16) | (0xc90c >> 2),
460         0x00000000,
461         (0x8e00 << 16) | (0xc90c >> 2),
462         0x00000000,
463         (0x9e00 << 16) | (0xc90c >> 2),
464         0x00000000,
465         (0xae00 << 16) | (0xc90c >> 2),
466         0x00000000,
467         (0xbe00 << 16) | (0xc90c >> 2),
468         0x00000000,
469         (0x4e00 << 16) | (0xc910 >> 2),
470         0x00000000,
471         (0x5e00 << 16) | (0xc910 >> 2),
472         0x00000000,
473         (0x6e00 << 16) | (0xc910 >> 2),
474         0x00000000,
475         (0x7e00 << 16) | (0xc910 >> 2),
476         0x00000000,
477         (0x8e00 << 16) | (0xc910 >> 2),
478         0x00000000,
479         (0x9e00 << 16) | (0xc910 >> 2),
480         0x00000000,
481         (0xae00 << 16) | (0xc910 >> 2),
482         0x00000000,
483         (0xbe00 << 16) | (0xc910 >> 2),
484         0x00000000,
485         (0x0e00 << 16) | (0xc99c >> 2),
486         0x00000000,
487         (0x0e00 << 16) | (0x9834 >> 2),
488         0x00000000,
489         (0x0000 << 16) | (0x30f00 >> 2),
490         0x00000000,
491         (0x0001 << 16) | (0x30f00 >> 2),
492         0x00000000,
493         (0x0000 << 16) | (0x30f04 >> 2),
494         0x00000000,
495         (0x0001 << 16) | (0x30f04 >> 2),
496         0x00000000,
497         (0x0000 << 16) | (0x30f08 >> 2),
498         0x00000000,
499         (0x0001 << 16) | (0x30f08 >> 2),
500         0x00000000,
501         (0x0000 << 16) | (0x30f0c >> 2),
502         0x00000000,
503         (0x0001 << 16) | (0x30f0c >> 2),
504         0x00000000,
505         (0x0600 << 16) | (0x9b7c >> 2),
506         0x00000000,
507         (0x0e00 << 16) | (0x8a14 >> 2),
508         0x00000000,
509         (0x0e00 << 16) | (0x8a18 >> 2),
510         0x00000000,
511         (0x0600 << 16) | (0x30a00 >> 2),
512         0x00000000,
513         (0x0e00 << 16) | (0x8bf0 >> 2),
514         0x00000000,
515         (0x0e00 << 16) | (0x8bcc >> 2),
516         0x00000000,
517         (0x0e00 << 16) | (0x8b24 >> 2),
518         0x00000000,
519         (0x0e00 << 16) | (0x30a04 >> 2),
520         0x00000000,
521         (0x0600 << 16) | (0x30a10 >> 2),
522         0x00000000,
523         (0x0600 << 16) | (0x30a14 >> 2),
524         0x00000000,
525         (0x0600 << 16) | (0x30a18 >> 2),
526         0x00000000,
527         (0x0600 << 16) | (0x30a2c >> 2),
528         0x00000000,
529         (0x0e00 << 16) | (0xc700 >> 2),
530         0x00000000,
531         (0x0e00 << 16) | (0xc704 >> 2),
532         0x00000000,
533         (0x0e00 << 16) | (0xc708 >> 2),
534         0x00000000,
535         (0x0e00 << 16) | (0xc768 >> 2),
536         0x00000000,
537         (0x0400 << 16) | (0xc770 >> 2),
538         0x00000000,
539         (0x0400 << 16) | (0xc774 >> 2),
540         0x00000000,
541         (0x0400 << 16) | (0xc778 >> 2),
542         0x00000000,
543         (0x0400 << 16) | (0xc77c >> 2),
544         0x00000000,
545         (0x0400 << 16) | (0xc780 >> 2),
546         0x00000000,
547         (0x0400 << 16) | (0xc784 >> 2),
548         0x00000000,
549         (0x0400 << 16) | (0xc788 >> 2),
550         0x00000000,
551         (0x0400 << 16) | (0xc78c >> 2),
552         0x00000000,
553         (0x0400 << 16) | (0xc798 >> 2),
554         0x00000000,
555         (0x0400 << 16) | (0xc79c >> 2),
556         0x00000000,
557         (0x0400 << 16) | (0xc7a0 >> 2),
558         0x00000000,
559         (0x0400 << 16) | (0xc7a4 >> 2),
560         0x00000000,
561         (0x0400 << 16) | (0xc7a8 >> 2),
562         0x00000000,
563         (0x0400 << 16) | (0xc7ac >> 2),
564         0x00000000,
565         (0x0400 << 16) | (0xc7b0 >> 2),
566         0x00000000,
567         (0x0400 << 16) | (0xc7b4 >> 2),
568         0x00000000,
569         (0x0e00 << 16) | (0x9100 >> 2),
570         0x00000000,
571         (0x0e00 << 16) | (0x3c010 >> 2),
572         0x00000000,
573         (0x0e00 << 16) | (0x92a8 >> 2),
574         0x00000000,
575         (0x0e00 << 16) | (0x92ac >> 2),
576         0x00000000,
577         (0x0e00 << 16) | (0x92b4 >> 2),
578         0x00000000,
579         (0x0e00 << 16) | (0x92b8 >> 2),
580         0x00000000,
581         (0x0e00 << 16) | (0x92bc >> 2),
582         0x00000000,
583         (0x0e00 << 16) | (0x92c0 >> 2),
584         0x00000000,
585         (0x0e00 << 16) | (0x92c4 >> 2),
586         0x00000000,
587         (0x0e00 << 16) | (0x92c8 >> 2),
588         0x00000000,
589         (0x0e00 << 16) | (0x92cc >> 2),
590         0x00000000,
591         (0x0e00 << 16) | (0x92d0 >> 2),
592         0x00000000,
593         (0x0e00 << 16) | (0x8c00 >> 2),
594         0x00000000,
595         (0x0e00 << 16) | (0x8c04 >> 2),
596         0x00000000,
597         (0x0e00 << 16) | (0x8c20 >> 2),
598         0x00000000,
599         (0x0e00 << 16) | (0x8c38 >> 2),
600         0x00000000,
601         (0x0e00 << 16) | (0x8c3c >> 2),
602         0x00000000,
603         (0x0e00 << 16) | (0xae00 >> 2),
604         0x00000000,
605         (0x0e00 << 16) | (0x9604 >> 2),
606         0x00000000,
607         (0x0e00 << 16) | (0xac08 >> 2),
608         0x00000000,
609         (0x0e00 << 16) | (0xac0c >> 2),
610         0x00000000,
611         (0x0e00 << 16) | (0xac10 >> 2),
612         0x00000000,
613         (0x0e00 << 16) | (0xac14 >> 2),
614         0x00000000,
615         (0x0e00 << 16) | (0xac58 >> 2),
616         0x00000000,
617         (0x0e00 << 16) | (0xac68 >> 2),
618         0x00000000,
619         (0x0e00 << 16) | (0xac6c >> 2),
620         0x00000000,
621         (0x0e00 << 16) | (0xac70 >> 2),
622         0x00000000,
623         (0x0e00 << 16) | (0xac74 >> 2),
624         0x00000000,
625         (0x0e00 << 16) | (0xac78 >> 2),
626         0x00000000,
627         (0x0e00 << 16) | (0xac7c >> 2),
628         0x00000000,
629         (0x0e00 << 16) | (0xac80 >> 2),
630         0x00000000,
631         (0x0e00 << 16) | (0xac84 >> 2),
632         0x00000000,
633         (0x0e00 << 16) | (0xac88 >> 2),
634         0x00000000,
635         (0x0e00 << 16) | (0xac8c >> 2),
636         0x00000000,
637         (0x0e00 << 16) | (0x970c >> 2),
638         0x00000000,
639         (0x0e00 << 16) | (0x9714 >> 2),
640         0x00000000,
641         (0x0e00 << 16) | (0x9718 >> 2),
642         0x00000000,
643         (0x0e00 << 16) | (0x971c >> 2),
644         0x00000000,
645         (0x0e00 << 16) | (0x31068 >> 2),
646         0x00000000,
647         (0x4e00 << 16) | (0x31068 >> 2),
648         0x00000000,
649         (0x5e00 << 16) | (0x31068 >> 2),
650         0x00000000,
651         (0x6e00 << 16) | (0x31068 >> 2),
652         0x00000000,
653         (0x7e00 << 16) | (0x31068 >> 2),
654         0x00000000,
655         (0x8e00 << 16) | (0x31068 >> 2),
656         0x00000000,
657         (0x9e00 << 16) | (0x31068 >> 2),
658         0x00000000,
659         (0xae00 << 16) | (0x31068 >> 2),
660         0x00000000,
661         (0xbe00 << 16) | (0x31068 >> 2),
662         0x00000000,
663         (0x0e00 << 16) | (0xcd10 >> 2),
664         0x00000000,
665         (0x0e00 << 16) | (0xcd14 >> 2),
666         0x00000000,
667         (0x0e00 << 16) | (0x88b0 >> 2),
668         0x00000000,
669         (0x0e00 << 16) | (0x88b4 >> 2),
670         0x00000000,
671         (0x0e00 << 16) | (0x88b8 >> 2),
672         0x00000000,
673         (0x0e00 << 16) | (0x88bc >> 2),
674         0x00000000,
675         (0x0400 << 16) | (0x89c0 >> 2),
676         0x00000000,
677         (0x0e00 << 16) | (0x88c4 >> 2),
678         0x00000000,
679         (0x0e00 << 16) | (0x88c8 >> 2),
680         0x00000000,
681         (0x0e00 << 16) | (0x88d0 >> 2),
682         0x00000000,
683         (0x0e00 << 16) | (0x88d4 >> 2),
684         0x00000000,
685         (0x0e00 << 16) | (0x88d8 >> 2),
686         0x00000000,
687         (0x0e00 << 16) | (0x8980 >> 2),
688         0x00000000,
689         (0x0e00 << 16) | (0x30938 >> 2),
690         0x00000000,
691         (0x0e00 << 16) | (0x3093c >> 2),
692         0x00000000,
693         (0x0e00 << 16) | (0x30940 >> 2),
694         0x00000000,
695         (0x0e00 << 16) | (0x89a0 >> 2),
696         0x00000000,
697         (0x0e00 << 16) | (0x30900 >> 2),
698         0x00000000,
699         (0x0e00 << 16) | (0x30904 >> 2),
700         0x00000000,
701         (0x0e00 << 16) | (0x89b4 >> 2),
702         0x00000000,
703         (0x0e00 << 16) | (0x3c210 >> 2),
704         0x00000000,
705         (0x0e00 << 16) | (0x3c214 >> 2),
706         0x00000000,
707         (0x0e00 << 16) | (0x3c218 >> 2),
708         0x00000000,
709         (0x0e00 << 16) | (0x8904 >> 2),
710         0x00000000,
711         0x5,
712         (0x0e00 << 16) | (0x8c28 >> 2),
713         (0x0e00 << 16) | (0x8c2c >> 2),
714         (0x0e00 << 16) | (0x8c30 >> 2),
715         (0x0e00 << 16) | (0x8c34 >> 2),
716         (0x0e00 << 16) | (0x9600 >> 2),
717 };
718
719 static const u32 kalindi_rlc_save_restore_register_list[] =
720 {
721         (0x0e00 << 16) | (0xc12c >> 2),
722         0x00000000,
723         (0x0e00 << 16) | (0xc140 >> 2),
724         0x00000000,
725         (0x0e00 << 16) | (0xc150 >> 2),
726         0x00000000,
727         (0x0e00 << 16) | (0xc15c >> 2),
728         0x00000000,
729         (0x0e00 << 16) | (0xc168 >> 2),
730         0x00000000,
731         (0x0e00 << 16) | (0xc170 >> 2),
732         0x00000000,
733         (0x0e00 << 16) | (0xc204 >> 2),
734         0x00000000,
735         (0x0e00 << 16) | (0xc2b4 >> 2),
736         0x00000000,
737         (0x0e00 << 16) | (0xc2b8 >> 2),
738         0x00000000,
739         (0x0e00 << 16) | (0xc2bc >> 2),
740         0x00000000,
741         (0x0e00 << 16) | (0xc2c0 >> 2),
742         0x00000000,
743         (0x0e00 << 16) | (0x8228 >> 2),
744         0x00000000,
745         (0x0e00 << 16) | (0x829c >> 2),
746         0x00000000,
747         (0x0e00 << 16) | (0x869c >> 2),
748         0x00000000,
749         (0x0600 << 16) | (0x98f4 >> 2),
750         0x00000000,
751         (0x0e00 << 16) | (0x98f8 >> 2),
752         0x00000000,
753         (0x0e00 << 16) | (0x9900 >> 2),
754         0x00000000,
755         (0x0e00 << 16) | (0xc260 >> 2),
756         0x00000000,
757         (0x0e00 << 16) | (0x90e8 >> 2),
758         0x00000000,
759         (0x0e00 << 16) | (0x3c000 >> 2),
760         0x00000000,
761         (0x0e00 << 16) | (0x3c00c >> 2),
762         0x00000000,
763         (0x0e00 << 16) | (0x8c1c >> 2),
764         0x00000000,
765         (0x0e00 << 16) | (0x9700 >> 2),
766         0x00000000,
767         (0x0e00 << 16) | (0xcd20 >> 2),
768         0x00000000,
769         (0x4e00 << 16) | (0xcd20 >> 2),
770         0x00000000,
771         (0x5e00 << 16) | (0xcd20 >> 2),
772         0x00000000,
773         (0x6e00 << 16) | (0xcd20 >> 2),
774         0x00000000,
775         (0x7e00 << 16) | (0xcd20 >> 2),
776         0x00000000,
777         (0x0e00 << 16) | (0x89bc >> 2),
778         0x00000000,
779         (0x0e00 << 16) | (0x8900 >> 2),
780         0x00000000,
781         0x3,
782         (0x0e00 << 16) | (0xc130 >> 2),
783         0x00000000,
784         (0x0e00 << 16) | (0xc134 >> 2),
785         0x00000000,
786         (0x0e00 << 16) | (0xc1fc >> 2),
787         0x00000000,
788         (0x0e00 << 16) | (0xc208 >> 2),
789         0x00000000,
790         (0x0e00 << 16) | (0xc264 >> 2),
791         0x00000000,
792         (0x0e00 << 16) | (0xc268 >> 2),
793         0x00000000,
794         (0x0e00 << 16) | (0xc26c >> 2),
795         0x00000000,
796         (0x0e00 << 16) | (0xc270 >> 2),
797         0x00000000,
798         (0x0e00 << 16) | (0xc274 >> 2),
799         0x00000000,
800         (0x0e00 << 16) | (0xc28c >> 2),
801         0x00000000,
802         (0x0e00 << 16) | (0xc290 >> 2),
803         0x00000000,
804         (0x0e00 << 16) | (0xc294 >> 2),
805         0x00000000,
806         (0x0e00 << 16) | (0xc298 >> 2),
807         0x00000000,
808         (0x0e00 << 16) | (0xc2a0 >> 2),
809         0x00000000,
810         (0x0e00 << 16) | (0xc2a4 >> 2),
811         0x00000000,
812         (0x0e00 << 16) | (0xc2a8 >> 2),
813         0x00000000,
814         (0x0e00 << 16) | (0xc2ac >> 2),
815         0x00000000,
816         (0x0e00 << 16) | (0x301d0 >> 2),
817         0x00000000,
818         (0x0e00 << 16) | (0x30238 >> 2),
819         0x00000000,
820         (0x0e00 << 16) | (0x30250 >> 2),
821         0x00000000,
822         (0x0e00 << 16) | (0x30254 >> 2),
823         0x00000000,
824         (0x0e00 << 16) | (0x30258 >> 2),
825         0x00000000,
826         (0x0e00 << 16) | (0x3025c >> 2),
827         0x00000000,
828         (0x4e00 << 16) | (0xc900 >> 2),
829         0x00000000,
830         (0x5e00 << 16) | (0xc900 >> 2),
831         0x00000000,
832         (0x6e00 << 16) | (0xc900 >> 2),
833         0x00000000,
834         (0x7e00 << 16) | (0xc900 >> 2),
835         0x00000000,
836         (0x4e00 << 16) | (0xc904 >> 2),
837         0x00000000,
838         (0x5e00 << 16) | (0xc904 >> 2),
839         0x00000000,
840         (0x6e00 << 16) | (0xc904 >> 2),
841         0x00000000,
842         (0x7e00 << 16) | (0xc904 >> 2),
843         0x00000000,
844         (0x4e00 << 16) | (0xc908 >> 2),
845         0x00000000,
846         (0x5e00 << 16) | (0xc908 >> 2),
847         0x00000000,
848         (0x6e00 << 16) | (0xc908 >> 2),
849         0x00000000,
850         (0x7e00 << 16) | (0xc908 >> 2),
851         0x00000000,
852         (0x4e00 << 16) | (0xc90c >> 2),
853         0x00000000,
854         (0x5e00 << 16) | (0xc90c >> 2),
855         0x00000000,
856         (0x6e00 << 16) | (0xc90c >> 2),
857         0x00000000,
858         (0x7e00 << 16) | (0xc90c >> 2),
859         0x00000000,
860         (0x4e00 << 16) | (0xc910 >> 2),
861         0x00000000,
862         (0x5e00 << 16) | (0xc910 >> 2),
863         0x00000000,
864         (0x6e00 << 16) | (0xc910 >> 2),
865         0x00000000,
866         (0x7e00 << 16) | (0xc910 >> 2),
867         0x00000000,
868         (0x0e00 << 16) | (0xc99c >> 2),
869         0x00000000,
870         (0x0e00 << 16) | (0x9834 >> 2),
871         0x00000000,
872         (0x0000 << 16) | (0x30f00 >> 2),
873         0x00000000,
874         (0x0000 << 16) | (0x30f04 >> 2),
875         0x00000000,
876         (0x0000 << 16) | (0x30f08 >> 2),
877         0x00000000,
878         (0x0000 << 16) | (0x30f0c >> 2),
879         0x00000000,
880         (0x0600 << 16) | (0x9b7c >> 2),
881         0x00000000,
882         (0x0e00 << 16) | (0x8a14 >> 2),
883         0x00000000,
884         (0x0e00 << 16) | (0x8a18 >> 2),
885         0x00000000,
886         (0x0600 << 16) | (0x30a00 >> 2),
887         0x00000000,
888         (0x0e00 << 16) | (0x8bf0 >> 2),
889         0x00000000,
890         (0x0e00 << 16) | (0x8bcc >> 2),
891         0x00000000,
892         (0x0e00 << 16) | (0x8b24 >> 2),
893         0x00000000,
894         (0x0e00 << 16) | (0x30a04 >> 2),
895         0x00000000,
896         (0x0600 << 16) | (0x30a10 >> 2),
897         0x00000000,
898         (0x0600 << 16) | (0x30a14 >> 2),
899         0x00000000,
900         (0x0600 << 16) | (0x30a18 >> 2),
901         0x00000000,
902         (0x0600 << 16) | (0x30a2c >> 2),
903         0x00000000,
904         (0x0e00 << 16) | (0xc700 >> 2),
905         0x00000000,
906         (0x0e00 << 16) | (0xc704 >> 2),
907         0x00000000,
908         (0x0e00 << 16) | (0xc708 >> 2),
909         0x00000000,
910         (0x0e00 << 16) | (0xc768 >> 2),
911         0x00000000,
912         (0x0400 << 16) | (0xc770 >> 2),
913         0x00000000,
914         (0x0400 << 16) | (0xc774 >> 2),
915         0x00000000,
916         (0x0400 << 16) | (0xc798 >> 2),
917         0x00000000,
918         (0x0400 << 16) | (0xc79c >> 2),
919         0x00000000,
920         (0x0e00 << 16) | (0x9100 >> 2),
921         0x00000000,
922         (0x0e00 << 16) | (0x3c010 >> 2),
923         0x00000000,
924         (0x0e00 << 16) | (0x8c00 >> 2),
925         0x00000000,
926         (0x0e00 << 16) | (0x8c04 >> 2),
927         0x00000000,
928         (0x0e00 << 16) | (0x8c20 >> 2),
929         0x00000000,
930         (0x0e00 << 16) | (0x8c38 >> 2),
931         0x00000000,
932         (0x0e00 << 16) | (0x8c3c >> 2),
933         0x00000000,
934         (0x0e00 << 16) | (0xae00 >> 2),
935         0x00000000,
936         (0x0e00 << 16) | (0x9604 >> 2),
937         0x00000000,
938         (0x0e00 << 16) | (0xac08 >> 2),
939         0x00000000,
940         (0x0e00 << 16) | (0xac0c >> 2),
941         0x00000000,
942         (0x0e00 << 16) | (0xac10 >> 2),
943         0x00000000,
944         (0x0e00 << 16) | (0xac14 >> 2),
945         0x00000000,
946         (0x0e00 << 16) | (0xac58 >> 2),
947         0x00000000,
948         (0x0e00 << 16) | (0xac68 >> 2),
949         0x00000000,
950         (0x0e00 << 16) | (0xac6c >> 2),
951         0x00000000,
952         (0x0e00 << 16) | (0xac70 >> 2),
953         0x00000000,
954         (0x0e00 << 16) | (0xac74 >> 2),
955         0x00000000,
956         (0x0e00 << 16) | (0xac78 >> 2),
957         0x00000000,
958         (0x0e00 << 16) | (0xac7c >> 2),
959         0x00000000,
960         (0x0e00 << 16) | (0xac80 >> 2),
961         0x00000000,
962         (0x0e00 << 16) | (0xac84 >> 2),
963         0x00000000,
964         (0x0e00 << 16) | (0xac88 >> 2),
965         0x00000000,
966         (0x0e00 << 16) | (0xac8c >> 2),
967         0x00000000,
968         (0x0e00 << 16) | (0x970c >> 2),
969         0x00000000,
970         (0x0e00 << 16) | (0x9714 >> 2),
971         0x00000000,
972         (0x0e00 << 16) | (0x9718 >> 2),
973         0x00000000,
974         (0x0e00 << 16) | (0x971c >> 2),
975         0x00000000,
976         (0x0e00 << 16) | (0x31068 >> 2),
977         0x00000000,
978         (0x4e00 << 16) | (0x31068 >> 2),
979         0x00000000,
980         (0x5e00 << 16) | (0x31068 >> 2),
981         0x00000000,
982         (0x6e00 << 16) | (0x31068 >> 2),
983         0x00000000,
984         (0x7e00 << 16) | (0x31068 >> 2),
985         0x00000000,
986         (0x0e00 << 16) | (0xcd10 >> 2),
987         0x00000000,
988         (0x0e00 << 16) | (0xcd14 >> 2),
989         0x00000000,
990         (0x0e00 << 16) | (0x88b0 >> 2),
991         0x00000000,
992         (0x0e00 << 16) | (0x88b4 >> 2),
993         0x00000000,
994         (0x0e00 << 16) | (0x88b8 >> 2),
995         0x00000000,
996         (0x0e00 << 16) | (0x88bc >> 2),
997         0x00000000,
998         (0x0400 << 16) | (0x89c0 >> 2),
999         0x00000000,
1000         (0x0e00 << 16) | (0x88c4 >> 2),
1001         0x00000000,
1002         (0x0e00 << 16) | (0x88c8 >> 2),
1003         0x00000000,
1004         (0x0e00 << 16) | (0x88d0 >> 2),
1005         0x00000000,
1006         (0x0e00 << 16) | (0x88d4 >> 2),
1007         0x00000000,
1008         (0x0e00 << 16) | (0x88d8 >> 2),
1009         0x00000000,
1010         (0x0e00 << 16) | (0x8980 >> 2),
1011         0x00000000,
1012         (0x0e00 << 16) | (0x30938 >> 2),
1013         0x00000000,
1014         (0x0e00 << 16) | (0x3093c >> 2),
1015         0x00000000,
1016         (0x0e00 << 16) | (0x30940 >> 2),
1017         0x00000000,
1018         (0x0e00 << 16) | (0x89a0 >> 2),
1019         0x00000000,
1020         (0x0e00 << 16) | (0x30900 >> 2),
1021         0x00000000,
1022         (0x0e00 << 16) | (0x30904 >> 2),
1023         0x00000000,
1024         (0x0e00 << 16) | (0x89b4 >> 2),
1025         0x00000000,
1026         (0x0e00 << 16) | (0x3e1fc >> 2),
1027         0x00000000,
1028         (0x0e00 << 16) | (0x3c210 >> 2),
1029         0x00000000,
1030         (0x0e00 << 16) | (0x3c214 >> 2),
1031         0x00000000,
1032         (0x0e00 << 16) | (0x3c218 >> 2),
1033         0x00000000,
1034         (0x0e00 << 16) | (0x8904 >> 2),
1035         0x00000000,
1036         0x5,
1037         (0x0e00 << 16) | (0x8c28 >> 2),
1038         (0x0e00 << 16) | (0x8c2c >> 2),
1039         (0x0e00 << 16) | (0x8c30 >> 2),
1040         (0x0e00 << 16) | (0x8c34 >> 2),
1041         (0x0e00 << 16) | (0x9600 >> 2),
1042 };
1043
1044 static const u32 bonaire_golden_spm_registers[] =
1045 {
1046         0x30800, 0xe0ffffff, 0xe0000000
1047 };
1048
1049 static const u32 bonaire_golden_common_registers[] =
1050 {
1051         0xc770, 0xffffffff, 0x00000800,
1052         0xc774, 0xffffffff, 0x00000800,
1053         0xc798, 0xffffffff, 0x00007fbf,
1054         0xc79c, 0xffffffff, 0x00007faf
1055 };
1056
1057 static const u32 bonaire_golden_registers[] =
1058 {
1059         0x3354, 0x00000333, 0x00000333,
1060         0x3350, 0x000c0fc0, 0x00040200,
1061         0x9a10, 0x00010000, 0x00058208,
1062         0x3c000, 0xffff1fff, 0x00140000,
1063         0x3c200, 0xfdfc0fff, 0x00000100,
1064         0x3c234, 0x40000000, 0x40000200,
1065         0x9830, 0xffffffff, 0x00000000,
1066         0x9834, 0xf00fffff, 0x00000400,
1067         0x9838, 0x0002021c, 0x00020200,
1068         0xc78, 0x00000080, 0x00000000,
1069         0x5bb0, 0x000000f0, 0x00000070,
1070         0x5bc0, 0xf0311fff, 0x80300000,
1071         0x98f8, 0x73773777, 0x12010001,
1072         0x350c, 0x00810000, 0x408af000,
1073         0x7030, 0x31000111, 0x00000011,
1074         0x2f48, 0x73773777, 0x12010001,
1075         0x220c, 0x00007fb6, 0x0021a1b1,
1076         0x2210, 0x00007fb6, 0x002021b1,
1077         0x2180, 0x00007fb6, 0x00002191,
1078         0x2218, 0x00007fb6, 0x002121b1,
1079         0x221c, 0x00007fb6, 0x002021b1,
1080         0x21dc, 0x00007fb6, 0x00002191,
1081         0x21e0, 0x00007fb6, 0x00002191,
1082         0x3628, 0x0000003f, 0x0000000a,
1083         0x362c, 0x0000003f, 0x0000000a,
1084         0x2ae4, 0x00073ffe, 0x000022a2,
1085         0x240c, 0x000007ff, 0x00000000,
1086         0x8a14, 0xf000003f, 0x00000007,
1087         0x8bf0, 0x00002001, 0x00000001,
1088         0x8b24, 0xffffffff, 0x00ffffff,
1089         0x30a04, 0x0000ff0f, 0x00000000,
1090         0x28a4c, 0x07ffffff, 0x06000000,
1091         0x4d8, 0x00000fff, 0x00000100,
1092         0x3e78, 0x00000001, 0x00000002,
1093         0x9100, 0x03000000, 0x0362c688,
1094         0x8c00, 0x000000ff, 0x00000001,
1095         0xe40, 0x00001fff, 0x00001fff,
1096         0x9060, 0x0000007f, 0x00000020,
1097         0x9508, 0x00010000, 0x00010000,
1098         0xac14, 0x000003ff, 0x000000f3,
1099         0xac0c, 0xffffffff, 0x00001032
1100 };
1101
1102 static const u32 bonaire_mgcg_cgcg_init[] =
1103 {
1104         0xc420, 0xffffffff, 0xfffffffc,
1105         0x30800, 0xffffffff, 0xe0000000,
1106         0x3c2a0, 0xffffffff, 0x00000100,
1107         0x3c208, 0xffffffff, 0x00000100,
1108         0x3c2c0, 0xffffffff, 0xc0000100,
1109         0x3c2c8, 0xffffffff, 0xc0000100,
1110         0x3c2c4, 0xffffffff, 0xc0000100,
1111         0x55e4, 0xffffffff, 0x00600100,
1112         0x3c280, 0xffffffff, 0x00000100,
1113         0x3c214, 0xffffffff, 0x06000100,
1114         0x3c220, 0xffffffff, 0x00000100,
1115         0x3c218, 0xffffffff, 0x06000100,
1116         0x3c204, 0xffffffff, 0x00000100,
1117         0x3c2e0, 0xffffffff, 0x00000100,
1118         0x3c224, 0xffffffff, 0x00000100,
1119         0x3c200, 0xffffffff, 0x00000100,
1120         0x3c230, 0xffffffff, 0x00000100,
1121         0x3c234, 0xffffffff, 0x00000100,
1122         0x3c250, 0xffffffff, 0x00000100,
1123         0x3c254, 0xffffffff, 0x00000100,
1124         0x3c258, 0xffffffff, 0x00000100,
1125         0x3c25c, 0xffffffff, 0x00000100,
1126         0x3c260, 0xffffffff, 0x00000100,
1127         0x3c27c, 0xffffffff, 0x00000100,
1128         0x3c278, 0xffffffff, 0x00000100,
1129         0x3c210, 0xffffffff, 0x06000100,
1130         0x3c290, 0xffffffff, 0x00000100,
1131         0x3c274, 0xffffffff, 0x00000100,
1132         0x3c2b4, 0xffffffff, 0x00000100,
1133         0x3c2b0, 0xffffffff, 0x00000100,
1134         0x3c270, 0xffffffff, 0x00000100,
1135         0x30800, 0xffffffff, 0xe0000000,
1136         0x3c020, 0xffffffff, 0x00010000,
1137         0x3c024, 0xffffffff, 0x00030002,
1138         0x3c028, 0xffffffff, 0x00040007,
1139         0x3c02c, 0xffffffff, 0x00060005,
1140         0x3c030, 0xffffffff, 0x00090008,
1141         0x3c034, 0xffffffff, 0x00010000,
1142         0x3c038, 0xffffffff, 0x00030002,
1143         0x3c03c, 0xffffffff, 0x00040007,
1144         0x3c040, 0xffffffff, 0x00060005,
1145         0x3c044, 0xffffffff, 0x00090008,
1146         0x3c048, 0xffffffff, 0x00010000,
1147         0x3c04c, 0xffffffff, 0x00030002,
1148         0x3c050, 0xffffffff, 0x00040007,
1149         0x3c054, 0xffffffff, 0x00060005,
1150         0x3c058, 0xffffffff, 0x00090008,
1151         0x3c05c, 0xffffffff, 0x00010000,
1152         0x3c060, 0xffffffff, 0x00030002,
1153         0x3c064, 0xffffffff, 0x00040007,
1154         0x3c068, 0xffffffff, 0x00060005,
1155         0x3c06c, 0xffffffff, 0x00090008,
1156         0x3c070, 0xffffffff, 0x00010000,
1157         0x3c074, 0xffffffff, 0x00030002,
1158         0x3c078, 0xffffffff, 0x00040007,
1159         0x3c07c, 0xffffffff, 0x00060005,
1160         0x3c080, 0xffffffff, 0x00090008,
1161         0x3c084, 0xffffffff, 0x00010000,
1162         0x3c088, 0xffffffff, 0x00030002,
1163         0x3c08c, 0xffffffff, 0x00040007,
1164         0x3c090, 0xffffffff, 0x00060005,
1165         0x3c094, 0xffffffff, 0x00090008,
1166         0x3c098, 0xffffffff, 0x00010000,
1167         0x3c09c, 0xffffffff, 0x00030002,
1168         0x3c0a0, 0xffffffff, 0x00040007,
1169         0x3c0a4, 0xffffffff, 0x00060005,
1170         0x3c0a8, 0xffffffff, 0x00090008,
1171         0x3c000, 0xffffffff, 0x96e00200,
1172         0x8708, 0xffffffff, 0x00900100,
1173         0xc424, 0xffffffff, 0x0020003f,
1174         0x38, 0xffffffff, 0x0140001c,
1175         0x3c, 0x000f0000, 0x000f0000,
1176         0x220, 0xffffffff, 0xC060000C,
1177         0x224, 0xc0000fff, 0x00000100,
1178         0xf90, 0xffffffff, 0x00000100,
1179         0xf98, 0x00000101, 0x00000000,
1180         0x20a8, 0xffffffff, 0x00000104,
1181         0x55e4, 0xff000fff, 0x00000100,
1182         0x30cc, 0xc0000fff, 0x00000104,
1183         0xc1e4, 0x00000001, 0x00000001,
1184         0xd00c, 0xff000ff0, 0x00000100,
1185         0xd80c, 0xff000ff0, 0x00000100
1186 };
1187
1188 static const u32 spectre_golden_spm_registers[] =
1189 {
1190         0x30800, 0xe0ffffff, 0xe0000000
1191 };
1192
1193 static const u32 spectre_golden_common_registers[] =
1194 {
1195         0xc770, 0xffffffff, 0x00000800,
1196         0xc774, 0xffffffff, 0x00000800,
1197         0xc798, 0xffffffff, 0x00007fbf,
1198         0xc79c, 0xffffffff, 0x00007faf
1199 };
1200
1201 static const u32 spectre_golden_registers[] =
1202 {
1203         0x3c000, 0xffff1fff, 0x96940200,
1204         0x3c00c, 0xffff0001, 0xff000000,
1205         0x3c200, 0xfffc0fff, 0x00000100,
1206         0x6ed8, 0x00010101, 0x00010000,
1207         0x9834, 0xf00fffff, 0x00000400,
1208         0x9838, 0xfffffffc, 0x00020200,
1209         0x5bb0, 0x000000f0, 0x00000070,
1210         0x5bc0, 0xf0311fff, 0x80300000,
1211         0x98f8, 0x73773777, 0x12010001,
1212         0x9b7c, 0x00ff0000, 0x00fc0000,
1213         0x2f48, 0x73773777, 0x12010001,
1214         0x8a14, 0xf000003f, 0x00000007,
1215         0x8b24, 0xffffffff, 0x00ffffff,
1216         0x28350, 0x3f3f3fff, 0x00000082,
1217         0x28354, 0x0000003f, 0x00000000,
1218         0x3e78, 0x00000001, 0x00000002,
1219         0x913c, 0xffff03df, 0x00000004,
1220         0xc768, 0x00000008, 0x00000008,
1221         0x8c00, 0x000008ff, 0x00000800,
1222         0x9508, 0x00010000, 0x00010000,
1223         0xac0c, 0xffffffff, 0x54763210,
1224         0x214f8, 0x01ff01ff, 0x00000002,
1225         0x21498, 0x007ff800, 0x00200000,
1226         0x2015c, 0xffffffff, 0x00000f40,
1227         0x30934, 0xffffffff, 0x00000001
1228 };
1229
1230 static const u32 spectre_mgcg_cgcg_init[] =
1231 {
1232         0xc420, 0xffffffff, 0xfffffffc,
1233         0x30800, 0xffffffff, 0xe0000000,
1234         0x3c2a0, 0xffffffff, 0x00000100,
1235         0x3c208, 0xffffffff, 0x00000100,
1236         0x3c2c0, 0xffffffff, 0x00000100,
1237         0x3c2c8, 0xffffffff, 0x00000100,
1238         0x3c2c4, 0xffffffff, 0x00000100,
1239         0x55e4, 0xffffffff, 0x00600100,
1240         0x3c280, 0xffffffff, 0x00000100,
1241         0x3c214, 0xffffffff, 0x06000100,
1242         0x3c220, 0xffffffff, 0x00000100,
1243         0x3c218, 0xffffffff, 0x06000100,
1244         0x3c204, 0xffffffff, 0x00000100,
1245         0x3c2e0, 0xffffffff, 0x00000100,
1246         0x3c224, 0xffffffff, 0x00000100,
1247         0x3c200, 0xffffffff, 0x00000100,
1248         0x3c230, 0xffffffff, 0x00000100,
1249         0x3c234, 0xffffffff, 0x00000100,
1250         0x3c250, 0xffffffff, 0x00000100,
1251         0x3c254, 0xffffffff, 0x00000100,
1252         0x3c258, 0xffffffff, 0x00000100,
1253         0x3c25c, 0xffffffff, 0x00000100,
1254         0x3c260, 0xffffffff, 0x00000100,
1255         0x3c27c, 0xffffffff, 0x00000100,
1256         0x3c278, 0xffffffff, 0x00000100,
1257         0x3c210, 0xffffffff, 0x06000100,
1258         0x3c290, 0xffffffff, 0x00000100,
1259         0x3c274, 0xffffffff, 0x00000100,
1260         0x3c2b4, 0xffffffff, 0x00000100,
1261         0x3c2b0, 0xffffffff, 0x00000100,
1262         0x3c270, 0xffffffff, 0x00000100,
1263         0x30800, 0xffffffff, 0xe0000000,
1264         0x3c020, 0xffffffff, 0x00010000,
1265         0x3c024, 0xffffffff, 0x00030002,
1266         0x3c028, 0xffffffff, 0x00040007,
1267         0x3c02c, 0xffffffff, 0x00060005,
1268         0x3c030, 0xffffffff, 0x00090008,
1269         0x3c034, 0xffffffff, 0x00010000,
1270         0x3c038, 0xffffffff, 0x00030002,
1271         0x3c03c, 0xffffffff, 0x00040007,
1272         0x3c040, 0xffffffff, 0x00060005,
1273         0x3c044, 0xffffffff, 0x00090008,
1274         0x3c048, 0xffffffff, 0x00010000,
1275         0x3c04c, 0xffffffff, 0x00030002,
1276         0x3c050, 0xffffffff, 0x00040007,
1277         0x3c054, 0xffffffff, 0x00060005,
1278         0x3c058, 0xffffffff, 0x00090008,
1279         0x3c05c, 0xffffffff, 0x00010000,
1280         0x3c060, 0xffffffff, 0x00030002,
1281         0x3c064, 0xffffffff, 0x00040007,
1282         0x3c068, 0xffffffff, 0x00060005,
1283         0x3c06c, 0xffffffff, 0x00090008,
1284         0x3c070, 0xffffffff, 0x00010000,
1285         0x3c074, 0xffffffff, 0x00030002,
1286         0x3c078, 0xffffffff, 0x00040007,
1287         0x3c07c, 0xffffffff, 0x00060005,
1288         0x3c080, 0xffffffff, 0x00090008,
1289         0x3c084, 0xffffffff, 0x00010000,
1290         0x3c088, 0xffffffff, 0x00030002,
1291         0x3c08c, 0xffffffff, 0x00040007,
1292         0x3c090, 0xffffffff, 0x00060005,
1293         0x3c094, 0xffffffff, 0x00090008,
1294         0x3c098, 0xffffffff, 0x00010000,
1295         0x3c09c, 0xffffffff, 0x00030002,
1296         0x3c0a0, 0xffffffff, 0x00040007,
1297         0x3c0a4, 0xffffffff, 0x00060005,
1298         0x3c0a8, 0xffffffff, 0x00090008,
1299         0x3c0ac, 0xffffffff, 0x00010000,
1300         0x3c0b0, 0xffffffff, 0x00030002,
1301         0x3c0b4, 0xffffffff, 0x00040007,
1302         0x3c0b8, 0xffffffff, 0x00060005,
1303         0x3c0bc, 0xffffffff, 0x00090008,
1304         0x3c000, 0xffffffff, 0x96e00200,
1305         0x8708, 0xffffffff, 0x00900100,
1306         0xc424, 0xffffffff, 0x0020003f,
1307         0x38, 0xffffffff, 0x0140001c,
1308         0x3c, 0x000f0000, 0x000f0000,
1309         0x220, 0xffffffff, 0xC060000C,
1310         0x224, 0xc0000fff, 0x00000100,
1311         0xf90, 0xffffffff, 0x00000100,
1312         0xf98, 0x00000101, 0x00000000,
1313         0x20a8, 0xffffffff, 0x00000104,
1314         0x55e4, 0xff000fff, 0x00000100,
1315         0x30cc, 0xc0000fff, 0x00000104,
1316         0xc1e4, 0x00000001, 0x00000001,
1317         0xd00c, 0xff000ff0, 0x00000100,
1318         0xd80c, 0xff000ff0, 0x00000100
1319 };
1320
1321 static const u32 kalindi_golden_spm_registers[] =
1322 {
1323         0x30800, 0xe0ffffff, 0xe0000000
1324 };
1325
1326 static const u32 kalindi_golden_common_registers[] =
1327 {
1328         0xc770, 0xffffffff, 0x00000800,
1329         0xc774, 0xffffffff, 0x00000800,
1330         0xc798, 0xffffffff, 0x00007fbf,
1331         0xc79c, 0xffffffff, 0x00007faf
1332 };
1333
1334 static const u32 kalindi_golden_registers[] =
1335 {
1336         0x3c000, 0xffffdfff, 0x6e944040,
1337         0x55e4, 0xff607fff, 0xfc000100,
1338         0x3c220, 0xff000fff, 0x00000100,
1339         0x3c224, 0xff000fff, 0x00000100,
1340         0x3c200, 0xfffc0fff, 0x00000100,
1341         0x6ed8, 0x00010101, 0x00010000,
1342         0x9830, 0xffffffff, 0x00000000,
1343         0x9834, 0xf00fffff, 0x00000400,
1344         0x5bb0, 0x000000f0, 0x00000070,
1345         0x5bc0, 0xf0311fff, 0x80300000,
1346         0x98f8, 0x73773777, 0x12010001,
1347         0x98fc, 0xffffffff, 0x00000010,
1348         0x9b7c, 0x00ff0000, 0x00fc0000,
1349         0x8030, 0x00001f0f, 0x0000100a,
1350         0x2f48, 0x73773777, 0x12010001,
1351         0x2408, 0x000fffff, 0x000c007f,
1352         0x8a14, 0xf000003f, 0x00000007,
1353         0x8b24, 0x3fff3fff, 0x00ffcfff,
1354         0x30a04, 0x0000ff0f, 0x00000000,
1355         0x28a4c, 0x07ffffff, 0x06000000,
1356         0x4d8, 0x00000fff, 0x00000100,
1357         0x3e78, 0x00000001, 0x00000002,
1358         0xc768, 0x00000008, 0x00000008,
1359         0x8c00, 0x000000ff, 0x00000003,
1360         0x214f8, 0x01ff01ff, 0x00000002,
1361         0x21498, 0x007ff800, 0x00200000,
1362         0x2015c, 0xffffffff, 0x00000f40,
1363         0x88c4, 0x001f3ae3, 0x00000082,
1364         0x88d4, 0x0000001f, 0x00000010,
1365         0x30934, 0xffffffff, 0x00000000
1366 };
1367
1368 static const u32 kalindi_mgcg_cgcg_init[] =
1369 {
1370         0xc420, 0xffffffff, 0xfffffffc,
1371         0x30800, 0xffffffff, 0xe0000000,
1372         0x3c2a0, 0xffffffff, 0x00000100,
1373         0x3c208, 0xffffffff, 0x00000100,
1374         0x3c2c0, 0xffffffff, 0x00000100,
1375         0x3c2c8, 0xffffffff, 0x00000100,
1376         0x3c2c4, 0xffffffff, 0x00000100,
1377         0x55e4, 0xffffffff, 0x00600100,
1378         0x3c280, 0xffffffff, 0x00000100,
1379         0x3c214, 0xffffffff, 0x06000100,
1380         0x3c220, 0xffffffff, 0x00000100,
1381         0x3c218, 0xffffffff, 0x06000100,
1382         0x3c204, 0xffffffff, 0x00000100,
1383         0x3c2e0, 0xffffffff, 0x00000100,
1384         0x3c224, 0xffffffff, 0x00000100,
1385         0x3c200, 0xffffffff, 0x00000100,
1386         0x3c230, 0xffffffff, 0x00000100,
1387         0x3c234, 0xffffffff, 0x00000100,
1388         0x3c250, 0xffffffff, 0x00000100,
1389         0x3c254, 0xffffffff, 0x00000100,
1390         0x3c258, 0xffffffff, 0x00000100,
1391         0x3c25c, 0xffffffff, 0x00000100,
1392         0x3c260, 0xffffffff, 0x00000100,
1393         0x3c27c, 0xffffffff, 0x00000100,
1394         0x3c278, 0xffffffff, 0x00000100,
1395         0x3c210, 0xffffffff, 0x06000100,
1396         0x3c290, 0xffffffff, 0x00000100,
1397         0x3c274, 0xffffffff, 0x00000100,
1398         0x3c2b4, 0xffffffff, 0x00000100,
1399         0x3c2b0, 0xffffffff, 0x00000100,
1400         0x3c270, 0xffffffff, 0x00000100,
1401         0x30800, 0xffffffff, 0xe0000000,
1402         0x3c020, 0xffffffff, 0x00010000,
1403         0x3c024, 0xffffffff, 0x00030002,
1404         0x3c028, 0xffffffff, 0x00040007,
1405         0x3c02c, 0xffffffff, 0x00060005,
1406         0x3c030, 0xffffffff, 0x00090008,
1407         0x3c034, 0xffffffff, 0x00010000,
1408         0x3c038, 0xffffffff, 0x00030002,
1409         0x3c03c, 0xffffffff, 0x00040007,
1410         0x3c040, 0xffffffff, 0x00060005,
1411         0x3c044, 0xffffffff, 0x00090008,
1412         0x3c000, 0xffffffff, 0x96e00200,
1413         0x8708, 0xffffffff, 0x00900100,
1414         0xc424, 0xffffffff, 0x0020003f,
1415         0x38, 0xffffffff, 0x0140001c,
1416         0x3c, 0x000f0000, 0x000f0000,
1417         0x220, 0xffffffff, 0xC060000C,
1418         0x224, 0xc0000fff, 0x00000100,
1419         0x20a8, 0xffffffff, 0x00000104,
1420         0x55e4, 0xff000fff, 0x00000100,
1421         0x30cc, 0xc0000fff, 0x00000104,
1422         0xc1e4, 0x00000001, 0x00000001,
1423         0xd00c, 0xff000ff0, 0x00000100,
1424         0xd80c, 0xff000ff0, 0x00000100
1425 };
1426
1427 static const u32 hawaii_golden_spm_registers[] =
1428 {
1429         0x30800, 0xe0ffffff, 0xe0000000
1430 };
1431
1432 static const u32 hawaii_golden_common_registers[] =
1433 {
1434         0x30800, 0xffffffff, 0xe0000000,
1435         0x28350, 0xffffffff, 0x3a00161a,
1436         0x28354, 0xffffffff, 0x0000002e,
1437         0x9a10, 0xffffffff, 0x00018208,
1438         0x98f8, 0xffffffff, 0x12011003
1439 };
1440
1441 static const u32 hawaii_golden_registers[] =
1442 {
1443         0x3354, 0x00000333, 0x00000333,
1444         0x9a10, 0x00010000, 0x00058208,
1445         0x9830, 0xffffffff, 0x00000000,
1446         0x9834, 0xf00fffff, 0x00000400,
1447         0x9838, 0x0002021c, 0x00020200,
1448         0xc78, 0x00000080, 0x00000000,
1449         0x5bb0, 0x000000f0, 0x00000070,
1450         0x5bc0, 0xf0311fff, 0x80300000,
1451         0x350c, 0x00810000, 0x408af000,
1452         0x7030, 0x31000111, 0x00000011,
1453         0x2f48, 0x73773777, 0x12010001,
1454         0x2120, 0x0000007f, 0x0000001b,
1455         0x21dc, 0x00007fb6, 0x00002191,
1456         0x3628, 0x0000003f, 0x0000000a,
1457         0x362c, 0x0000003f, 0x0000000a,
1458         0x2ae4, 0x00073ffe, 0x000022a2,
1459         0x240c, 0x000007ff, 0x00000000,
1460         0x8bf0, 0x00002001, 0x00000001,
1461         0x8b24, 0xffffffff, 0x00ffffff,
1462         0x30a04, 0x0000ff0f, 0x00000000,
1463         0x28a4c, 0x07ffffff, 0x06000000,
1464         0x3e78, 0x00000001, 0x00000002,
1465         0xc768, 0x00000008, 0x00000008,
1466         0xc770, 0x00000f00, 0x00000800,
1467         0xc774, 0x00000f00, 0x00000800,
1468         0xc798, 0x00ffffff, 0x00ff7fbf,
1469         0xc79c, 0x00ffffff, 0x00ff7faf,
1470         0x8c00, 0x000000ff, 0x00000800,
1471         0xe40, 0x00001fff, 0x00001fff,
1472         0x9060, 0x0000007f, 0x00000020,
1473         0x9508, 0x00010000, 0x00010000,
1474         0xae00, 0x00100000, 0x000ff07c,
1475         0xac14, 0x000003ff, 0x0000000f,
1476         0xac10, 0xffffffff, 0x7564fdec,
1477         0xac0c, 0xffffffff, 0x3120b9a8,
1478         0xac08, 0x20000000, 0x0f9c0000
1479 };
1480
1481 static const u32 hawaii_mgcg_cgcg_init[] =
1482 {
1483         0xc420, 0xffffffff, 0xfffffffd,
1484         0x30800, 0xffffffff, 0xe0000000,
1485         0x3c2a0, 0xffffffff, 0x00000100,
1486         0x3c208, 0xffffffff, 0x00000100,
1487         0x3c2c0, 0xffffffff, 0x00000100,
1488         0x3c2c8, 0xffffffff, 0x00000100,
1489         0x3c2c4, 0xffffffff, 0x00000100,
1490         0x55e4, 0xffffffff, 0x00200100,
1491         0x3c280, 0xffffffff, 0x00000100,
1492         0x3c214, 0xffffffff, 0x06000100,
1493         0x3c220, 0xffffffff, 0x00000100,
1494         0x3c218, 0xffffffff, 0x06000100,
1495         0x3c204, 0xffffffff, 0x00000100,
1496         0x3c2e0, 0xffffffff, 0x00000100,
1497         0x3c224, 0xffffffff, 0x00000100,
1498         0x3c200, 0xffffffff, 0x00000100,
1499         0x3c230, 0xffffffff, 0x00000100,
1500         0x3c234, 0xffffffff, 0x00000100,
1501         0x3c250, 0xffffffff, 0x00000100,
1502         0x3c254, 0xffffffff, 0x00000100,
1503         0x3c258, 0xffffffff, 0x00000100,
1504         0x3c25c, 0xffffffff, 0x00000100,
1505         0x3c260, 0xffffffff, 0x00000100,
1506         0x3c27c, 0xffffffff, 0x00000100,
1507         0x3c278, 0xffffffff, 0x00000100,
1508         0x3c210, 0xffffffff, 0x06000100,
1509         0x3c290, 0xffffffff, 0x00000100,
1510         0x3c274, 0xffffffff, 0x00000100,
1511         0x3c2b4, 0xffffffff, 0x00000100,
1512         0x3c2b0, 0xffffffff, 0x00000100,
1513         0x3c270, 0xffffffff, 0x00000100,
1514         0x30800, 0xffffffff, 0xe0000000,
1515         0x3c020, 0xffffffff, 0x00010000,
1516         0x3c024, 0xffffffff, 0x00030002,
1517         0x3c028, 0xffffffff, 0x00040007,
1518         0x3c02c, 0xffffffff, 0x00060005,
1519         0x3c030, 0xffffffff, 0x00090008,
1520         0x3c034, 0xffffffff, 0x00010000,
1521         0x3c038, 0xffffffff, 0x00030002,
1522         0x3c03c, 0xffffffff, 0x00040007,
1523         0x3c040, 0xffffffff, 0x00060005,
1524         0x3c044, 0xffffffff, 0x00090008,
1525         0x3c048, 0xffffffff, 0x00010000,
1526         0x3c04c, 0xffffffff, 0x00030002,
1527         0x3c050, 0xffffffff, 0x00040007,
1528         0x3c054, 0xffffffff, 0x00060005,
1529         0x3c058, 0xffffffff, 0x00090008,
1530         0x3c05c, 0xffffffff, 0x00010000,
1531         0x3c060, 0xffffffff, 0x00030002,
1532         0x3c064, 0xffffffff, 0x00040007,
1533         0x3c068, 0xffffffff, 0x00060005,
1534         0x3c06c, 0xffffffff, 0x00090008,
1535         0x3c070, 0xffffffff, 0x00010000,
1536         0x3c074, 0xffffffff, 0x00030002,
1537         0x3c078, 0xffffffff, 0x00040007,
1538         0x3c07c, 0xffffffff, 0x00060005,
1539         0x3c080, 0xffffffff, 0x00090008,
1540         0x3c084, 0xffffffff, 0x00010000,
1541         0x3c088, 0xffffffff, 0x00030002,
1542         0x3c08c, 0xffffffff, 0x00040007,
1543         0x3c090, 0xffffffff, 0x00060005,
1544         0x3c094, 0xffffffff, 0x00090008,
1545         0x3c098, 0xffffffff, 0x00010000,
1546         0x3c09c, 0xffffffff, 0x00030002,
1547         0x3c0a0, 0xffffffff, 0x00040007,
1548         0x3c0a4, 0xffffffff, 0x00060005,
1549         0x3c0a8, 0xffffffff, 0x00090008,
1550         0x3c0ac, 0xffffffff, 0x00010000,
1551         0x3c0b0, 0xffffffff, 0x00030002,
1552         0x3c0b4, 0xffffffff, 0x00040007,
1553         0x3c0b8, 0xffffffff, 0x00060005,
1554         0x3c0bc, 0xffffffff, 0x00090008,
1555         0x3c0c0, 0xffffffff, 0x00010000,
1556         0x3c0c4, 0xffffffff, 0x00030002,
1557         0x3c0c8, 0xffffffff, 0x00040007,
1558         0x3c0cc, 0xffffffff, 0x00060005,
1559         0x3c0d0, 0xffffffff, 0x00090008,
1560         0x3c0d4, 0xffffffff, 0x00010000,
1561         0x3c0d8, 0xffffffff, 0x00030002,
1562         0x3c0dc, 0xffffffff, 0x00040007,
1563         0x3c0e0, 0xffffffff, 0x00060005,
1564         0x3c0e4, 0xffffffff, 0x00090008,
1565         0x3c0e8, 0xffffffff, 0x00010000,
1566         0x3c0ec, 0xffffffff, 0x00030002,
1567         0x3c0f0, 0xffffffff, 0x00040007,
1568         0x3c0f4, 0xffffffff, 0x00060005,
1569         0x3c0f8, 0xffffffff, 0x00090008,
1570         0xc318, 0xffffffff, 0x00020200,
1571         0x3350, 0xffffffff, 0x00000200,
1572         0x15c0, 0xffffffff, 0x00000400,
1573         0x55e8, 0xffffffff, 0x00000000,
1574         0x2f50, 0xffffffff, 0x00000902,
1575         0x3c000, 0xffffffff, 0x96940200,
1576         0x8708, 0xffffffff, 0x00900100,
1577         0xc424, 0xffffffff, 0x0020003f,
1578         0x38, 0xffffffff, 0x0140001c,
1579         0x3c, 0x000f0000, 0x000f0000,
1580         0x220, 0xffffffff, 0xc060000c,
1581         0x224, 0xc0000fff, 0x00000100,
1582         0xf90, 0xffffffff, 0x00000100,
1583         0xf98, 0x00000101, 0x00000000,
1584         0x20a8, 0xffffffff, 0x00000104,
1585         0x55e4, 0xff000fff, 0x00000100,
1586         0x30cc, 0xc0000fff, 0x00000104,
1587         0xc1e4, 0x00000001, 0x00000001,
1588         0xd00c, 0xff000ff0, 0x00000100,
1589         0xd80c, 0xff000ff0, 0x00000100
1590 };
1591
1592 static const u32 godavari_golden_registers[] =
1593 {
1594         0x55e4, 0xff607fff, 0xfc000100,
1595         0x6ed8, 0x00010101, 0x00010000,
1596         0x9830, 0xffffffff, 0x00000000,
1597         0x98302, 0xf00fffff, 0x00000400,
1598         0x6130, 0xffffffff, 0x00010000,
1599         0x5bb0, 0x000000f0, 0x00000070,
1600         0x5bc0, 0xf0311fff, 0x80300000,
1601         0x98f8, 0x73773777, 0x12010001,
1602         0x98fc, 0xffffffff, 0x00000010,
1603         0x8030, 0x00001f0f, 0x0000100a,
1604         0x2f48, 0x73773777, 0x12010001,
1605         0x2408, 0x000fffff, 0x000c007f,
1606         0x8a14, 0xf000003f, 0x00000007,
1607         0x8b24, 0xffffffff, 0x00ff0fff,
1608         0x30a04, 0x0000ff0f, 0x00000000,
1609         0x28a4c, 0x07ffffff, 0x06000000,
1610         0x4d8, 0x00000fff, 0x00000100,
1611         0xd014, 0x00010000, 0x00810001,
1612         0xd814, 0x00010000, 0x00810001,
1613         0x3e78, 0x00000001, 0x00000002,
1614         0xc768, 0x00000008, 0x00000008,
1615         0xc770, 0x00000f00, 0x00000800,
1616         0xc774, 0x00000f00, 0x00000800,
1617         0xc798, 0x00ffffff, 0x00ff7fbf,
1618         0xc79c, 0x00ffffff, 0x00ff7faf,
1619         0x8c00, 0x000000ff, 0x00000001,
1620         0x214f8, 0x01ff01ff, 0x00000002,
1621         0x21498, 0x007ff800, 0x00200000,
1622         0x2015c, 0xffffffff, 0x00000f40,
1623         0x88c4, 0x001f3ae3, 0x00000082,
1624         0x88d4, 0x0000001f, 0x00000010,
1625         0x30934, 0xffffffff, 0x00000000
1626 };
1627
1628
1629 static void cik_init_golden_registers(struct radeon_device *rdev)
1630 {
1631         /* Some of the registers might be dependent on GRBM_GFX_INDEX */
1632         mutex_lock(&rdev->grbm_idx_mutex);
1633         switch (rdev->family) {
1634         case CHIP_BONAIRE:
1635                 radeon_program_register_sequence(rdev,
1636                                                  bonaire_mgcg_cgcg_init,
1637                                                  (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));
1638                 radeon_program_register_sequence(rdev,
1639                                                  bonaire_golden_registers,
1640                                                  (const u32)ARRAY_SIZE(bonaire_golden_registers));
1641                 radeon_program_register_sequence(rdev,
1642                                                  bonaire_golden_common_registers,
1643                                                  (const u32)ARRAY_SIZE(bonaire_golden_common_registers));
1644                 radeon_program_register_sequence(rdev,
1645                                                  bonaire_golden_spm_registers,
1646                                                  (const u32)ARRAY_SIZE(bonaire_golden_spm_registers));
1647                 break;
1648         case CHIP_KABINI:
1649                 radeon_program_register_sequence(rdev,
1650                                                  kalindi_mgcg_cgcg_init,
1651                                                  (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
1652                 radeon_program_register_sequence(rdev,
1653                                                  kalindi_golden_registers,
1654                                                  (const u32)ARRAY_SIZE(kalindi_golden_registers));
1655                 radeon_program_register_sequence(rdev,
1656                                                  kalindi_golden_common_registers,
1657                                                  (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
1658                 radeon_program_register_sequence(rdev,
1659                                                  kalindi_golden_spm_registers,
1660                                                  (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
1661                 break;
1662         case CHIP_MULLINS:
1663                 radeon_program_register_sequence(rdev,
1664                                                  kalindi_mgcg_cgcg_init,
1665                                                  (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
1666                 radeon_program_register_sequence(rdev,
1667                                                  godavari_golden_registers,
1668                                                  (const u32)ARRAY_SIZE(godavari_golden_registers));
1669                 radeon_program_register_sequence(rdev,
1670                                                  kalindi_golden_common_registers,
1671                                                  (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
1672                 radeon_program_register_sequence(rdev,
1673                                                  kalindi_golden_spm_registers,
1674                                                  (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
1675                 break;
1676         case CHIP_KAVERI:
1677                 radeon_program_register_sequence(rdev,
1678                                                  spectre_mgcg_cgcg_init,
1679                                                  (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init));
1680                 radeon_program_register_sequence(rdev,
1681                                                  spectre_golden_registers,
1682                                                  (const u32)ARRAY_SIZE(spectre_golden_registers));
1683                 radeon_program_register_sequence(rdev,
1684                                                  spectre_golden_common_registers,
1685                                                  (const u32)ARRAY_SIZE(spectre_golden_common_registers));
1686                 radeon_program_register_sequence(rdev,
1687                                                  spectre_golden_spm_registers,
1688                                                  (const u32)ARRAY_SIZE(spectre_golden_spm_registers));
1689                 break;
1690         case CHIP_HAWAII:
1691                 radeon_program_register_sequence(rdev,
1692                                                  hawaii_mgcg_cgcg_init,
1693                                                  (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init));
1694                 radeon_program_register_sequence(rdev,
1695                                                  hawaii_golden_registers,
1696                                                  (const u32)ARRAY_SIZE(hawaii_golden_registers));
1697                 radeon_program_register_sequence(rdev,
1698                                                  hawaii_golden_common_registers,
1699                                                  (const u32)ARRAY_SIZE(hawaii_golden_common_registers));
1700                 radeon_program_register_sequence(rdev,
1701                                                  hawaii_golden_spm_registers,
1702                                                  (const u32)ARRAY_SIZE(hawaii_golden_spm_registers));
1703                 break;
1704         default:
1705                 break;
1706         }
1707         mutex_unlock(&rdev->grbm_idx_mutex);
1708 }
1709
1710 /**
1711  * cik_get_xclk - get the xclk
1712  *
1713  * @rdev: radeon_device pointer
1714  *
1715  * Returns the reference clock used by the gfx engine
1716  * (CIK).
1717  */
1718 u32 cik_get_xclk(struct radeon_device *rdev)
1719 {
1720         u32 reference_clock = rdev->clock.spll.reference_freq;
1721
1722         if (rdev->flags & RADEON_IS_IGP) {
1723                 if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK)
1724                         return reference_clock / 2;
1725         } else {
1726                 if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE)
1727                         return reference_clock / 4;
1728         }
1729         return reference_clock;
1730 }
1731
1732 /**
1733  * cik_mm_rdoorbell - read a doorbell dword
1734  *
1735  * @rdev: radeon_device pointer
1736  * @index: doorbell index
1737  *
1738  * Returns the value in the doorbell aperture at the
1739  * requested doorbell index (CIK).
1740  */
1741 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index)
1742 {
1743         if (index < rdev->doorbell.num_doorbells) {
1744                 return readl(rdev->doorbell.ptr + index);
1745         } else {
1746                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
1747                 return 0;
1748         }
1749 }
1750
1751 /**
1752  * cik_mm_wdoorbell - write a doorbell dword
1753  *
1754  * @rdev: radeon_device pointer
1755  * @index: doorbell index
1756  * @v: value to write
1757  *
1758  * Writes @v to the doorbell aperture at the
1759  * requested doorbell index (CIK).
1760  */
1761 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v)
1762 {
1763         if (index < rdev->doorbell.num_doorbells) {
1764                 writel(v, rdev->doorbell.ptr + index);
1765         } else {
1766                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
1767         }
1768 }
1769
1770 #define BONAIRE_IO_MC_REGS_SIZE 36
1771
1772 static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] =
1773 {
1774         {0x00000070, 0x04400000},
1775         {0x00000071, 0x80c01803},
1776         {0x00000072, 0x00004004},
1777         {0x00000073, 0x00000100},
1778         {0x00000074, 0x00ff0000},
1779         {0x00000075, 0x34000000},
1780         {0x00000076, 0x08000014},
1781         {0x00000077, 0x00cc08ec},
1782         {0x00000078, 0x00000400},
1783         {0x00000079, 0x00000000},
1784         {0x0000007a, 0x04090000},
1785         {0x0000007c, 0x00000000},
1786         {0x0000007e, 0x4408a8e8},
1787         {0x0000007f, 0x00000304},
1788         {0x00000080, 0x00000000},
1789         {0x00000082, 0x00000001},
1790         {0x00000083, 0x00000002},
1791         {0x00000084, 0xf3e4f400},
1792         {0x00000085, 0x052024e3},
1793         {0x00000087, 0x00000000},
1794         {0x00000088, 0x01000000},
1795         {0x0000008a, 0x1c0a0000},
1796         {0x0000008b, 0xff010000},
1797         {0x0000008d, 0xffffefff},
1798         {0x0000008e, 0xfff3efff},
1799         {0x0000008f, 0xfff3efbf},
1800         {0x00000092, 0xf7ffffff},
1801         {0x00000093, 0xffffff7f},
1802         {0x00000095, 0x00101101},
1803         {0x00000096, 0x00000fff},
1804         {0x00000097, 0x00116fff},
1805         {0x00000098, 0x60010000},
1806         {0x00000099, 0x10010000},
1807         {0x0000009a, 0x00006000},
1808         {0x0000009b, 0x00001000},
1809         {0x0000009f, 0x00b48000}
1810 };
1811
1812 #define HAWAII_IO_MC_REGS_SIZE 22
1813
1814 static const u32 hawaii_io_mc_regs[HAWAII_IO_MC_REGS_SIZE][2] =
1815 {
1816         {0x0000007d, 0x40000000},
1817         {0x0000007e, 0x40180304},
1818         {0x0000007f, 0x0000ff00},
1819         {0x00000081, 0x00000000},
1820         {0x00000083, 0x00000800},
1821         {0x00000086, 0x00000000},
1822         {0x00000087, 0x00000100},
1823         {0x00000088, 0x00020100},
1824         {0x00000089, 0x00000000},
1825         {0x0000008b, 0x00040000},
1826         {0x0000008c, 0x00000100},
1827         {0x0000008e, 0xff010000},
1828         {0x00000090, 0xffffefff},
1829         {0x00000091, 0xfff3efff},
1830         {0x00000092, 0xfff3efbf},
1831         {0x00000093, 0xf7ffffff},
1832         {0x00000094, 0xffffff7f},
1833         {0x00000095, 0x00000fff},
1834         {0x00000096, 0x00116fff},
1835         {0x00000097, 0x60010000},
1836         {0x00000098, 0x10010000},
1837         {0x0000009f, 0x00c79000}
1838 };
1839
1840
1841 /**
1842  * cik_srbm_select - select specific register instances
1843  *
1844  * @rdev: radeon_device pointer
1845  * @me: selected ME (micro engine)
1846  * @pipe: pipe
1847  * @queue: queue
1848  * @vmid: VMID
1849  *
1850  * Switches the currently active registers instances.  Some
1851  * registers are instanced per VMID, others are instanced per
1852  * me/pipe/queue combination.
1853  */
1854 static void cik_srbm_select(struct radeon_device *rdev,
1855                             u32 me, u32 pipe, u32 queue, u32 vmid)
1856 {
1857         u32 srbm_gfx_cntl = (PIPEID(pipe & 0x3) |
1858                              MEID(me & 0x3) |
1859                              VMID(vmid & 0xf) |
1860                              QUEUEID(queue & 0x7));
1861         WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl);
1862 }
1863
1864 /* ucode loading */
1865 /**
1866  * ci_mc_load_microcode - load MC ucode into the hw
1867  *
1868  * @rdev: radeon_device pointer
1869  *
1870  * Load the GDDR MC ucode into the hw (CIK).
1871  * Returns 0 on success, error on failure.
1872  */
1873 int ci_mc_load_microcode(struct radeon_device *rdev)
1874 {
1875         const __be32 *fw_data = NULL;
1876         const __le32 *new_fw_data = NULL;
1877         u32 running, tmp;
1878         u32 *io_mc_regs = NULL;
1879         const __le32 *new_io_mc_regs = NULL;
1880         int i, regs_size, ucode_size;
1881
1882         if (!rdev->mc_fw)
1883                 return -EINVAL;
1884
1885         if (rdev->new_fw) {
1886                 const struct mc_firmware_header_v1_0 *hdr =
1887                         (const struct mc_firmware_header_v1_0 *)rdev->mc_fw->data;
1888
1889                 radeon_ucode_print_mc_hdr(&hdr->header);
1890
1891                 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
1892                 new_io_mc_regs = (const __le32 *)
1893                         (rdev->mc_fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
1894                 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1895                 new_fw_data = (const __le32 *)
1896                         (rdev->mc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1897         } else {
1898                 ucode_size = rdev->mc_fw->size / 4;
1899
1900                 switch (rdev->family) {
1901                 case CHIP_BONAIRE:
1902                         io_mc_regs = (u32 *)&bonaire_io_mc_regs;
1903                         regs_size = BONAIRE_IO_MC_REGS_SIZE;
1904                         break;
1905                 case CHIP_HAWAII:
1906                         io_mc_regs = (u32 *)&hawaii_io_mc_regs;
1907                         regs_size = HAWAII_IO_MC_REGS_SIZE;
1908                         break;
1909                 default:
1910                         return -EINVAL;
1911                 }
1912                 fw_data = (const __be32 *)rdev->mc_fw->data;
1913         }
1914
1915         running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
1916
1917         if (running == 0) {
1918                 /* reset the engine and set to writable */
1919                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1920                 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
1921
1922                 /* load mc io regs */
1923                 for (i = 0; i < regs_size; i++) {
1924                         if (rdev->new_fw) {
1925                                 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
1926                                 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
1927                         } else {
1928                                 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
1929                                 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
1930                         }
1931                 }
1932
1933                 tmp = RREG32(MC_SEQ_MISC0);
1934                 if ((rdev->pdev->device == 0x6649) && ((tmp & 0xff00) == 0x5600)) {
1935                         WREG32(MC_SEQ_IO_DEBUG_INDEX, 5);
1936                         WREG32(MC_SEQ_IO_DEBUG_DATA, 0x00000023);
1937                         WREG32(MC_SEQ_IO_DEBUG_INDEX, 9);
1938                         WREG32(MC_SEQ_IO_DEBUG_DATA, 0x000001f0);
1939                 }
1940
1941                 /* load the MC ucode */
1942                 for (i = 0; i < ucode_size; i++) {
1943                         if (rdev->new_fw)
1944                                 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
1945                         else
1946                                 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
1947                 }
1948
1949                 /* put the engine back into the active state */
1950                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1951                 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
1952                 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
1953
1954                 /* wait for training to complete */
1955                 for (i = 0; i < rdev->usec_timeout; i++) {
1956                         if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
1957                                 break;
1958                         udelay(1);
1959                 }
1960                 for (i = 0; i < rdev->usec_timeout; i++) {
1961                         if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
1962                                 break;
1963                         udelay(1);
1964                 }
1965         }
1966
1967         return 0;
1968 }
1969
1970 /**
1971  * cik_init_microcode - load ucode images from disk
1972  *
1973  * @rdev: radeon_device pointer
1974  *
1975  * Use the firmware interface to load the ucode images into
1976  * the driver (not loaded into hw).
1977  * Returns 0 on success, error on failure.
1978  */
1979 static int cik_init_microcode(struct radeon_device *rdev)
1980 {
1981         const char *chip_name;
1982         const char *new_chip_name;
1983         size_t pfp_req_size, me_req_size, ce_req_size,
1984                 mec_req_size, rlc_req_size, mc_req_size = 0,
1985                 sdma_req_size, smc_req_size = 0, mc2_req_size = 0;
1986         char fw_name[30];
1987         int new_fw = 0;
1988         int err;
1989         int num_fw;
1990         bool new_smc = false;
1991
1992         DRM_DEBUG("\n");
1993
1994         switch (rdev->family) {
1995         case CHIP_BONAIRE:
1996                 chip_name = "BONAIRE";
1997                 if ((rdev->pdev->revision == 0x80) ||
1998                     (rdev->pdev->revision == 0x81) ||
1999                     (rdev->pdev->device == 0x665f))
2000                         new_smc = true;
2001                 new_chip_name = "bonaire";
2002                 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
2003                 me_req_size = CIK_ME_UCODE_SIZE * 4;
2004                 ce_req_size = CIK_CE_UCODE_SIZE * 4;
2005                 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
2006                 rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
2007                 mc_req_size = BONAIRE_MC_UCODE_SIZE * 4;
2008                 mc2_req_size = BONAIRE_MC2_UCODE_SIZE * 4;
2009                 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
2010                 smc_req_size = ALIGN(BONAIRE_SMC_UCODE_SIZE, 4);
2011                 num_fw = 8;
2012                 break;
2013         case CHIP_HAWAII:
2014                 chip_name = "HAWAII";
2015                 if (rdev->pdev->revision == 0x80)
2016                         new_smc = true;
2017                 new_chip_name = "hawaii";
2018                 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
2019                 me_req_size = CIK_ME_UCODE_SIZE * 4;
2020                 ce_req_size = CIK_CE_UCODE_SIZE * 4;
2021                 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
2022                 rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
2023                 mc_req_size = HAWAII_MC_UCODE_SIZE * 4;
2024                 mc2_req_size = HAWAII_MC2_UCODE_SIZE * 4;
2025                 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
2026                 smc_req_size = ALIGN(HAWAII_SMC_UCODE_SIZE, 4);
2027                 num_fw = 8;
2028                 break;
2029         case CHIP_KAVERI:
2030                 chip_name = "KAVERI";
2031                 new_chip_name = "kaveri";
2032                 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
2033                 me_req_size = CIK_ME_UCODE_SIZE * 4;
2034                 ce_req_size = CIK_CE_UCODE_SIZE * 4;
2035                 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
2036                 rlc_req_size = KV_RLC_UCODE_SIZE * 4;
2037                 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
2038                 num_fw = 7;
2039                 break;
2040         case CHIP_KABINI:
2041                 chip_name = "KABINI";
2042                 new_chip_name = "kabini";
2043                 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
2044                 me_req_size = CIK_ME_UCODE_SIZE * 4;
2045                 ce_req_size = CIK_CE_UCODE_SIZE * 4;
2046                 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
2047                 rlc_req_size = KB_RLC_UCODE_SIZE * 4;
2048                 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
2049                 num_fw = 6;
2050                 break;
2051         case CHIP_MULLINS:
2052                 chip_name = "MULLINS";
2053                 new_chip_name = "mullins";
2054                 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
2055                 me_req_size = CIK_ME_UCODE_SIZE * 4;
2056                 ce_req_size = CIK_CE_UCODE_SIZE * 4;
2057                 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
2058                 rlc_req_size = ML_RLC_UCODE_SIZE * 4;
2059                 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
2060                 num_fw = 6;
2061                 break;
2062         default: BUG();
2063         }
2064
2065         DRM_INFO("Loading %s Microcode\n", new_chip_name);
2066
2067         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", new_chip_name);
2068         err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
2069         if (err) {
2070                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2071                 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
2072                 if (err)
2073                         goto out;
2074                 if (rdev->pfp_fw->size != pfp_req_size) {
2075                         pr_err("cik_cp: Bogus length %zu in firmware \"%s\"\n",
2076                                rdev->pfp_fw->size, fw_name);
2077                         err = -EINVAL;
2078                         goto out;
2079                 }
2080         } else {
2081                 err = radeon_ucode_validate(rdev->pfp_fw);
2082                 if (err) {
2083                         pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2084                                fw_name);
2085                         goto out;
2086                 } else {
2087                         new_fw++;
2088                 }
2089         }
2090
2091         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", new_chip_name);
2092         err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
2093         if (err) {
2094                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2095                 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
2096                 if (err)
2097                         goto out;
2098                 if (rdev->me_fw->size != me_req_size) {
2099                         pr_err("cik_cp: Bogus length %zu in firmware \"%s\"\n",
2100                                rdev->me_fw->size, fw_name);
2101                         err = -EINVAL;
2102                 }
2103         } else {
2104                 err = radeon_ucode_validate(rdev->me_fw);
2105                 if (err) {
2106                         pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2107                                fw_name);
2108                         goto out;
2109                 } else {
2110                         new_fw++;
2111                 }
2112         }
2113
2114         snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", new_chip_name);
2115         err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
2116         if (err) {
2117                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
2118                 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
2119                 if (err)
2120                         goto out;
2121                 if (rdev->ce_fw->size != ce_req_size) {
2122                         pr_err("cik_cp: Bogus length %zu in firmware \"%s\"\n",
2123                                rdev->ce_fw->size, fw_name);
2124                         err = -EINVAL;
2125                 }
2126         } else {
2127                 err = radeon_ucode_validate(rdev->ce_fw);
2128                 if (err) {
2129                         pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2130                                fw_name);
2131                         goto out;
2132                 } else {
2133                         new_fw++;
2134                 }
2135         }
2136
2137         snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", new_chip_name);
2138         err = request_firmware(&rdev->mec_fw, fw_name, rdev->dev);
2139         if (err) {
2140                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
2141                 err = request_firmware(&rdev->mec_fw, fw_name, rdev->dev);
2142                 if (err)
2143                         goto out;
2144                 if (rdev->mec_fw->size != mec_req_size) {
2145                         pr_err("cik_cp: Bogus length %zu in firmware \"%s\"\n",
2146                                rdev->mec_fw->size, fw_name);
2147                         err = -EINVAL;
2148                 }
2149         } else {
2150                 err = radeon_ucode_validate(rdev->mec_fw);
2151                 if (err) {
2152                         pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2153                                fw_name);
2154                         goto out;
2155                 } else {
2156                         new_fw++;
2157                 }
2158         }
2159
2160         if (rdev->family == CHIP_KAVERI) {
2161                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", new_chip_name);
2162                 err = request_firmware(&rdev->mec2_fw, fw_name, rdev->dev);
2163                 if (err) {
2164                         goto out;
2165                 } else {
2166                         err = radeon_ucode_validate(rdev->mec2_fw);
2167                         if (err) {
2168                                 goto out;
2169                         } else {
2170                                 new_fw++;
2171                         }
2172                 }
2173         }
2174
2175         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", new_chip_name);
2176         err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
2177         if (err) {
2178                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
2179                 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
2180                 if (err)
2181                         goto out;
2182                 if (rdev->rlc_fw->size != rlc_req_size) {
2183                         pr_err("cik_rlc: Bogus length %zu in firmware \"%s\"\n",
2184                                rdev->rlc_fw->size, fw_name);
2185                         err = -EINVAL;
2186                 }
2187         } else {
2188                 err = radeon_ucode_validate(rdev->rlc_fw);
2189                 if (err) {
2190                         pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2191                                fw_name);
2192                         goto out;
2193                 } else {
2194                         new_fw++;
2195                 }
2196         }
2197
2198         snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", new_chip_name);
2199         err = request_firmware(&rdev->sdma_fw, fw_name, rdev->dev);
2200         if (err) {
2201                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
2202                 err = request_firmware(&rdev->sdma_fw, fw_name, rdev->dev);
2203                 if (err)
2204                         goto out;
2205                 if (rdev->sdma_fw->size != sdma_req_size) {
2206                         pr_err("cik_sdma: Bogus length %zu in firmware \"%s\"\n",
2207                                rdev->sdma_fw->size, fw_name);
2208                         err = -EINVAL;
2209                 }
2210         } else {
2211                 err = radeon_ucode_validate(rdev->sdma_fw);
2212                 if (err) {
2213                         pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2214                                fw_name);
2215                         goto out;
2216                 } else {
2217                         new_fw++;
2218                 }
2219         }
2220
2221         /* No SMC, MC ucode on APUs */
2222         if (!(rdev->flags & RADEON_IS_IGP)) {
2223                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", new_chip_name);
2224                 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
2225                 if (err) {
2226                         snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc2.bin", chip_name);
2227                         err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
2228                         if (err) {
2229                                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
2230                                 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
2231                                 if (err)
2232                                         goto out;
2233                         }
2234                         if ((rdev->mc_fw->size != mc_req_size) &&
2235                             (rdev->mc_fw->size != mc2_req_size)){
2236                                 pr_err("cik_mc: Bogus length %zu in firmware \"%s\"\n",
2237                                        rdev->mc_fw->size, fw_name);
2238                                 err = -EINVAL;
2239                         }
2240                         DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->size);
2241                 } else {
2242                         err = radeon_ucode_validate(rdev->mc_fw);
2243                         if (err) {
2244                                 pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2245                                        fw_name);
2246                                 goto out;
2247                         } else {
2248                                 new_fw++;
2249                         }
2250                 }
2251
2252                 if (new_smc)
2253                         snprintf(fw_name, sizeof(fw_name), "radeon/%s_k_smc.bin", new_chip_name);
2254                 else
2255                         snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", new_chip_name);
2256                 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
2257                 if (err) {
2258                         snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
2259                         err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
2260                         if (err) {
2261                                 pr_err("smc: error loading firmware \"%s\"\n",
2262                                        fw_name);
2263                                 release_firmware(rdev->smc_fw);
2264                                 rdev->smc_fw = NULL;
2265                                 err = 0;
2266                         } else if (rdev->smc_fw->size != smc_req_size) {
2267                                 pr_err("cik_smc: Bogus length %zu in firmware \"%s\"\n",
2268                                        rdev->smc_fw->size, fw_name);
2269                                 err = -EINVAL;
2270                         }
2271                 } else {
2272                         err = radeon_ucode_validate(rdev->smc_fw);
2273                         if (err) {
2274                                 pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2275                                        fw_name);
2276                                 goto out;
2277                         } else {
2278                                 new_fw++;
2279                         }
2280                 }
2281         }
2282
2283         if (new_fw == 0) {
2284                 rdev->new_fw = false;
2285         } else if (new_fw < num_fw) {
2286                 pr_err("ci_fw: mixing new and old firmware!\n");
2287                 err = -EINVAL;
2288         } else {
2289                 rdev->new_fw = true;
2290         }
2291
2292 out:
2293         if (err) {
2294                 if (err != -EINVAL)
2295                         pr_err("cik_cp: Failed to load firmware \"%s\"\n",
2296                                fw_name);
2297                 release_firmware(rdev->pfp_fw);
2298                 rdev->pfp_fw = NULL;
2299                 release_firmware(rdev->me_fw);
2300                 rdev->me_fw = NULL;
2301                 release_firmware(rdev->ce_fw);
2302                 rdev->ce_fw = NULL;
2303                 release_firmware(rdev->mec_fw);
2304                 rdev->mec_fw = NULL;
2305                 release_firmware(rdev->mec2_fw);
2306                 rdev->mec2_fw = NULL;
2307                 release_firmware(rdev->rlc_fw);
2308                 rdev->rlc_fw = NULL;
2309                 release_firmware(rdev->sdma_fw);
2310                 rdev->sdma_fw = NULL;
2311                 release_firmware(rdev->mc_fw);
2312                 rdev->mc_fw = NULL;
2313                 release_firmware(rdev->smc_fw);
2314                 rdev->smc_fw = NULL;
2315         }
2316         return err;
2317 }
2318
2319 /*
2320  * Core functions
2321  */
2322 /**
2323  * cik_tiling_mode_table_init - init the hw tiling table
2324  *
2325  * @rdev: radeon_device pointer
2326  *
2327  * Starting with SI, the tiling setup is done globally in a
2328  * set of 32 tiling modes.  Rather than selecting each set of
2329  * parameters per surface as on older asics, we just select
2330  * which index in the tiling table we want to use, and the
2331  * surface uses those parameters (CIK).
2332  */
2333 static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2334 {
2335         u32 *tile = rdev->config.cik.tile_mode_array;
2336         u32 *macrotile = rdev->config.cik.macrotile_mode_array;
2337         const u32 num_tile_mode_states =
2338                         ARRAY_SIZE(rdev->config.cik.tile_mode_array);
2339         const u32 num_secondary_tile_mode_states =
2340                         ARRAY_SIZE(rdev->config.cik.macrotile_mode_array);
2341         u32 reg_offset, split_equal_to_row_size;
2342         u32 num_pipe_configs;
2343         u32 num_rbs = rdev->config.cik.max_backends_per_se *
2344                 rdev->config.cik.max_shader_engines;
2345
2346         switch (rdev->config.cik.mem_row_size_in_kb) {
2347         case 1:
2348                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
2349                 break;
2350         case 2:
2351         default:
2352                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
2353                 break;
2354         case 4:
2355                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
2356                 break;
2357         }
2358
2359         num_pipe_configs = rdev->config.cik.max_tile_pipes;
2360         if (num_pipe_configs > 8)
2361                 num_pipe_configs = 16;
2362
2363         for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2364                 tile[reg_offset] = 0;
2365         for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2366                 macrotile[reg_offset] = 0;
2367
2368         switch(num_pipe_configs) {
2369         case 16:
2370                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2371                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2372                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2373                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2374                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2375                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2376                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2377                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2378                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2379                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2380                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2381                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2382                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2383                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2384                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2385                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2386                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2387                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2388                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2389                            TILE_SPLIT(split_equal_to_row_size));
2390                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2391                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2392                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2393                 tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2394                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2395                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2396                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2397                 tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2398                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2399                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2400                            TILE_SPLIT(split_equal_to_row_size));
2401                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2402                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2403                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2404                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2405                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2406                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2407                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2408                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2409                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2410                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2411                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2412                             PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2413                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2414                 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2415                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2416                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2417                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2418                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2419                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2420                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2421                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2422                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2423                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2424                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2425                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2426                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2427                             PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2428                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2429                 tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2430                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2431                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2432                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2433                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2434                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2435                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2436                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2437                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2438                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2439                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2440                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2441                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2442                             PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2443                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2444                 tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2445                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2446                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2447                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2448
2449                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2450                            BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2451                            MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2452                            NUM_BANKS(ADDR_SURF_16_BANK));
2453                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2454                            BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2455                            MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2456                            NUM_BANKS(ADDR_SURF_16_BANK));
2457                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2458                            BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2459                            MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2460                            NUM_BANKS(ADDR_SURF_16_BANK));
2461                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2462                            BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2463                            MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2464                            NUM_BANKS(ADDR_SURF_16_BANK));
2465                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2466                            BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2467                            MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2468                            NUM_BANKS(ADDR_SURF_8_BANK));
2469                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2470                            BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2471                            MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2472                            NUM_BANKS(ADDR_SURF_4_BANK));
2473                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2474                            BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2475                            MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2476                            NUM_BANKS(ADDR_SURF_2_BANK));
2477                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2478                            BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2479                            MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2480                            NUM_BANKS(ADDR_SURF_16_BANK));
2481                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2482                            BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2483                            MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2484                            NUM_BANKS(ADDR_SURF_16_BANK));
2485                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2486                             BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2487                             MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2488                             NUM_BANKS(ADDR_SURF_16_BANK));
2489                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2490                             BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2491                             MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2492                             NUM_BANKS(ADDR_SURF_8_BANK));
2493                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2494                             BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2495                             MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2496                             NUM_BANKS(ADDR_SURF_4_BANK));
2497                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2498                             BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2499                             MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2500                             NUM_BANKS(ADDR_SURF_2_BANK));
2501                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2502                             BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2503                             MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2504                             NUM_BANKS(ADDR_SURF_2_BANK));
2505
2506                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2507                         WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
2508                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2509                         WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
2510                 break;
2511
2512         case 8:
2513                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2514                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2515                            PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2516                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2517                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2518                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2519                            PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2520                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2521                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2522                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2523                            PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2524                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2525                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2526                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2527                            PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2528                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2529                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2530                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2531                            PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2532                            TILE_SPLIT(split_equal_to_row_size));
2533                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2534                            PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2535                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2536                 tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2537                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2538                            PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2539                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2540                 tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2541                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2542                            PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2543                            TILE_SPLIT(split_equal_to_row_size));
2544                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2545                            PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2546                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2547                            PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2548                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2549                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2550                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2551                             PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2552                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2553                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2554                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2555                             PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2556                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2557                 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2558                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2559                             PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2560                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2561                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2562                             PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2563                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2564                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2565                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2566                             PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2567                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2568                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2569                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2570                             PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2571                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2572                 tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2573                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2574                             PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2575                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2576                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2577                             PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2578                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2579                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2580                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2581                             PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2582                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2583                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2584                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2585                             PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2586                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2587                 tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2588                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2589                             PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2590                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2591
2592                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2593                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2594                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2595                                 NUM_BANKS(ADDR_SURF_16_BANK));
2596                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2597                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2598                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2599                                 NUM_BANKS(ADDR_SURF_16_BANK));
2600                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2601                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2602                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2603                                 NUM_BANKS(ADDR_SURF_16_BANK));
2604                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2605                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2606                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2607                                 NUM_BANKS(ADDR_SURF_16_BANK));
2608                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2609                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2610                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2611                                 NUM_BANKS(ADDR_SURF_8_BANK));
2612                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2613                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2614                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2615                                 NUM_BANKS(ADDR_SURF_4_BANK));
2616                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2617                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2618                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2619                                 NUM_BANKS(ADDR_SURF_2_BANK));
2620                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2621                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2622                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2623                                 NUM_BANKS(ADDR_SURF_16_BANK));
2624                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2625                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2626                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2627                                 NUM_BANKS(ADDR_SURF_16_BANK));
2628                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2629                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2630                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2631                                 NUM_BANKS(ADDR_SURF_16_BANK));
2632                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2633                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2634                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2635                                 NUM_BANKS(ADDR_SURF_16_BANK));
2636                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2637                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2638                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2639                                 NUM_BANKS(ADDR_SURF_8_BANK));
2640                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2641                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2642                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2643                                 NUM_BANKS(ADDR_SURF_4_BANK));
2644                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2645                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2646                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2647                                 NUM_BANKS(ADDR_SURF_2_BANK));
2648
2649                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2650                         WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
2651                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2652                         WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
2653                 break;
2654
2655         case 4:
2656                 if (num_rbs == 4) {
2657                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2658                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2659                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2660                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2661                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2662                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2663                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2664                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2665                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2666                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2667                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2668                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2669                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2670                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2671                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2672                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2673                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2674                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2675                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2676                            TILE_SPLIT(split_equal_to_row_size));
2677                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2678                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2679                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2680                 tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2681                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2682                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2683                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2684                 tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2685                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2686                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2687                            TILE_SPLIT(split_equal_to_row_size));
2688                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2689                            PIPE_CONFIG(ADDR_SURF_P4_16x16));
2690                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2691                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2692                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2693                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2694                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2695                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2696                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2697                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2698                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2699                             PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2700                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2701                 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2702                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2703                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2704                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2705                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2706                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2707                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2708                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2709                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2710                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2711                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2712                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2713                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2714                             PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2715                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2716                 tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2717                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2718                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2719                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2720                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2721                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2722                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2723                 tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2724                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2725                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2726                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2727                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2728                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2729                             PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2730                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2731                 tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2732                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2733                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2734                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2735
2736                 } else if (num_rbs < 4) {
2737                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2738                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2739                            PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2740                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2741                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2742                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2743                            PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2744                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2745                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2746                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2747                            PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2748                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2749                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2750                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2751                            PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2752                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2753                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2754                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2755                            PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2756                            TILE_SPLIT(split_equal_to_row_size));
2757                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2758                            PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2759                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2760                 tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2761                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2762                            PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2763                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2764                 tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2765                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2766                            PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2767                            TILE_SPLIT(split_equal_to_row_size));
2768                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2769                            PIPE_CONFIG(ADDR_SURF_P4_8x16));
2770                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2771                            PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2772                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2773                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2774                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2775                             PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2776                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2777                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2778                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2779                             PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2780                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2781                 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2782                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2783                             PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2784                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2785                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2786                             PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2787                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2788                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2789                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2790                             PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2791                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2792                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2793                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2794                             PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2795                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2796                 tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2797                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2798                             PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2799                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2800                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2801                             PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2802                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2803                 tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2804                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2805                             PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2806                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2807                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2808                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2809                             PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2810                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2811                 tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2812                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2813                             PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2814                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2815                 }
2816
2817                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2818                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2819                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2820                                 NUM_BANKS(ADDR_SURF_16_BANK));
2821                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2822                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2823                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2824                                 NUM_BANKS(ADDR_SURF_16_BANK));
2825                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2826                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2827                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2828                                 NUM_BANKS(ADDR_SURF_16_BANK));
2829                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2830                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2831                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2832                                 NUM_BANKS(ADDR_SURF_16_BANK));
2833                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2834                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2835                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2836                                 NUM_BANKS(ADDR_SURF_16_BANK));
2837                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2838                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2839                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2840                                 NUM_BANKS(ADDR_SURF_8_BANK));
2841                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2842                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2843                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2844                                 NUM_BANKS(ADDR_SURF_4_BANK));
2845                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2846                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2847                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2848                                 NUM_BANKS(ADDR_SURF_16_BANK));
2849                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2850                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2851                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2852                                 NUM_BANKS(ADDR_SURF_16_BANK));
2853                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2854                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2855                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2856                                 NUM_BANKS(ADDR_SURF_16_BANK));
2857                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2858                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2859                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2860                                 NUM_BANKS(ADDR_SURF_16_BANK));
2861                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2862                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2863                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2864                                 NUM_BANKS(ADDR_SURF_16_BANK));
2865                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2866                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2867                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2868                                 NUM_BANKS(ADDR_SURF_8_BANK));
2869                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2870                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2871                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2872                                 NUM_BANKS(ADDR_SURF_4_BANK));
2873
2874                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2875                         WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
2876                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2877                         WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
2878                 break;
2879
2880         case 2:
2881                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2882                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2883                            PIPE_CONFIG(ADDR_SURF_P2) |
2884                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2885                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2886                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2887                            PIPE_CONFIG(ADDR_SURF_P2) |
2888                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2889                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2890                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2891                            PIPE_CONFIG(ADDR_SURF_P2) |
2892                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2893                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2894                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2895                            PIPE_CONFIG(ADDR_SURF_P2) |
2896                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2897                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2898                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2899                            PIPE_CONFIG(ADDR_SURF_P2) |
2900                            TILE_SPLIT(split_equal_to_row_size));
2901                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2902                            PIPE_CONFIG(ADDR_SURF_P2) |
2903                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2904                 tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2905                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2906                            PIPE_CONFIG(ADDR_SURF_P2) |
2907                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2908                 tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2909                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2910                            PIPE_CONFIG(ADDR_SURF_P2) |
2911                            TILE_SPLIT(split_equal_to_row_size));
2912                 tile[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2913                            PIPE_CONFIG(ADDR_SURF_P2);
2914                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2915                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2916                            PIPE_CONFIG(ADDR_SURF_P2));
2917                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2918                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2919                             PIPE_CONFIG(ADDR_SURF_P2) |
2920                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2921                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2922                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2923                             PIPE_CONFIG(ADDR_SURF_P2) |
2924                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2925                 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2926                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2927                             PIPE_CONFIG(ADDR_SURF_P2) |
2928                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2929                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2930                             PIPE_CONFIG(ADDR_SURF_P2) |
2931                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2932                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2933                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2934                             PIPE_CONFIG(ADDR_SURF_P2) |
2935                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2936                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2937                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2938                             PIPE_CONFIG(ADDR_SURF_P2) |
2939                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2940                 tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2941                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2942                             PIPE_CONFIG(ADDR_SURF_P2) |
2943                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2944                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2945                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2946                             PIPE_CONFIG(ADDR_SURF_P2));
2947                 tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2948                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2949                             PIPE_CONFIG(ADDR_SURF_P2) |
2950                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2951                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2952                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2953                             PIPE_CONFIG(ADDR_SURF_P2) |
2954                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2955                 tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2956                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2957                             PIPE_CONFIG(ADDR_SURF_P2) |
2958                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2959
2960                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2961                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2962                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2963                                 NUM_BANKS(ADDR_SURF_16_BANK));
2964                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2965                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2966                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2967                                 NUM_BANKS(ADDR_SURF_16_BANK));
2968                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2969                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2970                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2971                                 NUM_BANKS(ADDR_SURF_16_BANK));
2972                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2973                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2974                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2975                                 NUM_BANKS(ADDR_SURF_16_BANK));
2976                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2977                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2978                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2979                                 NUM_BANKS(ADDR_SURF_16_BANK));
2980