Merge remote branch 'anholt/drm-intel-next' into drm-next-stage
[sfrench/cifs-2.6.git] / drivers / gpu / drm / radeon / atombios_dp.c
1 /*
2  * Copyright 2007-8 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include "atom-bits.h"
32 #include "drm_dp_helper.h"
33
34 /* move these to drm_dp_helper.c/h */
35 #define DP_LINK_CONFIGURATION_SIZE 9
36 #define DP_LINK_STATUS_SIZE        6
37 #define DP_DPCD_SIZE               8
38
39 static char *voltage_names[] = {
40         "0.4V", "0.6V", "0.8V", "1.2V"
41 };
42 static char *pre_emph_names[] = {
43         "0dB", "3.5dB", "6dB", "9.5dB"
44 };
45
46 static const int dp_clocks[] = {
47         54000,  /* 1 lane, 1.62 Ghz */
48         90000,  /* 1 lane, 2.70 Ghz */
49         108000, /* 2 lane, 1.62 Ghz */
50         180000, /* 2 lane, 2.70 Ghz */
51         216000, /* 4 lane, 1.62 Ghz */
52         360000, /* 4 lane, 2.70 Ghz */
53 };
54
55 static const int num_dp_clocks = sizeof(dp_clocks) / sizeof(int);
56
57 /* common helper functions */
58 static int dp_lanes_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
59 {
60         int i;
61         u8 max_link_bw;
62         u8 max_lane_count;
63
64         if (!dpcd)
65                 return 0;
66
67         max_link_bw = dpcd[DP_MAX_LINK_RATE];
68         max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
69
70         switch (max_link_bw) {
71         case DP_LINK_BW_1_62:
72         default:
73                 for (i = 0; i < num_dp_clocks; i++) {
74                         if (i % 2)
75                                 continue;
76                         switch (max_lane_count) {
77                         case 1:
78                                 if (i > 1)
79                                         return 0;
80                                 break;
81                         case 2:
82                                 if (i > 3)
83                                         return 0;
84                                 break;
85                         case 4:
86                         default:
87                                 break;
88                         }
89                         if (dp_clocks[i] > mode_clock) {
90                                 if (i < 2)
91                                         return 1;
92                                 else if (i < 4)
93                                         return 2;
94                                 else
95                                         return 4;
96                         }
97                 }
98                 break;
99         case DP_LINK_BW_2_7:
100                 for (i = 0; i < num_dp_clocks; i++) {
101                         switch (max_lane_count) {
102                         case 1:
103                                 if (i > 1)
104                                         return 0;
105                                 break;
106                         case 2:
107                                 if (i > 3)
108                                         return 0;
109                                 break;
110                         case 4:
111                         default:
112                                 break;
113                         }
114                         if (dp_clocks[i] > mode_clock) {
115                                 if (i < 2)
116                                         return 1;
117                                 else if (i < 4)
118                                         return 2;
119                                 else
120                                         return 4;
121                         }
122                 }
123                 break;
124         }
125
126         return 0;
127 }
128
129 static int dp_link_clock_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
130 {
131         int i;
132         u8 max_link_bw;
133         u8 max_lane_count;
134
135         if (!dpcd)
136                 return 0;
137
138         max_link_bw = dpcd[DP_MAX_LINK_RATE];
139         max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
140
141         switch (max_link_bw) {
142         case DP_LINK_BW_1_62:
143         default:
144                 for (i = 0; i < num_dp_clocks; i++) {
145                         if (i % 2)
146                                 continue;
147                         switch (max_lane_count) {
148                         case 1:
149                                 if (i > 1)
150                                         return 0;
151                                 break;
152                         case 2:
153                                 if (i > 3)
154                                         return 0;
155                                 break;
156                         case 4:
157                         default:
158                                 break;
159                         }
160                         if (dp_clocks[i] > mode_clock)
161                                 return 162000;
162                 }
163                 break;
164         case DP_LINK_BW_2_7:
165                 for (i = 0; i < num_dp_clocks; i++) {
166                         switch (max_lane_count) {
167                         case 1:
168                                 if (i > 1)
169                                         return 0;
170                                 break;
171                         case 2:
172                                 if (i > 3)
173                                         return 0;
174                                 break;
175                         case 4:
176                         default:
177                                 break;
178                         }
179                         if (dp_clocks[i] > mode_clock)
180                                 return (i % 2) ? 270000 : 162000;
181                 }
182         }
183
184         return 0;
185 }
186
187 int dp_mode_valid(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
188 {
189         int lanes = dp_lanes_for_mode_clock(dpcd, mode_clock);
190         int bw = dp_lanes_for_mode_clock(dpcd, mode_clock);
191
192         if ((lanes == 0) || (bw == 0))
193                 return MODE_CLOCK_HIGH;
194
195         return MODE_OK;
196 }
197
198 static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
199 {
200         return link_status[r - DP_LANE0_1_STATUS];
201 }
202
203 static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
204                              int lane)
205 {
206         int i = DP_LANE0_1_STATUS + (lane >> 1);
207         int s = (lane & 1) * 4;
208         u8 l = dp_link_status(link_status, i);
209         return (l >> s) & 0xf;
210 }
211
212 static bool dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
213                                  int lane_count)
214 {
215         int lane;
216         u8 lane_status;
217
218         for (lane = 0; lane < lane_count; lane++) {
219                 lane_status = dp_get_lane_status(link_status, lane);
220                 if ((lane_status & DP_LANE_CR_DONE) == 0)
221                         return false;
222         }
223         return true;
224 }
225
226 static bool dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
227                              int lane_count)
228 {
229         u8 lane_align;
230         u8 lane_status;
231         int lane;
232
233         lane_align = dp_link_status(link_status,
234                                     DP_LANE_ALIGN_STATUS_UPDATED);
235         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
236                 return false;
237         for (lane = 0; lane < lane_count; lane++) {
238                 lane_status = dp_get_lane_status(link_status, lane);
239                 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
240                         return false;
241         }
242         return true;
243 }
244
245 static u8 dp_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
246                                         int lane)
247
248 {
249         int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
250         int s = ((lane & 1) ?
251                  DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
252                  DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
253         u8 l = dp_link_status(link_status, i);
254
255         return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
256 }
257
258 static u8 dp_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
259                                              int lane)
260 {
261         int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
262         int s = ((lane & 1) ?
263                  DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
264                  DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
265         u8 l = dp_link_status(link_status, i);
266
267         return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
268 }
269
270 /* XXX fix me -- chip specific */
271 #define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_1200
272 static u8 dp_pre_emphasis_max(u8 voltage_swing)
273 {
274         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
275         case DP_TRAIN_VOLTAGE_SWING_400:
276                 return DP_TRAIN_PRE_EMPHASIS_6;
277         case DP_TRAIN_VOLTAGE_SWING_600:
278                 return DP_TRAIN_PRE_EMPHASIS_6;
279         case DP_TRAIN_VOLTAGE_SWING_800:
280                 return DP_TRAIN_PRE_EMPHASIS_3_5;
281         case DP_TRAIN_VOLTAGE_SWING_1200:
282         default:
283                 return DP_TRAIN_PRE_EMPHASIS_0;
284         }
285 }
286
287 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
288                                 int lane_count,
289                                 u8 train_set[4])
290 {
291         u8 v = 0;
292         u8 p = 0;
293         int lane;
294
295         for (lane = 0; lane < lane_count; lane++) {
296                 u8 this_v = dp_get_adjust_request_voltage(link_status, lane);
297                 u8 this_p = dp_get_adjust_request_pre_emphasis(link_status, lane);
298
299                 DRM_DEBUG("requested signal parameters: lane %d voltage %s pre_emph %s\n",
300                           lane,
301                           voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
302                           pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
303
304                 if (this_v > v)
305                         v = this_v;
306                 if (this_p > p)
307                         p = this_p;
308         }
309
310         if (v >= DP_VOLTAGE_MAX)
311                 v = DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
312
313         if (p >= dp_pre_emphasis_max(v))
314                 p = dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
315
316         DRM_DEBUG("using signal parameters: voltage %s pre_emph %s\n",
317                   voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
318                   pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
319
320         for (lane = 0; lane < 4; lane++)
321                 train_set[lane] = v | p;
322 }
323
324
325 /* radeon aux chan functions */
326 bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
327                            int num_bytes, u8 *read_byte,
328                            u8 read_buf_len, u8 delay)
329 {
330         struct drm_device *dev = chan->dev;
331         struct radeon_device *rdev = dev->dev_private;
332         PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION args;
333         int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
334         unsigned char *base;
335         int retry_count = 0;
336
337         memset(&args, 0, sizeof(args));
338
339         base = (unsigned char *)rdev->mode_info.atom_context->scratch;
340
341 retry:
342         memcpy(base, req_bytes, num_bytes);
343
344         args.lpAuxRequest = 0;
345         args.lpDataOut = 16;
346         args.ucDataOutLen = 0;
347         args.ucChannelID = chan->rec.i2c_id;
348         args.ucDelay = delay / 10;
349
350         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
351
352         if (args.ucReplyStatus && !args.ucDataOutLen) {
353                 if (args.ucReplyStatus == 0x20 && retry_count++ < 10)
354                         goto retry;
355                 DRM_DEBUG("failed to get auxch %02x%02x %02x %02x 0x%02x %02x after %d retries\n",
356                           req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3],
357                           chan->rec.i2c_id, args.ucReplyStatus, retry_count);
358                 return false;
359         }
360
361         if (args.ucDataOutLen && read_byte && read_buf_len) {
362                 if (read_buf_len < args.ucDataOutLen) {
363                         DRM_ERROR("Buffer to small for return answer %d %d\n",
364                                   read_buf_len, args.ucDataOutLen);
365                         return false;
366                 }
367                 {
368                         int len = min(read_buf_len, args.ucDataOutLen);
369                         memcpy(read_byte, base + 16, len);
370                 }
371         }
372         return true;
373 }
374
375 bool radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, uint16_t address,
376                                 uint8_t send_bytes, uint8_t *send)
377 {
378         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
379         u8 msg[20];
380         u8 msg_len, dp_msg_len;
381         bool ret;
382
383         dp_msg_len = 4;
384         msg[0] = address;
385         msg[1] = address >> 8;
386         msg[2] = AUX_NATIVE_WRITE << 4;
387         dp_msg_len += send_bytes;
388         msg[3] = (dp_msg_len << 4) | (send_bytes - 1);
389
390         if (send_bytes > 16)
391                 return false;
392
393         memcpy(&msg[4], send, send_bytes);
394         msg_len = 4 + send_bytes;
395         ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, msg, msg_len, NULL, 0, 0);
396         return ret;
397 }
398
399 bool radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, uint16_t address,
400                                uint8_t delay, uint8_t expected_bytes,
401                                uint8_t *read_p)
402 {
403         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
404         u8 msg[20];
405         u8 msg_len, dp_msg_len;
406         bool ret = false;
407         msg_len = 4;
408         dp_msg_len = 4;
409         msg[0] = address;
410         msg[1] = address >> 8;
411         msg[2] = AUX_NATIVE_READ << 4;
412         msg[3] = (dp_msg_len) << 4;
413         msg[3] |= expected_bytes - 1;
414
415         ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, msg, msg_len, read_p, expected_bytes, delay);
416         return ret;
417 }
418
419 /* radeon dp functions */
420 static u8 radeon_dp_encoder_service(struct radeon_device *rdev, int action, int dp_clock,
421                                     uint8_t ucconfig, uint8_t lane_num)
422 {
423         DP_ENCODER_SERVICE_PARAMETERS args;
424         int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
425
426         memset(&args, 0, sizeof(args));
427         args.ucLinkClock = dp_clock / 10;
428         args.ucConfig = ucconfig;
429         args.ucAction = action;
430         args.ucLaneNum = lane_num;
431         args.ucStatus = 0;
432
433         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
434         return args.ucStatus;
435 }
436
437 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
438 {
439         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
440         struct drm_device *dev = radeon_connector->base.dev;
441         struct radeon_device *rdev = dev->dev_private;
442
443         return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
444                                          dig_connector->dp_i2c_bus->rec.i2c_id, 0);
445 }
446
447 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
448 {
449         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
450         u8 msg[25];
451         int ret;
452
453         ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, 0, 8, msg);
454         if (ret) {
455                 memcpy(dig_connector->dpcd, msg, 8);
456                 {
457                         int i;
458                         DRM_DEBUG("DPCD: ");
459                         for (i = 0; i < 8; i++)
460                                 DRM_DEBUG("%02x ", msg[i]);
461                         DRM_DEBUG("\n");
462                 }
463                 return true;
464         }
465         dig_connector->dpcd[0] = 0;
466         return false;
467 }
468
469 void radeon_dp_set_link_config(struct drm_connector *connector,
470                                struct drm_display_mode *mode)
471 {
472         struct radeon_connector *radeon_connector;
473         struct radeon_connector_atom_dig *dig_connector;
474
475         if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
476             (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
477                 return;
478
479         radeon_connector = to_radeon_connector(connector);
480         if (!radeon_connector->con_priv)
481                 return;
482         dig_connector = radeon_connector->con_priv;
483
484         dig_connector->dp_clock =
485                 dp_link_clock_for_mode_clock(dig_connector->dpcd, mode->clock);
486         dig_connector->dp_lane_count =
487                 dp_lanes_for_mode_clock(dig_connector->dpcd, mode->clock);
488 }
489
490 int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
491                                 struct drm_display_mode *mode)
492 {
493         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
494
495         return dp_mode_valid(dig_connector->dpcd, mode->clock);
496 }
497
498 static bool atom_dp_get_link_status(struct radeon_connector *radeon_connector,
499                                     u8 link_status[DP_LINK_STATUS_SIZE])
500 {
501         int ret;
502         ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, 100,
503                                         DP_LINK_STATUS_SIZE, link_status);
504         if (!ret) {
505                 DRM_ERROR("displayport link status failed\n");
506                 return false;
507         }
508
509         DRM_DEBUG("link status %02x %02x %02x %02x %02x %02x\n",
510                   link_status[0], link_status[1], link_status[2],
511                   link_status[3], link_status[4], link_status[5]);
512         return true;
513 }
514
515 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
516 {
517         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
518         u8 link_status[DP_LINK_STATUS_SIZE];
519
520         if (!atom_dp_get_link_status(radeon_connector, link_status))
521                 return false;
522         if (dp_channel_eq_ok(link_status, dig_connector->dp_lane_count))
523                 return false;
524         return true;
525 }
526
527 static void dp_set_power(struct radeon_connector *radeon_connector, u8 power_state)
528 {
529         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
530
531         if (dig_connector->dpcd[0] >= 0x11) {
532                 radeon_dp_aux_native_write(radeon_connector, DP_SET_POWER, 1,
533                                            &power_state);
534         }
535 }
536
537 static void dp_set_downspread(struct radeon_connector *radeon_connector, u8 downspread)
538 {
539         radeon_dp_aux_native_write(radeon_connector, DP_DOWNSPREAD_CTRL, 1,
540                                    &downspread);
541 }
542
543 static void dp_set_link_bw_lanes(struct radeon_connector *radeon_connector,
544                                  u8 link_configuration[DP_LINK_CONFIGURATION_SIZE])
545 {
546         radeon_dp_aux_native_write(radeon_connector, DP_LINK_BW_SET, 2,
547                                    link_configuration);
548 }
549
550 static void dp_update_dpvs_emph(struct radeon_connector *radeon_connector,
551                                 struct drm_encoder *encoder,
552                                 u8 train_set[4])
553 {
554         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
555         int i;
556
557         for (i = 0; i < dig_connector->dp_lane_count; i++)
558                 atombios_dig_transmitter_setup(encoder,
559                                                ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
560                                                i, train_set[i]);
561
562         radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_LANE0_SET,
563                                    dig_connector->dp_lane_count, train_set);
564 }
565
566 static void dp_set_training(struct radeon_connector *radeon_connector,
567                             u8 training)
568 {
569         radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_PATTERN_SET,
570                                    1, &training);
571 }
572
573 void dp_link_train(struct drm_encoder *encoder,
574                    struct drm_connector *connector)
575 {
576         struct drm_device *dev = encoder->dev;
577         struct radeon_device *rdev = dev->dev_private;
578         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
579         struct radeon_encoder_atom_dig *dig;
580         struct radeon_connector *radeon_connector;
581         struct radeon_connector_atom_dig *dig_connector;
582         int enc_id = 0;
583         bool clock_recovery, channel_eq;
584         u8 link_status[DP_LINK_STATUS_SIZE];
585         u8 link_configuration[DP_LINK_CONFIGURATION_SIZE];
586         u8 tries, voltage;
587         u8 train_set[4];
588         int i;
589
590         if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
591             (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
592                 return;
593
594         if (!radeon_encoder->enc_priv)
595                 return;
596         dig = radeon_encoder->enc_priv;
597
598         radeon_connector = to_radeon_connector(connector);
599         if (!radeon_connector->con_priv)
600                 return;
601         dig_connector = radeon_connector->con_priv;
602
603         if (dig->dig_encoder)
604                 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
605         else
606                 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
607         if (dig_connector->linkb)
608                 enc_id |= ATOM_DP_CONFIG_LINK_B;
609         else
610                 enc_id |= ATOM_DP_CONFIG_LINK_A;
611
612         memset(link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
613         if (dig_connector->dp_clock == 270000)
614                 link_configuration[0] = DP_LINK_BW_2_7;
615         else
616                 link_configuration[0] = DP_LINK_BW_1_62;
617         link_configuration[1] = dig_connector->dp_lane_count;
618         if (dig_connector->dpcd[0] >= 0x11)
619                 link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
620
621         /* power up the sink */
622         dp_set_power(radeon_connector, DP_SET_POWER_D0);
623         /* disable the training pattern on the sink */
624         dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
625         /* set link bw and lanes on the sink */
626         dp_set_link_bw_lanes(radeon_connector, link_configuration);
627         /* disable downspread on the sink */
628         dp_set_downspread(radeon_connector, 0);
629         /* start training on the source */
630         radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_START,
631                                   dig_connector->dp_clock, enc_id, 0);
632         /* set training pattern 1 on the source */
633         radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
634                                   dig_connector->dp_clock, enc_id, 0);
635
636         /* set initial vs/emph */
637         memset(train_set, 0, 4);
638         udelay(400);
639         /* set training pattern 1 on the sink */
640         dp_set_training(radeon_connector, DP_TRAINING_PATTERN_1);
641
642         dp_update_dpvs_emph(radeon_connector, encoder, train_set);
643
644         /* clock recovery loop */
645         clock_recovery = false;
646         tries = 0;
647         voltage = 0xff;
648         for (;;) {
649                 udelay(100);
650                 if (!atom_dp_get_link_status(radeon_connector, link_status))
651                         break;
652
653                 if (dp_clock_recovery_ok(link_status, dig_connector->dp_lane_count)) {
654                         clock_recovery = true;
655                         break;
656                 }
657
658                 for (i = 0; i < dig_connector->dp_lane_count; i++) {
659                         if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
660                                 break;
661                 }
662                 if (i == dig_connector->dp_lane_count) {
663                         DRM_ERROR("clock recovery reached max voltage\n");
664                         break;
665                 }
666
667                 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
668                         ++tries;
669                         if (tries == 5) {
670                                 DRM_ERROR("clock recovery tried 5 times\n");
671                                 break;
672                         }
673                 } else
674                         tries = 0;
675
676                 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
677
678                 /* Compute new train_set as requested by sink */
679                 dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set);
680                 dp_update_dpvs_emph(radeon_connector, encoder, train_set);
681         }
682         if (!clock_recovery)
683                 DRM_ERROR("clock recovery failed\n");
684         else
685                 DRM_DEBUG("clock recovery at voltage %d pre-emphasis %d\n",
686                           train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
687                           (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
688                           DP_TRAIN_PRE_EMPHASIS_SHIFT);
689
690
691         /* set training pattern 2 on the sink */
692         dp_set_training(radeon_connector, DP_TRAINING_PATTERN_2);
693         /* set training pattern 2 on the source */
694         radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
695                                   dig_connector->dp_clock, enc_id, 1);
696
697         /* channel equalization loop */
698         tries = 0;
699         channel_eq = false;
700         for (;;) {
701                 udelay(400);
702                 if (!atom_dp_get_link_status(radeon_connector, link_status))
703                         break;
704
705                 if (dp_channel_eq_ok(link_status, dig_connector->dp_lane_count)) {
706                         channel_eq = true;
707                         break;
708                 }
709
710                 /* Try 5 times */
711                 if (tries > 5) {
712                         DRM_ERROR("channel eq failed: 5 tries\n");
713                         break;
714                 }
715
716                 /* Compute new train_set as requested by sink */
717                 dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set);
718                 dp_update_dpvs_emph(radeon_connector, encoder, train_set);
719
720                 tries++;
721         }
722
723         if (!channel_eq)
724                 DRM_ERROR("channel eq failed\n");
725         else
726                 DRM_DEBUG("channel eq at voltage %d pre-emphasis %d\n",
727                           train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
728                           (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
729                           >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
730
731         /* disable the training pattern on the sink */
732         dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
733
734         radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
735                                   dig_connector->dp_clock, enc_id, 0);
736 }
737
738 int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
739                          uint8_t write_byte, uint8_t *read_byte)
740 {
741         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
742         struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
743         int ret = 0;
744         uint16_t address = algo_data->address;
745         uint8_t msg[5];
746         uint8_t reply[2];
747         int msg_len, dp_msg_len;
748         int reply_bytes;
749
750         /* Set up the command byte */
751         if (mode & MODE_I2C_READ)
752                 msg[2] = AUX_I2C_READ << 4;
753         else
754                 msg[2] = AUX_I2C_WRITE << 4;
755
756         if (!(mode & MODE_I2C_STOP))
757                 msg[2] |= AUX_I2C_MOT << 4;
758
759         msg[0] = address;
760         msg[1] = address >> 8;
761
762         reply_bytes = 1;
763
764         msg_len = 4;
765         dp_msg_len = 3;
766         switch (mode) {
767         case MODE_I2C_WRITE:
768                 msg[4] = write_byte;
769                 msg_len++;
770                 dp_msg_len += 2;
771                 break;
772         case MODE_I2C_READ:
773                 dp_msg_len += 1;
774                 break;
775         default:
776                 break;
777         }
778
779         msg[3] = (dp_msg_len) << 4;
780         ret = radeon_process_aux_ch(auxch, msg, msg_len, reply, reply_bytes, 0);
781
782         if (ret) {
783                 if (read_byte)
784                         *read_byte = reply[0];
785                 return reply_bytes;
786         }
787         return -EREMOTEIO;
788 }
789