drm/radeon/kms: update new pll algo
[sfrench/cifs-2.6.git] / drivers / gpu / drm / radeon / atombios_dp.c
1 /*
2  * Copyright 2007-8 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include "atom-bits.h"
32 #include "drm_dp_helper.h"
33
34 /* move these to drm_dp_helper.c/h */
35 #define DP_LINK_CONFIGURATION_SIZE 9
36 #define DP_LINK_STATUS_SIZE        6
37 #define DP_DPCD_SIZE               8
38
39 static char *voltage_names[] = {
40         "0.4V", "0.6V", "0.8V", "1.2V"
41 };
42 static char *pre_emph_names[] = {
43         "0dB", "3.5dB", "6dB", "9.5dB"
44 };
45
46 static const int dp_clocks[] = {
47         54000,  /* 1 lane, 1.62 Ghz */
48         90000,  /* 1 lane, 2.70 Ghz */
49         108000, /* 2 lane, 1.62 Ghz */
50         180000, /* 2 lane, 2.70 Ghz */
51         216000, /* 4 lane, 1.62 Ghz */
52         360000, /* 4 lane, 2.70 Ghz */
53 };
54
55 static const int num_dp_clocks = sizeof(dp_clocks) / sizeof(int);
56
57 /* common helper functions */
58 static int dp_lanes_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
59 {
60         int i;
61         u8 max_link_bw;
62         u8 max_lane_count;
63
64         if (!dpcd)
65                 return 0;
66
67         max_link_bw = dpcd[DP_MAX_LINK_RATE];
68         max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
69
70         switch (max_link_bw) {
71         case DP_LINK_BW_1_62:
72         default:
73                 for (i = 0; i < num_dp_clocks; i++) {
74                         if (i % 2)
75                                 continue;
76                         switch (max_lane_count) {
77                         case 1:
78                                 if (i > 1)
79                                         return 0;
80                                 break;
81                         case 2:
82                                 if (i > 3)
83                                         return 0;
84                                 break;
85                         case 4:
86                         default:
87                                 break;
88                         }
89                         if (dp_clocks[i] > mode_clock) {
90                                 if (i < 2)
91                                         return 1;
92                                 else if (i < 4)
93                                         return 2;
94                                 else
95                                         return 4;
96                         }
97                 }
98                 break;
99         case DP_LINK_BW_2_7:
100                 for (i = 0; i < num_dp_clocks; i++) {
101                         switch (max_lane_count) {
102                         case 1:
103                                 if (i > 1)
104                                         return 0;
105                                 break;
106                         case 2:
107                                 if (i > 3)
108                                         return 0;
109                                 break;
110                         case 4:
111                         default:
112                                 break;
113                         }
114                         if (dp_clocks[i] > mode_clock) {
115                                 if (i < 2)
116                                         return 1;
117                                 else if (i < 4)
118                                         return 2;
119                                 else
120                                         return 4;
121                         }
122                 }
123                 break;
124         }
125
126         return 0;
127 }
128
129 static int dp_link_clock_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
130 {
131         int i;
132         u8 max_link_bw;
133         u8 max_lane_count;
134
135         if (!dpcd)
136                 return 0;
137
138         max_link_bw = dpcd[DP_MAX_LINK_RATE];
139         max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
140
141         switch (max_link_bw) {
142         case DP_LINK_BW_1_62:
143         default:
144                 for (i = 0; i < num_dp_clocks; i++) {
145                         if (i % 2)
146                                 continue;
147                         switch (max_lane_count) {
148                         case 1:
149                                 if (i > 1)
150                                         return 0;
151                                 break;
152                         case 2:
153                                 if (i > 3)
154                                         return 0;
155                                 break;
156                         case 4:
157                         default:
158                                 break;
159                         }
160                         if (dp_clocks[i] > mode_clock)
161                                 return 162000;
162                 }
163                 break;
164         case DP_LINK_BW_2_7:
165                 for (i = 0; i < num_dp_clocks; i++) {
166                         switch (max_lane_count) {
167                         case 1:
168                                 if (i > 1)
169                                         return 0;
170                                 break;
171                         case 2:
172                                 if (i > 3)
173                                         return 0;
174                                 break;
175                         case 4:
176                         default:
177                                 break;
178                         }
179                         if (dp_clocks[i] > mode_clock)
180                                 return (i % 2) ? 270000 : 162000;
181                 }
182         }
183
184         return 0;
185 }
186
187 int dp_mode_valid(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
188 {
189         int lanes = dp_lanes_for_mode_clock(dpcd, mode_clock);
190         int bw = dp_lanes_for_mode_clock(dpcd, mode_clock);
191
192         if ((lanes == 0) || (bw == 0))
193                 return MODE_CLOCK_HIGH;
194
195         return MODE_OK;
196 }
197
198 static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
199 {
200         return link_status[r - DP_LANE0_1_STATUS];
201 }
202
203 static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
204                              int lane)
205 {
206         int i = DP_LANE0_1_STATUS + (lane >> 1);
207         int s = (lane & 1) * 4;
208         u8 l = dp_link_status(link_status, i);
209         return (l >> s) & 0xf;
210 }
211
212 static bool dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
213                                  int lane_count)
214 {
215         int lane;
216         u8 lane_status;
217
218         for (lane = 0; lane < lane_count; lane++) {
219                 lane_status = dp_get_lane_status(link_status, lane);
220                 if ((lane_status & DP_LANE_CR_DONE) == 0)
221                         return false;
222         }
223         return true;
224 }
225
226 static bool dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
227                              int lane_count)
228 {
229         u8 lane_align;
230         u8 lane_status;
231         int lane;
232
233         lane_align = dp_link_status(link_status,
234                                     DP_LANE_ALIGN_STATUS_UPDATED);
235         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
236                 return false;
237         for (lane = 0; lane < lane_count; lane++) {
238                 lane_status = dp_get_lane_status(link_status, lane);
239                 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
240                         return false;
241         }
242         return true;
243 }
244
245 static u8 dp_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
246                                         int lane)
247
248 {
249         int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
250         int s = ((lane & 1) ?
251                  DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
252                  DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
253         u8 l = dp_link_status(link_status, i);
254
255         return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
256 }
257
258 static u8 dp_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
259                                              int lane)
260 {
261         int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
262         int s = ((lane & 1) ?
263                  DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
264                  DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
265         u8 l = dp_link_status(link_status, i);
266
267         return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
268 }
269
270 /* XXX fix me -- chip specific */
271 #define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_1200
272 static u8 dp_pre_emphasis_max(u8 voltage_swing)
273 {
274         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
275         case DP_TRAIN_VOLTAGE_SWING_400:
276                 return DP_TRAIN_PRE_EMPHASIS_6;
277         case DP_TRAIN_VOLTAGE_SWING_600:
278                 return DP_TRAIN_PRE_EMPHASIS_6;
279         case DP_TRAIN_VOLTAGE_SWING_800:
280                 return DP_TRAIN_PRE_EMPHASIS_3_5;
281         case DP_TRAIN_VOLTAGE_SWING_1200:
282         default:
283                 return DP_TRAIN_PRE_EMPHASIS_0;
284         }
285 }
286
287 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
288                                 int lane_count,
289                                 u8 train_set[4])
290 {
291         u8 v = 0;
292         u8 p = 0;
293         int lane;
294
295         for (lane = 0; lane < lane_count; lane++) {
296                 u8 this_v = dp_get_adjust_request_voltage(link_status, lane);
297                 u8 this_p = dp_get_adjust_request_pre_emphasis(link_status, lane);
298
299                 DRM_DEBUG("requested signal parameters: lane %d voltage %s pre_emph %s\n",
300                           lane,
301                           voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
302                           pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
303
304                 if (this_v > v)
305                         v = this_v;
306                 if (this_p > p)
307                         p = this_p;
308         }
309
310         if (v >= DP_VOLTAGE_MAX)
311                 v = DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
312
313         if (p >= dp_pre_emphasis_max(v))
314                 p = dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
315
316         DRM_DEBUG("using signal parameters: voltage %s pre_emph %s\n",
317                   voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
318                   pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
319
320         for (lane = 0; lane < 4; lane++)
321                 train_set[lane] = v | p;
322 }
323
324 union aux_channel_transaction {
325         PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
326         PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
327 };
328
329 /* radeon aux chan functions */
330 bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
331                            int num_bytes, u8 *read_byte,
332                            u8 read_buf_len, u8 delay)
333 {
334         struct drm_device *dev = chan->dev;
335         struct radeon_device *rdev = dev->dev_private;
336         union aux_channel_transaction args;
337         int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
338         unsigned char *base;
339
340         memset(&args, 0, sizeof(args));
341
342         base = (unsigned char *)rdev->mode_info.atom_context->scratch;
343
344         memcpy(base, req_bytes, num_bytes);
345
346         args.v1.lpAuxRequest = 0;
347         args.v1.lpDataOut = 16;
348         args.v1.ucDataOutLen = 0;
349         args.v1.ucChannelID = chan->rec.i2c_id;
350         args.v1.ucDelay = delay / 10;
351         if (ASIC_IS_DCE4(rdev))
352                 args.v2.ucHPD_ID = chan->rec.hpd_id;
353
354         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
355
356         if (args.v1.ucReplyStatus) {
357                 DRM_DEBUG("failed to get auxch %02x%02x %02x %02x 0x%02x %02x\n",
358                           req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3],
359                           chan->rec.i2c_id, args.v1.ucReplyStatus);
360                 return false;
361         }
362
363         if (args.v1.ucDataOutLen && read_byte && read_buf_len) {
364                 if (read_buf_len < args.v1.ucDataOutLen) {
365                         DRM_ERROR("Buffer to small for return answer %d %d\n",
366                                   read_buf_len, args.v1.ucDataOutLen);
367                         return false;
368                 }
369                 {
370                         int len = min(read_buf_len, args.v1.ucDataOutLen);
371                         memcpy(read_byte, base + 16, len);
372                 }
373         }
374         return true;
375 }
376
377 bool radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, uint16_t address,
378                                 uint8_t send_bytes, uint8_t *send)
379 {
380         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
381         u8 msg[20];
382         u8 msg_len, dp_msg_len;
383         bool ret;
384
385         dp_msg_len = 4;
386         msg[0] = address;
387         msg[1] = address >> 8;
388         msg[2] = AUX_NATIVE_WRITE << 4;
389         dp_msg_len += send_bytes;
390         msg[3] = (dp_msg_len << 4) | (send_bytes - 1);
391
392         if (send_bytes > 16)
393                 return false;
394
395         memcpy(&msg[4], send, send_bytes);
396         msg_len = 4 + send_bytes;
397         ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, msg, msg_len, NULL, 0, 0);
398         return ret;
399 }
400
401 bool radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, uint16_t address,
402                                uint8_t delay, uint8_t expected_bytes,
403                                uint8_t *read_p)
404 {
405         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
406         u8 msg[20];
407         u8 msg_len, dp_msg_len;
408         bool ret = false;
409         msg_len = 4;
410         dp_msg_len = 4;
411         msg[0] = address;
412         msg[1] = address >> 8;
413         msg[2] = AUX_NATIVE_READ << 4;
414         msg[3] = (dp_msg_len) << 4;
415         msg[3] |= expected_bytes - 1;
416
417         ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, msg, msg_len, read_p, expected_bytes, delay);
418         return ret;
419 }
420
421 /* radeon dp functions */
422 static u8 radeon_dp_encoder_service(struct radeon_device *rdev, int action, int dp_clock,
423                                     uint8_t ucconfig, uint8_t lane_num)
424 {
425         DP_ENCODER_SERVICE_PARAMETERS args;
426         int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
427
428         memset(&args, 0, sizeof(args));
429         args.ucLinkClock = dp_clock / 10;
430         args.ucConfig = ucconfig;
431         args.ucAction = action;
432         args.ucLaneNum = lane_num;
433         args.ucStatus = 0;
434
435         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
436         return args.ucStatus;
437 }
438
439 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
440 {
441         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
442         struct drm_device *dev = radeon_connector->base.dev;
443         struct radeon_device *rdev = dev->dev_private;
444
445         return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
446                                          dig_connector->dp_i2c_bus->rec.i2c_id, 0);
447 }
448
449 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
450 {
451         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
452         u8 msg[25];
453         int ret;
454
455         ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, 0, 8, msg);
456         if (ret) {
457                 memcpy(dig_connector->dpcd, msg, 8);
458                 {
459                         int i;
460                         DRM_DEBUG("DPCD: ");
461                         for (i = 0; i < 8; i++)
462                                 DRM_DEBUG("%02x ", msg[i]);
463                         DRM_DEBUG("\n");
464                 }
465                 return true;
466         }
467         dig_connector->dpcd[0] = 0;
468         return false;
469 }
470
471 void radeon_dp_set_link_config(struct drm_connector *connector,
472                                struct drm_display_mode *mode)
473 {
474         struct radeon_connector *radeon_connector;
475         struct radeon_connector_atom_dig *dig_connector;
476
477         if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
478             (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
479                 return;
480
481         radeon_connector = to_radeon_connector(connector);
482         if (!radeon_connector->con_priv)
483                 return;
484         dig_connector = radeon_connector->con_priv;
485
486         dig_connector->dp_clock =
487                 dp_link_clock_for_mode_clock(dig_connector->dpcd, mode->clock);
488         dig_connector->dp_lane_count =
489                 dp_lanes_for_mode_clock(dig_connector->dpcd, mode->clock);
490 }
491
492 int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
493                                 struct drm_display_mode *mode)
494 {
495         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
496
497         return dp_mode_valid(dig_connector->dpcd, mode->clock);
498 }
499
500 static bool atom_dp_get_link_status(struct radeon_connector *radeon_connector,
501                                     u8 link_status[DP_LINK_STATUS_SIZE])
502 {
503         int ret;
504         ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, 100,
505                                         DP_LINK_STATUS_SIZE, link_status);
506         if (!ret) {
507                 DRM_ERROR("displayport link status failed\n");
508                 return false;
509         }
510
511         DRM_DEBUG("link status %02x %02x %02x %02x %02x %02x\n",
512                   link_status[0], link_status[1], link_status[2],
513                   link_status[3], link_status[4], link_status[5]);
514         return true;
515 }
516
517 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
518 {
519         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
520         u8 link_status[DP_LINK_STATUS_SIZE];
521
522         if (!atom_dp_get_link_status(radeon_connector, link_status))
523                 return false;
524         if (dp_channel_eq_ok(link_status, dig_connector->dp_lane_count))
525                 return false;
526         return true;
527 }
528
529 static void dp_set_power(struct radeon_connector *radeon_connector, u8 power_state)
530 {
531         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
532
533         if (dig_connector->dpcd[0] >= 0x11) {
534                 radeon_dp_aux_native_write(radeon_connector, DP_SET_POWER, 1,
535                                            &power_state);
536         }
537 }
538
539 static void dp_set_downspread(struct radeon_connector *radeon_connector, u8 downspread)
540 {
541         radeon_dp_aux_native_write(radeon_connector, DP_DOWNSPREAD_CTRL, 1,
542                                    &downspread);
543 }
544
545 static void dp_set_link_bw_lanes(struct radeon_connector *radeon_connector,
546                                  u8 link_configuration[DP_LINK_CONFIGURATION_SIZE])
547 {
548         radeon_dp_aux_native_write(radeon_connector, DP_LINK_BW_SET, 2,
549                                    link_configuration);
550 }
551
552 static void dp_update_dpvs_emph(struct radeon_connector *radeon_connector,
553                                 struct drm_encoder *encoder,
554                                 u8 train_set[4])
555 {
556         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
557         int i;
558
559         for (i = 0; i < dig_connector->dp_lane_count; i++)
560                 atombios_dig_transmitter_setup(encoder,
561                                                ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
562                                                i, train_set[i]);
563
564         radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_LANE0_SET,
565                                    dig_connector->dp_lane_count, train_set);
566 }
567
568 static void dp_set_training(struct radeon_connector *radeon_connector,
569                             u8 training)
570 {
571         radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_PATTERN_SET,
572                                    1, &training);
573 }
574
575 void dp_link_train(struct drm_encoder *encoder,
576                    struct drm_connector *connector)
577 {
578         struct drm_device *dev = encoder->dev;
579         struct radeon_device *rdev = dev->dev_private;
580         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
581         struct radeon_encoder_atom_dig *dig;
582         struct radeon_connector *radeon_connector;
583         struct radeon_connector_atom_dig *dig_connector;
584         int enc_id = 0;
585         bool clock_recovery, channel_eq;
586         u8 link_status[DP_LINK_STATUS_SIZE];
587         u8 link_configuration[DP_LINK_CONFIGURATION_SIZE];
588         u8 tries, voltage;
589         u8 train_set[4];
590         int i;
591
592         if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
593             (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
594                 return;
595
596         if (!radeon_encoder->enc_priv)
597                 return;
598         dig = radeon_encoder->enc_priv;
599
600         radeon_connector = to_radeon_connector(connector);
601         if (!radeon_connector->con_priv)
602                 return;
603         dig_connector = radeon_connector->con_priv;
604
605         if (dig->dig_encoder)
606                 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
607         else
608                 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
609         if (dig_connector->linkb)
610                 enc_id |= ATOM_DP_CONFIG_LINK_B;
611         else
612                 enc_id |= ATOM_DP_CONFIG_LINK_A;
613
614         memset(link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
615         if (dig_connector->dp_clock == 270000)
616                 link_configuration[0] = DP_LINK_BW_2_7;
617         else
618                 link_configuration[0] = DP_LINK_BW_1_62;
619         link_configuration[1] = dig_connector->dp_lane_count;
620         if (dig_connector->dpcd[0] >= 0x11)
621                 link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
622
623         /* power up the sink */
624         dp_set_power(radeon_connector, DP_SET_POWER_D0);
625         /* disable the training pattern on the sink */
626         dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
627         /* set link bw and lanes on the sink */
628         dp_set_link_bw_lanes(radeon_connector, link_configuration);
629         /* disable downspread on the sink */
630         dp_set_downspread(radeon_connector, 0);
631         if (ASIC_IS_DCE4(rdev)) {
632                 /* start training on the source */
633                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_START);
634                 /* set training pattern 1 on the source */
635                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1);
636         } else {
637                 /* start training on the source */
638                 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_START,
639                                           dig_connector->dp_clock, enc_id, 0);
640                 /* set training pattern 1 on the source */
641                 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
642                                           dig_connector->dp_clock, enc_id, 0);
643         }
644
645         /* set initial vs/emph */
646         memset(train_set, 0, 4);
647         udelay(400);
648         /* set training pattern 1 on the sink */
649         dp_set_training(radeon_connector, DP_TRAINING_PATTERN_1);
650
651         dp_update_dpvs_emph(radeon_connector, encoder, train_set);
652
653         /* clock recovery loop */
654         clock_recovery = false;
655         tries = 0;
656         voltage = 0xff;
657         for (;;) {
658                 udelay(100);
659                 if (!atom_dp_get_link_status(radeon_connector, link_status))
660                         break;
661
662                 if (dp_clock_recovery_ok(link_status, dig_connector->dp_lane_count)) {
663                         clock_recovery = true;
664                         break;
665                 }
666
667                 for (i = 0; i < dig_connector->dp_lane_count; i++) {
668                         if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
669                                 break;
670                 }
671                 if (i == dig_connector->dp_lane_count) {
672                         DRM_ERROR("clock recovery reached max voltage\n");
673                         break;
674                 }
675
676                 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
677                         ++tries;
678                         if (tries == 5) {
679                                 DRM_ERROR("clock recovery tried 5 times\n");
680                                 break;
681                         }
682                 } else
683                         tries = 0;
684
685                 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
686
687                 /* Compute new train_set as requested by sink */
688                 dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set);
689                 dp_update_dpvs_emph(radeon_connector, encoder, train_set);
690         }
691         if (!clock_recovery)
692                 DRM_ERROR("clock recovery failed\n");
693         else
694                 DRM_DEBUG("clock recovery at voltage %d pre-emphasis %d\n",
695                           train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
696                           (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
697                           DP_TRAIN_PRE_EMPHASIS_SHIFT);
698
699
700         /* set training pattern 2 on the sink */
701         dp_set_training(radeon_connector, DP_TRAINING_PATTERN_2);
702         /* set training pattern 2 on the source */
703         if (ASIC_IS_DCE4(rdev))
704                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2);
705         else
706                 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
707                                           dig_connector->dp_clock, enc_id, 1);
708
709         /* channel equalization loop */
710         tries = 0;
711         channel_eq = false;
712         for (;;) {
713                 udelay(400);
714                 if (!atom_dp_get_link_status(radeon_connector, link_status))
715                         break;
716
717                 if (dp_channel_eq_ok(link_status, dig_connector->dp_lane_count)) {
718                         channel_eq = true;
719                         break;
720                 }
721
722                 /* Try 5 times */
723                 if (tries > 5) {
724                         DRM_ERROR("channel eq failed: 5 tries\n");
725                         break;
726                 }
727
728                 /* Compute new train_set as requested by sink */
729                 dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set);
730                 dp_update_dpvs_emph(radeon_connector, encoder, train_set);
731
732                 tries++;
733         }
734
735         if (!channel_eq)
736                 DRM_ERROR("channel eq failed\n");
737         else
738                 DRM_DEBUG("channel eq at voltage %d pre-emphasis %d\n",
739                           train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
740                           (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
741                           >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
742
743         /* disable the training pattern on the sink */
744         if (ASIC_IS_DCE4(rdev))
745                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE);
746         else
747                 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
748                                           dig_connector->dp_clock, enc_id, 0);
749
750         radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
751                                   dig_connector->dp_clock, enc_id, 0);
752 }
753
754 int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
755                          uint8_t write_byte, uint8_t *read_byte)
756 {
757         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
758         struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
759         int ret = 0;
760         uint16_t address = algo_data->address;
761         uint8_t msg[5];
762         uint8_t reply[2];
763         int msg_len, dp_msg_len;
764         int reply_bytes;
765
766         /* Set up the command byte */
767         if (mode & MODE_I2C_READ)
768                 msg[2] = AUX_I2C_READ << 4;
769         else
770                 msg[2] = AUX_I2C_WRITE << 4;
771
772         if (!(mode & MODE_I2C_STOP))
773                 msg[2] |= AUX_I2C_MOT << 4;
774
775         msg[0] = address;
776         msg[1] = address >> 8;
777
778         reply_bytes = 1;
779
780         msg_len = 4;
781         dp_msg_len = 3;
782         switch (mode) {
783         case MODE_I2C_WRITE:
784                 msg[4] = write_byte;
785                 msg_len++;
786                 dp_msg_len += 2;
787                 break;
788         case MODE_I2C_READ:
789                 dp_msg_len += 1;
790                 break;
791         default:
792                 break;
793         }
794
795         msg[3] = (dp_msg_len) << 4;
796         ret = radeon_process_aux_ch(auxch, msg, msg_len, reply, reply_bytes, 0);
797
798         if (ret) {
799                 if (read_byte)
800                         *read_byte = reply[0];
801                 return reply_bytes;
802         }
803         return -EREMOTEIO;
804 }
805