2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
32 #include "drm_dp_helper.h"
34 /* move these to drm_dp_helper.c/h */
35 #define DP_LINK_CONFIGURATION_SIZE 9
36 #define DP_LINK_STATUS_SIZE 6
37 #define DP_DPCD_SIZE 8
39 static char *voltage_names[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
42 static char *pre_emph_names[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
46 static const int dp_clocks[] = {
47 54000, /* 1 lane, 1.62 Ghz */
48 90000, /* 1 lane, 2.70 Ghz */
49 108000, /* 2 lane, 1.62 Ghz */
50 180000, /* 2 lane, 2.70 Ghz */
51 216000, /* 4 lane, 1.62 Ghz */
52 360000, /* 4 lane, 2.70 Ghz */
55 static const int num_dp_clocks = sizeof(dp_clocks) / sizeof(int);
57 /* common helper functions */
58 static int dp_lanes_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
67 max_link_bw = dpcd[DP_MAX_LINK_RATE];
68 max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
70 switch (max_link_bw) {
73 for (i = 0; i < num_dp_clocks; i++) {
76 switch (max_lane_count) {
89 if (dp_clocks[i] > mode_clock) {
100 for (i = 0; i < num_dp_clocks; i++) {
101 switch (max_lane_count) {
114 if (dp_clocks[i] > mode_clock) {
129 static int dp_link_clock_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
138 max_link_bw = dpcd[DP_MAX_LINK_RATE];
139 max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
141 switch (max_link_bw) {
142 case DP_LINK_BW_1_62:
144 for (i = 0; i < num_dp_clocks; i++) {
147 switch (max_lane_count) {
160 if (dp_clocks[i] > mode_clock)
165 for (i = 0; i < num_dp_clocks; i++) {
166 switch (max_lane_count) {
179 if (dp_clocks[i] > mode_clock)
180 return (i % 2) ? 270000 : 162000;
187 int dp_mode_valid(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
189 int lanes = dp_lanes_for_mode_clock(dpcd, mode_clock);
190 int bw = dp_lanes_for_mode_clock(dpcd, mode_clock);
192 if ((lanes == 0) || (bw == 0))
193 return MODE_CLOCK_HIGH;
198 static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
200 return link_status[r - DP_LANE0_1_STATUS];
203 static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
206 int i = DP_LANE0_1_STATUS + (lane >> 1);
207 int s = (lane & 1) * 4;
208 u8 l = dp_link_status(link_status, i);
209 return (l >> s) & 0xf;
212 static bool dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
218 for (lane = 0; lane < lane_count; lane++) {
219 lane_status = dp_get_lane_status(link_status, lane);
220 if ((lane_status & DP_LANE_CR_DONE) == 0)
226 static bool dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
233 lane_align = dp_link_status(link_status,
234 DP_LANE_ALIGN_STATUS_UPDATED);
235 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
237 for (lane = 0; lane < lane_count; lane++) {
238 lane_status = dp_get_lane_status(link_status, lane);
239 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
245 static u8 dp_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
249 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
250 int s = ((lane & 1) ?
251 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
252 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
253 u8 l = dp_link_status(link_status, i);
255 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
258 static u8 dp_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
261 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
262 int s = ((lane & 1) ?
263 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
264 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
265 u8 l = dp_link_status(link_status, i);
267 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
270 /* XXX fix me -- chip specific */
271 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
272 static u8 dp_pre_emphasis_max(u8 voltage_swing)
274 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
275 case DP_TRAIN_VOLTAGE_SWING_400:
276 return DP_TRAIN_PRE_EMPHASIS_6;
277 case DP_TRAIN_VOLTAGE_SWING_600:
278 return DP_TRAIN_PRE_EMPHASIS_6;
279 case DP_TRAIN_VOLTAGE_SWING_800:
280 return DP_TRAIN_PRE_EMPHASIS_3_5;
281 case DP_TRAIN_VOLTAGE_SWING_1200:
283 return DP_TRAIN_PRE_EMPHASIS_0;
287 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
295 for (lane = 0; lane < lane_count; lane++) {
296 u8 this_v = dp_get_adjust_request_voltage(link_status, lane);
297 u8 this_p = dp_get_adjust_request_pre_emphasis(link_status, lane);
299 DRM_DEBUG("requested signal parameters: lane %d voltage %s pre_emph %s\n",
301 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
302 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
310 if (v >= DP_VOLTAGE_MAX)
311 v = DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
313 if (p >= dp_pre_emphasis_max(v))
314 p = dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
316 DRM_DEBUG("using signal parameters: voltage %s pre_emph %s\n",
317 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
318 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
320 for (lane = 0; lane < 4; lane++)
321 train_set[lane] = v | p;
324 union aux_channel_transaction {
325 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
326 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
329 /* radeon aux chan functions */
330 bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
331 int num_bytes, u8 *read_byte,
332 u8 read_buf_len, u8 delay)
334 struct drm_device *dev = chan->dev;
335 struct radeon_device *rdev = dev->dev_private;
336 union aux_channel_transaction args;
337 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
340 memset(&args, 0, sizeof(args));
342 base = (unsigned char *)rdev->mode_info.atom_context->scratch;
344 memcpy(base, req_bytes, num_bytes);
346 args.v1.lpAuxRequest = 0;
347 args.v1.lpDataOut = 16;
348 args.v1.ucDataOutLen = 0;
349 args.v1.ucChannelID = chan->rec.i2c_id;
350 args.v1.ucDelay = delay / 10;
351 if (ASIC_IS_DCE4(rdev))
352 args.v2.ucHPD_ID = chan->rec.hpd_id;
354 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
356 if (args.v1.ucReplyStatus) {
357 DRM_DEBUG("failed to get auxch %02x%02x %02x %02x 0x%02x %02x\n",
358 req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3],
359 chan->rec.i2c_id, args.v1.ucReplyStatus);
363 if (args.v1.ucDataOutLen && read_byte && read_buf_len) {
364 if (read_buf_len < args.v1.ucDataOutLen) {
365 DRM_ERROR("Buffer to small for return answer %d %d\n",
366 read_buf_len, args.v1.ucDataOutLen);
370 int len = min(read_buf_len, args.v1.ucDataOutLen);
371 memcpy(read_byte, base + 16, len);
377 bool radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, uint16_t address,
378 uint8_t send_bytes, uint8_t *send)
380 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
382 u8 msg_len, dp_msg_len;
387 msg[1] = address >> 8;
388 msg[2] = AUX_NATIVE_WRITE << 4;
389 dp_msg_len += send_bytes;
390 msg[3] = (dp_msg_len << 4) | (send_bytes - 1);
395 memcpy(&msg[4], send, send_bytes);
396 msg_len = 4 + send_bytes;
397 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, msg, msg_len, NULL, 0, 0);
401 bool radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, uint16_t address,
402 uint8_t delay, uint8_t expected_bytes,
405 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
407 u8 msg_len, dp_msg_len;
412 msg[1] = address >> 8;
413 msg[2] = AUX_NATIVE_READ << 4;
414 msg[3] = (dp_msg_len) << 4;
415 msg[3] |= expected_bytes - 1;
417 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, msg, msg_len, read_p, expected_bytes, delay);
421 /* radeon dp functions */
422 static u8 radeon_dp_encoder_service(struct radeon_device *rdev, int action, int dp_clock,
423 uint8_t ucconfig, uint8_t lane_num)
425 DP_ENCODER_SERVICE_PARAMETERS args;
426 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
428 memset(&args, 0, sizeof(args));
429 args.ucLinkClock = dp_clock / 10;
430 args.ucConfig = ucconfig;
431 args.ucAction = action;
432 args.ucLaneNum = lane_num;
435 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
436 return args.ucStatus;
439 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
441 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
442 struct drm_device *dev = radeon_connector->base.dev;
443 struct radeon_device *rdev = dev->dev_private;
445 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
446 dig_connector->dp_i2c_bus->rec.i2c_id, 0);
449 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
451 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
455 ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, 0, 8, msg);
457 memcpy(dig_connector->dpcd, msg, 8);
461 for (i = 0; i < 8; i++)
462 DRM_DEBUG("%02x ", msg[i]);
467 dig_connector->dpcd[0] = 0;
471 void radeon_dp_set_link_config(struct drm_connector *connector,
472 struct drm_display_mode *mode)
474 struct radeon_connector *radeon_connector;
475 struct radeon_connector_atom_dig *dig_connector;
477 if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
478 (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
481 radeon_connector = to_radeon_connector(connector);
482 if (!radeon_connector->con_priv)
484 dig_connector = radeon_connector->con_priv;
486 dig_connector->dp_clock =
487 dp_link_clock_for_mode_clock(dig_connector->dpcd, mode->clock);
488 dig_connector->dp_lane_count =
489 dp_lanes_for_mode_clock(dig_connector->dpcd, mode->clock);
492 int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
493 struct drm_display_mode *mode)
495 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
497 return dp_mode_valid(dig_connector->dpcd, mode->clock);
500 static bool atom_dp_get_link_status(struct radeon_connector *radeon_connector,
501 u8 link_status[DP_LINK_STATUS_SIZE])
504 ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, 100,
505 DP_LINK_STATUS_SIZE, link_status);
507 DRM_ERROR("displayport link status failed\n");
511 DRM_DEBUG("link status %02x %02x %02x %02x %02x %02x\n",
512 link_status[0], link_status[1], link_status[2],
513 link_status[3], link_status[4], link_status[5]);
517 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
519 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
520 u8 link_status[DP_LINK_STATUS_SIZE];
522 if (!atom_dp_get_link_status(radeon_connector, link_status))
524 if (dp_channel_eq_ok(link_status, dig_connector->dp_lane_count))
529 static void dp_set_power(struct radeon_connector *radeon_connector, u8 power_state)
531 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
533 if (dig_connector->dpcd[0] >= 0x11) {
534 radeon_dp_aux_native_write(radeon_connector, DP_SET_POWER, 1,
539 static void dp_set_downspread(struct radeon_connector *radeon_connector, u8 downspread)
541 radeon_dp_aux_native_write(radeon_connector, DP_DOWNSPREAD_CTRL, 1,
545 static void dp_set_link_bw_lanes(struct radeon_connector *radeon_connector,
546 u8 link_configuration[DP_LINK_CONFIGURATION_SIZE])
548 radeon_dp_aux_native_write(radeon_connector, DP_LINK_BW_SET, 2,
552 static void dp_update_dpvs_emph(struct radeon_connector *radeon_connector,
553 struct drm_encoder *encoder,
556 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
559 for (i = 0; i < dig_connector->dp_lane_count; i++)
560 atombios_dig_transmitter_setup(encoder,
561 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
564 radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_LANE0_SET,
565 dig_connector->dp_lane_count, train_set);
568 static void dp_set_training(struct radeon_connector *radeon_connector,
571 radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_PATTERN_SET,
575 void dp_link_train(struct drm_encoder *encoder,
576 struct drm_connector *connector)
578 struct drm_device *dev = encoder->dev;
579 struct radeon_device *rdev = dev->dev_private;
580 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
581 struct radeon_encoder_atom_dig *dig;
582 struct radeon_connector *radeon_connector;
583 struct radeon_connector_atom_dig *dig_connector;
585 bool clock_recovery, channel_eq;
586 u8 link_status[DP_LINK_STATUS_SIZE];
587 u8 link_configuration[DP_LINK_CONFIGURATION_SIZE];
592 if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
593 (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
596 if (!radeon_encoder->enc_priv)
598 dig = radeon_encoder->enc_priv;
600 radeon_connector = to_radeon_connector(connector);
601 if (!radeon_connector->con_priv)
603 dig_connector = radeon_connector->con_priv;
605 if (dig->dig_encoder)
606 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
608 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
609 if (dig_connector->linkb)
610 enc_id |= ATOM_DP_CONFIG_LINK_B;
612 enc_id |= ATOM_DP_CONFIG_LINK_A;
614 memset(link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
615 if (dig_connector->dp_clock == 270000)
616 link_configuration[0] = DP_LINK_BW_2_7;
618 link_configuration[0] = DP_LINK_BW_1_62;
619 link_configuration[1] = dig_connector->dp_lane_count;
620 if (dig_connector->dpcd[0] >= 0x11)
621 link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
623 /* power up the sink */
624 dp_set_power(radeon_connector, DP_SET_POWER_D0);
625 /* disable the training pattern on the sink */
626 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
627 /* set link bw and lanes on the sink */
628 dp_set_link_bw_lanes(radeon_connector, link_configuration);
629 /* disable downspread on the sink */
630 dp_set_downspread(radeon_connector, 0);
631 if (ASIC_IS_DCE4(rdev)) {
632 /* start training on the source */
633 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_START);
634 /* set training pattern 1 on the source */
635 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1);
637 /* start training on the source */
638 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_START,
639 dig_connector->dp_clock, enc_id, 0);
640 /* set training pattern 1 on the source */
641 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
642 dig_connector->dp_clock, enc_id, 0);
645 /* set initial vs/emph */
646 memset(train_set, 0, 4);
648 /* set training pattern 1 on the sink */
649 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_1);
651 dp_update_dpvs_emph(radeon_connector, encoder, train_set);
653 /* clock recovery loop */
654 clock_recovery = false;
659 if (!atom_dp_get_link_status(radeon_connector, link_status))
662 if (dp_clock_recovery_ok(link_status, dig_connector->dp_lane_count)) {
663 clock_recovery = true;
667 for (i = 0; i < dig_connector->dp_lane_count; i++) {
668 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
671 if (i == dig_connector->dp_lane_count) {
672 DRM_ERROR("clock recovery reached max voltage\n");
676 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
679 DRM_ERROR("clock recovery tried 5 times\n");
685 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
687 /* Compute new train_set as requested by sink */
688 dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set);
689 dp_update_dpvs_emph(radeon_connector, encoder, train_set);
692 DRM_ERROR("clock recovery failed\n");
694 DRM_DEBUG("clock recovery at voltage %d pre-emphasis %d\n",
695 train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
696 (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
697 DP_TRAIN_PRE_EMPHASIS_SHIFT);
700 /* set training pattern 2 on the sink */
701 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_2);
702 /* set training pattern 2 on the source */
703 if (ASIC_IS_DCE4(rdev))
704 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2);
706 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
707 dig_connector->dp_clock, enc_id, 1);
709 /* channel equalization loop */
714 if (!atom_dp_get_link_status(radeon_connector, link_status))
717 if (dp_channel_eq_ok(link_status, dig_connector->dp_lane_count)) {
724 DRM_ERROR("channel eq failed: 5 tries\n");
728 /* Compute new train_set as requested by sink */
729 dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set);
730 dp_update_dpvs_emph(radeon_connector, encoder, train_set);
736 DRM_ERROR("channel eq failed\n");
738 DRM_DEBUG("channel eq at voltage %d pre-emphasis %d\n",
739 train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
740 (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
741 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
743 /* disable the training pattern on the sink */
744 if (ASIC_IS_DCE4(rdev))
745 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE);
747 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
748 dig_connector->dp_clock, enc_id, 0);
750 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
751 dig_connector->dp_clock, enc_id, 0);
754 int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
755 uint8_t write_byte, uint8_t *read_byte)
757 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
758 struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
760 uint16_t address = algo_data->address;
763 int msg_len, dp_msg_len;
766 /* Set up the command byte */
767 if (mode & MODE_I2C_READ)
768 msg[2] = AUX_I2C_READ << 4;
770 msg[2] = AUX_I2C_WRITE << 4;
772 if (!(mode & MODE_I2C_STOP))
773 msg[2] |= AUX_I2C_MOT << 4;
776 msg[1] = address >> 8;
795 msg[3] = (dp_msg_len) << 4;
796 ret = radeon_process_aux_ch(auxch, msg, msg_len, reply, reply_bytes, 0);
800 *read_byte = reply[0];