drivers/gpu/drm/omapdrm/omap_crtc.c

   1 /*
   2  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   3  * Author: Rob Clark <rob@ti.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <drm/drm_atomic.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_crtc.h>
  21 #include <drm/drm_crtc_helper.h>
  22 #include <drm/drm_mode.h>
  23 #include <drm/drm_plane_helper.h>
  24 #include <linux/math64.h>
  25
  26 #include "omap_drv.h"
  27
  28 #define to_omap_crtc_state(x) container_of(x, struct omap_crtc_state, base)
  29
  30 struct omap_crtc_state {
  31         /* Must be first. */
  32         struct drm_crtc_state base;
  33         /* Shadow values for legacy userspace support. */
  34         unsigned int rotation;
  35         unsigned int zpos;
  36 };
  37
  38 #define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
  39
  40 struct omap_crtc {
  41         struct drm_crtc base;
  42
  43         const char *name;
  44         struct omap_drm_pipeline *pipe;
  45         enum omap_channel channel;
  46
  47         struct videomode vm;
  48
  49         bool ignore_digit_sync_lost;
  50
  51         bool enabled;
  52         bool pending;
  53         wait_queue_head_t pending_wait;
  54         struct drm_pending_vblank_event *event;
  55 };
  56
  57 /* -----------------------------------------------------------------------------
  58  * Helper Functions
  59  */
  60
  61 struct videomode *omap_crtc_timings(struct drm_crtc *crtc)
  62 {
  63         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  64         return &omap_crtc->vm;
  65 }
  66
  67 enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
  68 {
  69         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  70         return omap_crtc->channel;
  71 }
  72
  73 static bool omap_crtc_is_pending(struct drm_crtc *crtc)
  74 {
  75         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  76         unsigned long flags;
  77         bool pending;
  78
  79         spin_lock_irqsave(&crtc->dev->event_lock, flags);
  80         pending = omap_crtc->pending;
  81         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
  82
  83         return pending;
  84 }
  85
  86 int omap_crtc_wait_pending(struct drm_crtc *crtc)
  87 {
  88         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  89
  90         /*
  91          * Timeout is set to a "sufficiently" high value, which should cover
  92          * a single frame refresh even on slower displays.
  93          */
  94         return wait_event_timeout(omap_crtc->pending_wait,
  95                                   !omap_crtc_is_pending(crtc),
  96                                   msecs_to_jiffies(250));
  97 }
  98
  99 /* -----------------------------------------------------------------------------
 100  * DSS Manager Functions
 101  */
 102
 103 /*
 104  * Manager-ops, callbacks from output when they need to configure
 105  * the upstream part of the video pipe.
 106  *
 107  * Most of these we can ignore until we add support for command-mode
 108  * panels.. for video-mode the crtc-helpers already do an adequate
 109  * job of sequencing the setup of the video pipe in the proper order
 110  */
 111
 112 /* we can probably ignore these until we support command-mode panels: */
 113 static void omap_crtc_dss_start_update(struct omap_drm_private *priv,
 114                                        enum omap_channel channel)
 115 {
 116 }
 117
 118 /* Called only from the encoder enable/disable and suspend/resume handlers. */
 119 static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
 120 {
 121         struct drm_device *dev = crtc->dev;
 122         struct omap_drm_private *priv = dev->dev_private;
 123         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 124         enum omap_channel channel = omap_crtc->channel;
 125         struct omap_irq_wait *wait;
 126         u32 framedone_irq, vsync_irq;
 127         int ret;
 128
 129         if (WARN_ON(omap_crtc->enabled == enable))
 130                 return;
 131
 132         if (omap_crtc->pipe->output->output_type == OMAP_DISPLAY_TYPE_HDMI) {
 133                 priv->dispc_ops->mgr_enable(priv->dispc, channel, enable);
 134                 omap_crtc->enabled = enable;
 135                 return;
 136         }
 137
 138         if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
 139                 /*
 140                  * Digit output produces some sync lost interrupts during the
 141                  * first frame when enabling, so we need to ignore those.
 142                  */
 143                 omap_crtc->ignore_digit_sync_lost = true;
 144         }
 145
 146         framedone_irq = priv->dispc_ops->mgr_get_framedone_irq(priv->dispc,
 147                                                                channel);
 148         vsync_irq = priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel);
 149
 150         if (enable) {
 151                 wait = omap_irq_wait_init(dev, vsync_irq, 1);
 152         } else {
 153                 /*
 154                  * When we disable the digit output, we need to wait for
 155                  * FRAMEDONE to know that DISPC has finished with the output.
 156                  *
 157                  * OMAP2/3 does not have FRAMEDONE irq for digit output, and in
 158                  * that case we need to use vsync interrupt, and wait for both
 159                  * even and odd frames.
 160                  */
 161
 162                 if (framedone_irq)
 163                         wait = omap_irq_wait_init(dev, framedone_irq, 1);
 164                 else
 165                         wait = omap_irq_wait_init(dev, vsync_irq, 2);
 166         }
 167
 168         priv->dispc_ops->mgr_enable(priv->dispc, channel, enable);
 169         omap_crtc->enabled = enable;
 170
 171         ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
 172         if (ret) {
 173                 dev_err(dev->dev, "%s: timeout waiting for %s\n",
 174                                 omap_crtc->name, enable ? "enable" : "disable");
 175         }
 176
 177         if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
 178                 omap_crtc->ignore_digit_sync_lost = false;
 179                 /* make sure the irq handler sees the value above */
 180                 mb();
 181         }
 182 }
 183
 184
 185 static int omap_crtc_dss_enable(struct omap_drm_private *priv,
 186                                 enum omap_channel channel)
 187 {
 188         struct drm_crtc *crtc = priv->channels[channel]->crtc;
 189         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 190
 191         priv->dispc_ops->mgr_set_timings(priv->dispc, omap_crtc->channel,
 192                                          &omap_crtc->vm);
 193         omap_crtc_set_enabled(&omap_crtc->base, true);
 194
 195         return 0;
 196 }
 197
 198 static void omap_crtc_dss_disable(struct omap_drm_private *priv,
 199                                   enum omap_channel channel)
 200 {
 201         struct drm_crtc *crtc = priv->channels[channel]->crtc;
 202         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 203
 204         omap_crtc_set_enabled(&omap_crtc->base, false);
 205 }
 206
 207 static void omap_crtc_dss_set_timings(struct omap_drm_private *priv,
 208                 enum omap_channel channel,
 209                 const struct videomode *vm)
 210 {
 211         struct drm_crtc *crtc = priv->channels[channel]->crtc;
 212         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 213
 214         DBG("%s", omap_crtc->name);
 215         omap_crtc->vm = *vm;
 216 }
 217
 218 static void omap_crtc_dss_set_lcd_config(struct omap_drm_private *priv,
 219                 enum omap_channel channel,
 220                 const struct dss_lcd_mgr_config *config)
 221 {
 222         struct drm_crtc *crtc = priv->channels[channel]->crtc;
 223         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 224
 225         DBG("%s", omap_crtc->name);
 226         priv->dispc_ops->mgr_set_lcd_config(priv->dispc, omap_crtc->channel,
 227                                             config);
 228 }
 229
 230 static int omap_crtc_dss_register_framedone(
 231                 struct omap_drm_private *priv, enum omap_channel channel,
 232                 void (*handler)(void *), void *data)
 233 {
 234         return 0;
 235 }
 236
 237 static void omap_crtc_dss_unregister_framedone(
 238                 struct omap_drm_private *priv, enum omap_channel channel,
 239                 void (*handler)(void *), void *data)
 240 {
 241 }
 242
 243 static const struct dss_mgr_ops mgr_ops = {
 244         .start_update = omap_crtc_dss_start_update,
 245         .enable = omap_crtc_dss_enable,
 246         .disable = omap_crtc_dss_disable,
 247         .set_timings = omap_crtc_dss_set_timings,
 248         .set_lcd_config = omap_crtc_dss_set_lcd_config,
 249         .register_framedone_handler = omap_crtc_dss_register_framedone,
 250         .unregister_framedone_handler = omap_crtc_dss_unregister_framedone,
 251 };
 252
 253 /* -----------------------------------------------------------------------------
 254  * Setup, Flush and Page Flip
 255  */
 256
 257 void omap_crtc_error_irq(struct drm_crtc *crtc, u32 irqstatus)
 258 {
 259         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 260
 261         if (omap_crtc->ignore_digit_sync_lost) {
 262                 irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
 263                 if (!irqstatus)
 264                         return;
 265         }
 266
 267         DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);
 268 }
 269
 270 void omap_crtc_vblank_irq(struct drm_crtc *crtc)
 271 {
 272         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 273         struct drm_device *dev = omap_crtc->base.dev;
 274         struct omap_drm_private *priv = dev->dev_private;
 275         bool pending;
 276
 277         spin_lock(&crtc->dev->event_lock);
 278         /*
 279          * If the dispc is busy we're racing the flush operation. Try again on
 280          * the next vblank interrupt.
 281          */
 282         if (priv->dispc_ops->mgr_go_busy(priv->dispc, omap_crtc->channel)) {
 283                 spin_unlock(&crtc->dev->event_lock);
 284                 return;
 285         }
 286
 287         /* Send the vblank event if one has been requested. */
 288         if (omap_crtc->event) {
 289                 drm_crtc_send_vblank_event(crtc, omap_crtc->event);
 290                 omap_crtc->event = NULL;
 291         }
 292
 293         pending = omap_crtc->pending;
 294         omap_crtc->pending = false;
 295         spin_unlock(&crtc->dev->event_lock);
 296
 297         if (pending)
 298                 drm_crtc_vblank_put(crtc);
 299
 300         /* Wake up omap_atomic_complete. */
 301         wake_up(&omap_crtc->pending_wait);
 302
 303         DBG("%s: apply done", omap_crtc->name);
 304 }
 305
 306 static void omap_crtc_write_crtc_properties(struct drm_crtc *crtc)
 307 {
 308         struct omap_drm_private *priv = crtc->dev->dev_private;
 309         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 310         struct omap_overlay_manager_info info;
 311
 312         memset(&info, 0, sizeof(info));
 313
 314         info.default_color = 0x000000;
 315         info.trans_enabled = false;
 316         info.partial_alpha_enabled = false;
 317         info.cpr_enable = false;
 318
 319         priv->dispc_ops->mgr_setup(priv->dispc, omap_crtc->channel, &info);
 320 }
 321
 322 /* -----------------------------------------------------------------------------
 323  * CRTC Functions
 324  */
 325
 326 static void omap_crtc_destroy(struct drm_crtc *crtc)
 327 {
 328         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 329
 330         DBG("%s", omap_crtc->name);
 331
 332         drm_crtc_cleanup(crtc);
 333
 334         kfree(omap_crtc);
 335 }
 336
 337 static void omap_crtc_arm_event(struct drm_crtc *crtc)
 338 {
 339         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 340
 341         WARN_ON(omap_crtc->pending);
 342         omap_crtc->pending = true;
 343
 344         if (crtc->state->event) {
 345                 omap_crtc->event = crtc->state->event;
 346                 crtc->state->event = NULL;
 347         }
 348 }
 349
 350 static void omap_crtc_atomic_enable(struct drm_crtc *crtc,
 351                                     struct drm_crtc_state *old_state)
 352 {
 353         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 354         int ret;
 355
 356         DBG("%s", omap_crtc->name);
 357
 358         spin_lock_irq(&crtc->dev->event_lock);
 359         drm_crtc_vblank_on(crtc);
 360         ret = drm_crtc_vblank_get(crtc);
 361         WARN_ON(ret != 0);
 362
 363         omap_crtc_arm_event(crtc);
 364         spin_unlock_irq(&crtc->dev->event_lock);
 365 }
 366
 367 static void omap_crtc_atomic_disable(struct drm_crtc *crtc,
 368                                      struct drm_crtc_state *old_state)
 369 {
 370         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 371
 372         DBG("%s", omap_crtc->name);
 373
 374         spin_lock_irq(&crtc->dev->event_lock);
 375         if (crtc->state->event) {
 376                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 377                 crtc->state->event = NULL;
 378         }
 379         spin_unlock_irq(&crtc->dev->event_lock);
 380
 381         drm_crtc_vblank_off(crtc);
 382 }
 383
 384 static enum drm_mode_status omap_crtc_mode_valid(struct drm_crtc *crtc,
 385                                         const struct drm_display_mode *mode)
 386 {
 387         struct omap_drm_private *priv = crtc->dev->dev_private;
 388
 389         /* Check for bandwidth limit */
 390         if (priv->max_bandwidth) {
 391                 /*
 392                  * Estimation for the bandwidth need of a given mode with one
 393                  * full screen plane:
 394                  * bandwidth = resolution * 32bpp * (pclk / (vtotal * htotal))
 395                  *                                      ^^ Refresh rate ^^
 396                  *
 397                  * The interlaced mode is taken into account by using the
 398                  * pixelclock in the calculation.
 399                  *
 400                  * The equation is rearranged for 64bit arithmetic.
 401                  */
 402                 uint64_t bandwidth = mode->clock * 1000;
 403                 unsigned int bpp = 4;
 404
 405                 bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp;
 406                 bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal);
 407
 408                 /*
 409                  * Reject modes which would need more bandwidth if used with one
 410                  * full resolution plane (most common use case).
 411                  */
 412                 if (priv->max_bandwidth < bandwidth)
 413                         return MODE_BAD;
 414         }
 415
 416         return MODE_OK;
 417 }
 418
 419 static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
 420 {
 421         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 422         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 423
 424         DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
 425             omap_crtc->name, mode->base.id, mode->name,
 426             mode->vrefresh, mode->clock,
 427             mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal,
 428             mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal,
 429             mode->type, mode->flags);
 430
 431         drm_display_mode_to_videomode(mode, &omap_crtc->vm);
 432 }
 433
 434 static int omap_crtc_atomic_check(struct drm_crtc *crtc,
 435                                 struct drm_crtc_state *state)
 436 {
 437         struct drm_plane_state *pri_state;
 438
 439         if (state->color_mgmt_changed && state->gamma_lut) {
 440                 unsigned int length = state->gamma_lut->length /
 441                         sizeof(struct drm_color_lut);
 442
 443                 if (length < 2)
 444                         return -EINVAL;
 445         }
 446
 447         pri_state = drm_atomic_get_new_plane_state(state->state, crtc->primary);
 448         if (pri_state) {
 449                 struct omap_crtc_state *omap_crtc_state =
 450                         to_omap_crtc_state(state);
 451
 452                 /* Mirror new values for zpos and rotation in omap_crtc_state */
 453                 omap_crtc_state->zpos = pri_state->zpos;
 454                 omap_crtc_state->rotation = pri_state->rotation;
 455         }
 456
 457         return 0;
 458 }
 459
 460 static void omap_crtc_atomic_begin(struct drm_crtc *crtc,
 461                                    struct drm_crtc_state *old_crtc_state)
 462 {
 463 }
 464
 465 static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
 466                                    struct drm_crtc_state *old_crtc_state)
 467 {
 468         struct omap_drm_private *priv = crtc->dev->dev_private;
 469         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 470         int ret;
 471
 472         if (crtc->state->color_mgmt_changed) {
 473                 struct drm_color_lut *lut = NULL;
 474                 unsigned int length = 0;
 475
 476                 if (crtc->state->gamma_lut) {
 477                         lut = (struct drm_color_lut *)
 478                                 crtc->state->gamma_lut->data;
 479                         length = crtc->state->gamma_lut->length /
 480                                 sizeof(*lut);
 481                 }
 482                 priv->dispc_ops->mgr_set_gamma(priv->dispc, omap_crtc->channel,
 483                                                lut, length);
 484         }
 485
 486         omap_crtc_write_crtc_properties(crtc);
 487
 488         /* Only flush the CRTC if it is currently enabled. */
 489         if (!omap_crtc->enabled)
 490                 return;
 491
 492         DBG("%s: GO", omap_crtc->name);
 493
 494         ret = drm_crtc_vblank_get(crtc);
 495         WARN_ON(ret != 0);
 496
 497         spin_lock_irq(&crtc->dev->event_lock);
 498         priv->dispc_ops->mgr_go(priv->dispc, omap_crtc->channel);
 499         omap_crtc_arm_event(crtc);
 500         spin_unlock_irq(&crtc->dev->event_lock);
 501 }
 502
 503 static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
 504                                          struct drm_crtc_state *state,
 505                                          struct drm_property *property,
 506                                          u64 val)
 507 {
 508         struct omap_drm_private *priv = crtc->dev->dev_private;
 509         struct drm_plane_state *plane_state;
 510
 511         /*
 512          * Delegate property set to the primary plane. Get the plane state and
 513          * set the property directly, the shadow copy will be assigned in the
 514          * omap_crtc_atomic_check callback. This way updates to plane state will
 515          * always be mirrored in the crtc state correctly.
 516          */
 517         plane_state = drm_atomic_get_plane_state(state->state, crtc->primary);
 518         if (IS_ERR(plane_state))
 519                 return PTR_ERR(plane_state);
 520
 521         if (property == crtc->primary->rotation_property)
 522                 plane_state->rotation = val;
 523         else if (property == priv->zorder_prop)
 524                 plane_state->zpos = val;
 525         else
 526                 return -EINVAL;
 527
 528         return 0;
 529 }
 530
 531 static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
 532                                          const struct drm_crtc_state *state,
 533                                          struct drm_property *property,
 534                                          u64 *val)
 535 {
 536         struct omap_drm_private *priv = crtc->dev->dev_private;
 537         struct omap_crtc_state *omap_state = to_omap_crtc_state(state);
 538
 539         if (property == crtc->primary->rotation_property)
 540                 *val = omap_state->rotation;
 541         else if (property == priv->zorder_prop)
 542                 *val = omap_state->zpos;
 543         else
 544                 return -EINVAL;
 545
 546         return 0;
 547 }
 548
 549 static void omap_crtc_reset(struct drm_crtc *crtc)
 550 {
 551         if (crtc->state)
 552                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
 553
 554         kfree(crtc->state);
 555         crtc->state = kzalloc(sizeof(struct omap_crtc_state), GFP_KERNEL);
 556
 557         if (crtc->state)
 558                 crtc->state->crtc = crtc;
 559 }
 560
 561 static struct drm_crtc_state *
 562 omap_crtc_duplicate_state(struct drm_crtc *crtc)
 563 {
 564         struct omap_crtc_state *state, *current_state;
 565
 566         if (WARN_ON(!crtc->state))
 567                 return NULL;
 568
 569         current_state = to_omap_crtc_state(crtc->state);
 570
 571         state = kmalloc(sizeof(*state), GFP_KERNEL);
 572         if (!state)
 573                 return NULL;
 574
 575         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 576
 577         state->zpos = current_state->zpos;
 578         state->rotation = current_state->rotation;
 579
 580         return &state->base;
 581 }
 582
 583 static const struct drm_crtc_funcs omap_crtc_funcs = {
 584         .reset = omap_crtc_reset,
 585         .set_config = drm_atomic_helper_set_config,
 586         .destroy = omap_crtc_destroy,
 587         .page_flip = drm_atomic_helper_page_flip,
 588         .gamma_set = drm_atomic_helper_legacy_gamma_set,
 589         .atomic_duplicate_state = omap_crtc_duplicate_state,
 590         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 591         .atomic_set_property = omap_crtc_atomic_set_property,
 592         .atomic_get_property = omap_crtc_atomic_get_property,
 593         .enable_vblank = omap_irq_enable_vblank,
 594         .disable_vblank = omap_irq_disable_vblank,
 595 };
 596
 597 static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
 598         .mode_set_nofb = omap_crtc_mode_set_nofb,
 599         .atomic_check = omap_crtc_atomic_check,
 600         .atomic_begin = omap_crtc_atomic_begin,
 601         .atomic_flush = omap_crtc_atomic_flush,
 602         .atomic_enable = omap_crtc_atomic_enable,
 603         .atomic_disable = omap_crtc_atomic_disable,
 604         .mode_valid = omap_crtc_mode_valid,
 605 };
 606
 607 /* -----------------------------------------------------------------------------
 608  * Init and Cleanup
 609  */
 610
 611 static const char *channel_names[] = {
 612         [OMAP_DSS_CHANNEL_LCD] = "lcd",
 613         [OMAP_DSS_CHANNEL_DIGIT] = "tv",
 614         [OMAP_DSS_CHANNEL_LCD2] = "lcd2",
 615         [OMAP_DSS_CHANNEL_LCD3] = "lcd3",
 616 };
 617
 618 void omap_crtc_pre_init(struct omap_drm_private *priv)
 619 {
 620         dss_install_mgr_ops(priv->dss, &mgr_ops, priv);
 621 }
 622
 623 void omap_crtc_pre_uninit(struct omap_drm_private *priv)
 624 {
 625         dss_uninstall_mgr_ops(priv->dss);
 626 }
 627
 628 /* initialize crtc */
 629 struct drm_crtc *omap_crtc_init(struct drm_device *dev,
 630                                 struct omap_drm_pipeline *pipe,
 631                                 struct drm_plane *plane)
 632 {
 633         struct omap_drm_private *priv = dev->dev_private;
 634         struct drm_crtc *crtc = NULL;
 635         struct omap_crtc *omap_crtc;
 636         enum omap_channel channel;
 637         int ret;
 638
 639         channel = pipe->output->dispc_channel;
 640
 641         DBG("%s", channel_names[channel]);
 642
 643         omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
 644         if (!omap_crtc)
 645                 return ERR_PTR(-ENOMEM);
 646
 647         crtc = &omap_crtc->base;
 648
 649         init_waitqueue_head(&omap_crtc->pending_wait);
 650
 651         omap_crtc->pipe = pipe;
 652         omap_crtc->channel = channel;
 653         omap_crtc->name = channel_names[channel];
 654
 655         ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
 656                                         &omap_crtc_funcs, NULL);
 657         if (ret < 0) {
 658                 dev_err(dev->dev, "%s(): could not init crtc for: %s\n",
 659                         __func__, pipe->display->name);
 660                 kfree(omap_crtc);
 661                 return ERR_PTR(ret);
 662         }
 663
 664         drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
 665
 666         /* The dispc API adapts to what ever size, but the HW supports
 667          * 256 element gamma table for LCDs and 1024 element table for
 668          * OMAP_DSS_CHANNEL_DIGIT. X server assumes 256 element gamma
 669          * tables so lets use that. Size of HW gamma table can be
 670          * extracted with dispc_mgr_gamma_size(). If it returns 0
 671          * gamma table is not supprted.
 672          */
 673         if (priv->dispc_ops->mgr_gamma_size(priv->dispc, channel)) {
 674                 unsigned int gamma_lut_size = 256;
 675
 676                 drm_crtc_enable_color_mgmt(crtc, 0, false, gamma_lut_size);
 677                 drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size);
 678         }
 679
 680         omap_plane_install_properties(crtc->primary, &crtc->base);
 681
 682         return crtc;
 683 }