drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c

   1 /*
   2  * HDMI CEC
   3  *
   4  * Based on the CEC code from hdmi_ti_4xxx_ip.c from Android.
   5  *
   6  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
   7  * Authors: Yong Zhi
   8  *      Mythri pk <mythripk@ti.com>
   9  *
  10  * Heavily modified to use the linux CEC framework:
  11  *
  12  * Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
  13  *
  14  * This program is free software; you may redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; version 2 of the License.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  21  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  22  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  23  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  24  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25  * SOFTWARE.
  26  */
  27
  28 #include <linux/kernel.h>
  29 #include <linux/err.h>
  30 #include <linux/io.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/slab.h>
  33
  34 #include "dss.h"
  35 #include "hdmi.h"
  36 #include "hdmi4_core.h"
  37 #include "hdmi4_cec.h"
  38
  39 /* HDMI CEC */
  40 #define HDMI_CEC_DEV_ID                         0x900
  41 #define HDMI_CEC_SPEC                           0x904
  42
  43 /* Not really a debug register, more a low-level control register */
  44 #define HDMI_CEC_DBG_3                          0x91C
  45 #define HDMI_CEC_TX_INIT                        0x920
  46 #define HDMI_CEC_TX_DEST                        0x924
  47 #define HDMI_CEC_SETUP                          0x938
  48 #define HDMI_CEC_TX_COMMAND                     0x93C
  49 #define HDMI_CEC_TX_OPERAND                     0x940
  50 #define HDMI_CEC_TRANSMIT_DATA                  0x97C
  51 #define HDMI_CEC_CA_7_0                         0x988
  52 #define HDMI_CEC_CA_15_8                        0x98C
  53 #define HDMI_CEC_INT_STATUS_0                   0x998
  54 #define HDMI_CEC_INT_STATUS_1                   0x99C
  55 #define HDMI_CEC_INT_ENABLE_0                   0x990
  56 #define HDMI_CEC_INT_ENABLE_1                   0x994
  57 #define HDMI_CEC_RX_CONTROL                     0x9B0
  58 #define HDMI_CEC_RX_COUNT                       0x9B4
  59 #define HDMI_CEC_RX_CMD_HEADER                  0x9B8
  60 #define HDMI_CEC_RX_COMMAND                     0x9BC
  61 #define HDMI_CEC_RX_OPERAND                     0x9C0
  62
  63 #define HDMI_CEC_TX_FIFO_INT_MASK               0x64
  64 #define HDMI_CEC_RETRANSMIT_CNT_INT_MASK        0x2
  65
  66 #define HDMI_CORE_CEC_RETRY    200
  67
  68 static void hdmi_cec_received_msg(struct hdmi_core_data *core)
  69 {
  70         u32 cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff;
  71
  72         /* While there are CEC frames in the FIFO */
  73         while (cnt & 0x70) {
  74                 /* and the frame doesn't have an error */
  75                 if (!(cnt & 0x80)) {
  76                         struct cec_msg msg = {};
  77                         unsigned int i;
  78
  79                         /* then read the message */
  80                         msg.len = cnt & 0xf;
  81                         msg.msg[0] = hdmi_read_reg(core->base,
  82                                                    HDMI_CEC_RX_CMD_HEADER);
  83                         msg.msg[1] = hdmi_read_reg(core->base,
  84                                                    HDMI_CEC_RX_COMMAND);
  85                         for (i = 0; i < msg.len; i++) {
  86                                 unsigned int reg = HDMI_CEC_RX_OPERAND + i * 4;
  87
  88                                 msg.msg[2 + i] =
  89                                         hdmi_read_reg(core->base, reg);
  90                         }
  91                         msg.len += 2;
  92                         cec_received_msg(core->adap, &msg);
  93                 }
  94                 /* Clear the current frame from the FIFO */
  95                 hdmi_write_reg(core->base, HDMI_CEC_RX_CONTROL, 1);
  96                 /* Wait until the current frame is cleared */
  97                 while (hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL) & 1)
  98                         udelay(1);
  99                 /*
 100                  * Re-read the count register and loop to see if there are
 101                  * more messages in the FIFO.
 102                  */
 103                 cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff;
 104         }
 105 }
 106
 107 static void hdmi_cec_transmit_fifo_empty(struct hdmi_core_data *core, u32 stat1)
 108 {
 109         if (stat1 & 2) {
 110                 u32 dbg3 = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
 111
 112                 cec_transmit_done(core->adap,
 113                                   CEC_TX_STATUS_NACK |
 114                                   CEC_TX_STATUS_MAX_RETRIES,
 115                                   0, (dbg3 >> 4) & 7, 0, 0);
 116         } else if (stat1 & 1) {
 117                 cec_transmit_done(core->adap,
 118                                   CEC_TX_STATUS_ARB_LOST |
 119                                   CEC_TX_STATUS_MAX_RETRIES,
 120                                   0, 0, 0, 0);
 121         } else if (stat1 == 0) {
 122                 cec_transmit_done(core->adap, CEC_TX_STATUS_OK,
 123                                   0, 0, 0, 0);
 124         }
 125 }
 126
 127 void hdmi4_cec_irq(struct hdmi_core_data *core)
 128 {
 129         u32 stat0 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0);
 130         u32 stat1 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1);
 131
 132         hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0, stat0);
 133         hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, stat1);
 134
 135         if (stat0 & 0x40)
 136                 REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
 137         else if (stat0 & 0x24)
 138                 hdmi_cec_transmit_fifo_empty(core, stat1);
 139         if (stat1 & 2) {
 140                 u32 dbg3 = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
 141
 142                 cec_transmit_done(core->adap,
 143                                   CEC_TX_STATUS_NACK |
 144                                   CEC_TX_STATUS_MAX_RETRIES,
 145                                   0, (dbg3 >> 4) & 7, 0, 0);
 146         } else if (stat1 & 1) {
 147                 cec_transmit_done(core->adap,
 148                                   CEC_TX_STATUS_ARB_LOST |
 149                                   CEC_TX_STATUS_MAX_RETRIES,
 150                                   0, 0, 0, 0);
 151         }
 152         if (stat0 & 0x02)
 153                 hdmi_cec_received_msg(core);
 154         if (stat1 & 0x3)
 155                 REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
 156 }
 157
 158 static bool hdmi_cec_clear_tx_fifo(struct cec_adapter *adap)
 159 {
 160         struct hdmi_core_data *core = cec_get_drvdata(adap);
 161         int retry = HDMI_CORE_CEC_RETRY;
 162         int temp;
 163
 164         REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
 165         while (retry) {
 166                 temp = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
 167                 if (FLD_GET(temp, 7, 7) == 0)
 168                         break;
 169                 retry--;
 170         }
 171         return retry != 0;
 172 }
 173
 174 static bool hdmi_cec_clear_rx_fifo(struct cec_adapter *adap)
 175 {
 176         struct hdmi_core_data *core = cec_get_drvdata(adap);
 177         int retry = HDMI_CORE_CEC_RETRY;
 178         int temp;
 179
 180         hdmi_write_reg(core->base, HDMI_CEC_RX_CONTROL, 0x3);
 181         retry = HDMI_CORE_CEC_RETRY;
 182         while (retry) {
 183                 temp = hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL);
 184                 if (FLD_GET(temp, 1, 0) == 0)
 185                         break;
 186                 retry--;
 187         }
 188         return retry != 0;
 189 }
 190
 191 static int hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
 192 {
 193         struct hdmi_core_data *core = cec_get_drvdata(adap);
 194         int temp, err;
 195
 196         if (!enable) {
 197                 hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0);
 198                 hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0);
 199                 REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0, 3, 3);
 200                 hdmi_wp_clear_irqenable(core->wp, HDMI_IRQ_CORE);
 201                 hdmi_wp_set_irqstatus(core->wp, HDMI_IRQ_CORE);
 202                 hdmi4_core_disable(NULL);
 203                 return 0;
 204         }
 205         err = hdmi4_core_enable(NULL);
 206         if (err)
 207                 return err;
 208
 209         /* Clear TX FIFO */
 210         if (!hdmi_cec_clear_tx_fifo(adap)) {
 211                 pr_err("cec-%s: could not clear TX FIFO\n", adap->name);
 212                 return -EIO;
 213         }
 214
 215         /* Clear RX FIFO */
 216         if (!hdmi_cec_clear_rx_fifo(adap)) {
 217                 pr_err("cec-%s: could not clear RX FIFO\n", adap->name);
 218                 return -EIO;
 219         }
 220
 221         /* Clear CEC interrupts */
 222         hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1,
 223                 hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1));
 224         hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0,
 225                 hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0));
 226
 227         /* Enable HDMI core interrupts */
 228         hdmi_wp_set_irqenable(core->wp, HDMI_IRQ_CORE);
 229         /* Unmask CEC interrupt */
 230         REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0x1, 3, 3);
 231         /*
 232          * Enable CEC interrupts:
 233          * Transmit Buffer Full/Empty Change event
 234          * Transmitter FIFO Empty event
 235          * Receiver FIFO Not Empty event
 236          */
 237         hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0x26);
 238         /*
 239          * Enable CEC interrupts:
 240          * RX FIFO Overrun Error event
 241          * Short Pulse Detected event
 242          * Frame Retransmit Count Exceeded event
 243          * Start Bit Irregularity event
 244          */
 245         hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0x0f);
 246
 247         /* cec calibration enable (self clearing) */
 248         hdmi_write_reg(core->base, HDMI_CEC_SETUP, 0x03);
 249         msleep(20);
 250         hdmi_write_reg(core->base, HDMI_CEC_SETUP, 0x04);
 251
 252         temp = hdmi_read_reg(core->base, HDMI_CEC_SETUP);
 253         if (FLD_GET(temp, 4, 4) != 0) {
 254                 temp = FLD_MOD(temp, 0, 4, 4);
 255                 hdmi_write_reg(core->base, HDMI_CEC_SETUP, temp);
 256
 257                 /*
 258                  * If we enabled CEC in middle of a CEC message on the bus,
 259                  * we could have start bit irregularity and/or short
 260                  * pulse event. Clear them now.
 261                  */
 262                 temp = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1);
 263                 temp = FLD_MOD(0x0, 0x5, 2, 0);
 264                 hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, temp);
 265         }
 266         return 0;
 267 }
 268
 269 static int hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
 270 {
 271         struct hdmi_core_data *core = cec_get_drvdata(adap);
 272         u32 v;
 273
 274         if (log_addr == CEC_LOG_ADDR_INVALID) {
 275                 hdmi_write_reg(core->base, HDMI_CEC_CA_7_0, 0);
 276                 hdmi_write_reg(core->base, HDMI_CEC_CA_15_8, 0);
 277                 return 0;
 278         }
 279         if (log_addr <= 7) {
 280                 v = hdmi_read_reg(core->base, HDMI_CEC_CA_7_0);
 281                 v |= 1 << log_addr;
 282                 hdmi_write_reg(core->base, HDMI_CEC_CA_7_0, v);
 283         } else {
 284                 v = hdmi_read_reg(core->base, HDMI_CEC_CA_15_8);
 285                 v |= 1 << (log_addr - 8);
 286                 hdmi_write_reg(core->base, HDMI_CEC_CA_15_8, v);
 287         }
 288         return 0;
 289 }
 290
 291 static int hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
 292                                    u32 signal_free_time, struct cec_msg *msg)
 293 {
 294         struct hdmi_core_data *core = cec_get_drvdata(adap);
 295         int temp;
 296         u32 i;
 297
 298         /* Clear TX FIFO */
 299         if (!hdmi_cec_clear_tx_fifo(adap)) {
 300                 pr_err("cec-%s: could not clear TX FIFO for transmit\n",
 301                        adap->name);
 302                 return -EIO;
 303         }
 304
 305         /* Clear TX interrupts */
 306         hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0,
 307                        HDMI_CEC_TX_FIFO_INT_MASK);
 308
 309         hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1,
 310                        HDMI_CEC_RETRANSMIT_CNT_INT_MASK);
 311
 312         /* Set the retry count */
 313         REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, attempts - 1, 6, 4);
 314
 315         /* Set the initiator addresses */
 316         hdmi_write_reg(core->base, HDMI_CEC_TX_INIT, cec_msg_initiator(msg));
 317
 318         /* Set destination id */
 319         temp = cec_msg_destination(msg);
 320         if (msg->len == 1)
 321                 temp |= 0x80;
 322         hdmi_write_reg(core->base, HDMI_CEC_TX_DEST, temp);
 323         if (msg->len == 1)
 324                 return 0;
 325
 326         /* Setup command and arguments for the command */
 327         hdmi_write_reg(core->base, HDMI_CEC_TX_COMMAND, msg->msg[1]);
 328
 329         for (i = 0; i < msg->len - 2; i++)
 330                 hdmi_write_reg(core->base, HDMI_CEC_TX_OPERAND + i * 4,
 331                                msg->msg[2 + i]);
 332
 333         /* Operand count */
 334         hdmi_write_reg(core->base, HDMI_CEC_TRANSMIT_DATA,
 335                        (msg->len - 2) | 0x10);
 336         return 0;
 337 }
 338
 339 static const struct cec_adap_ops hdmi_cec_adap_ops = {
 340         .adap_enable = hdmi_cec_adap_enable,
 341         .adap_log_addr = hdmi_cec_adap_log_addr,
 342         .adap_transmit = hdmi_cec_adap_transmit,
 343 };
 344
 345 void hdmi4_cec_set_phys_addr(struct hdmi_core_data *core, u16 pa)
 346 {
 347         cec_s_phys_addr(core->adap, pa, false);
 348 }
 349
 350 int hdmi4_cec_init(struct platform_device *pdev, struct hdmi_core_data *core,
 351                   struct hdmi_wp_data *wp)
 352 {
 353         const u32 caps = CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS |
 354                          CEC_CAP_PASSTHROUGH | CEC_CAP_RC;
 355         int ret;
 356
 357         core->adap = cec_allocate_adapter(&hdmi_cec_adap_ops, core,
 358                 "omap4", caps, CEC_MAX_LOG_ADDRS);
 359         ret = PTR_ERR_OR_ZERO(core->adap);
 360         if (ret < 0)
 361                 return ret;
 362         core->wp = wp;
 363
 364         /*
 365          * Initialize CEC clock divider: CEC needs 2MHz clock hence
 366          * set the devider to 24 to get 48/24=2MHz clock
 367          */
 368         REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0);
 369
 370         ret = cec_register_adapter(core->adap, &pdev->dev);
 371         if (ret < 0) {
 372                 cec_delete_adapter(core->adap);
 373                 return ret;
 374         }
 375         return 0;
 376 }
 377
 378 void hdmi4_cec_uninit(struct hdmi_core_data *core)
 379 {
 380         cec_unregister_adapter(core->adap);
 381 }