drivers/gpu/drm/omapdrm/dss/dss.c

   1 /*
   2  * Copyright (C) 2009 Nokia Corporation
   3  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
   4  *
   5  * Some code and ideas taken from drivers/video/omap/ driver
   6  * by Imre Deak.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published by
  10  * the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #define DSS_SUBSYS_NAME "DSS"
  22
  23 #include <linux/debugfs.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/io.h>
  28 #include <linux/export.h>
  29 #include <linux/err.h>
  30 #include <linux/delay.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/clk.h>
  33 #include <linux/pinctrl/consumer.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/pm_runtime.h>
  36 #include <linux/gfp.h>
  37 #include <linux/sizes.h>
  38 #include <linux/mfd/syscon.h>
  39 #include <linux/regmap.h>
  40 #include <linux/of.h>
  41 #include <linux/of_device.h>
  42 #include <linux/of_graph.h>
  43 #include <linux/regulator/consumer.h>
  44 #include <linux/suspend.h>
  45 #include <linux/component.h>
  46 #include <linux/sys_soc.h>
  47
  48 #include "omapdss.h"
  49 #include "dss.h"
  50
  51 struct dss_reg {
  52         u16 idx;
  53 };
  54
  55 #define DSS_REG(idx)                    ((const struct dss_reg) { idx })
  56
  57 #define DSS_REVISION                    DSS_REG(0x0000)
  58 #define DSS_SYSCONFIG                   DSS_REG(0x0010)
  59 #define DSS_SYSSTATUS                   DSS_REG(0x0014)
  60 #define DSS_CONTROL                     DSS_REG(0x0040)
  61 #define DSS_SDI_CONTROL                 DSS_REG(0x0044)
  62 #define DSS_PLL_CONTROL                 DSS_REG(0x0048)
  63 #define DSS_SDI_STATUS                  DSS_REG(0x005C)
  64
  65 #define REG_GET(dss, idx, start, end) \
  66         FLD_GET(dss_read_reg(dss, idx), start, end)
  67
  68 #define REG_FLD_MOD(dss, idx, val, start, end) \
  69         dss_write_reg(dss, idx, \
  70                       FLD_MOD(dss_read_reg(dss, idx), val, start, end))
  71
  72 struct dss_ops {
  73         int (*dpi_select_source)(struct dss_device *dss, int port,
  74                                  enum omap_channel channel);
  75         int (*select_lcd_source)(struct dss_device *dss,
  76                                  enum omap_channel channel,
  77                                  enum dss_clk_source clk_src);
  78 };
  79
  80 struct dss_features {
  81         enum dss_model model;
  82         u8 fck_div_max;
  83         unsigned int fck_freq_max;
  84         u8 dss_fck_multiplier;
  85         const char *parent_clk_name;
  86         const enum omap_display_type *ports;
  87         int num_ports;
  88         const enum omap_dss_output_id *outputs;
  89         const struct dss_ops *ops;
  90         struct dss_reg_field dispc_clk_switch;
  91         bool has_lcd_clk_src;
  92 };
  93
  94 static const char * const dss_generic_clk_source_names[] = {
  95         [DSS_CLK_SRC_FCK]       = "FCK",
  96         [DSS_CLK_SRC_PLL1_1]    = "PLL1:1",
  97         [DSS_CLK_SRC_PLL1_2]    = "PLL1:2",
  98         [DSS_CLK_SRC_PLL1_3]    = "PLL1:3",
  99         [DSS_CLK_SRC_PLL2_1]    = "PLL2:1",
 100         [DSS_CLK_SRC_PLL2_2]    = "PLL2:2",
 101         [DSS_CLK_SRC_PLL2_3]    = "PLL2:3",
 102         [DSS_CLK_SRC_HDMI_PLL]  = "HDMI PLL",
 103 };
 104
 105 static inline void dss_write_reg(struct dss_device *dss,
 106                                  const struct dss_reg idx, u32 val)
 107 {
 108         __raw_writel(val, dss->base + idx.idx);
 109 }
 110
 111 static inline u32 dss_read_reg(struct dss_device *dss, const struct dss_reg idx)
 112 {
 113         return __raw_readl(dss->base + idx.idx);
 114 }
 115
 116 #define SR(dss, reg) \
 117         dss->ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(dss, DSS_##reg)
 118 #define RR(dss, reg) \
 119         dss_write_reg(dss, DSS_##reg, dss->ctx[(DSS_##reg).idx / sizeof(u32)])
 120
 121 static void dss_save_context(struct dss_device *dss)
 122 {
 123         DSSDBG("dss_save_context\n");
 124
 125         SR(dss, CONTROL);
 126
 127         if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) {
 128                 SR(dss, SDI_CONTROL);
 129                 SR(dss, PLL_CONTROL);
 130         }
 131
 132         dss->ctx_valid = true;
 133
 134         DSSDBG("context saved\n");
 135 }
 136
 137 static void dss_restore_context(struct dss_device *dss)
 138 {
 139         DSSDBG("dss_restore_context\n");
 140
 141         if (!dss->ctx_valid)
 142                 return;
 143
 144         RR(dss, CONTROL);
 145
 146         if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) {
 147                 RR(dss, SDI_CONTROL);
 148                 RR(dss, PLL_CONTROL);
 149         }
 150
 151         DSSDBG("context restored\n");
 152 }
 153
 154 #undef SR
 155 #undef RR
 156
 157 void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable)
 158 {
 159         unsigned int shift;
 160         unsigned int val;
 161
 162         if (!pll->dss->syscon_pll_ctrl)
 163                 return;
 164
 165         val = !enable;
 166
 167         switch (pll->id) {
 168         case DSS_PLL_VIDEO1:
 169                 shift = 0;
 170                 break;
 171         case DSS_PLL_VIDEO2:
 172                 shift = 1;
 173                 break;
 174         case DSS_PLL_HDMI:
 175                 shift = 2;
 176                 break;
 177         default:
 178                 DSSERR("illegal DSS PLL ID %d\n", pll->id);
 179                 return;
 180         }
 181
 182         regmap_update_bits(pll->dss->syscon_pll_ctrl,
 183                            pll->dss->syscon_pll_ctrl_offset,
 184                            1 << shift, val << shift);
 185 }
 186
 187 static int dss_ctrl_pll_set_control_mux(struct dss_device *dss,
 188                                         enum dss_clk_source clk_src,
 189                                         enum omap_channel channel)
 190 {
 191         unsigned int shift, val;
 192
 193         if (!dss->syscon_pll_ctrl)
 194                 return -EINVAL;
 195
 196         switch (channel) {
 197         case OMAP_DSS_CHANNEL_LCD:
 198                 shift = 3;
 199
 200                 switch (clk_src) {
 201                 case DSS_CLK_SRC_PLL1_1:
 202                         val = 0; break;
 203                 case DSS_CLK_SRC_HDMI_PLL:
 204                         val = 1; break;
 205                 default:
 206                         DSSERR("error in PLL mux config for LCD\n");
 207                         return -EINVAL;
 208                 }
 209
 210                 break;
 211         case OMAP_DSS_CHANNEL_LCD2:
 212                 shift = 5;
 213
 214                 switch (clk_src) {
 215                 case DSS_CLK_SRC_PLL1_3:
 216                         val = 0; break;
 217                 case DSS_CLK_SRC_PLL2_3:
 218                         val = 1; break;
 219                 case DSS_CLK_SRC_HDMI_PLL:
 220                         val = 2; break;
 221                 default:
 222                         DSSERR("error in PLL mux config for LCD2\n");
 223                         return -EINVAL;
 224                 }
 225
 226                 break;
 227         case OMAP_DSS_CHANNEL_LCD3:
 228                 shift = 7;
 229
 230                 switch (clk_src) {
 231                 case DSS_CLK_SRC_PLL2_1:
 232                         val = 0; break;
 233                 case DSS_CLK_SRC_PLL1_3:
 234                         val = 1; break;
 235                 case DSS_CLK_SRC_HDMI_PLL:
 236                         val = 2; break;
 237                 default:
 238                         DSSERR("error in PLL mux config for LCD3\n");
 239                         return -EINVAL;
 240                 }
 241
 242                 break;
 243         default:
 244                 DSSERR("error in PLL mux config\n");
 245                 return -EINVAL;
 246         }
 247
 248         regmap_update_bits(dss->syscon_pll_ctrl, dss->syscon_pll_ctrl_offset,
 249                 0x3 << shift, val << shift);
 250
 251         return 0;
 252 }
 253
 254 void dss_sdi_init(struct dss_device *dss, int datapairs)
 255 {
 256         u32 l;
 257
 258         BUG_ON(datapairs > 3 || datapairs < 1);
 259
 260         l = dss_read_reg(dss, DSS_SDI_CONTROL);
 261         l = FLD_MOD(l, 0xf, 19, 15);            /* SDI_PDIV */
 262         l = FLD_MOD(l, datapairs-1, 3, 2);      /* SDI_PRSEL */
 263         l = FLD_MOD(l, 2, 1, 0);                /* SDI_BWSEL */
 264         dss_write_reg(dss, DSS_SDI_CONTROL, l);
 265
 266         l = dss_read_reg(dss, DSS_PLL_CONTROL);
 267         l = FLD_MOD(l, 0x7, 25, 22);    /* SDI_PLL_FREQSEL */
 268         l = FLD_MOD(l, 0xb, 16, 11);    /* SDI_PLL_REGN */
 269         l = FLD_MOD(l, 0xb4, 10, 1);    /* SDI_PLL_REGM */
 270         dss_write_reg(dss, DSS_PLL_CONTROL, l);
 271 }
 272
 273 int dss_sdi_enable(struct dss_device *dss)
 274 {
 275         unsigned long timeout;
 276
 277         dispc_pck_free_enable(dss->dispc, 1);
 278
 279         /* Reset SDI PLL */
 280         REG_FLD_MOD(dss, DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
 281         udelay(1);      /* wait 2x PCLK */
 282
 283         /* Lock SDI PLL */
 284         REG_FLD_MOD(dss, DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
 285
 286         /* Waiting for PLL lock request to complete */
 287         timeout = jiffies + msecs_to_jiffies(500);
 288         while (dss_read_reg(dss, DSS_SDI_STATUS) & (1 << 6)) {
 289                 if (time_after_eq(jiffies, timeout)) {
 290                         DSSERR("PLL lock request timed out\n");
 291                         goto err1;
 292                 }
 293         }
 294
 295         /* Clearing PLL_GO bit */
 296         REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 28, 28);
 297
 298         /* Waiting for PLL to lock */
 299         timeout = jiffies + msecs_to_jiffies(500);
 300         while (!(dss_read_reg(dss, DSS_SDI_STATUS) & (1 << 5))) {
 301                 if (time_after_eq(jiffies, timeout)) {
 302                         DSSERR("PLL lock timed out\n");
 303                         goto err1;
 304                 }
 305         }
 306
 307         dispc_lcd_enable_signal(dss->dispc, 1);
 308
 309         /* Waiting for SDI reset to complete */
 310         timeout = jiffies + msecs_to_jiffies(500);
 311         while (!(dss_read_reg(dss, DSS_SDI_STATUS) & (1 << 2))) {
 312                 if (time_after_eq(jiffies, timeout)) {
 313                         DSSERR("SDI reset timed out\n");
 314                         goto err2;
 315                 }
 316         }
 317
 318         return 0;
 319
 320  err2:
 321         dispc_lcd_enable_signal(dss->dispc, 0);
 322  err1:
 323         /* Reset SDI PLL */
 324         REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 325
 326         dispc_pck_free_enable(dss->dispc, 0);
 327
 328         return -ETIMEDOUT;
 329 }
 330
 331 void dss_sdi_disable(struct dss_device *dss)
 332 {
 333         dispc_lcd_enable_signal(dss->dispc, 0);
 334
 335         dispc_pck_free_enable(dss->dispc, 0);
 336
 337         /* Reset SDI PLL */
 338         REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 339 }
 340
 341 const char *dss_get_clk_source_name(enum dss_clk_source clk_src)
 342 {
 343         return dss_generic_clk_source_names[clk_src];
 344 }
 345
 346 static void dss_dump_clocks(struct dss_device *dss, struct seq_file *s)
 347 {
 348         const char *fclk_name;
 349         unsigned long fclk_rate;
 350
 351         if (dss_runtime_get(dss))
 352                 return;
 353
 354         seq_printf(s, "- DSS -\n");
 355
 356         fclk_name = dss_get_clk_source_name(DSS_CLK_SRC_FCK);
 357         fclk_rate = clk_get_rate(dss->dss_clk);
 358
 359         seq_printf(s, "%s = %lu\n",
 360                         fclk_name,
 361                         fclk_rate);
 362
 363         dss_runtime_put(dss);
 364 }
 365
 366 static int dss_dump_regs(struct seq_file *s, void *p)
 367 {
 368         struct dss_device *dss = s->private;
 369
 370 #define DUMPREG(dss, r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(dss, r))
 371
 372         if (dss_runtime_get(dss))
 373                 return 0;
 374
 375         DUMPREG(dss, DSS_REVISION);
 376         DUMPREG(dss, DSS_SYSCONFIG);
 377         DUMPREG(dss, DSS_SYSSTATUS);
 378         DUMPREG(dss, DSS_CONTROL);
 379
 380         if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) {
 381                 DUMPREG(dss, DSS_SDI_CONTROL);
 382                 DUMPREG(dss, DSS_PLL_CONTROL);
 383                 DUMPREG(dss, DSS_SDI_STATUS);
 384         }
 385
 386         dss_runtime_put(dss);
 387 #undef DUMPREG
 388         return 0;
 389 }
 390
 391 static int dss_debug_dump_clocks(struct seq_file *s, void *p)
 392 {
 393         struct dss_device *dss = s->private;
 394
 395         dss_dump_clocks(dss, s);
 396         dispc_dump_clocks(dss->dispc, s);
 397         return 0;
 398 }
 399
 400 static int dss_get_channel_index(enum omap_channel channel)
 401 {
 402         switch (channel) {
 403         case OMAP_DSS_CHANNEL_LCD:
 404                 return 0;
 405         case OMAP_DSS_CHANNEL_LCD2:
 406                 return 1;
 407         case OMAP_DSS_CHANNEL_LCD3:
 408                 return 2;
 409         default:
 410                 WARN_ON(1);
 411                 return 0;
 412         }
 413 }
 414
 415 static void dss_select_dispc_clk_source(struct dss_device *dss,
 416                                         enum dss_clk_source clk_src)
 417 {
 418         int b;
 419
 420         /*
 421          * We always use PRCM clock as the DISPC func clock, except on DSS3,
 422          * where we don't have separate DISPC and LCD clock sources.
 423          */
 424         if (WARN_ON(dss->feat->has_lcd_clk_src && clk_src != DSS_CLK_SRC_FCK))
 425                 return;
 426
 427         switch (clk_src) {
 428         case DSS_CLK_SRC_FCK:
 429                 b = 0;
 430                 break;
 431         case DSS_CLK_SRC_PLL1_1:
 432                 b = 1;
 433                 break;
 434         case DSS_CLK_SRC_PLL2_1:
 435                 b = 2;
 436                 break;
 437         default:
 438                 BUG();
 439                 return;
 440         }
 441
 442         REG_FLD_MOD(dss, DSS_CONTROL, b,                /* DISPC_CLK_SWITCH */
 443                     dss->feat->dispc_clk_switch.start,
 444                     dss->feat->dispc_clk_switch.end);
 445
 446         dss->dispc_clk_source = clk_src;
 447 }
 448
 449 void dss_select_dsi_clk_source(struct dss_device *dss, int dsi_module,
 450                                enum dss_clk_source clk_src)
 451 {
 452         int b, pos;
 453
 454         switch (clk_src) {
 455         case DSS_CLK_SRC_FCK:
 456                 b = 0;
 457                 break;
 458         case DSS_CLK_SRC_PLL1_2:
 459                 BUG_ON(dsi_module != 0);
 460                 b = 1;
 461                 break;
 462         case DSS_CLK_SRC_PLL2_2:
 463                 BUG_ON(dsi_module != 1);
 464                 b = 1;
 465                 break;
 466         default:
 467                 BUG();
 468                 return;
 469         }
 470
 471         pos = dsi_module == 0 ? 1 : 10;
 472         REG_FLD_MOD(dss, DSS_CONTROL, b, pos, pos);     /* DSIx_CLK_SWITCH */
 473
 474         dss->dsi_clk_source[dsi_module] = clk_src;
 475 }
 476
 477 static int dss_lcd_clk_mux_dra7(struct dss_device *dss,
 478                                 enum omap_channel channel,
 479                                 enum dss_clk_source clk_src)
 480 {
 481         const u8 ctrl_bits[] = {
 482                 [OMAP_DSS_CHANNEL_LCD] = 0,
 483                 [OMAP_DSS_CHANNEL_LCD2] = 12,
 484                 [OMAP_DSS_CHANNEL_LCD3] = 19,
 485         };
 486
 487         u8 ctrl_bit = ctrl_bits[channel];
 488         int r;
 489
 490         if (clk_src == DSS_CLK_SRC_FCK) {
 491                 /* LCDx_CLK_SWITCH */
 492                 REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
 493                 return -EINVAL;
 494         }
 495
 496         r = dss_ctrl_pll_set_control_mux(dss, clk_src, channel);
 497         if (r)
 498                 return r;
 499
 500         REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
 501
 502         return 0;
 503 }
 504
 505 static int dss_lcd_clk_mux_omap5(struct dss_device *dss,
 506                                  enum omap_channel channel,
 507                                  enum dss_clk_source clk_src)
 508 {
 509         const u8 ctrl_bits[] = {
 510                 [OMAP_DSS_CHANNEL_LCD] = 0,
 511                 [OMAP_DSS_CHANNEL_LCD2] = 12,
 512                 [OMAP_DSS_CHANNEL_LCD3] = 19,
 513         };
 514         const enum dss_clk_source allowed_plls[] = {
 515                 [OMAP_DSS_CHANNEL_LCD] = DSS_CLK_SRC_PLL1_1,
 516                 [OMAP_DSS_CHANNEL_LCD2] = DSS_CLK_SRC_FCK,
 517                 [OMAP_DSS_CHANNEL_LCD3] = DSS_CLK_SRC_PLL2_1,
 518         };
 519
 520         u8 ctrl_bit = ctrl_bits[channel];
 521
 522         if (clk_src == DSS_CLK_SRC_FCK) {
 523                 /* LCDx_CLK_SWITCH */
 524                 REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
 525                 return -EINVAL;
 526         }
 527
 528         if (WARN_ON(allowed_plls[channel] != clk_src))
 529                 return -EINVAL;
 530
 531         REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
 532
 533         return 0;
 534 }
 535
 536 static int dss_lcd_clk_mux_omap4(struct dss_device *dss,
 537                                  enum omap_channel channel,
 538                                  enum dss_clk_source clk_src)
 539 {
 540         const u8 ctrl_bits[] = {
 541                 [OMAP_DSS_CHANNEL_LCD] = 0,
 542                 [OMAP_DSS_CHANNEL_LCD2] = 12,
 543         };
 544         const enum dss_clk_source allowed_plls[] = {
 545                 [OMAP_DSS_CHANNEL_LCD] = DSS_CLK_SRC_PLL1_1,
 546                 [OMAP_DSS_CHANNEL_LCD2] = DSS_CLK_SRC_PLL2_1,
 547         };
 548
 549         u8 ctrl_bit = ctrl_bits[channel];
 550
 551         if (clk_src == DSS_CLK_SRC_FCK) {
 552                 /* LCDx_CLK_SWITCH */
 553                 REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
 554                 return 0;
 555         }
 556
 557         if (WARN_ON(allowed_plls[channel] != clk_src))
 558                 return -EINVAL;
 559
 560         REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
 561
 562         return 0;
 563 }
 564
 565 void dss_select_lcd_clk_source(struct dss_device *dss,
 566                                enum omap_channel channel,
 567                                enum dss_clk_source clk_src)
 568 {
 569         int idx = dss_get_channel_index(channel);
 570         int r;
 571
 572         if (!dss->feat->has_lcd_clk_src) {
 573                 dss_select_dispc_clk_source(dss, clk_src);
 574                 dss->lcd_clk_source[idx] = clk_src;
 575                 return;
 576         }
 577
 578         r = dss->feat->ops->select_lcd_source(dss, channel, clk_src);
 579         if (r)
 580                 return;
 581
 582         dss->lcd_clk_source[idx] = clk_src;
 583 }
 584
 585 enum dss_clk_source dss_get_dispc_clk_source(struct dss_device *dss)
 586 {
 587         return dss->dispc_clk_source;
 588 }
 589
 590 enum dss_clk_source dss_get_dsi_clk_source(struct dss_device *dss,
 591                                            int dsi_module)
 592 {
 593         return dss->dsi_clk_source[dsi_module];
 594 }
 595
 596 enum dss_clk_source dss_get_lcd_clk_source(struct dss_device *dss,
 597                                            enum omap_channel channel)
 598 {
 599         if (dss->feat->has_lcd_clk_src) {
 600                 int idx = dss_get_channel_index(channel);
 601                 return dss->lcd_clk_source[idx];
 602         } else {
 603                 /* LCD_CLK source is the same as DISPC_FCLK source for
 604                  * OMAP2 and OMAP3 */
 605                 return dss->dispc_clk_source;
 606         }
 607 }
 608
 609 bool dss_div_calc(struct dss_device *dss, unsigned long pck,
 610                   unsigned long fck_min, dss_div_calc_func func, void *data)
 611 {
 612         int fckd, fckd_start, fckd_stop;
 613         unsigned long fck;
 614         unsigned long fck_hw_max;
 615         unsigned long fckd_hw_max;
 616         unsigned long prate;
 617         unsigned int m;
 618
 619         fck_hw_max = dss->feat->fck_freq_max;
 620
 621         if (dss->parent_clk == NULL) {
 622                 unsigned int pckd;
 623
 624                 pckd = fck_hw_max / pck;
 625
 626                 fck = pck * pckd;
 627
 628                 fck = clk_round_rate(dss->dss_clk, fck);
 629
 630                 return func(fck, data);
 631         }
 632
 633         fckd_hw_max = dss->feat->fck_div_max;
 634
 635         m = dss->feat->dss_fck_multiplier;
 636         prate = clk_get_rate(dss->parent_clk);
 637
 638         fck_min = fck_min ? fck_min : 1;
 639
 640         fckd_start = min(prate * m / fck_min, fckd_hw_max);
 641         fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul);
 642
 643         for (fckd = fckd_start; fckd >= fckd_stop; --fckd) {
 644                 fck = DIV_ROUND_UP(prate, fckd) * m;
 645
 646                 if (func(fck, data))
 647                         return true;
 648         }
 649
 650         return false;
 651 }
 652
 653 int dss_set_fck_rate(struct dss_device *dss, unsigned long rate)
 654 {
 655         int r;
 656
 657         DSSDBG("set fck to %lu\n", rate);
 658
 659         r = clk_set_rate(dss->dss_clk, rate);
 660         if (r)
 661                 return r;
 662
 663         dss->dss_clk_rate = clk_get_rate(dss->dss_clk);
 664
 665         WARN_ONCE(dss->dss_clk_rate != rate, "clk rate mismatch: %lu != %lu",
 666                   dss->dss_clk_rate, rate);
 667
 668         return 0;
 669 }
 670
 671 unsigned long dss_get_dispc_clk_rate(struct dss_device *dss)
 672 {
 673         return dss->dss_clk_rate;
 674 }
 675
 676 unsigned long dss_get_max_fck_rate(struct dss_device *dss)
 677 {
 678         return dss->feat->fck_freq_max;
 679 }
 680
 681 static int dss_setup_default_clock(struct dss_device *dss)
 682 {
 683         unsigned long max_dss_fck, prate;
 684         unsigned long fck;
 685         unsigned int fck_div;
 686         int r;
 687
 688         max_dss_fck = dss->feat->fck_freq_max;
 689
 690         if (dss->parent_clk == NULL) {
 691                 fck = clk_round_rate(dss->dss_clk, max_dss_fck);
 692         } else {
 693                 prate = clk_get_rate(dss->parent_clk);
 694
 695                 fck_div = DIV_ROUND_UP(prate * dss->feat->dss_fck_multiplier,
 696                                 max_dss_fck);
 697                 fck = DIV_ROUND_UP(prate, fck_div)
 698                     * dss->feat->dss_fck_multiplier;
 699         }
 700
 701         r = dss_set_fck_rate(dss, fck);
 702         if (r)
 703                 return r;
 704
 705         return 0;
 706 }
 707
 708 void dss_set_venc_output(struct dss_device *dss, enum omap_dss_venc_type type)
 709 {
 710         int l = 0;
 711
 712         if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
 713                 l = 0;
 714         else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
 715                 l = 1;
 716         else
 717                 BUG();
 718
 719         /* venc out selection. 0 = comp, 1 = svideo */
 720         REG_FLD_MOD(dss, DSS_CONTROL, l, 6, 6);
 721 }
 722
 723 void dss_set_dac_pwrdn_bgz(struct dss_device *dss, bool enable)
 724 {
 725         /* DAC Power-Down Control */
 726         REG_FLD_MOD(dss, DSS_CONTROL, enable, 5, 5);
 727 }
 728
 729 void dss_select_hdmi_venc_clk_source(struct dss_device *dss,
 730                                      enum dss_hdmi_venc_clk_source_select src)
 731 {
 732         enum omap_dss_output_id outputs;
 733
 734         outputs = dss->feat->outputs[OMAP_DSS_CHANNEL_DIGIT];
 735
 736         /* Complain about invalid selections */
 737         WARN_ON((src == DSS_VENC_TV_CLK) && !(outputs & OMAP_DSS_OUTPUT_VENC));
 738         WARN_ON((src == DSS_HDMI_M_PCLK) && !(outputs & OMAP_DSS_OUTPUT_HDMI));
 739
 740         /* Select only if we have options */
 741         if ((outputs & OMAP_DSS_OUTPUT_VENC) &&
 742             (outputs & OMAP_DSS_OUTPUT_HDMI))
 743                 /* VENC_HDMI_SWITCH */
 744                 REG_FLD_MOD(dss, DSS_CONTROL, src, 15, 15);
 745 }
 746
 747 static int dss_dpi_select_source_omap2_omap3(struct dss_device *dss, int port,
 748                                              enum omap_channel channel)
 749 {
 750         if (channel != OMAP_DSS_CHANNEL_LCD)
 751                 return -EINVAL;
 752
 753         return 0;
 754 }
 755
 756 static int dss_dpi_select_source_omap4(struct dss_device *dss, int port,
 757                                        enum omap_channel channel)
 758 {
 759         int val;
 760
 761         switch (channel) {
 762         case OMAP_DSS_CHANNEL_LCD2:
 763                 val = 0;
 764                 break;
 765         case OMAP_DSS_CHANNEL_DIGIT:
 766                 val = 1;
 767                 break;
 768         default:
 769                 return -EINVAL;
 770         }
 771
 772         REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 17);
 773
 774         return 0;
 775 }
 776
 777 static int dss_dpi_select_source_omap5(struct dss_device *dss, int port,
 778                                        enum omap_channel channel)
 779 {
 780         int val;
 781
 782         switch (channel) {
 783         case OMAP_DSS_CHANNEL_LCD:
 784                 val = 1;
 785                 break;
 786         case OMAP_DSS_CHANNEL_LCD2:
 787                 val = 2;
 788                 break;
 789         case OMAP_DSS_CHANNEL_LCD3:
 790                 val = 3;
 791                 break;
 792         case OMAP_DSS_CHANNEL_DIGIT:
 793                 val = 0;
 794                 break;
 795         default:
 796                 return -EINVAL;
 797         }
 798
 799         REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 16);
 800
 801         return 0;
 802 }
 803
 804 static int dss_dpi_select_source_dra7xx(struct dss_device *dss, int port,
 805                                         enum omap_channel channel)
 806 {
 807         switch (port) {
 808         case 0:
 809                 return dss_dpi_select_source_omap5(dss, port, channel);
 810         case 1:
 811                 if (channel != OMAP_DSS_CHANNEL_LCD2)
 812                         return -EINVAL;
 813                 break;
 814         case 2:
 815                 if (channel != OMAP_DSS_CHANNEL_LCD3)
 816                         return -EINVAL;
 817                 break;
 818         default:
 819                 return -EINVAL;
 820         }
 821
 822         return 0;
 823 }
 824
 825 int dss_dpi_select_source(struct dss_device *dss, int port,
 826                           enum omap_channel channel)
 827 {
 828         return dss->feat->ops->dpi_select_source(dss, port, channel);
 829 }
 830
 831 static int dss_get_clocks(struct dss_device *dss)
 832 {
 833         struct clk *clk;
 834
 835         clk = devm_clk_get(&dss->pdev->dev, "fck");
 836         if (IS_ERR(clk)) {
 837                 DSSERR("can't get clock fck\n");
 838                 return PTR_ERR(clk);
 839         }
 840
 841         dss->dss_clk = clk;
 842
 843         if (dss->feat->parent_clk_name) {
 844                 clk = clk_get(NULL, dss->feat->parent_clk_name);
 845                 if (IS_ERR(clk)) {
 846                         DSSERR("Failed to get %s\n",
 847                                dss->feat->parent_clk_name);
 848                         return PTR_ERR(clk);
 849                 }
 850         } else {
 851                 clk = NULL;
 852         }
 853
 854         dss->parent_clk = clk;
 855
 856         return 0;
 857 }
 858
 859 static void dss_put_clocks(struct dss_device *dss)
 860 {
 861         if (dss->parent_clk)
 862                 clk_put(dss->parent_clk);
 863 }
 864
 865 int dss_runtime_get(struct dss_device *dss)
 866 {
 867         int r;
 868
 869         DSSDBG("dss_runtime_get\n");
 870
 871         r = pm_runtime_get_sync(&dss->pdev->dev);
 872         WARN_ON(r < 0);
 873         return r < 0 ? r : 0;
 874 }
 875
 876 void dss_runtime_put(struct dss_device *dss)
 877 {
 878         int r;
 879
 880         DSSDBG("dss_runtime_put\n");
 881
 882         r = pm_runtime_put_sync(&dss->pdev->dev);
 883         WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY);
 884 }
 885
 886 struct dss_device *dss_get_device(struct device *dev)
 887 {
 888         return dev_get_drvdata(dev);
 889 }
 890
 891 /* DEBUGFS */
 892 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
 893 static int dss_initialize_debugfs(struct dss_device *dss)
 894 {
 895         struct dentry *dir;
 896
 897         dir = debugfs_create_dir("omapdss", NULL);
 898         if (IS_ERR(dir))
 899                 return PTR_ERR(dir);
 900
 901         dss->debugfs.root = dir;
 902
 903         return 0;
 904 }
 905
 906 static void dss_uninitialize_debugfs(struct dss_device *dss)
 907 {
 908         debugfs_remove_recursive(dss->debugfs.root);
 909 }
 910
 911 struct dss_debugfs_entry {
 912         struct dentry *dentry;
 913         int (*show_fn)(struct seq_file *s, void *data);
 914         void *data;
 915 };
 916
 917 static int dss_debug_open(struct inode *inode, struct file *file)
 918 {
 919         struct dss_debugfs_entry *entry = inode->i_private;
 920
 921         return single_open(file, entry->show_fn, entry->data);
 922 }
 923
 924 static const struct file_operations dss_debug_fops = {
 925         .open           = dss_debug_open,
 926         .read           = seq_read,
 927         .llseek         = seq_lseek,
 928         .release        = single_release,
 929 };
 930
 931 struct dss_debugfs_entry *
 932 dss_debugfs_create_file(struct dss_device *dss, const char *name,
 933                         int (*show_fn)(struct seq_file *s, void *data),
 934                         void *data)
 935 {
 936         struct dss_debugfs_entry *entry;
 937         struct dentry *d;
 938
 939         entry = kzalloc(sizeof(*entry), GFP_KERNEL);
 940         if (!entry)
 941                 return ERR_PTR(-ENOMEM);
 942
 943         entry->show_fn = show_fn;
 944         entry->data = data;
 945
 946         d = debugfs_create_file(name, 0444, dss->debugfs.root, entry,
 947                                 &dss_debug_fops);
 948         if (IS_ERR(d)) {
 949                 kfree(entry);
 950                 return ERR_CAST(d);
 951         }
 952
 953         entry->dentry = d;
 954         return entry;
 955 }
 956
 957 void dss_debugfs_remove_file(struct dss_debugfs_entry *entry)
 958 {
 959         if (IS_ERR_OR_NULL(entry))
 960                 return;
 961
 962         debugfs_remove(entry->dentry);
 963         kfree(entry);
 964 }
 965
 966 #else /* CONFIG_OMAP2_DSS_DEBUGFS */
 967 static inline int dss_initialize_debugfs(struct dss_device *dss)
 968 {
 969         return 0;
 970 }
 971 static inline void dss_uninitialize_debugfs(struct dss_device *dss)
 972 {
 973 }
 974 #endif /* CONFIG_OMAP2_DSS_DEBUGFS */
 975
 976 static const struct dss_ops dss_ops_omap2_omap3 = {
 977         .dpi_select_source = &dss_dpi_select_source_omap2_omap3,
 978 };
 979
 980 static const struct dss_ops dss_ops_omap4 = {
 981         .dpi_select_source = &dss_dpi_select_source_omap4,
 982         .select_lcd_source = &dss_lcd_clk_mux_omap4,
 983 };
 984
 985 static const struct dss_ops dss_ops_omap5 = {
 986         .dpi_select_source = &dss_dpi_select_source_omap5,
 987         .select_lcd_source = &dss_lcd_clk_mux_omap5,
 988 };
 989
 990 static const struct dss_ops dss_ops_dra7 = {
 991         .dpi_select_source = &dss_dpi_select_source_dra7xx,
 992         .select_lcd_source = &dss_lcd_clk_mux_dra7,
 993 };
 994
 995 static const enum omap_display_type omap2plus_ports[] = {
 996         OMAP_DISPLAY_TYPE_DPI,
 997 };
 998
 999 static const enum omap_display_type omap34xx_ports[] = {
1000         OMAP_DISPLAY_TYPE_DPI,
1001         OMAP_DISPLAY_TYPE_SDI,
1002 };
1003
1004 static const enum omap_display_type dra7xx_ports[] = {
1005         OMAP_DISPLAY_TYPE_DPI,
1006         OMAP_DISPLAY_TYPE_DPI,
1007         OMAP_DISPLAY_TYPE_DPI,
1008 };
1009
1010 static const enum omap_dss_output_id omap2_dss_supported_outputs[] = {
1011         /* OMAP_DSS_CHANNEL_LCD */
1012         OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI,
1013
1014         /* OMAP_DSS_CHANNEL_DIGIT */
1015         OMAP_DSS_OUTPUT_VENC,
1016 };
1017
1018 static const enum omap_dss_output_id omap3430_dss_supported_outputs[] = {
1019         /* OMAP_DSS_CHANNEL_LCD */
1020         OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
1021         OMAP_DSS_OUTPUT_SDI | OMAP_DSS_OUTPUT_DSI1,
1022
1023         /* OMAP_DSS_CHANNEL_DIGIT */
1024         OMAP_DSS_OUTPUT_VENC,
1025 };
1026
1027 static const enum omap_dss_output_id omap3630_dss_supported_outputs[] = {
1028         /* OMAP_DSS_CHANNEL_LCD */
1029         OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
1030         OMAP_DSS_OUTPUT_DSI1,
1031
1032         /* OMAP_DSS_CHANNEL_DIGIT */
1033         OMAP_DSS_OUTPUT_VENC,
1034 };
1035
1036 static const enum omap_dss_output_id am43xx_dss_supported_outputs[] = {
1037         /* OMAP_DSS_CHANNEL_LCD */
1038         OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI,
1039 };
1040
1041 static const enum omap_dss_output_id omap4_dss_supported_outputs[] = {
1042         /* OMAP_DSS_CHANNEL_LCD */
1043         OMAP_DSS_OUTPUT_DBI | OMAP_DSS_OUTPUT_DSI1,
1044
1045         /* OMAP_DSS_CHANNEL_DIGIT */
1046         OMAP_DSS_OUTPUT_VENC | OMAP_DSS_OUTPUT_HDMI,
1047
1048         /* OMAP_DSS_CHANNEL_LCD2 */
1049         OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
1050         OMAP_DSS_OUTPUT_DSI2,
1051 };
1052
1053 static const enum omap_dss_output_id omap5_dss_supported_outputs[] = {
1054         /* OMAP_DSS_CHANNEL_LCD */
1055         OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
1056         OMAP_DSS_OUTPUT_DSI1 | OMAP_DSS_OUTPUT_DSI2,
1057
1058         /* OMAP_DSS_CHANNEL_DIGIT */
1059         OMAP_DSS_OUTPUT_HDMI,
1060
1061         /* OMAP_DSS_CHANNEL_LCD2 */
1062         OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
1063         OMAP_DSS_OUTPUT_DSI1,
1064
1065         /* OMAP_DSS_CHANNEL_LCD3 */
1066         OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
1067         OMAP_DSS_OUTPUT_DSI2,
1068 };
1069
1070 static const struct dss_features omap24xx_dss_feats = {
1071         .model                  =       DSS_MODEL_OMAP2,
1072         /*
1073          * fck div max is really 16, but the divider range has gaps. The range
1074          * from 1 to 6 has no gaps, so let's use that as a max.
1075          */
1076         .fck_div_max            =       6,
1077         .fck_freq_max           =       133000000,
1078         .dss_fck_multiplier     =       2,
1079         .parent_clk_name        =       "core_ck",
1080         .ports                  =       omap2plus_ports,
1081         .num_ports              =       ARRAY_SIZE(omap2plus_ports),
1082         .outputs                =       omap2_dss_supported_outputs,
1083         .ops                    =       &dss_ops_omap2_omap3,
1084         .dispc_clk_switch       =       { 0, 0 },
1085         .has_lcd_clk_src        =       false,
1086 };
1087
1088 static const struct dss_features omap34xx_dss_feats = {
1089         .model                  =       DSS_MODEL_OMAP3,
1090         .fck_div_max            =       16,
1091         .fck_freq_max           =       173000000,
1092         .dss_fck_multiplier     =       2,
1093         .parent_clk_name        =       "dpll4_ck",
1094         .ports                  =       omap34xx_ports,
1095         .outputs                =       omap3430_dss_supported_outputs,
1096         .num_ports              =       ARRAY_SIZE(omap34xx_ports),
1097         .ops                    =       &dss_ops_omap2_omap3,
1098         .dispc_clk_switch       =       { 0, 0 },
1099         .has_lcd_clk_src        =       false,
1100 };
1101
1102 static const struct dss_features omap3630_dss_feats = {
1103         .model                  =       DSS_MODEL_OMAP3,
1104         .fck_div_max            =       32,
1105         .fck_freq_max           =       173000000,
1106         .dss_fck_multiplier     =       1,
1107         .parent_clk_name        =       "dpll4_ck",
1108         .ports                  =       omap2plus_ports,
1109         .num_ports              =       ARRAY_SIZE(omap2plus_ports),
1110         .outputs                =       omap3630_dss_supported_outputs,
1111         .ops                    =       &dss_ops_omap2_omap3,
1112         .dispc_clk_switch       =       { 0, 0 },
1113         .has_lcd_clk_src        =       false,
1114 };
1115
1116 static const struct dss_features omap44xx_dss_feats = {
1117         .model                  =       DSS_MODEL_OMAP4,
1118         .fck_div_max            =       32,
1119         .fck_freq_max           =       186000000,
1120         .dss_fck_multiplier     =       1,
1121         .parent_clk_name        =       "dpll_per_x2_ck",
1122         .ports                  =       omap2plus_ports,
1123         .num_ports              =       ARRAY_SIZE(omap2plus_ports),
1124         .outputs                =       omap4_dss_supported_outputs,
1125         .ops                    =       &dss_ops_omap4,
1126         .dispc_clk_switch       =       { 9, 8 },
1127         .has_lcd_clk_src        =       true,
1128 };
1129
1130 static const struct dss_features omap54xx_dss_feats = {
1131         .model                  =       DSS_MODEL_OMAP5,
1132         .fck_div_max            =       64,
1133         .fck_freq_max           =       209250000,
1134         .dss_fck_multiplier     =       1,
1135         .parent_clk_name        =       "dpll_per_x2_ck",
1136         .ports                  =       omap2plus_ports,
1137         .num_ports              =       ARRAY_SIZE(omap2plus_ports),
1138         .outputs                =       omap5_dss_supported_outputs,
1139         .ops                    =       &dss_ops_omap5,
1140         .dispc_clk_switch       =       { 9, 7 },
1141         .has_lcd_clk_src        =       true,
1142 };
1143
1144 static const struct dss_features am43xx_dss_feats = {
1145         .model                  =       DSS_MODEL_OMAP3,
1146         .fck_div_max            =       0,
1147         .fck_freq_max           =       200000000,
1148         .dss_fck_multiplier     =       0,
1149         .parent_clk_name        =       NULL,
1150         .ports                  =       omap2plus_ports,
1151         .num_ports              =       ARRAY_SIZE(omap2plus_ports),
1152         .outputs                =       am43xx_dss_supported_outputs,
1153         .ops                    =       &dss_ops_omap2_omap3,
1154         .dispc_clk_switch       =       { 0, 0 },
1155         .has_lcd_clk_src        =       true,
1156 };
1157
1158 static const struct dss_features dra7xx_dss_feats = {
1159         .model                  =       DSS_MODEL_DRA7,
1160         .fck_div_max            =       64,
1161         .fck_freq_max           =       209250000,
1162         .dss_fck_multiplier     =       1,
1163         .parent_clk_name        =       "dpll_per_x2_ck",
1164         .ports                  =       dra7xx_ports,
1165         .num_ports              =       ARRAY_SIZE(dra7xx_ports),
1166         .outputs                =       omap5_dss_supported_outputs,
1167         .ops                    =       &dss_ops_dra7,
1168         .dispc_clk_switch       =       { 9, 7 },
1169         .has_lcd_clk_src        =       true,
1170 };
1171
1172 static int dss_init_ports(struct dss_device *dss)
1173 {
1174         struct platform_device *pdev = dss->pdev;
1175         struct device_node *parent = pdev->dev.of_node;
1176         struct device_node *port;
1177         unsigned int i;
1178         int r;
1179
1180         for (i = 0; i < dss->feat->num_ports; i++) {
1181                 port = of_graph_get_port_by_id(parent, i);
1182                 if (!port)
1183                         continue;
1184
1185                 switch (dss->feat->ports[i]) {
1186                 case OMAP_DISPLAY_TYPE_DPI:
1187                         r = dpi_init_port(dss, pdev, port, dss->feat->model);
1188                         if (r)
1189                                 return r;
1190                         break;
1191
1192                 case OMAP_DISPLAY_TYPE_SDI:
1193                         r = sdi_init_port(dss, pdev, port);
1194                         if (r)
1195                                 return r;
1196                         break;
1197
1198                 default:
1199                         break;
1200                 }
1201         }
1202
1203         return 0;
1204 }
1205
1206 static void dss_uninit_ports(struct dss_device *dss)
1207 {
1208         struct platform_device *pdev = dss->pdev;
1209         struct device_node *parent = pdev->dev.of_node;
1210         struct device_node *port;
1211         int i;
1212
1213         for (i = 0; i < dss->feat->num_ports; i++) {
1214                 port = of_graph_get_port_by_id(parent, i);
1215                 if (!port)
1216                         continue;
1217
1218                 switch (dss->feat->ports[i]) {
1219                 case OMAP_DISPLAY_TYPE_DPI:
1220                         dpi_uninit_port(port);
1221                         break;
1222                 case OMAP_DISPLAY_TYPE_SDI:
1223                         sdi_uninit_port(port);
1224                         break;
1225                 default:
1226                         break;
1227                 }
1228         }
1229 }
1230
1231 static int dss_video_pll_probe(struct dss_device *dss)
1232 {
1233         struct platform_device *pdev = dss->pdev;
1234         struct device_node *np = pdev->dev.of_node;
1235         struct regulator *pll_regulator;
1236         int r;
1237
1238         if (!np)
1239                 return 0;
1240
1241         if (of_property_read_bool(np, "syscon-pll-ctrl")) {
1242                 dss->syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np,
1243                         "syscon-pll-ctrl");
1244                 if (IS_ERR(dss->syscon_pll_ctrl)) {
1245                         dev_err(&pdev->dev,
1246                                 "failed to get syscon-pll-ctrl regmap\n");
1247                         return PTR_ERR(dss->syscon_pll_ctrl);
1248                 }
1249
1250                 if (of_property_read_u32_index(np, "syscon-pll-ctrl", 1,
1251                                 &dss->syscon_pll_ctrl_offset)) {
1252                         dev_err(&pdev->dev,
1253                                 "failed to get syscon-pll-ctrl offset\n");
1254                         return -EINVAL;
1255                 }
1256         }
1257
1258         pll_regulator = devm_regulator_get(&pdev->dev, "vdda_video");
1259         if (IS_ERR(pll_regulator)) {
1260                 r = PTR_ERR(pll_regulator);
1261
1262                 switch (r) {
1263                 case -ENOENT:
1264                         pll_regulator = NULL;
1265                         break;
1266
1267                 case -EPROBE_DEFER:
1268                         return -EPROBE_DEFER;
1269
1270                 default:
1271                         DSSERR("can't get DPLL VDDA regulator\n");
1272                         return r;
1273                 }
1274         }
1275
1276         if (of_property_match_string(np, "reg-names", "pll1") >= 0) {
1277                 dss->video1_pll = dss_video_pll_init(dss, pdev, 0,
1278                                                      pll_regulator);
1279                 if (IS_ERR(dss->video1_pll))
1280                         return PTR_ERR(dss->video1_pll);
1281         }
1282
1283         if (of_property_match_string(np, "reg-names", "pll2") >= 0) {
1284                 dss->video2_pll = dss_video_pll_init(dss, pdev, 1,
1285                                                      pll_regulator);
1286                 if (IS_ERR(dss->video2_pll)) {
1287                         dss_video_pll_uninit(dss->video1_pll);
1288                         return PTR_ERR(dss->video2_pll);
1289                 }
1290         }
1291
1292         return 0;
1293 }
1294
1295 /* DSS HW IP initialisation */
1296 static const struct of_device_id dss_of_match[] = {
1297         { .compatible = "ti,omap2-dss", .data = &omap24xx_dss_feats },
1298         { .compatible = "ti,omap3-dss", .data = &omap3630_dss_feats },
1299         { .compatible = "ti,omap4-dss", .data = &omap44xx_dss_feats },
1300         { .compatible = "ti,omap5-dss", .data = &omap54xx_dss_feats },
1301         { .compatible = "ti,dra7-dss",  .data = &dra7xx_dss_feats },
1302         {},
1303 };
1304 MODULE_DEVICE_TABLE(of, dss_of_match);
1305
1306 static const struct soc_device_attribute dss_soc_devices[] = {
1307         { .machine = "OMAP3430/3530", .data = &omap34xx_dss_feats },
1308         { .machine = "AM35??",        .data = &omap34xx_dss_feats },
1309         { .family  = "AM43xx",        .data = &am43xx_dss_feats },
1310         { /* sentinel */ }
1311 };
1312
1313 static int dss_bind(struct device *dev)
1314 {
1315         struct dss_device *dss = dev_get_drvdata(dev);
1316         struct platform_device *drm_pdev;
1317         int r;
1318
1319         r = component_bind_all(dev, NULL);
1320         if (r)
1321                 return r;
1322
1323         pm_set_vt_switch(0);
1324
1325         omapdss_set_dss(dss);
1326
1327         drm_pdev = platform_device_register_simple("omapdrm", 0, NULL, 0);
1328         if (IS_ERR(drm_pdev)) {
1329                 component_unbind_all(dev, NULL);
1330                 return PTR_ERR(drm_pdev);
1331         }
1332
1333         dss->drm_pdev = drm_pdev;
1334
1335         return 0;
1336 }
1337
1338 static void dss_unbind(struct device *dev)
1339 {
1340         struct dss_device *dss = dev_get_drvdata(dev);
1341
1342         platform_device_unregister(dss->drm_pdev);
1343
1344         omapdss_set_dss(NULL);
1345
1346         component_unbind_all(dev, NULL);
1347 }
1348
1349 static const struct component_master_ops dss_component_ops = {
1350         .bind = dss_bind,
1351         .unbind = dss_unbind,
1352 };
1353
1354 static int dss_component_compare(struct device *dev, void *data)
1355 {
1356         struct device *child = data;
1357         return dev == child;
1358 }
1359
1360 static int dss_add_child_component(struct device *dev, void *data)
1361 {
1362         struct component_match **match = data;
1363
1364         /*
1365          * HACK
1366          * We don't have a working driver for rfbi, so skip it here always.
1367          * Otherwise dss will never get probed successfully, as it will wait
1368          * for rfbi to get probed.
1369          */
1370         if (strstr(dev_name(dev), "rfbi"))
1371                 return 0;
1372
1373         component_match_add(dev->parent, match, dss_component_compare, dev);
1374
1375         return 0;
1376 }
1377
1378 static int dss_probe_hardware(struct dss_device *dss)
1379 {
1380         u32 rev;
1381         int r;
1382
1383         r = dss_runtime_get(dss);
1384         if (r)
1385                 return r;
1386
1387         dss->dss_clk_rate = clk_get_rate(dss->dss_clk);
1388
1389         /* Select DPLL */
1390         REG_FLD_MOD(dss, DSS_CONTROL, 0, 0, 0);
1391
1392         dss_select_dispc_clk_source(dss, DSS_CLK_SRC_FCK);
1393
1394 #ifdef CONFIG_OMAP2_DSS_VENC
1395         REG_FLD_MOD(dss, DSS_CONTROL, 1, 4, 4); /* venc dac demen */
1396         REG_FLD_MOD(dss, DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
1397         REG_FLD_MOD(dss, DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
1398 #endif
1399         dss->dsi_clk_source[0] = DSS_CLK_SRC_FCK;
1400         dss->dsi_clk_source[1] = DSS_CLK_SRC_FCK;
1401         dss->dispc_clk_source = DSS_CLK_SRC_FCK;
1402         dss->lcd_clk_source[0] = DSS_CLK_SRC_FCK;
1403         dss->lcd_clk_source[1] = DSS_CLK_SRC_FCK;
1404
1405         rev = dss_read_reg(dss, DSS_REVISION);
1406         pr_info("OMAP DSS rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
1407
1408         dss_runtime_put(dss);
1409
1410         return 0;
1411 }
1412
1413 static int dss_probe(struct platform_device *pdev)
1414 {
1415         const struct soc_device_attribute *soc;
1416         struct component_match *match = NULL;
1417         struct resource *dss_mem;
1418         struct dss_device *dss;
1419         int r;
1420
1421         dss = kzalloc(sizeof(*dss), GFP_KERNEL);
1422         if (!dss)
1423                 return -ENOMEM;
1424
1425         dss->pdev = pdev;
1426         platform_set_drvdata(pdev, dss);
1427
1428         r = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1429         if (r) {
1430                 dev_err(&pdev->dev, "Failed to set the DMA mask\n");
1431                 goto err_free_dss;
1432         }
1433
1434         /*
1435          * The various OMAP3-based SoCs can't be told apart using the compatible
1436          * string, use SoC device matching.
1437          */
1438         soc = soc_device_match(dss_soc_devices);
1439         if (soc)
1440                 dss->feat = soc->data;
1441         else
1442                 dss->feat = of_match_device(dss_of_match, &pdev->dev)->data;
1443
1444         /* Map I/O registers, get and setup clocks. */
1445         dss_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1446         dss->base = devm_ioremap_resource(&pdev->dev, dss_mem);
1447         if (IS_ERR(dss->base)) {
1448                 r = PTR_ERR(dss->base);
1449                 goto err_free_dss;
1450         }
1451
1452         r = dss_get_clocks(dss);
1453         if (r)
1454                 goto err_free_dss;
1455
1456         r = dss_setup_default_clock(dss);
1457         if (r)
1458                 goto err_put_clocks;
1459
1460         /* Setup the video PLLs and the DPI and SDI ports. */
1461         r = dss_video_pll_probe(dss);
1462         if (r)
1463                 goto err_put_clocks;
1464
1465         r = dss_init_ports(dss);
1466         if (r)
1467                 goto err_uninit_plls;
1468
1469         /* Enable runtime PM and probe the hardware. */
1470         pm_runtime_enable(&pdev->dev);
1471
1472         r = dss_probe_hardware(dss);
1473         if (r)
1474                 goto err_pm_runtime_disable;
1475
1476         /* Initialize debugfs. */
1477         r = dss_initialize_debugfs(dss);
1478         if (r)
1479                 goto err_pm_runtime_disable;
1480
1481         dss->debugfs.clk = dss_debugfs_create_file(dss, "clk",
1482                                                    dss_debug_dump_clocks, dss);
1483         dss->debugfs.dss = dss_debugfs_create_file(dss, "dss", dss_dump_regs,
1484                                                    dss);
1485
1486         /* Add all the child devices as components. */
1487         omapdss_gather_components(&pdev->dev);
1488
1489         device_for_each_child(&pdev->dev, &match, dss_add_child_component);
1490
1491         r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match);
1492         if (r)
1493                 goto err_uninit_debugfs;
1494
1495         return 0;
1496
1497 err_uninit_debugfs:
1498         dss_debugfs_remove_file(dss->debugfs.clk);
1499         dss_debugfs_remove_file(dss->debugfs.dss);
1500         dss_uninitialize_debugfs(dss);
1501
1502 err_pm_runtime_disable:
1503         pm_runtime_disable(&pdev->dev);
1504         dss_uninit_ports(dss);
1505
1506 err_uninit_plls:
1507         if (dss->video1_pll)
1508                 dss_video_pll_uninit(dss->video1_pll);
1509         if (dss->video2_pll)
1510                 dss_video_pll_uninit(dss->video2_pll);
1511
1512 err_put_clocks:
1513         dss_put_clocks(dss);
1514
1515 err_free_dss:
1516         kfree(dss);
1517
1518         return r;
1519 }
1520
1521 static int dss_remove(struct platform_device *pdev)
1522 {
1523         struct dss_device *dss = platform_get_drvdata(pdev);
1524
1525         component_master_del(&pdev->dev, &dss_component_ops);
1526
1527         dss_debugfs_remove_file(dss->debugfs.clk);
1528         dss_debugfs_remove_file(dss->debugfs.dss);
1529         dss_uninitialize_debugfs(dss);
1530
1531         pm_runtime_disable(&pdev->dev);
1532
1533         dss_uninit_ports(dss);
1534
1535         if (dss->video1_pll)
1536                 dss_video_pll_uninit(dss->video1_pll);
1537
1538         if (dss->video2_pll)
1539                 dss_video_pll_uninit(dss->video2_pll);
1540
1541         dss_put_clocks(dss);
1542
1543         kfree(dss);
1544
1545         return 0;
1546 }
1547
1548 static void dss_shutdown(struct platform_device *pdev)
1549 {
1550         struct omap_dss_device *dssdev = NULL;
1551
1552         DSSDBG("shutdown\n");
1553
1554         for_each_dss_display(dssdev) {
1555                 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
1556                         dssdev->ops->disable(dssdev);
1557         }
1558 }
1559
1560 static int dss_runtime_suspend(struct device *dev)
1561 {
1562         struct dss_device *dss = dev_get_drvdata(dev);
1563
1564         dss_save_context(dss);
1565         dss_set_min_bus_tput(dev, 0);
1566
1567         pinctrl_pm_select_sleep_state(dev);
1568
1569         return 0;
1570 }
1571
1572 static int dss_runtime_resume(struct device *dev)
1573 {
1574         struct dss_device *dss = dev_get_drvdata(dev);
1575         int r;
1576
1577         pinctrl_pm_select_default_state(dev);
1578
1579         /*
1580          * Set an arbitrarily high tput request to ensure OPP100.
1581          * What we should really do is to make a request to stay in OPP100,
1582          * without any tput requirements, but that is not currently possible
1583          * via the PM layer.
1584          */
1585
1586         r = dss_set_min_bus_tput(dev, 1000000000);
1587         if (r)
1588                 return r;
1589
1590         dss_restore_context(dss);
1591         return 0;
1592 }
1593
1594 static const struct dev_pm_ops dss_pm_ops = {
1595         .runtime_suspend = dss_runtime_suspend,
1596         .runtime_resume = dss_runtime_resume,
1597 };
1598
1599 struct platform_driver omap_dsshw_driver = {
1600         .probe          = dss_probe,
1601         .remove         = dss_remove,
1602         .shutdown       = dss_shutdown,
1603         .driver         = {
1604                 .name   = "omapdss_dss",
1605                 .pm     = &dss_pm_ops,
1606                 .of_match_table = dss_of_match,
1607                 .suppress_bind_attrs = true,
1608         },
1609 };