drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26
  27 #include <drm/drmP.h>
  28 #include <drm/drm_atomic.h>
  29 #include <drm/drm_atomic_helper.h>
  30 #include <drm/drm_crtc_helper.h>
  31 #include <drm/drm_dp_helper.h>
  32 #include <drm/drm_fb_helper.h>
  33 #include <drm/drm_plane_helper.h>
  34
  35 #include <nvif/class.h>
  36 #include <nvif/cl0002.h>
  37 #include <nvif/cl5070.h>
  38 #include <nvif/cl507a.h>
  39 #include <nvif/cl507b.h>
  40 #include <nvif/cl507c.h>
  41 #include <nvif/cl507d.h>
  42 #include <nvif/cl507e.h>
  43 #include <nvif/event.h>
  44
  45 #include "nouveau_drv.h"
  46 #include "nouveau_dma.h"
  47 #include "nouveau_gem.h"
  48 #include "nouveau_connector.h"
  49 #include "nouveau_encoder.h"
  50 #include "nouveau_crtc.h"
  51 #include "nouveau_fence.h"
  52 #include "nouveau_fbcon.h"
  53 #include "nv50_display.h"
  54
  55 #define EVO_DMA_NR 9
  56
  57 #define EVO_MASTER  (0x00)
  58 #define EVO_FLIP(c) (0x01 + (c))
  59 #define EVO_OVLY(c) (0x05 + (c))
  60 #define EVO_OIMM(c) (0x09 + (c))
  61 #define EVO_CURS(c) (0x0d + (c))
  62
  63 /* offsets in shared sync bo of various structures */
  64 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
  65 #define EVO_MAST_NTFY     EVO_SYNC(      0, 0x00)
  66 #define EVO_FLIP_SEM0(c)  EVO_SYNC((c) + 1, 0x00)
  67 #define EVO_FLIP_SEM1(c)  EVO_SYNC((c) + 1, 0x10)
  68 #define EVO_FLIP_NTFY0(c) EVO_SYNC((c) + 1, 0x20)
  69 #define EVO_FLIP_NTFY1(c) EVO_SYNC((c) + 1, 0x30)
  70
  71 /******************************************************************************
  72  * Atomic state
  73  *****************************************************************************/
  74 #define nv50_atom(p) container_of((p), struct nv50_atom, state)
  75
  76 struct nv50_atom {
  77         struct drm_atomic_state state;
  78
  79         struct list_head outp;
  80         bool lock_core;
  81         bool flush_disable;
  82 };
  83
  84 struct nv50_outp_atom {
  85         struct list_head head;
  86
  87         struct drm_encoder *encoder;
  88         bool flush_disable;
  89
  90         union {
  91                 struct {
  92                         bool ctrl:1;
  93                 };
  94                 u8 mask;
  95         } clr;
  96
  97         union {
  98                 struct {
  99                         bool ctrl:1;
 100                 };
 101                 u8 mask;
 102         } set;
 103 };
 104
 105 #define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state)
 106
 107 struct nv50_head_atom {
 108         struct drm_crtc_state state;
 109
 110         struct {
 111                 u16 iW;
 112                 u16 iH;
 113                 u16 oW;
 114                 u16 oH;
 115         } view;
 116
 117         struct nv50_head_mode {
 118                 bool interlace;
 119                 u32 clock;
 120                 struct {
 121                         u16 active;
 122                         u16 synce;
 123                         u16 blanke;
 124                         u16 blanks;
 125                 } h;
 126                 struct {
 127                         u32 active;
 128                         u16 synce;
 129                         u16 blanke;
 130                         u16 blanks;
 131                         u16 blank2s;
 132                         u16 blank2e;
 133                         u16 blankus;
 134                 } v;
 135         } mode;
 136
 137         struct {
 138                 u32 handle;
 139                 u64 offset:40;
 140         } lut;
 141
 142         struct {
 143                 bool visible;
 144                 u32 handle;
 145                 u64 offset:40;
 146                 u8  format;
 147                 u8  kind:7;
 148                 u8  layout:1;
 149                 u8  block:4;
 150                 u32 pitch:20;
 151                 u16 x;
 152                 u16 y;
 153                 u16 w;
 154                 u16 h;
 155         } core;
 156
 157         struct {
 158                 bool visible;
 159                 u32 handle;
 160                 u64 offset:40;
 161                 u8  layout:1;
 162                 u8  format:1;
 163         } curs;
 164
 165         struct {
 166                 u8  depth;
 167                 u8  cpp;
 168                 u16 x;
 169                 u16 y;
 170                 u16 w;
 171                 u16 h;
 172         } base;
 173
 174         struct {
 175                 u8 cpp;
 176         } ovly;
 177
 178         struct {
 179                 bool enable:1;
 180                 u8 bits:2;
 181                 u8 mode:4;
 182         } dither;
 183
 184         struct {
 185                 struct {
 186                         u16 cos:12;
 187                         u16 sin:12;
 188                 } sat;
 189         } procamp;
 190
 191         union {
 192                 struct {
 193                         bool core:1;
 194                         bool curs:1;
 195                 };
 196                 u8 mask;
 197         } clr;
 198
 199         union {
 200                 struct {
 201                         bool core:1;
 202                         bool curs:1;
 203                         bool view:1;
 204                         bool mode:1;
 205                         bool base:1;
 206                         bool ovly:1;
 207                         bool dither:1;
 208                         bool procamp:1;
 209                 };
 210                 u16 mask;
 211         } set;
 212 };
 213
 214 static inline struct nv50_head_atom *
 215 nv50_head_atom_get(struct drm_atomic_state *state, struct drm_crtc *crtc)
 216 {
 217         struct drm_crtc_state *statec = drm_atomic_get_crtc_state(state, crtc);
 218         if (IS_ERR(statec))
 219                 return (void *)statec;
 220         return nv50_head_atom(statec);
 221 }
 222
 223 #define nv50_wndw_atom(p) container_of((p), struct nv50_wndw_atom, state)
 224
 225 struct nv50_wndw_atom {
 226         struct drm_plane_state state;
 227         u8 interval;
 228
 229         struct drm_rect clip;
 230
 231         struct {
 232                 u32  handle;
 233                 u16  offset:12;
 234                 bool awaken:1;
 235         } ntfy;
 236
 237         struct {
 238                 u32 handle;
 239                 u16 offset:12;
 240                 u32 acquire;
 241                 u32 release;
 242         } sema;
 243
 244         struct {
 245                 u8 enable:2;
 246         } lut;
 247
 248         struct {
 249                 u8  mode:2;
 250                 u8  interval:4;
 251
 252                 u8  format;
 253                 u8  kind:7;
 254                 u8  layout:1;
 255                 u8  block:4;
 256                 u32 pitch:20;
 257                 u16 w;
 258                 u16 h;
 259
 260                 u32 handle;
 261                 u64 offset;
 262         } image;
 263
 264         struct {
 265                 u16 x;
 266                 u16 y;
 267         } point;
 268
 269         union {
 270                 struct {
 271                         bool ntfy:1;
 272                         bool sema:1;
 273                         bool image:1;
 274                 };
 275                 u8 mask;
 276         } clr;
 277
 278         union {
 279                 struct {
 280                         bool ntfy:1;
 281                         bool sema:1;
 282                         bool image:1;
 283                         bool lut:1;
 284                         bool point:1;
 285                 };
 286                 u8 mask;
 287         } set;
 288 };
 289
 290 /******************************************************************************
 291  * EVO channel
 292  *****************************************************************************/
 293
 294 struct nv50_chan {
 295         struct nvif_object user;
 296         struct nvif_device *device;
 297 };
 298
 299 static int
 300 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
 301                  const s32 *oclass, u8 head, void *data, u32 size,
 302                  struct nv50_chan *chan)
 303 {
 304         struct nvif_sclass *sclass;
 305         int ret, i, n;
 306
 307         chan->device = device;
 308
 309         ret = n = nvif_object_sclass_get(disp, &sclass);
 310         if (ret < 0)
 311                 return ret;
 312
 313         while (oclass[0]) {
 314                 for (i = 0; i < n; i++) {
 315                         if (sclass[i].oclass == oclass[0]) {
 316                                 ret = nvif_object_init(disp, 0, oclass[0],
 317                                                        data, size, &chan->user);
 318                                 if (ret == 0)
 319                                         nvif_object_map(&chan->user);
 320                                 nvif_object_sclass_put(&sclass);
 321                                 return ret;
 322                         }
 323                 }
 324                 oclass++;
 325         }
 326
 327         nvif_object_sclass_put(&sclass);
 328         return -ENOSYS;
 329 }
 330
 331 static void
 332 nv50_chan_destroy(struct nv50_chan *chan)
 333 {
 334         nvif_object_fini(&chan->user);
 335 }
 336
 337 /******************************************************************************
 338  * PIO EVO channel
 339  *****************************************************************************/
 340
 341 struct nv50_pioc {
 342         struct nv50_chan base;
 343 };
 344
 345 static void
 346 nv50_pioc_destroy(struct nv50_pioc *pioc)
 347 {
 348         nv50_chan_destroy(&pioc->base);
 349 }
 350
 351 static int
 352 nv50_pioc_create(struct nvif_device *device, struct nvif_object *disp,
 353                  const s32 *oclass, u8 head, void *data, u32 size,
 354                  struct nv50_pioc *pioc)
 355 {
 356         return nv50_chan_create(device, disp, oclass, head, data, size,
 357                                 &pioc->base);
 358 }
 359
 360 /******************************************************************************
 361  * Overlay Immediate
 362  *****************************************************************************/
 363
 364 struct nv50_oimm {
 365         struct nv50_pioc base;
 366 };
 367
 368 static int
 369 nv50_oimm_create(struct nvif_device *device, struct nvif_object *disp,
 370                  int head, struct nv50_oimm *oimm)
 371 {
 372         struct nv50_disp_cursor_v0 args = {
 373                 .head = head,
 374         };
 375         static const s32 oclass[] = {
 376                 GK104_DISP_OVERLAY,
 377                 GF110_DISP_OVERLAY,
 378                 GT214_DISP_OVERLAY,
 379                 G82_DISP_OVERLAY,
 380                 NV50_DISP_OVERLAY,
 381                 0
 382         };
 383
 384         return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args),
 385                                 &oimm->base);
 386 }
 387
 388 /******************************************************************************
 389  * DMA EVO channel
 390  *****************************************************************************/
 391
 392 struct nv50_dmac_ctxdma {
 393         struct list_head head;
 394         struct nvif_object object;
 395 };
 396
 397 struct nv50_dmac {
 398         struct nv50_chan base;
 399         dma_addr_t handle;
 400         u32 *ptr;
 401
 402         struct nvif_object sync;
 403         struct nvif_object vram;
 404         struct list_head ctxdma;
 405
 406         /* Protects against concurrent pushbuf access to this channel, lock is
 407          * grabbed by evo_wait (if the pushbuf reservation is successful) and
 408          * dropped again by evo_kick. */
 409         struct mutex lock;
 410 };
 411
 412 static void
 413 nv50_dmac_ctxdma_del(struct nv50_dmac_ctxdma *ctxdma)
 414 {
 415         nvif_object_fini(&ctxdma->object);
 416         list_del(&ctxdma->head);
 417         kfree(ctxdma);
 418 }
 419
 420 static struct nv50_dmac_ctxdma *
 421 nv50_dmac_ctxdma_new(struct nv50_dmac *dmac, struct nouveau_framebuffer *fb)
 422 {
 423         struct nouveau_drm *drm = nouveau_drm(fb->base.dev);
 424         struct nv50_dmac_ctxdma *ctxdma;
 425         const u8    kind = (fb->nvbo->tile_flags & 0x0000ff00) >> 8;
 426         const u32 handle = 0xfb000000 | kind;
 427         struct {
 428                 struct nv_dma_v0 base;
 429                 union {
 430                         struct nv50_dma_v0 nv50;
 431                         struct gf100_dma_v0 gf100;
 432                         struct gf119_dma_v0 gf119;
 433                 };
 434         } args = {};
 435         u32 argc = sizeof(args.base);
 436         int ret;
 437
 438         list_for_each_entry(ctxdma, &dmac->ctxdma, head) {
 439                 if (ctxdma->object.handle == handle)
 440                         return ctxdma;
 441         }
 442
 443         if (!(ctxdma = kzalloc(sizeof(*ctxdma), GFP_KERNEL)))
 444                 return ERR_PTR(-ENOMEM);
 445         list_add(&ctxdma->head, &dmac->ctxdma);
 446
 447         args.base.target = NV_DMA_V0_TARGET_VRAM;
 448         args.base.access = NV_DMA_V0_ACCESS_RDWR;
 449         args.base.start  = 0;
 450         args.base.limit  = drm->client.device.info.ram_user - 1;
 451
 452         if (drm->client.device.info.chipset < 0x80) {
 453                 args.nv50.part = NV50_DMA_V0_PART_256;
 454                 argc += sizeof(args.nv50);
 455         } else
 456         if (drm->client.device.info.chipset < 0xc0) {
 457                 args.nv50.part = NV50_DMA_V0_PART_256;
 458                 args.nv50.kind = kind;
 459                 argc += sizeof(args.nv50);
 460         } else
 461         if (drm->client.device.info.chipset < 0xd0) {
 462                 args.gf100.kind = kind;
 463                 argc += sizeof(args.gf100);
 464         } else {
 465                 args.gf119.page = GF119_DMA_V0_PAGE_LP;
 466                 args.gf119.kind = kind;
 467                 argc += sizeof(args.gf119);
 468         }
 469
 470         ret = nvif_object_init(&dmac->base.user, handle, NV_DMA_IN_MEMORY,
 471                                &args, argc, &ctxdma->object);
 472         if (ret) {
 473                 nv50_dmac_ctxdma_del(ctxdma);
 474                 return ERR_PTR(ret);
 475         }
 476
 477         return ctxdma;
 478 }
 479
 480 static void
 481 nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp)
 482 {
 483         struct nvif_device *device = dmac->base.device;
 484         struct nv50_dmac_ctxdma *ctxdma, *ctxtmp;
 485
 486         list_for_each_entry_safe(ctxdma, ctxtmp, &dmac->ctxdma, head) {
 487                 nv50_dmac_ctxdma_del(ctxdma);
 488         }
 489
 490         nvif_object_fini(&dmac->vram);
 491         nvif_object_fini(&dmac->sync);
 492
 493         nv50_chan_destroy(&dmac->base);
 494
 495         if (dmac->ptr) {
 496                 struct device *dev = nvxx_device(device)->dev;
 497                 dma_free_coherent(dev, PAGE_SIZE, dmac->ptr, dmac->handle);
 498         }
 499 }
 500
 501 static int
 502 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 503                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 504                  struct nv50_dmac *dmac)
 505 {
 506         struct nv50_disp_core_channel_dma_v0 *args = data;
 507         struct nvif_object pushbuf;
 508         int ret;
 509
 510         mutex_init(&dmac->lock);
 511
 512         dmac->ptr = dma_alloc_coherent(nvxx_device(device)->dev, PAGE_SIZE,
 513                                        &dmac->handle, GFP_KERNEL);
 514         if (!dmac->ptr)
 515                 return -ENOMEM;
 516
 517         ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY,
 518                                &(struct nv_dma_v0) {
 519                                         .target = NV_DMA_V0_TARGET_PCI_US,
 520                                         .access = NV_DMA_V0_ACCESS_RD,
 521                                         .start = dmac->handle + 0x0000,
 522                                         .limit = dmac->handle + 0x0fff,
 523                                }, sizeof(struct nv_dma_v0), &pushbuf);
 524         if (ret)
 525                 return ret;
 526
 527         args->pushbuf = nvif_handle(&pushbuf);
 528
 529         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 530                                &dmac->base);
 531         nvif_object_fini(&pushbuf);
 532         if (ret)
 533                 return ret;
 534
 535         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 536                                &(struct nv_dma_v0) {
 537                                         .target = NV_DMA_V0_TARGET_VRAM,
 538                                         .access = NV_DMA_V0_ACCESS_RDWR,
 539                                         .start = syncbuf + 0x0000,
 540                                         .limit = syncbuf + 0x0fff,
 541                                }, sizeof(struct nv_dma_v0),
 542                                &dmac->sync);
 543         if (ret)
 544                 return ret;
 545
 546         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 547                                &(struct nv_dma_v0) {
 548                                         .target = NV_DMA_V0_TARGET_VRAM,
 549                                         .access = NV_DMA_V0_ACCESS_RDWR,
 550                                         .start = 0,
 551                                         .limit = device->info.ram_user - 1,
 552                                }, sizeof(struct nv_dma_v0),
 553                                &dmac->vram);
 554         if (ret)
 555                 return ret;
 556
 557         INIT_LIST_HEAD(&dmac->ctxdma);
 558         return ret;
 559 }
 560
 561 /******************************************************************************
 562  * Core
 563  *****************************************************************************/
 564
 565 struct nv50_mast {
 566         struct nv50_dmac base;
 567 };
 568
 569 static int
 570 nv50_core_create(struct nvif_device *device, struct nvif_object *disp,
 571                  u64 syncbuf, struct nv50_mast *core)
 572 {
 573         struct nv50_disp_core_channel_dma_v0 args = {
 574                 .pushbuf = 0xb0007d00,
 575         };
 576         static const s32 oclass[] = {
 577                 GP102_DISP_CORE_CHANNEL_DMA,
 578                 GP100_DISP_CORE_CHANNEL_DMA,
 579                 GM200_DISP_CORE_CHANNEL_DMA,
 580                 GM107_DISP_CORE_CHANNEL_DMA,
 581                 GK110_DISP_CORE_CHANNEL_DMA,
 582                 GK104_DISP_CORE_CHANNEL_DMA,
 583                 GF110_DISP_CORE_CHANNEL_DMA,
 584                 GT214_DISP_CORE_CHANNEL_DMA,
 585                 GT206_DISP_CORE_CHANNEL_DMA,
 586                 GT200_DISP_CORE_CHANNEL_DMA,
 587                 G82_DISP_CORE_CHANNEL_DMA,
 588                 NV50_DISP_CORE_CHANNEL_DMA,
 589                 0
 590         };
 591
 592         return nv50_dmac_create(device, disp, oclass, 0, &args, sizeof(args),
 593                                 syncbuf, &core->base);
 594 }
 595
 596 /******************************************************************************
 597  * Base
 598  *****************************************************************************/
 599
 600 struct nv50_sync {
 601         struct nv50_dmac base;
 602         u32 addr;
 603         u32 data;
 604 };
 605
 606 static int
 607 nv50_base_create(struct nvif_device *device, struct nvif_object *disp,
 608                  int head, u64 syncbuf, struct nv50_sync *base)
 609 {
 610         struct nv50_disp_base_channel_dma_v0 args = {
 611                 .pushbuf = 0xb0007c00 | head,
 612                 .head = head,
 613         };
 614         static const s32 oclass[] = {
 615                 GK110_DISP_BASE_CHANNEL_DMA,
 616                 GK104_DISP_BASE_CHANNEL_DMA,
 617                 GF110_DISP_BASE_CHANNEL_DMA,
 618                 GT214_DISP_BASE_CHANNEL_DMA,
 619                 GT200_DISP_BASE_CHANNEL_DMA,
 620                 G82_DISP_BASE_CHANNEL_DMA,
 621                 NV50_DISP_BASE_CHANNEL_DMA,
 622                 0
 623         };
 624
 625         return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
 626                                 syncbuf, &base->base);
 627 }
 628
 629 /******************************************************************************
 630  * Overlay
 631  *****************************************************************************/
 632
 633 struct nv50_ovly {
 634         struct nv50_dmac base;
 635 };
 636
 637 static int
 638 nv50_ovly_create(struct nvif_device *device, struct nvif_object *disp,
 639                  int head, u64 syncbuf, struct nv50_ovly *ovly)
 640 {
 641         struct nv50_disp_overlay_channel_dma_v0 args = {
 642                 .pushbuf = 0xb0007e00 | head,
 643                 .head = head,
 644         };
 645         static const s32 oclass[] = {
 646                 GK104_DISP_OVERLAY_CONTROL_DMA,
 647                 GF110_DISP_OVERLAY_CONTROL_DMA,
 648                 GT214_DISP_OVERLAY_CHANNEL_DMA,
 649                 GT200_DISP_OVERLAY_CHANNEL_DMA,
 650                 G82_DISP_OVERLAY_CHANNEL_DMA,
 651                 NV50_DISP_OVERLAY_CHANNEL_DMA,
 652                 0
 653         };
 654
 655         return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
 656                                 syncbuf, &ovly->base);
 657 }
 658
 659 struct nv50_head {
 660         struct nouveau_crtc base;
 661         struct nv50_ovly ovly;
 662         struct nv50_oimm oimm;
 663 };
 664
 665 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
 666 #define nv50_ovly(c) (&nv50_head(c)->ovly)
 667 #define nv50_oimm(c) (&nv50_head(c)->oimm)
 668 #define nv50_chan(c) (&(c)->base.base)
 669 #define nv50_vers(c) nv50_chan(c)->user.oclass
 670
 671 struct nv50_disp {
 672         struct nvif_object *disp;
 673         struct nv50_mast mast;
 674
 675         struct nouveau_bo *sync;
 676
 677         struct mutex mutex;
 678 };
 679
 680 static struct nv50_disp *
 681 nv50_disp(struct drm_device *dev)
 682 {
 683         return nouveau_display(dev)->priv;
 684 }
 685
 686 #define nv50_mast(d) (&nv50_disp(d)->mast)
 687
 688 /******************************************************************************
 689  * EVO channel helpers
 690  *****************************************************************************/
 691 static u32 *
 692 evo_wait(void *evoc, int nr)
 693 {
 694         struct nv50_dmac *dmac = evoc;
 695         struct nvif_device *device = dmac->base.device;
 696         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 697
 698         mutex_lock(&dmac->lock);
 699         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 700                 dmac->ptr[put] = 0x20000000;
 701
 702                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 703                 if (nvif_msec(device, 2000,
 704                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 705                                 break;
 706                 ) < 0) {
 707                         mutex_unlock(&dmac->lock);
 708                         pr_err("nouveau: evo channel stalled\n");
 709                         return NULL;
 710                 }
 711
 712                 put = 0;
 713         }
 714
 715         return dmac->ptr + put;
 716 }
 717
 718 static void
 719 evo_kick(u32 *push, void *evoc)
 720 {
 721         struct nv50_dmac *dmac = evoc;
 722         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 723         mutex_unlock(&dmac->lock);
 724 }
 725
 726 #define evo_mthd(p, m, s) do {                                          \
 727         const u32 _m = (m), _s = (s);                                   \
 728         if (drm_debug & DRM_UT_KMS)                                     \
 729                 pr_err("%04x %d %s\n", _m, _s, __func__);               \
 730         *((p)++) = ((_s << 18) | _m);                                   \
 731 } while(0)
 732
 733 #define evo_data(p, d) do {                                             \
 734         const u32 _d = (d);                                             \
 735         if (drm_debug & DRM_UT_KMS)                                     \
 736                 pr_err("\t%08x\n", _d);                                 \
 737         *((p)++) = _d;                                                  \
 738 } while(0)
 739
 740 /******************************************************************************
 741  * Plane
 742  *****************************************************************************/
 743 #define nv50_wndw(p) container_of((p), struct nv50_wndw, plane)
 744
 745 struct nv50_wndw {
 746         const struct nv50_wndw_func *func;
 747         struct nv50_dmac *dmac;
 748
 749         struct drm_plane plane;
 750
 751         struct nvif_notify notify;
 752         u16 ntfy;
 753         u16 sema;
 754         u32 data;
 755 };
 756
 757 struct nv50_wndw_func {
 758         void *(*dtor)(struct nv50_wndw *);
 759         int (*acquire)(struct nv50_wndw *, struct nv50_wndw_atom *asyw,
 760                        struct nv50_head_atom *asyh);
 761         void (*release)(struct nv50_wndw *, struct nv50_wndw_atom *asyw,
 762                         struct nv50_head_atom *asyh);
 763         void (*prepare)(struct nv50_wndw *, struct nv50_head_atom *asyh,
 764                         struct nv50_wndw_atom *asyw);
 765
 766         void (*sema_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
 767         void (*sema_clr)(struct nv50_wndw *);
 768         void (*ntfy_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
 769         void (*ntfy_clr)(struct nv50_wndw *);
 770         int (*ntfy_wait_begun)(struct nv50_wndw *, struct nv50_wndw_atom *);
 771         void (*image_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
 772         void (*image_clr)(struct nv50_wndw *);
 773         void (*lut)(struct nv50_wndw *, struct nv50_wndw_atom *);
 774         void (*point)(struct nv50_wndw *, struct nv50_wndw_atom *);
 775
 776         u32 (*update)(struct nv50_wndw *, u32 interlock);
 777 };
 778
 779 static int
 780 nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
 781 {
 782         if (asyw->set.ntfy)
 783                 return wndw->func->ntfy_wait_begun(wndw, asyw);
 784         return 0;
 785 }
 786
 787 static u32
 788 nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 interlock, bool flush,
 789                     struct nv50_wndw_atom *asyw)
 790 {
 791         if (asyw->clr.sema && (!asyw->set.sema || flush))
 792                 wndw->func->sema_clr(wndw);
 793         if (asyw->clr.ntfy && (!asyw->set.ntfy || flush))
 794                 wndw->func->ntfy_clr(wndw);
 795         if (asyw->clr.image && (!asyw->set.image || flush))
 796                 wndw->func->image_clr(wndw);
 797
 798         return flush ? wndw->func->update(wndw, interlock) : 0;
 799 }
 800
 801 static u32
 802 nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 interlock,
 803                     struct nv50_wndw_atom *asyw)
 804 {
 805         if (interlock) {
 806                 asyw->image.mode = 0;
 807                 asyw->image.interval = 1;
 808         }
 809
 810         if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw);
 811         if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw);
 812         if (asyw->set.image) wndw->func->image_set(wndw, asyw);
 813         if (asyw->set.lut  ) wndw->func->lut      (wndw, asyw);
 814         if (asyw->set.point) wndw->func->point    (wndw, asyw);
 815
 816         return wndw->func->update(wndw, interlock);
 817 }
 818
 819 static void
 820 nv50_wndw_atomic_check_release(struct nv50_wndw *wndw,
 821                                struct nv50_wndw_atom *asyw,
 822                                struct nv50_head_atom *asyh)
 823 {
 824         struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
 825         NV_ATOMIC(drm, "%s release\n", wndw->plane.name);
 826         wndw->func->release(wndw, asyw, asyh);
 827         asyw->ntfy.handle = 0;
 828         asyw->sema.handle = 0;
 829 }
 830
 831 static int
 832 nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw,
 833                                struct nv50_wndw_atom *asyw,
 834                                struct nv50_head_atom *asyh,
 835                                u32 pflip_flags)
 836 {
 837         struct nouveau_framebuffer *fb = nouveau_framebuffer(asyw->state.fb);
 838         struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
 839         int ret;
 840
 841         NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name);
 842         asyw->clip.x1 = 0;
 843         asyw->clip.y1 = 0;
 844         asyw->clip.x2 = asyh->state.mode.hdisplay;
 845         asyw->clip.y2 = asyh->state.mode.vdisplay;
 846
 847         asyw->image.w = fb->base.width;
 848         asyw->image.h = fb->base.height;
 849         asyw->image.kind = (fb->nvbo->tile_flags & 0x0000ff00) >> 8;
 850
 851         asyw->interval = pflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ? 0 : 1;
 852
 853         if (asyw->image.kind) {
 854                 asyw->image.layout = 0;
 855                 if (drm->client.device.info.chipset >= 0xc0)
 856                         asyw->image.block = fb->nvbo->tile_mode >> 4;
 857                 else
 858                         asyw->image.block = fb->nvbo->tile_mode;
 859                 asyw->image.pitch = (fb->base.pitches[0] / 4) << 4;
 860         } else {
 861                 asyw->image.layout = 1;
 862                 asyw->image.block  = 0;
 863                 asyw->image.pitch  = fb->base.pitches[0];
 864         }
 865
 866         ret = wndw->func->acquire(wndw, asyw, asyh);
 867         if (ret)
 868                 return ret;
 869
 870         if (asyw->set.image) {
 871                 if (!(asyw->image.mode = asyw->interval ? 0 : 1))
 872                         asyw->image.interval = asyw->interval;
 873                 else
 874                         asyw->image.interval = 0;
 875         }
 876
 877         return 0;
 878 }
 879
 880 static int
 881 nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state)
 882 {
 883         struct nouveau_drm *drm = nouveau_drm(plane->dev);
 884         struct nv50_wndw *wndw = nv50_wndw(plane);
 885         struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state);
 886         struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
 887         struct nv50_head_atom *harm = NULL, *asyh = NULL;
 888         bool varm = false, asyv = false, asym = false;
 889         int ret;
 890         u32 pflip_flags = 0;
 891
 892         NV_ATOMIC(drm, "%s atomic_check\n", plane->name);
 893         if (asyw->state.crtc) {
 894                 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
 895                 if (IS_ERR(asyh))
 896                         return PTR_ERR(asyh);
 897                 asym = drm_atomic_crtc_needs_modeset(&asyh->state);
 898                 asyv = asyh->state.active;
 899                 pflip_flags = asyh->state.pageflip_flags;
 900         }
 901
 902         if (armw->state.crtc) {
 903                 harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc);
 904                 if (IS_ERR(harm))
 905                         return PTR_ERR(harm);
 906                 varm = harm->state.crtc->state->active;
 907         }
 908
 909         if (asyv) {
 910                 asyw->point.x = asyw->state.crtc_x;
 911                 asyw->point.y = asyw->state.crtc_y;
 912                 if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point)))
 913                         asyw->set.point = true;
 914
 915                 if (!varm || asym || armw->state.fb != asyw->state.fb) {
 916                         ret = nv50_wndw_atomic_check_acquire(
 917                                         wndw, asyw, asyh, pflip_flags);
 918                         if (ret)
 919                                 return ret;
 920                 }
 921         } else
 922         if (varm) {
 923                 nv50_wndw_atomic_check_release(wndw, asyw, harm);
 924         } else {
 925                 return 0;
 926         }
 927
 928         if (!asyv || asym) {
 929                 asyw->clr.ntfy = armw->ntfy.handle != 0;
 930                 asyw->clr.sema = armw->sema.handle != 0;
 931                 if (wndw->func->image_clr)
 932                         asyw->clr.image = armw->image.handle != 0;
 933                 asyw->set.lut = wndw->func->lut && asyv;
 934         }
 935
 936         return 0;
 937 }
 938
 939 static void
 940 nv50_wndw_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state)
 941 {
 942         struct nouveau_framebuffer *fb = nouveau_framebuffer(old_state->fb);
 943         struct nouveau_drm *drm = nouveau_drm(plane->dev);
 944
 945         NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb);
 946         if (!old_state->fb)
 947                 return;
 948
 949         nouveau_bo_unpin(fb->nvbo);
 950 }
 951
 952 static int
 953 nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state)
 954 {
 955         struct nouveau_framebuffer *fb = nouveau_framebuffer(state->fb);
 956         struct nouveau_drm *drm = nouveau_drm(plane->dev);
 957         struct nv50_wndw *wndw = nv50_wndw(plane);
 958         struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
 959         struct nv50_head_atom *asyh;
 960         struct nv50_dmac_ctxdma *ctxdma;
 961         int ret;
 962
 963         NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, state->fb);
 964         if (!asyw->state.fb)
 965                 return 0;
 966
 967         ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM, true);
 968         if (ret)
 969                 return ret;
 970
 971         ctxdma = nv50_dmac_ctxdma_new(wndw->dmac, fb);
 972         if (IS_ERR(ctxdma)) {
 973                 nouveau_bo_unpin(fb->nvbo);
 974                 return PTR_ERR(ctxdma);
 975         }
 976
 977         asyw->state.fence = reservation_object_get_excl_rcu(fb->nvbo->bo.resv);
 978         asyw->image.handle = ctxdma->object.handle;
 979         asyw->image.offset = fb->nvbo->bo.offset;
 980
 981         if (wndw->func->prepare) {
 982                 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
 983                 if (IS_ERR(asyh))
 984                         return PTR_ERR(asyh);
 985
 986                 wndw->func->prepare(wndw, asyh, asyw);
 987         }
 988
 989         return 0;
 990 }
 991
 992 static const struct drm_plane_helper_funcs
 993 nv50_wndw_helper = {
 994         .prepare_fb = nv50_wndw_prepare_fb,
 995         .cleanup_fb = nv50_wndw_cleanup_fb,
 996         .atomic_check = nv50_wndw_atomic_check,
 997 };
 998
 999 static void
1000 nv50_wndw_atomic_destroy_state(struct drm_plane *plane,
1001                                struct drm_plane_state *state)
1002 {
1003         struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
1004         __drm_atomic_helper_plane_destroy_state(&asyw->state);
1005         kfree(asyw);
1006 }
1007
1008 static struct drm_plane_state *
1009 nv50_wndw_atomic_duplicate_state(struct drm_plane *plane)
1010 {
1011         struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state);
1012         struct nv50_wndw_atom *asyw;
1013         if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL)))
1014                 return NULL;
1015         __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state);
1016         asyw->interval = 1;
1017         asyw->sema = armw->sema;
1018         asyw->ntfy = armw->ntfy;
1019         asyw->image = armw->image;
1020         asyw->point = armw->point;
1021         asyw->lut = armw->lut;
1022         asyw->clr.mask = 0;
1023         asyw->set.mask = 0;
1024         return &asyw->state;
1025 }
1026
1027 static void
1028 nv50_wndw_reset(struct drm_plane *plane)
1029 {
1030         struct nv50_wndw_atom *asyw;
1031
1032         if (WARN_ON(!(asyw = kzalloc(sizeof(*asyw), GFP_KERNEL))))
1033                 return;
1034
1035         if (plane->state)
1036                 plane->funcs->atomic_destroy_state(plane, plane->state);
1037         plane->state = &asyw->state;
1038         plane->state->plane = plane;
1039         plane->state->rotation = DRM_ROTATE_0;
1040 }
1041
1042 static void
1043 nv50_wndw_destroy(struct drm_plane *plane)
1044 {
1045         struct nv50_wndw *wndw = nv50_wndw(plane);
1046         void *data;
1047         nvif_notify_fini(&wndw->notify);
1048         data = wndw->func->dtor(wndw);
1049         drm_plane_cleanup(&wndw->plane);
1050         kfree(data);
1051 }
1052
1053 static const struct drm_plane_funcs
1054 nv50_wndw = {
1055         .update_plane = drm_atomic_helper_update_plane,
1056         .disable_plane = drm_atomic_helper_disable_plane,
1057         .destroy = nv50_wndw_destroy,
1058         .reset = nv50_wndw_reset,
1059         .set_property = drm_atomic_helper_plane_set_property,
1060         .atomic_duplicate_state = nv50_wndw_atomic_duplicate_state,
1061         .atomic_destroy_state = nv50_wndw_atomic_destroy_state,
1062 };
1063
1064 static void
1065 nv50_wndw_fini(struct nv50_wndw *wndw)
1066 {
1067         nvif_notify_put(&wndw->notify);
1068 }
1069
1070 static void
1071 nv50_wndw_init(struct nv50_wndw *wndw)
1072 {
1073         nvif_notify_get(&wndw->notify);
1074 }
1075
1076 static int
1077 nv50_wndw_ctor(const struct nv50_wndw_func *func, struct drm_device *dev,
1078                enum drm_plane_type type, const char *name, int index,
1079                struct nv50_dmac *dmac, const u32 *format, int nformat,
1080                struct nv50_wndw *wndw)
1081 {
1082         int ret;
1083
1084         wndw->func = func;
1085         wndw->dmac = dmac;
1086
1087         ret = drm_universal_plane_init(dev, &wndw->plane, 0, &nv50_wndw, format,
1088                                        nformat, type, "%s-%d", name, index);
1089         if (ret)
1090                 return ret;
1091
1092         drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper);
1093         return 0;
1094 }
1095
1096 /******************************************************************************
1097  * Cursor plane
1098  *****************************************************************************/
1099 #define nv50_curs(p) container_of((p), struct nv50_curs, wndw)
1100
1101 struct nv50_curs {
1102         struct nv50_wndw wndw;
1103         struct nvif_object chan;
1104 };
1105
1106 static u32
1107 nv50_curs_update(struct nv50_wndw *wndw, u32 interlock)
1108 {
1109         struct nv50_curs *curs = nv50_curs(wndw);
1110         nvif_wr32(&curs->chan, 0x0080, 0x00000000);
1111         return 0;
1112 }
1113
1114 static void
1115 nv50_curs_point(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1116 {
1117         struct nv50_curs *curs = nv50_curs(wndw);
1118         nvif_wr32(&curs->chan, 0x0084, (asyw->point.y << 16) | asyw->point.x);
1119 }
1120
1121 static void
1122 nv50_curs_prepare(struct nv50_wndw *wndw, struct nv50_head_atom *asyh,
1123                   struct nv50_wndw_atom *asyw)
1124 {
1125         asyh->curs.handle = nv50_disp(wndw->plane.dev)->mast.base.vram.handle;
1126         asyh->curs.offset = asyw->image.offset;
1127         asyh->set.curs = asyh->curs.visible;
1128 }
1129
1130 static void
1131 nv50_curs_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1132                   struct nv50_head_atom *asyh)
1133 {
1134         asyh->curs.visible = false;
1135 }
1136
1137 static int
1138 nv50_curs_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1139                   struct nv50_head_atom *asyh)
1140 {
1141         int ret;
1142
1143         ret = drm_plane_helper_check_state(&asyw->state, &asyw->clip,
1144                                            DRM_PLANE_HELPER_NO_SCALING,
1145                                            DRM_PLANE_HELPER_NO_SCALING,
1146                                            true, true);
1147         asyh->curs.visible = asyw->state.visible;
1148         if (ret || !asyh->curs.visible)
1149                 return ret;
1150
1151         switch (asyw->state.fb->width) {
1152         case 32: asyh->curs.layout = 0; break;
1153         case 64: asyh->curs.layout = 1; break;
1154         default:
1155                 return -EINVAL;
1156         }
1157
1158         if (asyw->state.fb->width != asyw->state.fb->height)
1159                 return -EINVAL;
1160
1161         switch (asyw->state.fb->format->format) {
1162         case DRM_FORMAT_ARGB8888: asyh->curs.format = 1; break;
1163         default:
1164                 WARN_ON(1);
1165                 return -EINVAL;
1166         }
1167
1168         return 0;
1169 }
1170
1171 static void *
1172 nv50_curs_dtor(struct nv50_wndw *wndw)
1173 {
1174         struct nv50_curs *curs = nv50_curs(wndw);
1175         nvif_object_fini(&curs->chan);
1176         return curs;
1177 }
1178
1179 static const u32
1180 nv50_curs_format[] = {
1181         DRM_FORMAT_ARGB8888,
1182 };
1183
1184 static const struct nv50_wndw_func
1185 nv50_curs = {
1186         .dtor = nv50_curs_dtor,
1187         .acquire = nv50_curs_acquire,
1188         .release = nv50_curs_release,
1189         .prepare = nv50_curs_prepare,
1190         .point = nv50_curs_point,
1191         .update = nv50_curs_update,
1192 };
1193
1194 static int
1195 nv50_curs_new(struct nouveau_drm *drm, struct nv50_head *head,
1196               struct nv50_curs **pcurs)
1197 {
1198         static const struct nvif_mclass curses[] = {
1199                 { GK104_DISP_CURSOR, 0 },
1200                 { GF110_DISP_CURSOR, 0 },
1201                 { GT214_DISP_CURSOR, 0 },
1202                 {   G82_DISP_CURSOR, 0 },
1203                 {  NV50_DISP_CURSOR, 0 },
1204                 {}
1205         };
1206         struct nv50_disp_cursor_v0 args = {
1207                 .head = head->base.index,
1208         };
1209         struct nv50_disp *disp = nv50_disp(drm->dev);
1210         struct nv50_curs *curs;
1211         int cid, ret;
1212
1213         cid = nvif_mclass(disp->disp, curses);
1214         if (cid < 0) {
1215                 NV_ERROR(drm, "No supported cursor immediate class\n");
1216                 return cid;
1217         }
1218
1219         if (!(curs = *pcurs = kzalloc(sizeof(*curs), GFP_KERNEL)))
1220                 return -ENOMEM;
1221
1222         ret = nv50_wndw_ctor(&nv50_curs, drm->dev, DRM_PLANE_TYPE_CURSOR,
1223                              "curs", head->base.index, &disp->mast.base,
1224                              nv50_curs_format, ARRAY_SIZE(nv50_curs_format),
1225                              &curs->wndw);
1226         if (ret) {
1227                 kfree(curs);
1228                 return ret;
1229         }
1230
1231         ret = nvif_object_init(disp->disp, 0, curses[cid].oclass, &args,
1232                                sizeof(args), &curs->chan);
1233         if (ret) {
1234                 NV_ERROR(drm, "curs%04x allocation failed: %d\n",
1235                          curses[cid].oclass, ret);
1236                 return ret;
1237         }
1238
1239         return 0;
1240 }
1241
1242 /******************************************************************************
1243  * Primary plane
1244  *****************************************************************************/
1245 #define nv50_base(p) container_of((p), struct nv50_base, wndw)
1246
1247 struct nv50_base {
1248         struct nv50_wndw wndw;
1249         struct nv50_sync chan;
1250         int id;
1251 };
1252
1253 static int
1254 nv50_base_notify(struct nvif_notify *notify)
1255 {
1256         return NVIF_NOTIFY_KEEP;
1257 }
1258
1259 static void
1260 nv50_base_lut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1261 {
1262         struct nv50_base *base = nv50_base(wndw);
1263         u32 *push;
1264         if ((push = evo_wait(&base->chan, 2))) {
1265                 evo_mthd(push, 0x00e0, 1);
1266                 evo_data(push, asyw->lut.enable << 30);
1267                 evo_kick(push, &base->chan);
1268         }
1269 }
1270
1271 static void
1272 nv50_base_image_clr(struct nv50_wndw *wndw)
1273 {
1274         struct nv50_base *base = nv50_base(wndw);
1275         u32 *push;
1276         if ((push = evo_wait(&base->chan, 4))) {
1277                 evo_mthd(push, 0x0084, 1);
1278                 evo_data(push, 0x00000000);
1279                 evo_mthd(push, 0x00c0, 1);
1280                 evo_data(push, 0x00000000);
1281                 evo_kick(push, &base->chan);
1282         }
1283 }
1284
1285 static void
1286 nv50_base_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1287 {
1288         struct nv50_base *base = nv50_base(wndw);
1289         const s32 oclass = base->chan.base.base.user.oclass;
1290         u32 *push;
1291         if ((push = evo_wait(&base->chan, 10))) {
1292                 evo_mthd(push, 0x0084, 1);
1293                 evo_data(push, (asyw->image.mode << 8) |
1294                                (asyw->image.interval << 4));
1295                 evo_mthd(push, 0x00c0, 1);
1296                 evo_data(push, asyw->image.handle);
1297                 if (oclass < G82_DISP_BASE_CHANNEL_DMA) {
1298                         evo_mthd(push, 0x0800, 5);
1299                         evo_data(push, asyw->image.offset >> 8);
1300                         evo_data(push, 0x00000000);
1301                         evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1302                         evo_data(push, (asyw->image.layout << 20) |
1303                                         asyw->image.pitch |
1304                                         asyw->image.block);
1305                         evo_data(push, (asyw->image.kind << 16) |
1306                                        (asyw->image.format << 8));
1307                 } else
1308                 if (oclass < GF110_DISP_BASE_CHANNEL_DMA) {
1309                         evo_mthd(push, 0x0800, 5);
1310                         evo_data(push, asyw->image.offset >> 8);
1311                         evo_data(push, 0x00000000);
1312                         evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1313                         evo_data(push, (asyw->image.layout << 20) |
1314                                         asyw->image.pitch |
1315                                         asyw->image.block);
1316                         evo_data(push, asyw->image.format << 8);
1317                 } else {
1318                         evo_mthd(push, 0x0400, 5);
1319                         evo_data(push, asyw->image.offset >> 8);
1320                         evo_data(push, 0x00000000);
1321                         evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1322                         evo_data(push, (asyw->image.layout << 24) |
1323                                         asyw->image.pitch |
1324                                         asyw->image.block);
1325                         evo_data(push, asyw->image.format << 8);
1326                 }
1327                 evo_kick(push, &base->chan);
1328         }
1329 }
1330
1331 static void
1332 nv50_base_ntfy_clr(struct nv50_wndw *wndw)
1333 {
1334         struct nv50_base *base = nv50_base(wndw);
1335         u32 *push;
1336         if ((push = evo_wait(&base->chan, 2))) {
1337                 evo_mthd(push, 0x00a4, 1);
1338                 evo_data(push, 0x00000000);
1339                 evo_kick(push, &base->chan);
1340         }
1341 }
1342
1343 static void
1344 nv50_base_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1345 {
1346         struct nv50_base *base = nv50_base(wndw);
1347         u32 *push;
1348         if ((push = evo_wait(&base->chan, 3))) {
1349                 evo_mthd(push, 0x00a0, 2);
1350                 evo_data(push, (asyw->ntfy.awaken << 30) | asyw->ntfy.offset);
1351                 evo_data(push, asyw->ntfy.handle);
1352                 evo_kick(push, &base->chan);
1353         }
1354 }
1355
1356 static void
1357 nv50_base_sema_clr(struct nv50_wndw *wndw)
1358 {
1359         struct nv50_base *base = nv50_base(wndw);
1360         u32 *push;
1361         if ((push = evo_wait(&base->chan, 2))) {
1362                 evo_mthd(push, 0x0094, 1);
1363                 evo_data(push, 0x00000000);
1364                 evo_kick(push, &base->chan);
1365         }
1366 }
1367
1368 static void
1369 nv50_base_sema_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1370 {
1371         struct nv50_base *base = nv50_base(wndw);
1372         u32 *push;
1373         if ((push = evo_wait(&base->chan, 5))) {
1374                 evo_mthd(push, 0x0088, 4);
1375                 evo_data(push, asyw->sema.offset);
1376                 evo_data(push, asyw->sema.acquire);
1377                 evo_data(push, asyw->sema.release);
1378                 evo_data(push, asyw->sema.handle);
1379                 evo_kick(push, &base->chan);
1380         }
1381 }
1382
1383 static u32
1384 nv50_base_update(struct nv50_wndw *wndw, u32 interlock)
1385 {
1386         struct nv50_base *base = nv50_base(wndw);
1387         u32 *push;
1388
1389         if (!(push = evo_wait(&base->chan, 2)))
1390                 return 0;
1391         evo_mthd(push, 0x0080, 1);
1392         evo_data(push, interlock);
1393         evo_kick(push, &base->chan);
1394
1395         if (base->chan.base.base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA)
1396                 return interlock ? 2 << (base->id * 8) : 0;
1397         return interlock ? 2 << (base->id * 4) : 0;
1398 }
1399
1400 static int
1401 nv50_base_ntfy_wait_begun(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1402 {
1403         struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
1404         struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
1405         if (nvif_msec(&drm->client.device, 2000ULL,
1406                 u32 data = nouveau_bo_rd32(disp->sync, asyw->ntfy.offset / 4);
1407                 if ((data & 0xc0000000) == 0x40000000)
1408                         break;
1409                 usleep_range(1, 2);
1410         ) < 0)
1411                 return -ETIMEDOUT;
1412         return 0;
1413 }
1414
1415 static void
1416 nv50_base_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1417                   struct nv50_head_atom *asyh)
1418 {
1419         asyh->base.cpp = 0;
1420 }
1421
1422 static int
1423 nv50_base_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1424                   struct nv50_head_atom *asyh)
1425 {
1426         const struct drm_framebuffer *fb = asyw->state.fb;
1427         int ret;
1428
1429         if (!fb->format->depth)
1430                 return -EINVAL;
1431
1432         ret = drm_plane_helper_check_state(&asyw->state, &asyw->clip,
1433                                            DRM_PLANE_HELPER_NO_SCALING,
1434                                            DRM_PLANE_HELPER_NO_SCALING,
1435                                            false, true);
1436         if (ret)
1437                 return ret;
1438
1439         asyh->base.depth = fb->format->depth;
1440         asyh->base.cpp = fb->format->cpp[0];
1441         asyh->base.x = asyw->state.src.x1 >> 16;
1442         asyh->base.y = asyw->state.src.y1 >> 16;
1443         asyh->base.w = asyw->state.fb->width;
1444         asyh->base.h = asyw->state.fb->height;
1445
1446         switch (fb->format->format) {
1447         case DRM_FORMAT_C8         : asyw->image.format = 0x1e; break;
1448         case DRM_FORMAT_RGB565     : asyw->image.format = 0xe8; break;
1449         case DRM_FORMAT_XRGB1555   :
1450         case DRM_FORMAT_ARGB1555   : asyw->image.format = 0xe9; break;
1451         case DRM_FORMAT_XRGB8888   :
1452         case DRM_FORMAT_ARGB8888   : asyw->image.format = 0xcf; break;
1453         case DRM_FORMAT_XBGR2101010:
1454         case DRM_FORMAT_ABGR2101010: asyw->image.format = 0xd1; break;
1455         case DRM_FORMAT_XBGR8888   :
1456         case DRM_FORMAT_ABGR8888   : asyw->image.format = 0xd5; break;
1457         default:
1458                 WARN_ON(1);
1459                 return -EINVAL;
1460         }
1461
1462         asyw->lut.enable = 1;
1463         asyw->set.image = true;
1464         return 0;
1465 }
1466
1467 static void *
1468 nv50_base_dtor(struct nv50_wndw *wndw)
1469 {
1470         struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
1471         struct nv50_base *base = nv50_base(wndw);
1472         nv50_dmac_destroy(&base->chan.base, disp->disp);
1473         return base;
1474 }
1475
1476 static const u32
1477 nv50_base_format[] = {
1478         DRM_FORMAT_C8,
1479         DRM_FORMAT_RGB565,
1480         DRM_FORMAT_XRGB1555,
1481         DRM_FORMAT_ARGB1555,
1482         DRM_FORMAT_XRGB8888,
1483         DRM_FORMAT_ARGB8888,
1484         DRM_FORMAT_XBGR2101010,
1485         DRM_FORMAT_ABGR2101010,
1486         DRM_FORMAT_XBGR8888,
1487         DRM_FORMAT_ABGR8888,
1488 };
1489
1490 static const struct nv50_wndw_func
1491 nv50_base = {
1492         .dtor = nv50_base_dtor,
1493         .acquire = nv50_base_acquire,
1494         .release = nv50_base_release,
1495         .sema_set = nv50_base_sema_set,
1496         .sema_clr = nv50_base_sema_clr,
1497         .ntfy_set = nv50_base_ntfy_set,
1498         .ntfy_clr = nv50_base_ntfy_clr,
1499         .ntfy_wait_begun = nv50_base_ntfy_wait_begun,
1500         .image_set = nv50_base_image_set,
1501         .image_clr = nv50_base_image_clr,
1502         .lut = nv50_base_lut,
1503         .update = nv50_base_update,
1504 };
1505
1506 static int
1507 nv50_base_new(struct nouveau_drm *drm, struct nv50_head *head,
1508               struct nv50_base **pbase)
1509 {
1510         struct nv50_disp *disp = nv50_disp(drm->dev);
1511         struct nv50_base *base;
1512         int ret;
1513
1514         if (!(base = *pbase = kzalloc(sizeof(*base), GFP_KERNEL)))
1515                 return -ENOMEM;
1516         base->id = head->base.index;
1517         base->wndw.ntfy = EVO_FLIP_NTFY0(base->id);
1518         base->wndw.sema = EVO_FLIP_SEM0(base->id);
1519         base->wndw.data = 0x00000000;
1520
1521         ret = nv50_wndw_ctor(&nv50_base, drm->dev, DRM_PLANE_TYPE_PRIMARY,
1522                              "base", base->id, &base->chan.base,
1523                              nv50_base_format, ARRAY_SIZE(nv50_base_format),
1524                              &base->wndw);
1525         if (ret) {
1526                 kfree(base);
1527                 return ret;
1528         }
1529
1530         ret = nv50_base_create(&drm->client.device, disp->disp, base->id,
1531                                disp->sync->bo.offset, &base->chan);
1532         if (ret)
1533                 return ret;
1534
1535         return nvif_notify_init(&base->chan.base.base.user, nv50_base_notify,
1536                                 false,
1537                                 NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT,
1538                                 &(struct nvif_notify_uevent_req) {},
1539                                 sizeof(struct nvif_notify_uevent_req),
1540                                 sizeof(struct nvif_notify_uevent_rep),
1541                                 &base->wndw.notify);
1542 }
1543
1544 /******************************************************************************
1545  * Head
1546  *****************************************************************************/
1547 static void
1548 nv50_head_procamp(struct nv50_head *head, struct nv50_head_atom *asyh)
1549 {
1550         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1551         u32 *push;
1552         if ((push = evo_wait(core, 2))) {
1553                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1554                         evo_mthd(push, 0x08a8 + (head->base.index * 0x400), 1);
1555                 else
1556                         evo_mthd(push, 0x0498 + (head->base.index * 0x300), 1);
1557                 evo_data(push, (asyh->procamp.sat.sin << 20) |
1558                                (asyh->procamp.sat.cos << 8));
1559                 evo_kick(push, core);
1560         }
1561 }
1562
1563 static void
1564 nv50_head_dither(struct nv50_head *head, struct nv50_head_atom *asyh)
1565 {
1566         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1567         u32 *push;
1568         if ((push = evo_wait(core, 2))) {
1569                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1570                         evo_mthd(push, 0x08a0 + (head->base.index * 0x0400), 1);
1571                 else
1572                 if (core->base.user.oclass < GK104_DISP_CORE_CHANNEL_DMA)
1573                         evo_mthd(push, 0x0490 + (head->base.index * 0x0300), 1);
1574                 else
1575                         evo_mthd(push, 0x04a0 + (head->base.index * 0x0300), 1);
1576                 evo_data(push, (asyh->dither.mode << 3) |
1577                                (asyh->dither.bits << 1) |
1578                                 asyh->dither.enable);
1579                 evo_kick(push, core);
1580         }
1581 }
1582
1583 static void
1584 nv50_head_ovly(struct nv50_head *head, struct nv50_head_atom *asyh)
1585 {
1586         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1587         u32 bounds = 0;
1588         u32 *push;
1589
1590         if (asyh->base.cpp) {
1591                 switch (asyh->base.cpp) {
1592                 case 8: bounds |= 0x00000500; break;
1593                 case 4: bounds |= 0x00000300; break;
1594                 case 2: bounds |= 0x00000100; break;
1595                 default:
1596                         WARN_ON(1);
1597                         break;
1598                 }
1599                 bounds |= 0x00000001;
1600         }
1601
1602         if ((push = evo_wait(core, 2))) {
1603                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1604                         evo_mthd(push, 0x0904 + head->base.index * 0x400, 1);
1605                 else
1606                         evo_mthd(push, 0x04d4 + head->base.index * 0x300, 1);
1607                 evo_data(push, bounds);
1608                 evo_kick(push, core);
1609         }
1610 }
1611
1612 static void
1613 nv50_head_base(struct nv50_head *head, struct nv50_head_atom *asyh)
1614 {
1615         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1616         u32 bounds = 0;
1617         u32 *push;
1618
1619         if (asyh->base.cpp) {
1620                 switch (asyh->base.cpp) {
1621                 case 8: bounds |= 0x00000500; break;
1622                 case 4: bounds |= 0x00000300; break;
1623                 case 2: bounds |= 0x00000100; break;
1624                 case 1: bounds |= 0x00000000; break;
1625                 default:
1626                         WARN_ON(1);
1627                         break;
1628                 }
1629                 bounds |= 0x00000001;
1630         }
1631
1632         if ((push = evo_wait(core, 2))) {
1633                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1634                         evo_mthd(push, 0x0900 + head->base.index * 0x400, 1);
1635                 else
1636                         evo_mthd(push, 0x04d0 + head->base.index * 0x300, 1);
1637                 evo_data(push, bounds);
1638                 evo_kick(push, core);
1639         }
1640 }
1641
1642 static void
1643 nv50_head_curs_clr(struct nv50_head *head)
1644 {
1645         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1646         u32 *push;
1647         if ((push = evo_wait(core, 4))) {
1648                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1649                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 1);
1650                         evo_data(push, 0x05000000);
1651                 } else
1652                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1653                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 1);
1654                         evo_data(push, 0x05000000);
1655                         evo_mthd(push, 0x089c + head->base.index * 0x400, 1);
1656                         evo_data(push, 0x00000000);
1657                 } else {
1658                         evo_mthd(push, 0x0480 + head->base.index * 0x300, 1);
1659                         evo_data(push, 0x05000000);
1660                         evo_mthd(push, 0x048c + head->base.index * 0x300, 1);
1661                         evo_data(push, 0x00000000);
1662                 }
1663                 evo_kick(push, core);
1664         }
1665 }
1666
1667 static void
1668 nv50_head_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1669 {
1670         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1671         u32 *push;
1672         if ((push = evo_wait(core, 5))) {
1673                 if (core->base.user.oclass < G82_DISP_BASE_CHANNEL_DMA) {
1674                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 2);
1675                         evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1676                                                     (asyh->curs.format << 24));
1677                         evo_data(push, asyh->curs.offset >> 8);
1678                 } else
1679                 if (core->base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA) {
1680                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 2);
1681                         evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1682                                                     (asyh->curs.format << 24));
1683                         evo_data(push, asyh->curs.offset >> 8);
1684                         evo_mthd(push, 0x089c + head->base.index * 0x400, 1);
1685                         evo_data(push, asyh->curs.handle);
1686                 } else {
1687                         evo_mthd(push, 0x0480 + head->base.index * 0x300, 2);
1688                         evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1689                                                     (asyh->curs.format << 24));
1690                         evo_data(push, asyh->curs.offset >> 8);
1691                         evo_mthd(push, 0x048c + head->base.index * 0x300, 1);
1692                         evo_data(push, asyh->curs.handle);
1693                 }
1694                 evo_kick(push, core);
1695         }
1696 }
1697
1698 static void
1699 nv50_head_core_clr(struct nv50_head *head)
1700 {
1701         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1702         u32 *push;
1703         if ((push = evo_wait(core, 2))) {
1704                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1705                         evo_mthd(push, 0x0874 + head->base.index * 0x400, 1);
1706                 else
1707                         evo_mthd(push, 0x0474 + head->base.index * 0x300, 1);
1708                 evo_data(push, 0x00000000);
1709                 evo_kick(push, core);
1710         }
1711 }
1712
1713 static void
1714 nv50_head_core_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1715 {
1716         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1717         u32 *push;
1718         if ((push = evo_wait(core, 9))) {
1719                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1720                         evo_mthd(push, 0x0860 + head->base.index * 0x400, 1);
1721                         evo_data(push, asyh->core.offset >> 8);
1722                         evo_mthd(push, 0x0868 + head->base.index * 0x400, 4);
1723                         evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1724                         evo_data(push, asyh->core.layout << 20 |
1725                                        (asyh->core.pitch >> 8) << 8 |
1726                                        asyh->core.block);
1727                         evo_data(push, asyh->core.kind << 16 |
1728                                        asyh->core.format << 8);
1729                         evo_data(push, asyh->core.handle);
1730                         evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1);
1731                         evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1732                         /* EVO will complain with INVALID_STATE if we have an
1733                          * active cursor and (re)specify HeadSetContextDmaIso
1734                          * without also updating HeadSetOffsetCursor.
1735                          */
1736                         asyh->set.curs = asyh->curs.visible;
1737                 } else
1738                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1739                         evo_mthd(push, 0x0860 + head->base.index * 0x400, 1);
1740                         evo_data(push, asyh->core.offset >> 8);
1741                         evo_mthd(push, 0x0868 + head->base.index * 0x400, 4);
1742                         evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1743                         evo_data(push, asyh->core.layout << 20 |
1744                                        (asyh->core.pitch >> 8) << 8 |
1745                                        asyh->core.block);
1746                         evo_data(push, asyh->core.format << 8);
1747                         evo_data(push, asyh->core.handle);
1748                         evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1);
1749                         evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1750                 } else {
1751                         evo_mthd(push, 0x0460 + head->base.index * 0x300, 1);
1752                         evo_data(push, asyh->core.offset >> 8);
1753                         evo_mthd(push, 0x0468 + head->base.index * 0x300, 4);
1754                         evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1755                         evo_data(push, asyh->core.layout << 24 |
1756                                        (asyh->core.pitch >> 8) << 8 |
1757                                        asyh->core.block);
1758                         evo_data(push, asyh->core.format << 8);
1759                         evo_data(push, asyh->core.handle);
1760                         evo_mthd(push, 0x04b0 + head->base.index * 0x300, 1);
1761                         evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1762                 }
1763                 evo_kick(push, core);
1764         }
1765 }
1766
1767 static void
1768 nv50_head_lut_clr(struct nv50_head *head)
1769 {
1770         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1771         u32 *push;
1772         if ((push = evo_wait(core, 4))) {
1773                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1774                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1);
1775                         evo_data(push, 0x40000000);
1776                 } else
1777                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1778                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1);
1779                         evo_data(push, 0x40000000);
1780                         evo_mthd(push, 0x085c + (head->base.index * 0x400), 1);
1781                         evo_data(push, 0x00000000);
1782                 } else {
1783                         evo_mthd(push, 0x0440 + (head->base.index * 0x300), 1);
1784                         evo_data(push, 0x03000000);
1785                         evo_mthd(push, 0x045c + (head->base.index * 0x300), 1);
1786                         evo_data(push, 0x00000000);
1787                 }
1788                 evo_kick(push, core);
1789         }
1790 }
1791
1792 static void
1793 nv50_head_lut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1794 {
1795         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1796         u32 *push;
1797         if ((push = evo_wait(core, 7))) {
1798                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1799                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2);
1800                         evo_data(push, 0xc0000000);
1801                         evo_data(push, asyh->lut.offset >> 8);
1802                 } else
1803                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1804                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2);
1805                         evo_data(push, 0xc0000000);
1806                         evo_data(push, asyh->lut.offset >> 8);
1807                         evo_mthd(push, 0x085c + (head->base.index * 0x400), 1);
1808                         evo_data(push, asyh->lut.handle);
1809                 } else {
1810                         evo_mthd(push, 0x0440 + (head->base.index * 0x300), 4);
1811                         evo_data(push, 0x83000000);
1812                         evo_data(push, asyh->lut.offset >> 8);
1813                         evo_data(push, 0x00000000);
1814                         evo_data(push, 0x00000000);
1815                         evo_mthd(push, 0x045c + (head->base.index * 0x300), 1);
1816                         evo_data(push, asyh->lut.handle);
1817                 }
1818                 evo_kick(push, core);
1819         }
1820 }
1821
1822 static void
1823 nv50_head_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
1824 {
1825         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1826         struct nv50_head_mode *m = &asyh->mode;
1827         u32 *push;
1828         if ((push = evo_wait(core, 14))) {
1829                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1830                         evo_mthd(push, 0x0804 + (head->base.index * 0x400), 2);
1831                         evo_data(push, 0x00800000 | m->clock);
1832                         evo_data(push, m->interlace ? 0x00000002 : 0x00000000);
1833                         evo_mthd(push, 0x0810 + (head->base.index * 0x400), 7);
1834                         evo_data(push, 0x00000000);
1835                         evo_data(push, (m->v.active  << 16) | m->h.active );
1836                         evo_data(push, (m->v.synce   << 16) | m->h.synce  );
1837                         evo_data(push, (m->v.blanke  << 16) | m->h.blanke );
1838                         evo_data(push, (m->v.blanks  << 16) | m->h.blanks );
1839                         evo_data(push, (m->v.blank2e << 16) | m->v.blank2s);
1840                         evo_data(push, asyh->mode.v.blankus);
1841                         evo_mthd(push, 0x082c + (head->base.index * 0x400), 1);
1842                         evo_data(push, 0x00000000);
1843                 } else {
1844                         evo_mthd(push, 0x0410 + (head->base.index * 0x300), 6);
1845                         evo_data(push, 0x00000000);
1846                         evo_data(push, (m->v.active  << 16) | m->h.active );
1847                         evo_data(push, (m->v.synce   << 16) | m->h.synce  );
1848                         evo_data(push, (m->v.blanke  << 16) | m->h.blanke );
1849                         evo_data(push, (m->v.blanks  << 16) | m->h.blanks );
1850                         evo_data(push, (m->v.blank2e << 16) | m->v.blank2s);
1851                         evo_mthd(push, 0x042c + (head->base.index * 0x300), 2);
1852                         evo_data(push, 0x00000000); /* ??? */
1853                         evo_data(push, 0xffffff00);
1854                         evo_mthd(push, 0x0450 + (head->base.index * 0x300), 3);
1855                         evo_data(push, m->clock * 1000);
1856                         evo_data(push, 0x00200000); /* ??? */
1857                         evo_data(push, m->clock * 1000);
1858                 }
1859                 evo_kick(push, core);
1860         }
1861 }
1862
1863 static void
1864 nv50_head_view(struct nv50_head *head, struct nv50_head_atom *asyh)
1865 {
1866         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1867         u32 *push;
1868         if ((push = evo_wait(core, 10))) {
1869                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1870                         evo_mthd(push, 0x08a4 + (head->base.index * 0x400), 1);
1871                         evo_data(push, 0x00000000);
1872                         evo_mthd(push, 0x08c8 + (head->base.index * 0x400), 1);
1873                         evo_data(push, (asyh->view.iH << 16) | asyh->view.iW);
1874                         evo_mthd(push, 0x08d8 + (head->base.index * 0x400), 2);
1875                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1876                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1877                 } else {
1878                         evo_mthd(push, 0x0494 + (head->base.index * 0x300), 1);
1879                         evo_data(push, 0x00000000);
1880                         evo_mthd(push, 0x04b8 + (head->base.index * 0x300), 1);
1881                         evo_data(push, (asyh->view.iH << 16) | asyh->view.iW);
1882                         evo_mthd(push, 0x04c0 + (head->base.index * 0x300), 3);
1883                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1884                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1885                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1886                 }
1887                 evo_kick(push, core);
1888         }
1889 }
1890
1891 static void
1892 nv50_head_flush_clr(struct nv50_head *head, struct nv50_head_atom *asyh, bool y)
1893 {
1894         if (asyh->clr.core && (!asyh->set.core || y))
1895                 nv50_head_lut_clr(head);
1896         if (asyh->clr.core && (!asyh->set.core || y))
1897                 nv50_head_core_clr(head);
1898         if (asyh->clr.curs && (!asyh->set.curs || y))
1899                 nv50_head_curs_clr(head);
1900 }
1901
1902 static void
1903 nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1904 {
1905         if (asyh->set.view   ) nv50_head_view    (head, asyh);
1906         if (asyh->set.mode   ) nv50_head_mode    (head, asyh);
1907         if (asyh->set.core   ) nv50_head_lut_set (head, asyh);
1908         if (asyh->set.core   ) nv50_head_core_set(head, asyh);
1909         if (asyh->set.curs   ) nv50_head_curs_set(head, asyh);
1910         if (asyh->set.base   ) nv50_head_base    (head, asyh);
1911         if (asyh->set.ovly   ) nv50_head_ovly    (head, asyh);
1912         if (asyh->set.dither ) nv50_head_dither  (head, asyh);
1913         if (asyh->set.procamp) nv50_head_procamp (head, asyh);
1914 }
1915
1916 static void
1917 nv50_head_atomic_check_procamp(struct nv50_head_atom *armh,
1918                                struct nv50_head_atom *asyh,
1919                                struct nouveau_conn_atom *asyc)
1920 {
1921         const int vib = asyc->procamp.color_vibrance - 100;
1922         const int hue = asyc->procamp.vibrant_hue - 90;
1923         const int adj = (vib > 0) ? 50 : 0;
1924         asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff;
1925         asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff;
1926         asyh->set.procamp = true;
1927 }
1928
1929 static void
1930 nv50_head_atomic_check_dither(struct nv50_head_atom *armh,
1931                               struct nv50_head_atom *asyh,
1932                               struct nouveau_conn_atom *asyc)
1933 {
1934         struct drm_connector *connector = asyc->state.connector;
1935         u32 mode = 0x00;
1936
1937         if (asyc->dither.mode == DITHERING_MODE_AUTO) {
1938                 if (asyh->base.depth > connector->display_info.bpc * 3)
1939                         mode = DITHERING_MODE_DYNAMIC2X2;
1940         } else {
1941                 mode = asyc->dither.mode;
1942         }
1943
1944         if (asyc->dither.depth == DITHERING_DEPTH_AUTO) {
1945                 if (connector->display_info.bpc >= 8)
1946                         mode |= DITHERING_DEPTH_8BPC;
1947         } else {
1948                 mode |= asyc->dither.depth;
1949         }
1950
1951         asyh->dither.enable = mode;
1952         asyh->dither.bits = mode >> 1;
1953         asyh->dither.mode = mode >> 3;
1954         asyh->set.dither = true;
1955 }
1956
1957 static void
1958 nv50_head_atomic_check_view(struct nv50_head_atom *armh,
1959                             struct nv50_head_atom *asyh,
1960                             struct nouveau_conn_atom *asyc)
1961 {
1962         struct drm_connector *connector = asyc->state.connector;
1963         struct drm_display_mode *omode = &asyh->state.adjusted_mode;
1964         struct drm_display_mode *umode = &asyh->state.mode;
1965         int mode = asyc->scaler.mode;
1966         struct edid *edid;
1967
1968         if (connector->edid_blob_ptr)
1969                 edid = (struct edid *)connector->edid_blob_ptr->data;
1970         else
1971                 edid = NULL;
1972
1973         if (!asyc->scaler.full) {
1974                 if (mode == DRM_MODE_SCALE_NONE)
1975                         omode = umode;
1976         } else {
1977                 /* Non-EDID LVDS/eDP mode. */
1978                 mode = DRM_MODE_SCALE_FULLSCREEN;
1979         }
1980
1981         asyh->view.iW = umode->hdisplay;
1982         asyh->view.iH = umode->vdisplay;
1983         asyh->view.oW = omode->hdisplay;
1984         asyh->view.oH = omode->vdisplay;
1985         if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
1986                 asyh->view.oH *= 2;
1987
1988         /* Add overscan compensation if necessary, will keep the aspect
1989          * ratio the same as the backend mode unless overridden by the
1990          * user setting both hborder and vborder properties.
1991          */
1992         if ((asyc->scaler.underscan.mode == UNDERSCAN_ON ||
1993             (asyc->scaler.underscan.mode == UNDERSCAN_AUTO &&
1994              drm_detect_hdmi_monitor(edid)))) {
1995                 u32 bX = asyc->scaler.underscan.hborder;
1996                 u32 bY = asyc->scaler.underscan.vborder;
1997                 u32 r = (asyh->view.oH << 19) / asyh->view.oW;
1998
1999                 if (bX) {
2000                         asyh->view.oW -= (bX * 2);
2001                         if (bY) asyh->view.oH -= (bY * 2);
2002                         else    asyh->view.oH  = ((asyh->view.oW * r) + (r / 2)) >> 19;
2003                 } else {
2004                         asyh->view.oW -= (asyh->view.oW >> 4) + 32;
2005                         if (bY) asyh->view.oH -= (bY * 2);
2006                         else    asyh->view.oH  = ((asyh->view.oW * r) + (r / 2)) >> 19;
2007                 }
2008         }
2009
2010         /* Handle CENTER/ASPECT scaling, taking into account the areas
2011          * removed already for overscan compensation.
2012          */
2013         switch (mode) {
2014         case DRM_MODE_SCALE_CENTER:
2015                 asyh->view.oW = min((u16)umode->hdisplay, asyh->view.oW);
2016                 asyh->view.oH = min((u16)umode->vdisplay, asyh->view.oH);
2017                 /* fall-through */
2018         case DRM_MODE_SCALE_ASPECT:
2019                 if (asyh->view.oH < asyh->view.oW) {
2020                         u32 r = (asyh->view.iW << 19) / asyh->view.iH;
2021                         asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19;
2022                 } else {
2023                         u32 r = (asyh->view.iH << 19) / asyh->view.iW;
2024                         asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
2025                 }
2026                 break;
2027         default:
2028                 break;
2029         }
2030
2031         asyh->set.view = true;
2032 }
2033
2034 static void
2035 nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
2036 {
2037         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
2038         u32 ilace   = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
2039         u32 vscan   = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
2040         u32 hbackp  =  mode->htotal - mode->hsync_end;
2041         u32 vbackp  = (mode->vtotal - mode->vsync_end) * vscan / ilace;
2042         u32 hfrontp =  mode->hsync_start - mode->hdisplay;
2043         u32 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
2044         u32 blankus;
2045         struct nv50_head_mode *m = &asyh->mode;
2046
2047         m->h.active = mode->htotal;
2048         m->h.synce  = mode->hsync_end - mode->hsync_start - 1;
2049         m->h.blanke = m->h.synce + hbackp;
2050         m->h.blanks = mode->htotal - hfrontp - 1;
2051
2052         m->v.active = mode->vtotal * vscan / ilace;
2053         m->v.synce  = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
2054         m->v.blanke = m->v.synce + vbackp;
2055         m->v.blanks = m->v.active - vfrontp - 1;
2056
2057         /*XXX: Safe underestimate, even "0" works */
2058         blankus = (m->v.active - mode->vdisplay - 2) * m->h.active;
2059         blankus *= 1000;
2060         blankus /= mode->clock;
2061         m->v.blankus = blankus;
2062
2063         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2064                 m->v.blank2e =  m->v.active + m->v.synce + vbackp;
2065                 m->v.blank2s =  m->v.blank2e + (mode->vdisplay * vscan / ilace);
2066                 m->v.active  = (m->v.active * 2) + 1;
2067                 m->interlace = true;
2068         } else {
2069                 m->v.blank2e = 0;
2070                 m->v.blank2s = 1;
2071                 m->interlace = false;
2072         }
2073         m->clock = mode->clock;
2074
2075         drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
2076         asyh->set.mode = true;
2077 }
2078
2079 static int
2080 nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state)
2081 {
2082         struct nouveau_drm *drm = nouveau_drm(crtc->dev);
2083         struct nv50_disp *disp = nv50_disp(crtc->dev);
2084         struct nv50_head *head = nv50_head(crtc);
2085         struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
2086         struct nv50_head_atom *asyh = nv50_head_atom(state);
2087         struct nouveau_conn_atom *asyc = NULL;
2088         struct drm_connector_state *conns;
2089         struct drm_connector *conn;
2090         int i;
2091
2092         NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active);
2093         if (asyh->state.active) {
2094                 for_each_connector_in_state(asyh->state.state, conn, conns, i) {
2095                         if (conns->crtc == crtc) {
2096                                 asyc = nouveau_conn_atom(conns);
2097                                 break;
2098                         }
2099                 }
2100
2101                 if (armh->state.active) {
2102                         if (asyc) {
2103                                 if (asyh->state.mode_changed)
2104                                         asyc->set.scaler = true;
2105                                 if (armh->base.depth != asyh->base.depth)
2106                                         asyc->set.dither = true;
2107                         }
2108                 } else {
2109                         asyc->set.mask = ~0;
2110                         asyh->set.mask = ~0;
2111                 }
2112
2113                 if (asyh->state.mode_changed)
2114                         nv50_head_atomic_check_mode(head, asyh);
2115
2116                 if (asyc) {
2117                         if (asyc->set.scaler)
2118                                 nv50_head_atomic_check_view(armh, asyh, asyc);
2119                         if (asyc->set.dither)
2120                                 nv50_head_atomic_check_dither(armh, asyh, asyc);
2121                         if (asyc->set.procamp)
2122                                 nv50_head_atomic_check_procamp(armh, asyh, asyc);
2123                 }
2124
2125                 if ((asyh->core.visible = (asyh->base.cpp != 0))) {
2126                         asyh->core.x = asyh->base.x;
2127                         asyh->core.y = asyh->base.y;
2128                         asyh->core.w = asyh->base.w;
2129                         asyh->core.h = asyh->base.h;
2130                 } else
2131                 if ((asyh->core.visible = asyh->curs.visible)) {
2132                         /*XXX: We need to either find some way of having the
2133                          *     primary base layer appear black, while still
2134                          *     being able to display the other layers, or we
2135                          *     need to allocate a dummy black surface here.
2136                          */
2137                         asyh->core.x = 0;
2138                         asyh->core.y = 0;
2139                         asyh->core.w = asyh->state.mode.hdisplay;
2140                         asyh->core.h = asyh->state.mode.vdisplay;
2141                 }
2142                 asyh->core.handle = disp->mast.base.vram.handle;
2143                 asyh->core.offset = 0;
2144                 asyh->core.format = 0xcf;
2145                 asyh->core.kind = 0;
2146                 asyh->core.layout = 1;
2147                 asyh->core.block = 0;
2148                 asyh->core.pitch = ALIGN(asyh->core.w, 64) * 4;
2149                 asyh->lut.handle = disp->mast.base.vram.handle;
2150                 asyh->lut.offset = head->base.lut.nvbo->bo.offset;
2151                 asyh->set.base = armh->base.cpp != asyh->base.cpp;
2152                 asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp;
2153         } else {
2154                 asyh->core.visible = false;
2155                 asyh->curs.visible = false;
2156                 asyh->base.cpp = 0;
2157                 asyh->ovly.cpp = 0;
2158         }
2159
2160         if (!drm_atomic_crtc_needs_modeset(&asyh->state)) {
2161                 if (asyh->core.visible) {
2162                         if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core)))
2163                                 asyh->set.core = true;
2164                 } else
2165                 if (armh->core.visible) {
2166                         asyh->clr.core = true;
2167                 }
2168
2169                 if (asyh->curs.visible) {
2170                         if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs)))
2171                                 asyh->set.curs = true;
2172                 } else
2173                 if (armh->curs.visible) {
2174                         asyh->clr.curs = true;
2175                 }
2176         } else {
2177                 asyh->clr.core = armh->core.visible;
2178                 asyh->clr.curs = armh->curs.visible;
2179                 asyh->set.core = asyh->core.visible;
2180                 asyh->set.curs = asyh->curs.visible;
2181         }
2182
2183         if (asyh->clr.mask || asyh->set.mask)
2184                 nv50_atom(asyh->state.state)->lock_core = true;
2185         return 0;
2186 }
2187
2188 static void
2189 nv50_head_lut_load(struct drm_crtc *crtc)
2190 {
2191         struct nv50_disp *disp = nv50_disp(crtc->dev);
2192         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
2193         void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
2194         int i;
2195
2196         for (i = 0; i < 256; i++) {
2197                 u16 r = nv_crtc->lut.r[i] >> 2;
2198                 u16 g = nv_crtc->lut.g[i] >> 2;
2199                 u16 b = nv_crtc->lut.b[i] >> 2;
2200
2201                 if (disp->disp->oclass < GF110_DISP) {
2202                         writew(r + 0x0000, lut + (i * 0x08) + 0);
2203                         writew(g + 0x0000, lut + (i * 0x08) + 2);
2204                         writew(b + 0x0000, lut + (i * 0x08) + 4);
2205                 } else {
2206                         writew(r + 0x6000, lut + (i * 0x20) + 0);
2207                         writew(g + 0x6000, lut + (i * 0x20) + 2);
2208                         writew(b + 0x6000, lut + (i * 0x20) + 4);
2209                 }
2210         }
2211 }
2212
2213 static const struct drm_crtc_helper_funcs
2214 nv50_head_help = {
2215         .load_lut = nv50_head_lut_load,
2216         .atomic_check = nv50_head_atomic_check,
2217 };
2218
2219 static int
2220 nv50_head_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
2221                     uint32_t size,
2222                     struct drm_modeset_acquire_ctx *ctx)
2223 {
2224         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
2225         u32 i;
2226
2227         for (i = 0; i < size; i++) {
2228                 nv_crtc->lut.r[i] = r[i];
2229                 nv_crtc->lut.g[i] = g[i];
2230                 nv_crtc->lut.b[i] = b[i];
2231         }
2232
2233         nv50_head_lut_load(crtc);
2234         return 0;
2235 }
2236
2237 static void
2238 nv50_head_atomic_destroy_state(struct drm_crtc *crtc,
2239                                struct drm_crtc_state *state)
2240 {
2241         struct nv50_head_atom *asyh = nv50_head_atom(state);
2242         __drm_atomic_helper_crtc_destroy_state(&asyh->state);
2243         kfree(asyh);
2244 }
2245
2246 static struct drm_crtc_state *
2247 nv50_head_atomic_duplicate_state(struct drm_crtc *crtc)
2248 {
2249         struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
2250         struct nv50_head_atom *asyh;
2251         if (!(asyh = kmalloc(sizeof(*asyh), GFP_KERNEL)))
2252                 return NULL;
2253         __drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state);
2254         asyh->view = armh->view;
2255         asyh->mode = armh->mode;
2256         asyh->lut  = armh->lut;
2257         asyh->core = armh->core;
2258         asyh->curs = armh->curs;
2259         asyh->base = armh->base;
2260         asyh->ovly = armh->ovly;
2261         asyh->dither = armh->dither;
2262         asyh->procamp = armh->procamp;
2263         asyh->clr.mask = 0;
2264         asyh->set.mask = 0;
2265         return &asyh->state;
2266 }
2267
2268 static void
2269 __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc,
2270                                struct drm_crtc_state *state)
2271 {
2272         if (crtc->state)
2273                 crtc->funcs->atomic_destroy_state(crtc, crtc->state);
2274         crtc->state = state;
2275         crtc->state->crtc = crtc;
2276 }
2277
2278 static void
2279 nv50_head_reset(struct drm_crtc *crtc)
2280 {
2281         struct nv50_head_atom *asyh;
2282
2283         if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL))))
2284                 return;
2285
2286         __drm_atomic_helper_crtc_reset(crtc, &asyh->state);
2287 }
2288
2289 static void
2290 nv50_head_destroy(struct drm_crtc *crtc)
2291 {
2292         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
2293         struct nv50_disp *disp = nv50_disp(crtc->dev);
2294         struct nv50_head *head = nv50_head(crtc);
2295
2296         nv50_dmac_destroy(&head->ovly.base, disp->disp);
2297         nv50_pioc_destroy(&head->oimm.base);
2298
2299         nouveau_bo_unmap(nv_crtc->lut.nvbo);
2300         if (nv_crtc->lut.nvbo)
2301                 nouveau_bo_unpin(nv_crtc->lut.nvbo);
2302         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
2303
2304         drm_crtc_cleanup(crtc);
2305         kfree(crtc);
2306 }
2307
2308 static const struct drm_crtc_funcs
2309 nv50_head_func = {
2310         .reset = nv50_head_reset,
2311         .gamma_set = nv50_head_gamma_set,
2312         .destroy = nv50_head_destroy,
2313         .set_config = drm_atomic_helper_set_config,
2314         .page_flip = drm_atomic_helper_page_flip,
2315         .set_property = drm_atomic_helper_crtc_set_property,
2316         .atomic_duplicate_state = nv50_head_atomic_duplicate_state,
2317         .atomic_destroy_state = nv50_head_atomic_destroy_state,
2318 };
2319
2320 static int
2321 nv50_head_create(struct drm_device *dev, int index)
2322 {
2323         struct nouveau_drm *drm = nouveau_drm(dev);
2324         struct nvif_device *device = &drm->client.device;
2325         struct nv50_disp *disp = nv50_disp(dev);
2326         struct nv50_head *head;
2327         struct nv50_base *base;
2328         struct nv50_curs *curs;
2329         struct drm_crtc *crtc;
2330         int ret, i;
2331
2332         head = kzalloc(sizeof(*head), GFP_KERNEL);
2333         if (!head)
2334                 return -ENOMEM;
2335
2336         head->base.index = index;
2337         for (i = 0; i < 256; i++) {
2338                 head->base.lut.r[i] = i << 8;
2339                 head->base.lut.g[i] = i << 8;
2340                 head->base.lut.b[i] = i << 8;
2341         }
2342
2343         ret = nv50_base_new(drm, head, &base);
2344         if (ret == 0)
2345                 ret = nv50_curs_new(drm, head, &curs);
2346         if (ret) {
2347                 kfree(head);
2348                 return ret;
2349         }
2350
2351         crtc = &head->base.base;
2352         drm_crtc_init_with_planes(dev, crtc, &base->wndw.plane,
2353                                   &curs->wndw.plane, &nv50_head_func,
2354                                   "head-%d", head->base.index);
2355         drm_crtc_helper_add(crtc, &nv50_head_help);
2356         drm_mode_crtc_set_gamma_size(crtc, 256);
2357
2358         ret = nouveau_bo_new(&drm->client, 8192, 0x100, TTM_PL_FLAG_VRAM,
2359                              0, 0x0000, NULL, NULL, &head->base.lut.nvbo);
2360         if (!ret) {
2361                 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM, true);
2362                 if (!ret) {
2363                         ret = nouveau_bo_map(head->base.lut.nvbo);
2364                         if (ret)
2365                                 nouveau_bo_unpin(head->base.lut.nvbo);
2366                 }
2367                 if (ret)
2368                         nouveau_bo_ref(NULL, &head->base.lut.nvbo);
2369         }
2370
2371         if (ret)
2372                 goto out;
2373
2374         /* allocate overlay resources */
2375         ret = nv50_oimm_create(device, disp->disp, index, &head->oimm);
2376         if (ret)
2377                 goto out;
2378
2379         ret = nv50_ovly_create(device, disp->disp, index, disp->sync->bo.offset,
2380                                &head->ovly);
2381         if (ret)
2382                 goto out;
2383
2384 out:
2385         if (ret)
2386                 nv50_head_destroy(crtc);
2387         return ret;
2388 }
2389
2390 /******************************************************************************
2391  * Output path helpers
2392  *****************************************************************************/
2393 static int
2394 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
2395                             struct drm_crtc_state *crtc_state,
2396                             struct drm_connector_state *conn_state,
2397                             struct drm_display_mode *native_mode)
2398 {
2399         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
2400         struct drm_display_mode *mode = &crtc_state->mode;
2401         struct drm_connector *connector = conn_state->connector;
2402         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
2403         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
2404
2405         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
2406         asyc->scaler.full = false;
2407         if (!native_mode)
2408                 return 0;
2409
2410         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
2411                 switch (connector->connector_type) {
2412                 case DRM_MODE_CONNECTOR_LVDS:
2413                 case DRM_MODE_CONNECTOR_eDP:
2414                         /* Force use of scaler for non-EDID modes. */
2415                         if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
2416                                 break;
2417                         mode = native_mode;
2418                         asyc->scaler.full = true;
2419                         break;
2420                 default:
2421                         break;
2422                 }
2423         } else {
2424                 mode = native_mode;
2425         }
2426
2427         if (!drm_mode_equal(adjusted_mode, mode)) {
2428                 drm_mode_copy(adjusted_mode, mode);
2429                 crtc_state->mode_changed = true;
2430         }
2431
2432         return 0;
2433 }
2434
2435 static int
2436 nv50_outp_atomic_check(struct drm_encoder *encoder,
2437                        struct drm_crtc_state *crtc_state,
2438                        struct drm_connector_state *conn_state)
2439 {
2440         struct nouveau_connector *nv_connector =
2441                 nouveau_connector(conn_state->connector);
2442         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
2443                                            nv_connector->native_mode);
2444 }
2445
2446 /******************************************************************************
2447  * DAC
2448  *****************************************************************************/
2449 static void
2450 nv50_dac_dpms(struct drm_encoder *encoder, int mode)
2451 {
2452         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2453         struct nv50_disp *disp = nv50_disp(encoder->dev);
2454         struct {
2455                 struct nv50_disp_mthd_v1 base;
2456                 struct nv50_disp_dac_pwr_v0 pwr;
2457         } args = {
2458                 .base.version = 1,
2459                 .base.method = NV50_DISP_MTHD_V1_DAC_PWR,
2460                 .base.hasht  = nv_encoder->dcb->hasht,
2461                 .base.hashm  = nv_encoder->dcb->hashm,
2462                 .pwr.state = 1,
2463                 .pwr.data  = 1,
2464                 .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND &&
2465                               mode != DRM_MODE_DPMS_OFF),
2466                 .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY &&
2467                               mode != DRM_MODE_DPMS_OFF),
2468         };
2469
2470         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2471 }
2472
2473 static void
2474 nv50_dac_disable(struct drm_encoder *encoder)
2475 {
2476         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2477         struct nv50_mast *mast = nv50_mast(encoder->dev);
2478         const int or = nv_encoder->or;
2479         u32 *push;
2480
2481         if (nv_encoder->crtc) {
2482                 push = evo_wait(mast, 4);
2483                 if (push) {
2484                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2485                                 evo_mthd(push, 0x0400 + (or * 0x080), 1);
2486                                 evo_data(push, 0x00000000);
2487                         } else {
2488                                 evo_mthd(push, 0x0180 + (or * 0x020), 1);
2489                                 evo_data(push, 0x00000000);
2490                         }
2491                         evo_kick(push, mast);
2492                 }
2493         }
2494
2495         nv_encoder->crtc = NULL;
2496 }
2497
2498 static void
2499 nv50_dac_enable(struct drm_encoder *encoder)
2500 {
2501         struct nv50_mast *mast = nv50_mast(encoder->dev);
2502         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2503         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2504         struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
2505         u32 *push;
2506
2507         push = evo_wait(mast, 8);
2508         if (push) {
2509                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2510                         u32 syncs = 0x00000000;
2511
2512                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2513                                 syncs |= 0x00000001;
2514                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2515                                 syncs |= 0x00000002;
2516
2517                         evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
2518                         evo_data(push, 1 << nv_crtc->index);
2519                         evo_data(push, syncs);
2520                 } else {
2521                         u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
2522                         u32 syncs = 0x00000001;
2523
2524                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2525                                 syncs |= 0x00000008;
2526                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2527                                 syncs |= 0x00000010;
2528
2529                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2530                                 magic |= 0x00000001;
2531
2532                         evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
2533                         evo_data(push, syncs);
2534                         evo_data(push, magic);
2535                         evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
2536                         evo_data(push, 1 << nv_crtc->index);
2537                 }
2538
2539                 evo_kick(push, mast);
2540         }
2541
2542         nv_encoder->crtc = encoder->crtc;
2543 }
2544
2545 static enum drm_connector_status
2546 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2547 {
2548         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2549         struct nv50_disp *disp = nv50_disp(encoder->dev);
2550         struct {
2551                 struct nv50_disp_mthd_v1 base;
2552                 struct nv50_disp_dac_load_v0 load;
2553         } args = {
2554                 .base.version = 1,
2555                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
2556                 .base.hasht  = nv_encoder->dcb->hasht,
2557                 .base.hashm  = nv_encoder->dcb->hashm,
2558         };
2559         int ret;
2560
2561         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
2562         if (args.load.data == 0)
2563                 args.load.data = 340;
2564
2565         ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
2566         if (ret || !args.load.load)
2567                 return connector_status_disconnected;
2568
2569         return connector_status_connected;
2570 }
2571
2572 static const struct drm_encoder_helper_funcs
2573 nv50_dac_help = {
2574         .dpms = nv50_dac_dpms,
2575         .atomic_check = nv50_outp_atomic_check,
2576         .enable = nv50_dac_enable,
2577         .disable = nv50_dac_disable,
2578         .detect = nv50_dac_detect
2579 };
2580
2581 static void
2582 nv50_dac_destroy(struct drm_encoder *encoder)
2583 {
2584         drm_encoder_cleanup(encoder);
2585         kfree(encoder);
2586 }
2587
2588 static const struct drm_encoder_funcs
2589 nv50_dac_func = {
2590         .destroy = nv50_dac_destroy,
2591 };
2592
2593 static int
2594 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
2595 {
2596         struct nouveau_drm *drm = nouveau_drm(connector->dev);
2597         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
2598         struct nvkm_i2c_bus *bus;
2599         struct nouveau_encoder *nv_encoder;
2600         struct drm_encoder *encoder;
2601         int type = DRM_MODE_ENCODER_DAC;
2602
2603         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2604         if (!nv_encoder)
2605                 return -ENOMEM;
2606         nv_encoder->dcb = dcbe;
2607         nv_encoder->or = ffs(dcbe->or) - 1;
2608
2609         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
2610         if (bus)
2611                 nv_encoder->i2c = &bus->i2c;
2612
2613         encoder = to_drm_encoder(nv_encoder);
2614         encoder->possible_crtcs = dcbe->heads;
2615         encoder->possible_clones = 0;
2616         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
2617                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
2618         drm_encoder_helper_add(encoder, &nv50_dac_help);
2619
2620         drm_mode_connector_attach_encoder(connector, encoder);
2621         return 0;
2622 }
2623
2624 /******************************************************************************
2625  * Audio
2626  *****************************************************************************/
2627 static void
2628 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
2629 {
2630         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2631         struct nv50_disp *disp = nv50_disp(encoder->dev);
2632         struct {
2633                 struct nv50_disp_mthd_v1 base;
2634                 struct nv50_disp_sor_hda_eld_v0 eld;
2635         } args = {
2636                 .base.version = 1,
2637                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
2638                 .base.hasht   = nv_encoder->dcb->hasht,
2639                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
2640                                 (0x0100 << nv_crtc->index),
2641         };
2642
2643         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2644 }
2645
2646 static void
2647 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
2648 {
2649         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2650         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2651         struct nouveau_connector *nv_connector;
2652         struct nv50_disp *disp = nv50_disp(encoder->dev);
2653         struct __packed {
2654                 struct {
2655                         struct nv50_disp_mthd_v1 mthd;
2656                         struct nv50_disp_sor_hda_eld_v0 eld;
2657                 } base;
2658                 u8 data[sizeof(nv_connector->base.eld)];
2659         } args = {
2660                 .base.mthd.version = 1,
2661                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
2662                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
2663                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
2664                                      (0x0100 << nv_crtc->index),
2665         };
2666
2667         nv_connector = nouveau_encoder_connector_get(nv_encoder);
2668         if (!drm_detect_monitor_audio(nv_connector->edid))
2669                 return;
2670
2671         drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
2672         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
2673
2674         nvif_mthd(disp->disp, 0, &args,
2675                   sizeof(args.base) + drm_eld_size(args.data));
2676 }
2677
2678 /******************************************************************************
2679  * HDMI
2680  *****************************************************************************/
2681 static void
2682 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
2683 {
2684         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2685         struct nv50_disp *disp = nv50_disp(encoder->dev);
2686         struct {
2687                 struct nv50_disp_mthd_v1 base;
2688                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
2689         } args = {
2690                 .base.version = 1,
2691                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
2692                 .base.hasht  = nv_encoder->dcb->hasht,
2693                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
2694                                (0x0100 << nv_crtc->index),
2695         };
2696
2697         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2698 }
2699
2700 static void
2701 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
2702 {
2703         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2704         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2705         struct nv50_disp *disp = nv50_disp(encoder->dev);
2706         struct {
2707                 struct nv50_disp_mthd_v1 base;
2708                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
2709         } args = {
2710                 .base.version = 1,
2711                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
2712                 .base.hasht  = nv_encoder->dcb->hasht,
2713                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
2714                                (0x0100 << nv_crtc->index),
2715                 .pwr.state = 1,
2716                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
2717         };
2718         struct nouveau_connector *nv_connector;
2719         u32 max_ac_packet;
2720
2721         nv_connector = nouveau_encoder_connector_get(nv_encoder);
2722         if (!drm_detect_hdmi_monitor(nv_connector->edid))
2723                 return;
2724
2725         max_ac_packet  = mode->htotal - mode->hdisplay;
2726         max_ac_packet -= args.pwr.rekey;
2727         max_ac_packet -= 18; /* constant from tegra */
2728         args.pwr.max_ac_packet = max_ac_packet / 32;
2729
2730         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2731         nv50_audio_enable(encoder, mode);
2732 }
2733
2734 /******************************************************************************
2735  * MST
2736  *****************************************************************************/
2737 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
2738 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
2739 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
2740
2741 struct nv50_mstm {
2742         struct nouveau_encoder *outp;
2743
2744         struct drm_dp_mst_topology_mgr mgr;
2745         struct nv50_msto *msto[4];
2746
2747         bool modified;
2748 };
2749
2750 struct nv50_mstc {
2751         struct nv50_mstm *mstm;
2752         struct drm_dp_mst_port *port;
2753         struct drm_connector connector;
2754
2755         struct drm_display_mode *native;
2756         struct edid *edid;
2757
2758         int pbn;
2759 };
2760
2761 struct nv50_msto {
2762         struct drm_encoder encoder;
2763
2764         struct nv50_head *head;
2765         struct nv50_mstc *mstc;
2766         bool disabled;
2767 };
2768
2769 static struct drm_dp_payload *
2770 nv50_msto_payload(struct nv50_msto *msto)
2771 {
2772         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2773         struct nv50_mstc *mstc = msto->mstc;
2774         struct nv50_mstm *mstm = mstc->mstm;
2775         int vcpi = mstc->port->vcpi.vcpi, i;
2776
2777         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
2778         for (i = 0; i < mstm->mgr.max_payloads; i++) {
2779                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
2780                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
2781                           mstm->outp->base.base.name, i, payload->vcpi,
2782                           payload->start_slot, payload->num_slots);
2783         }
2784
2785         for (i = 0; i < mstm->mgr.max_payloads; i++) {
2786                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
2787                 if (payload->vcpi == vcpi)
2788                         return payload;
2789         }
2790
2791         return NULL;
2792 }
2793
2794 static void
2795 nv50_msto_cleanup(struct nv50_msto *msto)
2796 {
2797         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2798         struct nv50_mstc *mstc = msto->mstc;
2799         struct nv50_mstm *mstm = mstc->mstm;
2800
2801         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
2802         if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto))
2803                 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
2804         if (msto->disabled) {
2805                 msto->mstc = NULL;
2806                 msto->head = NULL;
2807                 msto->disabled = false;
2808         }
2809 }
2810
2811 static void
2812 nv50_msto_prepare(struct nv50_msto *msto)
2813 {
2814         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2815         struct nv50_mstc *mstc = msto->mstc;
2816         struct nv50_mstm *mstm = mstc->mstm;
2817         struct {
2818                 struct nv50_disp_mthd_v1 base;
2819                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
2820         } args = {
2821                 .base.version = 1,
2822                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
2823                 .base.hasht  = mstm->outp->dcb->hasht,
2824                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
2825                                (0x0100 << msto->head->base.index),
2826         };
2827
2828         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
2829         if (mstc->port && mstc->port->vcpi.vcpi > 0) {
2830                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
2831                 if (payload) {
2832                         args.vcpi.start_slot = payload->start_slot;
2833                         args.vcpi.num_slots = payload->num_slots;
2834                         args.vcpi.pbn = mstc->port->vcpi.pbn;
2835                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
2836                 }
2837         }
2838
2839         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
2840                   msto->encoder.name, msto->head->base.base.name,
2841                   args.vcpi.start_slot, args.vcpi.num_slots,
2842                   args.vcpi.pbn, args.vcpi.aligned_pbn);
2843         nvif_mthd(&drm->display->disp, 0, &args, sizeof(args));
2844 }
2845
2846 static int
2847 nv50_msto_atomic_check(struct drm_encoder *encoder,
2848                        struct drm_crtc_state *crtc_state,
2849                        struct drm_connector_state *conn_state)
2850 {
2851         struct nv50_mstc *mstc = nv50_mstc(conn_state->connector);
2852         struct nv50_mstm *mstm = mstc->mstm;
2853         int bpp = conn_state->connector->display_info.bpc * 3;
2854         int slots;
2855
2856         mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp);
2857
2858         slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
2859         if (slots < 0)
2860                 return slots;
2861
2862         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
2863                                            mstc->native);
2864 }
2865
2866 static void
2867 nv50_msto_enable(struct drm_encoder *encoder)
2868 {
2869         struct nv50_head *head = nv50_head(encoder->crtc);
2870         struct nv50_msto *msto = nv50_msto(encoder);
2871         struct nv50_mstc *mstc = NULL;
2872         struct nv50_mstm *mstm = NULL;
2873         struct drm_connector *connector;
2874         u8 proto, depth;
2875         int slots;
2876         bool r;
2877
2878         drm_for_each_connector(connector, encoder->dev) {
2879                 if (connector->state->best_encoder == &msto->encoder) {
2880                         mstc = nv50_mstc(connector);
2881                         mstm = mstc->mstm;
2882                         break;
2883                 }
2884         }
2885
2886         if (WARN_ON(!mstc))
2887                 return;
2888
2889         slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
2890         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots);
2891         WARN_ON(!r);
2892
2893         if (mstm->outp->dcb->sorconf.link & 1)
2894                 proto = 0x8;
2895         else
2896                 proto = 0x9;
2897
2898         switch (mstc->connector.display_info.bpc) {
2899         case  6: depth = 0x2; break;
2900         case  8: depth = 0x5; break;
2901         case 10:
2902         default: depth = 0x6; break;
2903         }
2904
2905         mstm->outp->update(mstm->outp, head->base.index,
2906                            &head->base.base.state->adjusted_mode, proto, depth);
2907
2908         msto->head = head;
2909         msto->mstc = mstc;
2910         mstm->modified = true;
2911 }
2912
2913 static void
2914 nv50_msto_disable(struct drm_encoder *encoder)
2915 {
2916         struct nv50_msto *msto = nv50_msto(encoder);
2917         struct nv50_mstc *mstc = msto->mstc;
2918         struct nv50_mstm *mstm = mstc->mstm;
2919
2920         if (mstc->port)
2921                 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
2922
2923         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
2924         mstm->modified = true;
2925         msto->disabled = true;
2926 }
2927
2928 static const struct drm_encoder_helper_funcs
2929 nv50_msto_help = {
2930         .disable = nv50_msto_disable,
2931         .enable = nv50_msto_enable,
2932         .atomic_check = nv50_msto_atomic_check,
2933 };
2934
2935 static void
2936 nv50_msto_destroy(struct drm_encoder *encoder)
2937 {
2938         struct nv50_msto *msto = nv50_msto(encoder);
2939         drm_encoder_cleanup(&msto->encoder);
2940         kfree(msto);
2941 }
2942
2943 static const struct drm_encoder_funcs
2944 nv50_msto = {
2945         .destroy = nv50_msto_destroy,
2946 };
2947
2948 static int
2949 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
2950               struct nv50_msto **pmsto)
2951 {
2952         struct nv50_msto *msto;
2953         int ret;
2954
2955         if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
2956                 return -ENOMEM;
2957
2958         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
2959                                DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
2960         if (ret) {
2961                 kfree(*pmsto);
2962                 *pmsto = NULL;
2963                 return ret;
2964         }
2965
2966         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
2967         msto->encoder.possible_crtcs = heads;
2968         return 0;
2969 }
2970
2971 static struct drm_encoder *
2972 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
2973                               struct drm_connector_state *connector_state)
2974 {
2975         struct nv50_head *head = nv50_head(connector_state->crtc);
2976         struct nv50_mstc *mstc = nv50_mstc(connector);
2977         if (mstc->port) {
2978                 struct nv50_mstm *mstm = mstc->mstm;
2979                 return &mstm->msto[head->base.index]->encoder;
2980         }
2981         return NULL;
2982 }
2983
2984 static struct drm_encoder *
2985 nv50_mstc_best_encoder(struct drm_connector *connector)
2986 {
2987         struct nv50_mstc *mstc = nv50_mstc(connector);
2988         if (mstc->port) {
2989                 struct nv50_mstm *mstm = mstc->mstm;
2990                 return &mstm->msto[0]->encoder;
2991         }
2992         return NULL;
2993 }
2994
2995 static enum drm_mode_status
2996 nv50_mstc_mode_valid(struct drm_connector *connector,
2997                      struct drm_display_mode *mode)
2998 {
2999         return MODE_OK;
3000 }
3001
3002 static int
3003 nv50_mstc_get_modes(struct drm_connector *connector)
3004 {
3005         struct nv50_mstc *mstc = nv50_mstc(connector);
3006         int ret = 0;
3007
3008         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
3009         drm_mode_connector_update_edid_property(&mstc->connector, mstc->edid);
3010         if (mstc->edid) {
3011                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
3012                 drm_edid_to_eld(&mstc->connector, mstc->edid);
3013         }
3014
3015         if (!mstc->connector.display_info.bpc)
3016                 mstc->connector.display_info.bpc = 8;
3017
3018         if (mstc->native)
3019                 drm_mode_destroy(mstc->connector.dev, mstc->native);
3020         mstc->native = nouveau_conn_native_mode(&mstc->connector);
3021         return ret;
3022 }
3023
3024 static const struct drm_connector_helper_funcs
3025 nv50_mstc_help = {
3026         .get_modes = nv50_mstc_get_modes,
3027         .mode_valid = nv50_mstc_mode_valid,
3028         .best_encoder = nv50_mstc_best_encoder,
3029         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
3030 };
3031
3032 static enum drm_connector_status
3033 nv50_mstc_detect(struct drm_connector *connector, bool force)
3034 {
3035         struct nv50_mstc *mstc = nv50_mstc(connector);
3036         if (!mstc->port)
3037                 return connector_status_disconnected;
3038         return drm_dp_mst_detect_port(connector, mstc->port->mgr, mstc->port);
3039 }
3040
3041 static void
3042 nv50_mstc_destroy(struct drm_connector *connector)
3043 {
3044         struct nv50_mstc *mstc = nv50_mstc(connector);
3045         drm_connector_cleanup(&mstc->connector);
3046         kfree(mstc);
3047 }
3048
3049 static const struct drm_connector_funcs
3050 nv50_mstc = {
3051         .dpms = drm_atomic_helper_connector_dpms,
3052         .reset = nouveau_conn_reset,
3053         .detect = nv50_mstc_detect,
3054         .fill_modes = drm_helper_probe_single_connector_modes,
3055         .set_property = drm_atomic_helper_connector_set_property,
3056         .destroy = nv50_mstc_destroy,
3057         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
3058         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
3059         .atomic_set_property = nouveau_conn_atomic_set_property,
3060         .atomic_get_property = nouveau_conn_atomic_get_property,
3061 };
3062
3063 static int
3064 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
3065               const char *path, struct nv50_mstc **pmstc)
3066 {
3067         struct drm_device *dev = mstm->outp->base.base.dev;
3068         struct nv50_mstc *mstc;
3069         int ret, i;
3070
3071         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
3072                 return -ENOMEM;
3073         mstc->mstm = mstm;
3074         mstc->port = port;
3075
3076         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
3077                                  DRM_MODE_CONNECTOR_DisplayPort);
3078         if (ret) {
3079                 kfree(*pmstc);
3080                 *pmstc = NULL;
3081                 return ret;
3082         }
3083
3084         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
3085
3086         mstc->connector.funcs->reset(&mstc->connector);
3087         nouveau_conn_attach_properties(&mstc->connector);
3088
3089         for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto; i++)
3090                 drm_mode_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
3091
3092         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
3093         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
3094         drm_mode_connector_set_path_property(&mstc->connector, path);
3095         return 0;
3096 }
3097
3098 static void
3099 nv50_mstm_cleanup(struct nv50_mstm *mstm)
3100 {
3101         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
3102         struct drm_encoder *encoder;
3103         int ret;
3104
3105         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
3106         ret = drm_dp_check_act_status(&mstm->mgr);
3107
3108         ret = drm_dp_update_payload_part2(&mstm->mgr);
3109
3110         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
3111                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
3112                         struct nv50_msto *msto = nv50_msto(encoder);
3113                         struct nv50_mstc *mstc = msto->mstc;
3114                         if (mstc && mstc->mstm == mstm)
3115                                 nv50_msto_cleanup(msto);
3116                 }
3117         }
3118
3119         mstm->modified = false;
3120 }
3121
3122 static void
3123 nv50_mstm_prepare(struct nv50_mstm *mstm)
3124 {
3125         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
3126         struct drm_encoder *encoder;
3127         int ret;
3128
3129         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
3130         ret = drm_dp_update_payload_part1(&mstm->mgr);
3131
3132         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
3133                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
3134                         struct nv50_msto *msto = nv50_msto(encoder);
3135                         struct nv50_mstc *mstc = msto->mstc;
3136                         if (mstc && mstc->mstm == mstm)
3137                                 nv50_msto_prepare(msto);
3138                 }
3139         }
3140 }
3141
3142 static void
3143 nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr)
3144 {
3145         struct nv50_mstm *mstm = nv50_mstm(mgr);
3146         drm_kms_helper_hotplug_event(mstm->outp->base.base.dev);
3147 }
3148
3149 static void
3150 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
3151                             struct drm_connector *connector)
3152 {
3153         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3154         struct nv50_mstc *mstc = nv50_mstc(connector);
3155
3156         drm_connector_unregister(&mstc->connector);
3157
3158         drm_modeset_lock_all(drm->dev);
3159         drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
3160         mstc->port = NULL;
3161         drm_modeset_unlock_all(drm->dev);
3162
3163         drm_connector_unreference(&mstc->connector);
3164 }
3165
3166 static void
3167 nv50_mstm_register_connector(struct drm_connector *connector)
3168 {
3169         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3170
3171         drm_modeset_lock_all(drm->dev);
3172         drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
3173         drm_modeset_unlock_all(drm->dev);
3174
3175         drm_connector_register(connector);
3176 }
3177
3178 static struct drm_connector *
3179 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
3180                         struct drm_dp_mst_port *port, const char *path)
3181 {
3182         struct nv50_mstm *mstm = nv50_mstm(mgr);
3183         struct nv50_mstc *mstc;
3184         int ret;
3185
3186         ret = nv50_mstc_new(mstm, port, path, &mstc);
3187         if (ret) {
3188                 if (mstc)
3189                         mstc->connector.funcs->destroy(&mstc->connector);
3190                 return NULL;
3191         }
3192
3193         return &mstc->connector;
3194 }
3195
3196 static const struct drm_dp_mst_topology_cbs
3197 nv50_mstm = {
3198         .add_connector = nv50_mstm_add_connector,
3199         .register_connector = nv50_mstm_register_connector,
3200         .destroy_connector = nv50_mstm_destroy_connector,
3201         .hotplug = nv50_mstm_hotplug,
3202 };
3203
3204 void
3205 nv50_mstm_service(struct nv50_mstm *mstm)
3206 {
3207         struct drm_dp_aux *aux = mstm->mgr.aux;
3208         bool handled = true;
3209         int ret;
3210         u8 esi[8] = {};
3211
3212         while (handled) {
3213                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
3214                 if (ret != 8) {
3215                         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
3216                         return;
3217                 }
3218
3219                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
3220                 if (!handled)
3221                         break;
3222
3223                 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
3224         }
3225 }
3226
3227 void
3228 nv50_mstm_remove(struct nv50_mstm *mstm)
3229 {
3230         if (mstm)
3231                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
3232 }
3233
3234 static int
3235 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
3236 {
3237         struct nouveau_encoder *outp = mstm->outp;
3238         struct {
3239                 struct nv50_disp_mthd_v1 base;
3240                 struct nv50_disp_sor_dp_mst_link_v0 mst;
3241         } args = {
3242                 .base.version = 1,
3243                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
3244                 .base.hasht = outp->dcb->hasht,
3245                 .base.hashm = outp->dcb->hashm,
3246                 .mst.state = state,
3247         };
3248         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
3249         struct nvif_object *disp = &drm->display->disp;
3250         int ret;
3251
3252         if (dpcd >= 0x12) {
3253                 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CTRL, &dpcd);
3254                 if (ret < 0)
3255                         return ret;
3256
3257                 dpcd &= ~DP_MST_EN;
3258                 if (state)
3259                         dpcd |= DP_MST_EN;
3260
3261                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, dpcd);
3262                 if (ret < 0)
3263                         return ret;
3264         }
3265
3266         return nvif_mthd(disp, 0, &args, sizeof(args));
3267 }
3268
3269 int
3270 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
3271 {
3272         int ret, state = 0;
3273
3274         if (!mstm)
3275                 return 0;
3276
3277         if (dpcd[0] >= 0x12) {
3278                 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CAP, &dpcd[1]);
3279                 if (ret < 0)
3280                         return ret;
3281
3282                 if (!(dpcd[1] & DP_MST_CAP))
3283                         dpcd[0] = 0x11;
3284                 else
3285                         state = allow;
3286         }
3287
3288         ret = nv50_mstm_enable(mstm, dpcd[0], state);
3289         if (ret)
3290                 return ret;
3291
3292         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, state);
3293         if (ret)
3294                 return nv50_mstm_enable(mstm, dpcd[0], 0);
3295
3296         return mstm->mgr.mst_state;
3297 }
3298
3299 static void
3300 nv50_mstm_fini(struct nv50_mstm *mstm)
3301 {
3302         if (mstm && mstm->mgr.mst_state)
3303                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
3304 }
3305
3306 static void
3307 nv50_mstm_init(struct nv50_mstm *mstm)
3308 {
3309         if (mstm && mstm->mgr.mst_state)
3310                 drm_dp_mst_topology_mgr_resume(&mstm->mgr);
3311 }
3312
3313 static void
3314 nv50_mstm_del(struct nv50_mstm **pmstm)
3315 {
3316         struct nv50_mstm *mstm = *pmstm;
3317         if (mstm) {
3318                 kfree(*pmstm);
3319                 *pmstm = NULL;
3320         }
3321 }
3322
3323 static int
3324 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
3325               int conn_base_id, struct nv50_mstm **pmstm)
3326 {
3327         const int max_payloads = hweight8(outp->dcb->heads);
3328         struct drm_device *dev = outp->base.base.dev;
3329         struct nv50_mstm *mstm;
3330         int ret, i;
3331         u8 dpcd;
3332
3333         /* This is a workaround for some monitors not functioning
3334          * correctly in MST mode on initial module load.  I think
3335          * some bad interaction with the VBIOS may be responsible.
3336          *
3337          * A good ol' off and on again seems to work here ;)
3338          */
3339         ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
3340         if (ret >= 0 && dpcd >= 0x12)
3341                 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
3342
3343         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
3344                 return -ENOMEM;
3345         mstm->outp = outp;
3346         mstm->mgr.cbs = &nv50_mstm;
3347
3348         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
3349                                            max_payloads, conn_base_id);
3350         if (ret)
3351                 return ret;
3352
3353         for (i = 0; i < max_payloads; i++) {
3354                 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
3355                                     i, &mstm->msto[i]);
3356                 if (ret)
3357                         return ret;
3358         }
3359
3360         return 0;
3361 }
3362
3363 /******************************************************************************
3364  * SOR
3365  *****************************************************************************/
3366 static void
3367 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
3368 {
3369         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3370         struct nv50_disp *disp = nv50_disp(encoder->dev);
3371         struct {
3372                 struct nv50_disp_mthd_v1 base;
3373                 struct nv50_disp_sor_pwr_v0 pwr;
3374         } args = {
3375                 .base.version = 1,
3376                 .base.method = NV50_DISP_MTHD_V1_SOR_PWR,
3377                 .base.hasht  = nv_encoder->dcb->hasht,
3378                 .base.hashm  = nv_encoder->dcb->hashm,
3379                 .pwr.state = mode == DRM_MODE_DPMS_ON,
3380         };
3381
3382         nvif_mthd(disp->disp, 0, &args, sizeof(args));
3383 }
3384
3385 static void
3386 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
3387                 struct drm_display_mode *mode, u8 proto, u8 depth)
3388 {
3389         struct nv50_dmac *core = &nv50_mast(nv_encoder->base.base.dev)->base;
3390         u32 *push;
3391
3392         if (!mode) {
3393                 nv_encoder->ctrl &= ~BIT(head);
3394                 if (!(nv_encoder->ctrl & 0x0000000f))
3395                         nv_encoder->ctrl = 0;
3396         } else {
3397                 nv_encoder->ctrl |= proto << 8;
3398                 nv_encoder->ctrl |= BIT(head);
3399         }
3400
3401         if ((push = evo_wait(core, 6))) {
3402                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
3403                         if (mode) {
3404                                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3405                                         nv_encoder->ctrl |= 0x00001000;
3406                                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3407                                         nv_encoder->ctrl |= 0x00002000;
3408                                 nv_encoder->ctrl |= depth << 16;
3409                         }
3410                         evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
3411                 } else {
3412                         if (mode) {
3413                                 u32 magic = 0x31ec6000 | (head << 25);
3414                                 u32 syncs = 0x00000001;
3415                                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3416                                         syncs |= 0x00000008;
3417                                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3418                                         syncs |= 0x00000010;
3419                                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
3420                                         magic |= 0x00000001;
3421
3422                                 evo_mthd(push, 0x0404 + (head * 0x300), 2);
3423                                 evo_data(push, syncs | (depth << 6));
3424                                 evo_data(push, magic);
3425                         }
3426                         evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
3427                 }
3428                 evo_data(push, nv_encoder->ctrl);
3429                 evo_kick(push, core);
3430         }
3431 }
3432
3433 static void
3434 nv50_sor_disable(struct drm_encoder *encoder)
3435 {
3436         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3437         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
3438
3439         nv_encoder->crtc = NULL;
3440
3441         if (nv_crtc) {
3442                 struct nvkm_i2c_aux *aux = nv_encoder->aux;
3443                 u8 pwr;
3444
3445                 if (aux) {
3446                         int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
3447                         if (ret == 0) {
3448                                 pwr &= ~DP_SET_POWER_MASK;
3449                                 pwr |=  DP_SET_POWER_D3;
3450                                 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
3451                         }
3452                 }
3453
3454                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
3455                 nv50_audio_disable(encoder, nv_crtc);
3456                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
3457         }
3458 }
3459
3460 static void
3461 nv50_sor_enable(struct drm_encoder *encoder)
3462 {
3463         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3464         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
3465         struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
3466         struct {
3467                 struct nv50_disp_mthd_v1 base;
3468                 struct nv50_disp_sor_lvds_script_v0 lvds;
3469         } lvds = {
3470                 .base.version = 1,
3471                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
3472                 .base.hasht   = nv_encoder->dcb->hasht,
3473                 .base.hashm   = nv_encoder->dcb->hashm,
3474         };
3475         struct nv50_disp *disp = nv50_disp(encoder->dev);
3476         struct drm_device *dev = encoder->dev;
3477         struct nouveau_drm *drm = nouveau_drm(dev);
3478         struct nouveau_connector *nv_connector;
3479         struct nvbios *bios = &drm->vbios;
3480         u8 proto = 0xf;
3481         u8 depth = 0x0;
3482
3483         nv_connector = nouveau_encoder_connector_get(nv_encoder);
3484         nv_encoder->crtc = encoder->crtc;
3485
3486         switch (nv_encoder->dcb->type) {
3487         case DCB_OUTPUT_TMDS:
3488                 if (nv_encoder->dcb->sorconf.link & 1) {
3489                         proto = 0x1;
3490                         /* Only enable dual-link if:
3491                          *  - Need to (i.e. rate > 165MHz)
3492                          *  - DCB says we can
3493                          *  - Not an HDMI monitor, since there's no dual-link
3494                          *    on HDMI.
3495                          */
3496                         if (mode->clock >= 165000 &&
3497                             nv_encoder->dcb->duallink_possible &&
3498                             !drm_detect_hdmi_monitor(nv_connector->edid))
3499                                 proto |= 0x4;
3500                 } else {
3501                         proto = 0x2;
3502                 }
3503
3504                 nv50_hdmi_enable(&nv_encoder->base.base, mode);
3505                 break;
3506         case DCB_OUTPUT_LVDS:
3507                 proto = 0x0;
3508
3509                 if (bios->fp_no_ddc) {
3510                         if (bios->fp.dual_link)
3511                                 lvds.lvds.script |= 0x0100;
3512                         if (bios->fp.if_is_24bit)
3513                                 lvds.lvds.script |= 0x0200;
3514                 } else {
3515                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
3516                                 if (((u8 *)nv_connector->edid)[121] == 2)
3517                                         lvds.lvds.script |= 0x0100;
3518                         } else
3519                         if (mode->clock >= bios->fp.duallink_transition_clk) {
3520                                 lvds.lvds.script |= 0x0100;
3521                         }
3522
3523                         if (lvds.lvds.script & 0x0100) {
3524                                 if (bios->fp.strapless_is_24bit & 2)
3525                                         lvds.lvds.script |= 0x0200;
3526                         } else {
3527                                 if (bios->fp.strapless_is_24bit & 1)
3528                                         lvds.lvds.script |= 0x0200;
3529                         }
3530
3531                         if (nv_connector->base.display_info.bpc == 8)
3532                                 lvds.lvds.script |= 0x0200;
3533                 }
3534
3535                 nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds));
3536                 break;
3537         case DCB_OUTPUT_DP:
3538                 if (nv_connector->base.display_info.bpc == 6)
3539                         depth = 0x2;
3540                 else
3541                 if (nv_connector->base.display_info.bpc == 8)
3542                         depth = 0x5;
3543                 else
3544                         depth = 0x6;
3545
3546                 if (nv_encoder->dcb->sorconf.link & 1)
3547                         proto = 0x8;
3548                 else
3549                         proto = 0x9;
3550
3551                 nv50_audio_enable(encoder, mode);
3552                 break;
3553         default:
3554                 BUG();
3555                 break;
3556         }
3557
3558         nv_encoder->update(nv_encoder, nv_crtc->index, mode, proto, depth);
3559 }
3560
3561 static const struct drm_encoder_helper_funcs
3562 nv50_sor_help = {
3563         .dpms = nv50_sor_dpms,
3564         .atomic_check = nv50_outp_atomic_check,
3565         .enable = nv50_sor_enable,
3566         .disable = nv50_sor_disable,
3567 };
3568
3569 static void
3570 nv50_sor_destroy(struct drm_encoder *encoder)
3571 {
3572         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3573         nv50_mstm_del(&nv_encoder->dp.mstm);
3574         drm_encoder_cleanup(encoder);
3575         kfree(encoder);
3576 }
3577
3578 static const struct drm_encoder_funcs
3579 nv50_sor_func = {
3580         .destroy = nv50_sor_destroy,
3581 };
3582
3583 static int
3584 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
3585 {
3586         struct nouveau_connector *nv_connector = nouveau_connector(connector);
3587         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3588         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
3589         struct nouveau_encoder *nv_encoder;
3590         struct drm_encoder *encoder;
3591         int type, ret;
3592
3593         switch (dcbe->type) {
3594         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
3595         case DCB_OUTPUT_TMDS:
3596         case DCB_OUTPUT_DP:
3597         default:
3598                 type = DRM_MODE_ENCODER_TMDS;
3599                 break;
3600         }
3601
3602         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
3603         if (!nv_encoder)
3604                 return -ENOMEM;
3605         nv_encoder->dcb = dcbe;
3606         nv_encoder->or = ffs(dcbe->or) - 1;
3607         nv_encoder->update = nv50_sor_update;
3608
3609         encoder = to_drm_encoder(nv_encoder);
3610         encoder->possible_crtcs = dcbe->heads;
3611         encoder->possible_clones = 0;
3612         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
3613                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
3614         drm_encoder_helper_add(encoder, &nv50_sor_help);
3615
3616         drm_mode_connector_attach_encoder(connector, encoder);
3617
3618         if (dcbe->type == DCB_OUTPUT_DP) {
3619                 struct nvkm_i2c_aux *aux =
3620                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
3621                 if (aux) {
3622                         nv_encoder->i2c = &nv_connector->aux.ddc;
3623                         nv_encoder->aux = aux;
3624                 }
3625
3626                 /*TODO: Use DP Info Table to check for support. */
3627                 if (nv50_disp(encoder->dev)->disp->oclass >= GF110_DISP) {
3628                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
3629                                             nv_connector->base.base.id,
3630                                             &nv_encoder->dp.mstm);
3631                         if (ret)
3632                                 return ret;
3633                 }
3634         } else {
3635                 struct nvkm_i2c_bus *bus =
3636                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
3637                 if (bus)
3638                         nv_encoder->i2c = &bus->i2c;
3639         }
3640
3641         return 0;
3642 }
3643
3644 /******************************************************************************
3645  * PIOR
3646  *****************************************************************************/
3647 static void
3648 nv50_pior_dpms(struct drm_encoder *encoder, int mode)
3649 {
3650         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3651         struct nv50_disp *disp = nv50_disp(encoder->dev);
3652         struct {
3653                 struct nv50_disp_mthd_v1 base;
3654                 struct nv50_disp_pior_pwr_v0 pwr;
3655         } args = {
3656                 .base.version = 1,
3657                 .base.method = NV50_DISP_MTHD_V1_PIOR_PWR,
3658                 .base.hasht  = nv_encoder->dcb->hasht,
3659                 .base.hashm  = nv_encoder->dcb->hashm,
3660                 .pwr.state = mode == DRM_MODE_DPMS_ON,
3661                 .pwr.type = nv_encoder->dcb->type,
3662         };
3663
3664         nvif_mthd(disp->disp, 0, &args, sizeof(args));
3665 }
3666
3667 static int
3668 nv50_pior_atomic_check(struct drm_encoder *encoder,
3669                        struct drm_crtc_state *crtc_state,
3670                        struct drm_connector_state *conn_state)
3671 {
3672         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
3673         if (ret)
3674                 return ret;
3675         crtc_state->adjusted_mode.clock *= 2;
3676         return 0;
3677 }
3678
3679 static void
3680 nv50_pior_disable(struct drm_encoder *encoder)
3681 {
3682         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3683         struct nv50_mast *mast = nv50_mast(encoder->dev);
3684         const int or = nv_encoder->or;
3685         u32 *push;
3686
3687         if (nv_encoder->crtc) {
3688                 push = evo_wait(mast, 4);
3689                 if (push) {
3690                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
3691                                 evo_mthd(push, 0x0700 + (or * 0x040), 1);
3692                                 evo_data(push, 0x00000000);
3693                         }
3694                         evo_kick(push, mast);
3695                 }
3696         }
3697
3698         nv_encoder->crtc = NULL;
3699 }
3700
3701 static void
3702 nv50_pior_enable(struct drm_encoder *encoder)
3703 {
3704         struct nv50_mast *mast = nv50_mast(encoder->dev);
3705         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3706         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
3707         struct nouveau_connector *nv_connector;
3708         struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
3709         u8 owner = 1 << nv_crtc->index;
3710         u8 proto, depth;
3711         u32 *push;
3712
3713         nv_connector = nouveau_encoder_connector_get(nv_encoder);
3714         switch (nv_connector->base.display_info.bpc) {
3715         case 10: depth = 0x6; break;
3716         case  8: depth = 0x5; break;
3717         case  6: depth = 0x2; break;
3718         default: depth = 0x0; break;
3719         }
3720
3721         switch (nv_encoder->dcb->type) {
3722         case DCB_OUTPUT_TMDS:
3723         case DCB_OUTPUT_DP:
3724                 proto = 0x0;
3725                 break;
3726         default:
3727                 BUG();
3728                 break;
3729         }
3730
3731         push = evo_wait(mast, 8);
3732         if (push) {
3733                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
3734                         u32 ctrl = (depth << 16) | (proto << 8) | owner;
3735                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3736                                 ctrl |= 0x00001000;
3737                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3738                                 ctrl |= 0x00002000;
3739                         evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
3740                         evo_data(push, ctrl);
3741                 }
3742
3743                 evo_kick(push, mast);
3744         }
3745
3746         nv_encoder->crtc = encoder->crtc;
3747 }
3748
3749 static const struct drm_encoder_helper_funcs
3750 nv50_pior_help = {
3751         .dpms = nv50_pior_dpms,
3752         .atomic_check = nv50_pior_atomic_check,
3753         .enable = nv50_pior_enable,
3754         .disable = nv50_pior_disable,
3755 };
3756
3757 static void
3758 nv50_pior_destroy(struct drm_encoder *encoder)
3759 {
3760         drm_encoder_cleanup(encoder);
3761         kfree(encoder);
3762 }
3763
3764 static const struct drm_encoder_funcs
3765 nv50_pior_func = {
3766         .destroy = nv50_pior_destroy,
3767 };
3768
3769 static int
3770 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
3771 {
3772         struct nouveau_connector *nv_connector = nouveau_connector(connector);
3773         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3774         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
3775         struct nvkm_i2c_bus *bus = NULL;
3776         struct nvkm_i2c_aux *aux = NULL;
3777         struct i2c_adapter *ddc;
3778         struct nouveau_encoder *nv_encoder;
3779         struct drm_encoder *encoder;
3780         int type;
3781
3782         switch (dcbe->type) {
3783         case DCB_OUTPUT_TMDS:
3784                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
3785                 ddc  = bus ? &bus->i2c : NULL;
3786                 type = DRM_MODE_ENCODER_TMDS;
3787                 break;
3788         case DCB_OUTPUT_DP:
3789                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
3790                 ddc  = aux ? &nv_connector->aux.ddc : NULL;
3791                 type = DRM_MODE_ENCODER_TMDS;
3792                 break;
3793         default:
3794                 return -ENODEV;
3795         }
3796
3797         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
3798         if (!nv_encoder)
3799                 return -ENOMEM;
3800         nv_encoder->dcb = dcbe;
3801         nv_encoder->or = ffs(dcbe->or) - 1;
3802         nv_encoder->i2c = ddc;
3803         nv_encoder->aux = aux;
3804
3805         encoder = to_drm_encoder(nv_encoder);
3806         encoder->possible_crtcs = dcbe->heads;
3807         encoder->possible_clones = 0;
3808         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
3809                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
3810         drm_encoder_helper_add(encoder, &nv50_pior_help);
3811
3812         drm_mode_connector_attach_encoder(connector, encoder);
3813         return 0;
3814 }
3815
3816 /******************************************************************************
3817  * Atomic
3818  *****************************************************************************/
3819
3820 static void
3821 nv50_disp_atomic_commit_core(struct nouveau_drm *drm, u32 interlock)
3822 {
3823         struct nv50_disp *disp = nv50_disp(drm->dev);
3824         struct nv50_dmac *core = &disp->mast.base;
3825         struct nv50_mstm *mstm;
3826         struct drm_encoder *encoder;
3827         u32 *push;
3828
3829         NV_ATOMIC(drm, "commit core %08x\n", interlock);
3830
3831         drm_for_each_encoder(encoder, drm->dev) {
3832                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
3833                         mstm = nouveau_encoder(encoder)->dp.mstm;
3834                         if (mstm && mstm->modified)
3835                                 nv50_mstm_prepare(mstm);
3836                 }
3837         }
3838
3839         if ((push = evo_wait(core, 5))) {
3840                 evo_mthd(push, 0x0084, 1);
3841                 evo_data(push, 0x80000000);
3842                 evo_mthd(push, 0x0080, 2);
3843                 evo_data(push, interlock);
3844                 evo_data(push, 0x00000000);
3845                 nouveau_bo_wr32(disp->sync, 0, 0x00000000);
3846                 evo_kick(push, core);
3847                 if (nvif_msec(&drm->client.device, 2000ULL,
3848                         if (nouveau_bo_rd32(disp->sync, 0))
3849                                 break;
3850                         usleep_range(1, 2);
3851                 ) < 0)
3852                         NV_ERROR(drm, "EVO timeout\n");
3853         }
3854
3855         drm_for_each_encoder(encoder, drm->dev) {
3856                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
3857                         mstm = nouveau_encoder(encoder)->dp.mstm;
3858                         if (mstm && mstm->modified)
3859                                 nv50_mstm_cleanup(mstm);
3860                 }
3861         }
3862 }
3863
3864 static void
3865 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
3866 {
3867         struct drm_device *dev = state->dev;
3868         struct drm_crtc_state *crtc_state;
3869         struct drm_crtc *crtc;
3870         struct drm_plane_state *plane_state;
3871         struct drm_plane *plane;
3872         struct nouveau_drm *drm = nouveau_drm(dev);
3873         struct nv50_disp *disp = nv50_disp(dev);
3874         struct nv50_atom *atom = nv50_atom(state);
3875         struct nv50_outp_atom *outp, *outt;
3876         u32 interlock_core = 0;
3877         u32 interlock_chan = 0;
3878         int i;
3879
3880         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
3881         drm_atomic_helper_wait_for_fences(dev, state, false);
3882         drm_atomic_helper_wait_for_dependencies(state);
3883         drm_atomic_helper_update_legacy_modeset_state(dev, state);
3884
3885         if (atom->lock_core)
3886                 mutex_lock(&disp->mutex);
3887
3888         /* Disable head(s). */
3889         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3890                 struct nv50_head_atom *asyh = nv50_head_atom(crtc->state);
3891                 struct nv50_head *head = nv50_head(crtc);
3892
3893                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
3894                           asyh->clr.mask, asyh->set.mask);
3895
3896                 if (asyh->clr.mask) {
3897                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
3898                         interlock_core |= 1;
3899                 }
3900         }
3901
3902         /* Disable plane(s). */
3903         for_each_plane_in_state(state, plane, plane_state, i) {
3904                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state);
3905                 struct nv50_wndw *wndw = nv50_wndw(plane);
3906
3907                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
3908                           asyw->clr.mask, asyw->set.mask);
3909                 if (!asyw->clr.mask)
3910                         continue;
3911
3912                 interlock_chan |= nv50_wndw_flush_clr(wndw, interlock_core,
3913                                                       atom->flush_disable,
3914                                                       asyw);
3915         }
3916
3917         /* Disable output path(s). */
3918         list_for_each_entry(outp, &atom->outp, head) {
3919                 const struct drm_encoder_helper_funcs *help;
3920                 struct drm_encoder *encoder;
3921
3922                 encoder = outp->encoder;
3923                 help = encoder->helper_private;
3924
3925                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
3926                           outp->clr.mask, outp->set.mask);
3927
3928                 if (outp->clr.mask) {
3929                         help->disable(encoder);
3930                         interlock_core |= 1;
3931                         if (outp->flush_disable) {
3932                                 nv50_disp_atomic_commit_core(drm, interlock_chan);
3933                                 interlock_core = 0;
3934                                 interlock_chan = 0;
3935                         }
3936                 }
3937         }
3938
3939         /* Flush disable. */
3940         if (interlock_core) {
3941                 if (atom->flush_disable) {
3942                         nv50_disp_atomic_commit_core(drm, interlock_chan);
3943                         interlock_core = 0;
3944                         interlock_chan = 0;
3945                 }
3946         }
3947
3948         /* Update output path(s). */
3949         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
3950                 const struct drm_encoder_helper_funcs *help;
3951                 struct drm_encoder *encoder;
3952
3953                 encoder = outp->encoder;
3954                 help = encoder->helper_private;
3955
3956                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
3957                           outp->set.mask, outp->clr.mask);
3958
3959                 if (outp->set.mask) {
3960                         help->enable(encoder);
3961                         interlock_core = 1;
3962                 }
3963
3964                 list_del(&outp->head);
3965                 kfree(outp);
3966         }
3967
3968         /* Update head(s). */
3969         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3970                 struct nv50_head_atom *asyh = nv50_head_atom(crtc->state);
3971                 struct nv50_head *head = nv50_head(crtc);
3972
3973                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
3974                           asyh->set.mask, asyh->clr.mask);
3975
3976                 if (asyh->set.mask) {
3977                         nv50_head_flush_set(head, asyh);
3978                         interlock_core = 1;
3979                 }
3980         }
3981
3982         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3983                 if (crtc->state->event)
3984                         drm_crtc_vblank_get(crtc);
3985         }
3986
3987         /* Update plane(s). */
3988         for_each_plane_in_state(state, plane, plane_state, i) {
3989                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state);
3990                 struct nv50_wndw *wndw = nv50_wndw(plane);
3991
3992                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
3993                           asyw->set.mask, asyw->clr.mask);
3994                 if ( !asyw->set.mask &&
3995                     (!asyw->clr.mask || atom->flush_disable))
3996                         continue;
3997
3998                 interlock_chan |= nv50_wndw_flush_set(wndw, interlock_core, asyw);
3999         }
4000
4001         /* Flush update. */
4002         if (interlock_core) {
4003                 if (!interlock_chan && atom->state.legacy_cursor_update) {
4004                         u32 *push = evo_wait(&disp->mast, 2);
4005                         if (push) {
4006                                 evo_mthd(push, 0x0080, 1);
4007                                 evo_data(push, 0x00000000);
4008                                 evo_kick(push, &disp->mast);
4009                         }
4010                 } else {
4011                         nv50_disp_atomic_commit_core(drm, interlock_chan);
4012                 }
4013         }
4014
4015         if (atom->lock_core)
4016                 mutex_unlock(&disp->mutex);
4017
4018         /* Wait for HW to signal completion. */
4019         for_each_plane_in_state(state, plane, plane_state, i) {
4020                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state);
4021                 struct nv50_wndw *wndw = nv50_wndw(plane);
4022                 int ret = nv50_wndw_wait_armed(wndw, asyw);
4023                 if (ret)
4024                         NV_ERROR(drm, "%s: timeout\n", plane->name);
4025         }
4026
4027         for_each_crtc_in_state(state, crtc, crtc_state, i) {
4028                 if (crtc->state->event) {
4029                         unsigned long flags;
4030                         /* Get correct count/ts if racing with vblank irq */
4031                         drm_accurate_vblank_count(crtc);
4032                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
4033                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
4034                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4035                         crtc->state->event = NULL;
4036                         drm_crtc_vblank_put(crtc);
4037                 }
4038         }
4039
4040         drm_atomic_helper_commit_hw_done(state);
4041         drm_atomic_helper_cleanup_planes(dev, state);
4042         drm_atomic_helper_commit_cleanup_done(state);
4043         drm_atomic_state_put(state);
4044 }
4045
4046 static void
4047 nv50_disp_atomic_commit_work(struct work_struct *work)
4048 {
4049         struct drm_atomic_state *state =
4050                 container_of(work, typeof(*state), commit_work);
4051         nv50_disp_atomic_commit_tail(state);
4052 }
4053
4054 static int
4055 nv50_disp_atomic_commit(struct drm_device *dev,
4056                         struct drm_atomic_state *state, bool nonblock)
4057 {
4058         struct nouveau_drm *drm = nouveau_drm(dev);
4059         struct nv50_disp *disp = nv50_disp(dev);
4060         struct drm_plane_state *plane_state;
4061         struct drm_plane *plane;
4062         struct drm_crtc *crtc;
4063         bool active = false;
4064         int ret, i;
4065
4066         ret = pm_runtime_get_sync(dev->dev);
4067         if (ret < 0 && ret != -EACCES)
4068                 return ret;
4069
4070         ret = drm_atomic_helper_setup_commit(state, nonblock);
4071         if (ret)
4072                 goto done;
4073
4074         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
4075
4076         ret = drm_atomic_helper_prepare_planes(dev, state);
4077         if (ret)
4078                 goto done;
4079
4080         if (!nonblock) {
4081                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
4082                 if (ret)
4083                         goto done;
4084         }
4085
4086         for_each_plane_in_state(state, plane, plane_state, i) {
4087                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane_state);
4088                 struct nv50_wndw *wndw = nv50_wndw(plane);
4089                 if (asyw->set.image) {
4090                         asyw->ntfy.handle = wndw->dmac->sync.handle;
4091                         asyw->ntfy.offset = wndw->ntfy;
4092                         asyw->ntfy.awaken = false;
4093                         asyw->set.ntfy = true;
4094                         nouveau_bo_wr32(disp->sync, wndw->ntfy / 4, 0x00000000);
4095                         wndw->ntfy ^= 0x10;
4096                 }
4097         }
4098
4099         drm_atomic_helper_swap_state(state, true);
4100         drm_atomic_state_get(state);
4101
4102         if (nonblock)
4103                 queue_work(system_unbound_wq, &state->commit_work);
4104         else
4105                 nv50_disp_atomic_commit_tail(state);
4106
4107         drm_for_each_crtc(crtc, dev) {
4108                 if (crtc->state->enable) {
4109                         if (!drm->have_disp_power_ref) {
4110                                 drm->have_disp_power_ref = true;
4111                                 return ret;
4112                         }
4113                         active = true;
4114                         break;
4115                 }
4116         }
4117
4118         if (!active && drm->have_disp_power_ref) {
4119                 pm_runtime_put_autosuspend(dev->dev);
4120                 drm->have_disp_power_ref = false;
4121         }
4122
4123 done:
4124         pm_runtime_put_autosuspend(dev->dev);
4125         return ret;
4126 }
4127
4128 static struct nv50_outp_atom *
4129 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
4130 {
4131         struct nv50_outp_atom *outp;
4132
4133         list_for_each_entry(outp, &atom->outp, head) {
4134                 if (outp->encoder == encoder)
4135                         return outp;
4136         }
4137
4138         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
4139         if (!outp)
4140                 return ERR_PTR(-ENOMEM);
4141
4142         list_add(&outp->head, &atom->outp);
4143         outp->encoder = encoder;
4144         return outp;
4145 }
4146
4147 static int
4148 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
4149                                 struct drm_connector *connector)
4150 {
4151         struct drm_encoder *encoder = connector->state->best_encoder;
4152         struct drm_crtc_state *crtc_state;
4153         struct drm_crtc *crtc;
4154         struct nv50_outp_atom *outp;
4155
4156         if (!(crtc = connector->state->crtc))
4157                 return 0;
4158
4159         crtc_state = drm_atomic_get_existing_crtc_state(&atom->state, crtc);
4160         if (crtc->state->active && drm_atomic_crtc_needs_modeset(crtc_state)) {
4161                 outp = nv50_disp_outp_atomic_add(atom, encoder);
4162                 if (IS_ERR(outp))
4163                         return PTR_ERR(outp);
4164
4165                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
4166                         outp->flush_disable = true;
4167                         atom->flush_disable = true;
4168                 }
4169                 outp->clr.ctrl = true;
4170                 atom->lock_core = true;
4171         }
4172
4173         return 0;
4174 }
4175
4176 static int
4177 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
4178                                 struct drm_connector_state *connector_state)
4179 {
4180         struct drm_encoder *encoder = connector_state->best_encoder;
4181         struct drm_crtc_state *crtc_state;
4182         struct drm_crtc *crtc;
4183         struct nv50_outp_atom *outp;
4184
4185         if (!(crtc = connector_state->crtc))
4186                 return 0;
4187
4188         crtc_state = drm_atomic_get_existing_crtc_state(&atom->state, crtc);
4189         if (crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state)) {
4190                 outp = nv50_disp_outp_atomic_add(atom, encoder);
4191                 if (IS_ERR(outp))
4192                         return PTR_ERR(outp);
4193
4194                 outp->set.ctrl = true;
4195                 atom->lock_core = true;
4196         }
4197
4198         return 0;
4199 }
4200
4201 static int
4202 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
4203 {
4204         struct nv50_atom *atom = nv50_atom(state);
4205         struct drm_connector_state *connector_state;
4206         struct drm_connector *connector;
4207         int ret, i;
4208
4209         ret = drm_atomic_helper_check(dev, state);
4210         if (ret)
4211                 return ret;
4212
4213         for_each_connector_in_state(state, connector, connector_state, i) {
4214                 ret = nv50_disp_outp_atomic_check_clr(atom, connector);
4215                 if (ret)
4216                         return ret;
4217
4218                 ret = nv50_disp_outp_atomic_check_set(atom, connector_state);
4219                 if (ret)
4220                         return ret;
4221         }
4222
4223         return 0;
4224 }
4225
4226 static void
4227 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
4228 {
4229         struct nv50_atom *atom = nv50_atom(state);
4230         struct nv50_outp_atom *outp, *outt;
4231
4232         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
4233                 list_del(&outp->head);
4234                 kfree(outp);
4235         }
4236
4237         drm_atomic_state_default_clear(state);
4238 }
4239
4240 static void
4241 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
4242 {
4243         struct nv50_atom *atom = nv50_atom(state);
4244         drm_atomic_state_default_release(&atom->state);
4245         kfree(atom);
4246 }
4247
4248 static struct drm_atomic_state *
4249 nv50_disp_atomic_state_alloc(struct drm_device *dev)
4250 {
4251         struct nv50_atom *atom;
4252         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
4253             drm_atomic_state_init(dev, &atom->state) < 0) {
4254                 kfree(atom);
4255                 return NULL;
4256         }
4257         INIT_LIST_HEAD(&atom->outp);
4258         return &atom->state;
4259 }
4260
4261 static const struct drm_mode_config_funcs
4262 nv50_disp_func = {
4263         .fb_create = nouveau_user_framebuffer_create,
4264         .output_poll_changed = nouveau_fbcon_output_poll_changed,
4265         .atomic_check = nv50_disp_atomic_check,
4266         .atomic_commit = nv50_disp_atomic_commit,
4267         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
4268         .atomic_state_clear = nv50_disp_atomic_state_clear,
4269         .atomic_state_free = nv50_disp_atomic_state_free,
4270 };
4271
4272 /******************************************************************************
4273  * Init
4274  *****************************************************************************/
4275
4276 void
4277 nv50_display_fini(struct drm_device *dev)
4278 {
4279         struct nouveau_encoder *nv_encoder;
4280         struct drm_encoder *encoder;
4281         struct drm_plane *plane;
4282
4283         drm_for_each_plane(plane, dev) {
4284                 struct nv50_wndw *wndw = nv50_wndw(plane);
4285                 if (plane->funcs != &nv50_wndw)
4286                         continue;
4287                 nv50_wndw_fini(wndw);
4288         }
4289
4290         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4291                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
4292                         nv_encoder = nouveau_encoder(encoder);
4293                         nv50_mstm_fini(nv_encoder->dp.mstm);
4294                 }
4295         }
4296 }
4297
4298 int
4299 nv50_display_init(struct drm_device *dev)
4300 {
4301         struct drm_encoder *encoder;
4302         struct drm_plane *plane;
4303         struct drm_crtc *crtc;
4304         u32 *push;
4305
4306         push = evo_wait(nv50_mast(dev), 32);
4307         if (!push)
4308                 return -EBUSY;
4309
4310         evo_mthd(push, 0x0088, 1);
4311         evo_data(push, nv50_mast(dev)->base.sync.handle);
4312         evo_kick(push, nv50_mast(dev));
4313
4314         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4315                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
4316                         const struct drm_encoder_helper_funcs *help;
4317                         struct nouveau_encoder *nv_encoder;
4318
4319                         nv_encoder = nouveau_encoder(encoder);
4320                         help = encoder->helper_private;
4321                         if (help && help->dpms)
4322                                 help->dpms(encoder, DRM_MODE_DPMS_ON);
4323
4324                         nv50_mstm_init(nv_encoder->dp.mstm);
4325                 }
4326         }
4327
4328         drm_for_each_crtc(crtc, dev) {
4329                 nv50_head_lut_load(crtc);
4330         }
4331
4332         drm_for_each_plane(plane, dev) {
4333                 struct nv50_wndw *wndw = nv50_wndw(plane);
4334                 if (plane->funcs != &nv50_wndw)
4335                         continue;
4336                 nv50_wndw_init(wndw);
4337         }
4338
4339         return 0;
4340 }
4341
4342 void
4343 nv50_display_destroy(struct drm_device *dev)
4344 {
4345         struct nv50_disp *disp = nv50_disp(dev);
4346
4347         nv50_dmac_destroy(&disp->mast.base, disp->disp);
4348
4349         nouveau_bo_unmap(disp->sync);
4350         if (disp->sync)
4351                 nouveau_bo_unpin(disp->sync);
4352         nouveau_bo_ref(NULL, &disp->sync);
4353
4354         nouveau_display(dev)->priv = NULL;
4355         kfree(disp);
4356 }
4357
4358 MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
4359 static int nouveau_atomic = 0;
4360 module_param_named(atomic, nouveau_atomic, int, 0400);
4361
4362 int
4363 nv50_display_create(struct drm_device *dev)
4364 {
4365         struct nvif_device *device = &nouveau_drm(dev)->client.device;
4366         struct nouveau_drm *drm = nouveau_drm(dev);
4367         struct dcb_table *dcb = &drm->vbios.dcb;
4368         struct drm_connector *connector, *tmp;
4369         struct nv50_disp *disp;
4370         struct dcb_output *dcbe;
4371         int crtcs, ret, i;
4372
4373         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
4374         if (!disp)
4375                 return -ENOMEM;
4376
4377         mutex_init(&disp->mutex);
4378
4379         nouveau_display(dev)->priv = disp;
4380         nouveau_display(dev)->dtor = nv50_display_destroy;
4381         nouveau_display(dev)->init = nv50_display_init;
4382         nouveau_display(dev)->fini = nv50_display_fini;
4383         disp->disp = &nouveau_display(dev)->disp;
4384         dev->mode_config.funcs = &nv50_disp_func;
4385         if (nouveau_atomic)
4386                 dev->driver->driver_features |= DRIVER_ATOMIC;
4387
4388         /* small shared memory area we use for notifiers and semaphores */
4389         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
4390                              0, 0x0000, NULL, NULL, &disp->sync);
4391         if (!ret) {
4392                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
4393                 if (!ret) {
4394                         ret = nouveau_bo_map(disp->sync);
4395                         if (ret)
4396                                 nouveau_bo_unpin(disp->sync);
4397                 }
4398                 if (ret)
4399                         nouveau_bo_ref(NULL, &disp->sync);
4400         }
4401
4402         if (ret)
4403                 goto out;
4404
4405         /* allocate master evo channel */
4406         ret = nv50_core_create(device, disp->disp, disp->sync->bo.offset,
4407                               &disp->mast);
4408         if (ret)
4409                 goto out;
4410
4411         /* create crtc objects to represent the hw heads */
4412         if (disp->disp->oclass >= GF110_DISP)
4413                 crtcs = nvif_rd32(&device->object, 0x022448);
4414         else
4415                 crtcs = 2;
4416
4417         for (i = 0; i < crtcs; i++) {
4418                 ret = nv50_head_create(dev, i);
4419                 if (ret)
4420                         goto out;
4421         }
4422
4423         /* create encoder/connector objects based on VBIOS DCB table */
4424         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
4425                 connector = nouveau_connector_create(dev, dcbe->connector);
4426                 if (IS_ERR(connector))
4427                         continue;
4428
4429                 if (dcbe->location == DCB_LOC_ON_CHIP) {
4430                         switch (dcbe->type) {
4431                         case DCB_OUTPUT_TMDS:
4432                         case DCB_OUTPUT_LVDS:
4433                         case DCB_OUTPUT_DP:
4434                                 ret = nv50_sor_create(connector, dcbe);
4435                                 break;
4436                         case DCB_OUTPUT_ANALOG:
4437                                 ret = nv50_dac_create(connector, dcbe);
4438                                 break;
4439                         default:
4440                                 ret = -ENODEV;
4441                                 break;
4442                         }
4443                 } else {
4444                         ret = nv50_pior_create(connector, dcbe);
4445                 }
4446
4447                 if (ret) {
4448                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
4449                                      dcbe->location, dcbe->type,
4450                                      ffs(dcbe->or) - 1, ret);
4451                         ret = 0;
4452                 }
4453         }
4454
4455         /* cull any connectors we created that don't have an encoder */
4456         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
4457                 if (connector->encoder_ids[0])
4458                         continue;
4459
4460                 NV_WARN(drm, "%s has no encoders, removing\n",
4461                         connector->name);
4462                 connector->funcs->destroy(connector);
4463         }
4464
4465 out:
4466         if (ret)
4467                 nv50_display_destroy(dev);
4468         return ret;
4469 }