drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26
  27 #include <drm/drmP.h>
  28 #include <drm/drm_atomic.h>
  29 #include <drm/drm_atomic_helper.h>
  30 #include <drm/drm_crtc_helper.h>
  31 #include <drm/drm_dp_helper.h>
  32 #include <drm/drm_fb_helper.h>
  33 #include <drm/drm_plane_helper.h>
  34
  35 #include <nvif/class.h>
  36 #include <nvif/cl0002.h>
  37 #include <nvif/cl5070.h>
  38 #include <nvif/cl507a.h>
  39 #include <nvif/cl507b.h>
  40 #include <nvif/cl507c.h>
  41 #include <nvif/cl507d.h>
  42 #include <nvif/cl507e.h>
  43 #include <nvif/event.h>
  44
  45 #include "nouveau_drv.h"
  46 #include "nouveau_dma.h"
  47 #include "nouveau_gem.h"
  48 #include "nouveau_connector.h"
  49 #include "nouveau_encoder.h"
  50 #include "nouveau_crtc.h"
  51 #include "nouveau_fence.h"
  52 #include "nouveau_fbcon.h"
  53 #include "nv50_display.h"
  54
  55 #define EVO_DMA_NR 9
  56
  57 #define EVO_MASTER  (0x00)
  58 #define EVO_FLIP(c) (0x01 + (c))
  59 #define EVO_OVLY(c) (0x05 + (c))
  60 #define EVO_OIMM(c) (0x09 + (c))
  61 #define EVO_CURS(c) (0x0d + (c))
  62
  63 /* offsets in shared sync bo of various structures */
  64 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
  65 #define EVO_MAST_NTFY     EVO_SYNC(      0, 0x00)
  66 #define EVO_FLIP_SEM0(c)  EVO_SYNC((c) + 1, 0x00)
  67 #define EVO_FLIP_SEM1(c)  EVO_SYNC((c) + 1, 0x10)
  68 #define EVO_FLIP_NTFY0(c) EVO_SYNC((c) + 1, 0x20)
  69 #define EVO_FLIP_NTFY1(c) EVO_SYNC((c) + 1, 0x30)
  70
  71 /******************************************************************************
  72  * Atomic state
  73  *****************************************************************************/
  74 #define nv50_atom(p) container_of((p), struct nv50_atom, state)
  75
  76 struct nv50_atom {
  77         struct drm_atomic_state state;
  78
  79         struct list_head outp;
  80         bool lock_core;
  81         bool flush_disable;
  82 };
  83
  84 struct nv50_outp_atom {
  85         struct list_head head;
  86
  87         struct drm_encoder *encoder;
  88         bool flush_disable;
  89
  90         union {
  91                 struct {
  92                         bool ctrl:1;
  93                 };
  94                 u8 mask;
  95         } clr;
  96
  97         union {
  98                 struct {
  99                         bool ctrl:1;
 100                 };
 101                 u8 mask;
 102         } set;
 103 };
 104
 105 #define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state)
 106
 107 struct nv50_head_atom {
 108         struct drm_crtc_state state;
 109
 110         struct {
 111                 u16 iW;
 112                 u16 iH;
 113                 u16 oW;
 114                 u16 oH;
 115         } view;
 116
 117         struct nv50_head_mode {
 118                 bool interlace;
 119                 u32 clock;
 120                 struct {
 121                         u16 active;
 122                         u16 synce;
 123                         u16 blanke;
 124                         u16 blanks;
 125                 } h;
 126                 struct {
 127                         u32 active;
 128                         u16 synce;
 129                         u16 blanke;
 130                         u16 blanks;
 131                         u16 blank2s;
 132                         u16 blank2e;
 133                         u16 blankus;
 134                 } v;
 135         } mode;
 136
 137         struct {
 138                 u32 handle;
 139                 u64 offset:40;
 140         } lut;
 141
 142         struct {
 143                 bool visible;
 144                 u32 handle;
 145                 u64 offset:40;
 146                 u8  format;
 147                 u8  kind:7;
 148                 u8  layout:1;
 149                 u8  block:4;
 150                 u32 pitch:20;
 151                 u16 x;
 152                 u16 y;
 153                 u16 w;
 154                 u16 h;
 155         } core;
 156
 157         struct {
 158                 bool visible;
 159                 u32 handle;
 160                 u64 offset:40;
 161                 u8  layout:1;
 162                 u8  format:1;
 163         } curs;
 164
 165         struct {
 166                 u8  depth;
 167                 u8  cpp;
 168                 u16 x;
 169                 u16 y;
 170                 u16 w;
 171                 u16 h;
 172         } base;
 173
 174         struct {
 175                 u8 cpp;
 176         } ovly;
 177
 178         struct {
 179                 bool enable:1;
 180                 u8 bits:2;
 181                 u8 mode:4;
 182         } dither;
 183
 184         struct {
 185                 struct {
 186                         u16 cos:12;
 187                         u16 sin:12;
 188                 } sat;
 189         } procamp;
 190
 191         union {
 192                 struct {
 193                         bool core:1;
 194                         bool curs:1;
 195                 };
 196                 u8 mask;
 197         } clr;
 198
 199         union {
 200                 struct {
 201                         bool core:1;
 202                         bool curs:1;
 203                         bool view:1;
 204                         bool mode:1;
 205                         bool base:1;
 206                         bool ovly:1;
 207                         bool dither:1;
 208                         bool procamp:1;
 209                 };
 210                 u16 mask;
 211         } set;
 212 };
 213
 214 static inline struct nv50_head_atom *
 215 nv50_head_atom_get(struct drm_atomic_state *state, struct drm_crtc *crtc)
 216 {
 217         struct drm_crtc_state *statec = drm_atomic_get_crtc_state(state, crtc);
 218         if (IS_ERR(statec))
 219                 return (void *)statec;
 220         return nv50_head_atom(statec);
 221 }
 222
 223 #define nv50_wndw_atom(p) container_of((p), struct nv50_wndw_atom, state)
 224
 225 struct nv50_wndw_atom {
 226         struct drm_plane_state state;
 227         u8 interval;
 228
 229         struct drm_rect clip;
 230
 231         struct {
 232                 u32  handle;
 233                 u16  offset:12;
 234                 bool awaken:1;
 235         } ntfy;
 236
 237         struct {
 238                 u32 handle;
 239                 u16 offset:12;
 240                 u32 acquire;
 241                 u32 release;
 242         } sema;
 243
 244         struct {
 245                 u8 enable:2;
 246         } lut;
 247
 248         struct {
 249                 u8  mode:2;
 250                 u8  interval:4;
 251
 252                 u8  format;
 253                 u8  kind:7;
 254                 u8  layout:1;
 255                 u8  block:4;
 256                 u32 pitch:20;
 257                 u16 w;
 258                 u16 h;
 259
 260                 u32 handle;
 261                 u64 offset;
 262         } image;
 263
 264         struct {
 265                 u16 x;
 266                 u16 y;
 267         } point;
 268
 269         union {
 270                 struct {
 271                         bool ntfy:1;
 272                         bool sema:1;
 273                         bool image:1;
 274                 };
 275                 u8 mask;
 276         } clr;
 277
 278         union {
 279                 struct {
 280                         bool ntfy:1;
 281                         bool sema:1;
 282                         bool image:1;
 283                         bool lut:1;
 284                         bool point:1;
 285                 };
 286                 u8 mask;
 287         } set;
 288 };
 289
 290 /******************************************************************************
 291  * EVO channel
 292  *****************************************************************************/
 293
 294 struct nv50_chan {
 295         struct nvif_object user;
 296         struct nvif_device *device;
 297 };
 298
 299 static int
 300 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
 301                  const s32 *oclass, u8 head, void *data, u32 size,
 302                  struct nv50_chan *chan)
 303 {
 304         struct nvif_sclass *sclass;
 305         int ret, i, n;
 306
 307         chan->device = device;
 308
 309         ret = n = nvif_object_sclass_get(disp, &sclass);
 310         if (ret < 0)
 311                 return ret;
 312
 313         while (oclass[0]) {
 314                 for (i = 0; i < n; i++) {
 315                         if (sclass[i].oclass == oclass[0]) {
 316                                 ret = nvif_object_init(disp, 0, oclass[0],
 317                                                        data, size, &chan->user);
 318                                 if (ret == 0)
 319                                         nvif_object_map(&chan->user);
 320                                 nvif_object_sclass_put(&sclass);
 321                                 return ret;
 322                         }
 323                 }
 324                 oclass++;
 325         }
 326
 327         nvif_object_sclass_put(&sclass);
 328         return -ENOSYS;
 329 }
 330
 331 static void
 332 nv50_chan_destroy(struct nv50_chan *chan)
 333 {
 334         nvif_object_fini(&chan->user);
 335 }
 336
 337 /******************************************************************************
 338  * PIO EVO channel
 339  *****************************************************************************/
 340
 341 struct nv50_pioc {
 342         struct nv50_chan base;
 343 };
 344
 345 static void
 346 nv50_pioc_destroy(struct nv50_pioc *pioc)
 347 {
 348         nv50_chan_destroy(&pioc->base);
 349 }
 350
 351 static int
 352 nv50_pioc_create(struct nvif_device *device, struct nvif_object *disp,
 353                  const s32 *oclass, u8 head, void *data, u32 size,
 354                  struct nv50_pioc *pioc)
 355 {
 356         return nv50_chan_create(device, disp, oclass, head, data, size,
 357                                 &pioc->base);
 358 }
 359
 360 /******************************************************************************
 361  * Overlay Immediate
 362  *****************************************************************************/
 363
 364 struct nv50_oimm {
 365         struct nv50_pioc base;
 366 };
 367
 368 static int
 369 nv50_oimm_create(struct nvif_device *device, struct nvif_object *disp,
 370                  int head, struct nv50_oimm *oimm)
 371 {
 372         struct nv50_disp_cursor_v0 args = {
 373                 .head = head,
 374         };
 375         static const s32 oclass[] = {
 376                 GK104_DISP_OVERLAY,
 377                 GF110_DISP_OVERLAY,
 378                 GT214_DISP_OVERLAY,
 379                 G82_DISP_OVERLAY,
 380                 NV50_DISP_OVERLAY,
 381                 0
 382         };
 383
 384         return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args),
 385                                 &oimm->base);
 386 }
 387
 388 /******************************************************************************
 389  * DMA EVO channel
 390  *****************************************************************************/
 391
 392 struct nv50_dmac_ctxdma {
 393         struct list_head head;
 394         struct nvif_object object;
 395 };
 396
 397 struct nv50_dmac {
 398         struct nv50_chan base;
 399         dma_addr_t handle;
 400         u32 *ptr;
 401
 402         struct nvif_object sync;
 403         struct nvif_object vram;
 404         struct list_head ctxdma;
 405
 406         /* Protects against concurrent pushbuf access to this channel, lock is
 407          * grabbed by evo_wait (if the pushbuf reservation is successful) and
 408          * dropped again by evo_kick. */
 409         struct mutex lock;
 410 };
 411
 412 static void
 413 nv50_dmac_ctxdma_del(struct nv50_dmac_ctxdma *ctxdma)
 414 {
 415         nvif_object_fini(&ctxdma->object);
 416         list_del(&ctxdma->head);
 417         kfree(ctxdma);
 418 }
 419
 420 static struct nv50_dmac_ctxdma *
 421 nv50_dmac_ctxdma_new(struct nv50_dmac *dmac, struct nouveau_framebuffer *fb)
 422 {
 423         struct nouveau_drm *drm = nouveau_drm(fb->base.dev);
 424         struct nv50_dmac_ctxdma *ctxdma;
 425         const u8    kind = (fb->nvbo->tile_flags & 0x0000ff00) >> 8;
 426         const u32 handle = 0xfb000000 | kind;
 427         struct {
 428                 struct nv_dma_v0 base;
 429                 union {
 430                         struct nv50_dma_v0 nv50;
 431                         struct gf100_dma_v0 gf100;
 432                         struct gf119_dma_v0 gf119;
 433                 };
 434         } args = {};
 435         u32 argc = sizeof(args.base);
 436         int ret;
 437
 438         list_for_each_entry(ctxdma, &dmac->ctxdma, head) {
 439                 if (ctxdma->object.handle == handle)
 440                         return ctxdma;
 441         }
 442
 443         if (!(ctxdma = kzalloc(sizeof(*ctxdma), GFP_KERNEL)))
 444                 return ERR_PTR(-ENOMEM);
 445         list_add(&ctxdma->head, &dmac->ctxdma);
 446
 447         args.base.target = NV_DMA_V0_TARGET_VRAM;
 448         args.base.access = NV_DMA_V0_ACCESS_RDWR;
 449         args.base.start  = 0;
 450         args.base.limit  = drm->client.device.info.ram_user - 1;
 451
 452         if (drm->client.device.info.chipset < 0x80) {
 453                 args.nv50.part = NV50_DMA_V0_PART_256;
 454                 argc += sizeof(args.nv50);
 455         } else
 456         if (drm->client.device.info.chipset < 0xc0) {
 457                 args.nv50.part = NV50_DMA_V0_PART_256;
 458                 args.nv50.kind = kind;
 459                 argc += sizeof(args.nv50);
 460         } else
 461         if (drm->client.device.info.chipset < 0xd0) {
 462                 args.gf100.kind = kind;
 463                 argc += sizeof(args.gf100);
 464         } else {
 465                 args.gf119.page = GF119_DMA_V0_PAGE_LP;
 466                 args.gf119.kind = kind;
 467                 argc += sizeof(args.gf119);
 468         }
 469
 470         ret = nvif_object_init(&dmac->base.user, handle, NV_DMA_IN_MEMORY,
 471                                &args, argc, &ctxdma->object);
 472         if (ret) {
 473                 nv50_dmac_ctxdma_del(ctxdma);
 474                 return ERR_PTR(ret);
 475         }
 476
 477         return ctxdma;
 478 }
 479
 480 static void
 481 nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp)
 482 {
 483         struct nvif_device *device = dmac->base.device;
 484         struct nv50_dmac_ctxdma *ctxdma, *ctxtmp;
 485
 486         list_for_each_entry_safe(ctxdma, ctxtmp, &dmac->ctxdma, head) {
 487                 nv50_dmac_ctxdma_del(ctxdma);
 488         }
 489
 490         nvif_object_fini(&dmac->vram);
 491         nvif_object_fini(&dmac->sync);
 492
 493         nv50_chan_destroy(&dmac->base);
 494
 495         if (dmac->ptr) {
 496                 struct device *dev = nvxx_device(device)->dev;
 497                 dma_free_coherent(dev, PAGE_SIZE, dmac->ptr, dmac->handle);
 498         }
 499 }
 500
 501 static int
 502 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 503                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 504                  struct nv50_dmac *dmac)
 505 {
 506         struct nv50_disp_core_channel_dma_v0 *args = data;
 507         struct nvif_object pushbuf;
 508         int ret;
 509
 510         mutex_init(&dmac->lock);
 511
 512         dmac->ptr = dma_alloc_coherent(nvxx_device(device)->dev, PAGE_SIZE,
 513                                        &dmac->handle, GFP_KERNEL);
 514         if (!dmac->ptr)
 515                 return -ENOMEM;
 516
 517         ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY,
 518                                &(struct nv_dma_v0) {
 519                                         .target = NV_DMA_V0_TARGET_PCI_US,
 520                                         .access = NV_DMA_V0_ACCESS_RD,
 521                                         .start = dmac->handle + 0x0000,
 522                                         .limit = dmac->handle + 0x0fff,
 523                                }, sizeof(struct nv_dma_v0), &pushbuf);
 524         if (ret)
 525                 return ret;
 526
 527         args->pushbuf = nvif_handle(&pushbuf);
 528
 529         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 530                                &dmac->base);
 531         nvif_object_fini(&pushbuf);
 532         if (ret)
 533                 return ret;
 534
 535         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 536                                &(struct nv_dma_v0) {
 537                                         .target = NV_DMA_V0_TARGET_VRAM,
 538                                         .access = NV_DMA_V0_ACCESS_RDWR,
 539                                         .start = syncbuf + 0x0000,
 540                                         .limit = syncbuf + 0x0fff,
 541                                }, sizeof(struct nv_dma_v0),
 542                                &dmac->sync);
 543         if (ret)
 544                 return ret;
 545
 546         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 547                                &(struct nv_dma_v0) {
 548                                         .target = NV_DMA_V0_TARGET_VRAM,
 549                                         .access = NV_DMA_V0_ACCESS_RDWR,
 550                                         .start = 0,
 551                                         .limit = device->info.ram_user - 1,
 552                                }, sizeof(struct nv_dma_v0),
 553                                &dmac->vram);
 554         if (ret)
 555                 return ret;
 556
 557         INIT_LIST_HEAD(&dmac->ctxdma);
 558         return ret;
 559 }
 560
 561 /******************************************************************************
 562  * Core
 563  *****************************************************************************/
 564
 565 struct nv50_mast {
 566         struct nv50_dmac base;
 567 };
 568
 569 static int
 570 nv50_core_create(struct nvif_device *device, struct nvif_object *disp,
 571                  u64 syncbuf, struct nv50_mast *core)
 572 {
 573         struct nv50_disp_core_channel_dma_v0 args = {
 574                 .pushbuf = 0xb0007d00,
 575         };
 576         static const s32 oclass[] = {
 577                 GP102_DISP_CORE_CHANNEL_DMA,
 578                 GP100_DISP_CORE_CHANNEL_DMA,
 579                 GM200_DISP_CORE_CHANNEL_DMA,
 580                 GM107_DISP_CORE_CHANNEL_DMA,
 581                 GK110_DISP_CORE_CHANNEL_DMA,
 582                 GK104_DISP_CORE_CHANNEL_DMA,
 583                 GF110_DISP_CORE_CHANNEL_DMA,
 584                 GT214_DISP_CORE_CHANNEL_DMA,
 585                 GT206_DISP_CORE_CHANNEL_DMA,
 586                 GT200_DISP_CORE_CHANNEL_DMA,
 587                 G82_DISP_CORE_CHANNEL_DMA,
 588                 NV50_DISP_CORE_CHANNEL_DMA,
 589                 0
 590         };
 591
 592         return nv50_dmac_create(device, disp, oclass, 0, &args, sizeof(args),
 593                                 syncbuf, &core->base);
 594 }
 595
 596 /******************************************************************************
 597  * Base
 598  *****************************************************************************/
 599
 600 struct nv50_sync {
 601         struct nv50_dmac base;
 602         u32 addr;
 603         u32 data;
 604 };
 605
 606 static int
 607 nv50_base_create(struct nvif_device *device, struct nvif_object *disp,
 608                  int head, u64 syncbuf, struct nv50_sync *base)
 609 {
 610         struct nv50_disp_base_channel_dma_v0 args = {
 611                 .pushbuf = 0xb0007c00 | head,
 612                 .head = head,
 613         };
 614         static const s32 oclass[] = {
 615                 GK110_DISP_BASE_CHANNEL_DMA,
 616                 GK104_DISP_BASE_CHANNEL_DMA,
 617                 GF110_DISP_BASE_CHANNEL_DMA,
 618                 GT214_DISP_BASE_CHANNEL_DMA,
 619                 GT200_DISP_BASE_CHANNEL_DMA,
 620                 G82_DISP_BASE_CHANNEL_DMA,
 621                 NV50_DISP_BASE_CHANNEL_DMA,
 622                 0
 623         };
 624
 625         return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
 626                                 syncbuf, &base->base);
 627 }
 628
 629 /******************************************************************************
 630  * Overlay
 631  *****************************************************************************/
 632
 633 struct nv50_ovly {
 634         struct nv50_dmac base;
 635 };
 636
 637 static int
 638 nv50_ovly_create(struct nvif_device *device, struct nvif_object *disp,
 639                  int head, u64 syncbuf, struct nv50_ovly *ovly)
 640 {
 641         struct nv50_disp_overlay_channel_dma_v0 args = {
 642                 .pushbuf = 0xb0007e00 | head,
 643                 .head = head,
 644         };
 645         static const s32 oclass[] = {
 646                 GK104_DISP_OVERLAY_CONTROL_DMA,
 647                 GF110_DISP_OVERLAY_CONTROL_DMA,
 648                 GT214_DISP_OVERLAY_CHANNEL_DMA,
 649                 GT200_DISP_OVERLAY_CHANNEL_DMA,
 650                 G82_DISP_OVERLAY_CHANNEL_DMA,
 651                 NV50_DISP_OVERLAY_CHANNEL_DMA,
 652                 0
 653         };
 654
 655         return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
 656                                 syncbuf, &ovly->base);
 657 }
 658
 659 struct nv50_head {
 660         struct nouveau_crtc base;
 661         struct nv50_ovly ovly;
 662         struct nv50_oimm oimm;
 663 };
 664
 665 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
 666 #define nv50_ovly(c) (&nv50_head(c)->ovly)
 667 #define nv50_oimm(c) (&nv50_head(c)->oimm)
 668 #define nv50_chan(c) (&(c)->base.base)
 669 #define nv50_vers(c) nv50_chan(c)->user.oclass
 670
 671 struct nv50_disp {
 672         struct nvif_object *disp;
 673         struct nv50_mast mast;
 674
 675         struct nouveau_bo *sync;
 676
 677         struct mutex mutex;
 678 };
 679
 680 static struct nv50_disp *
 681 nv50_disp(struct drm_device *dev)
 682 {
 683         return nouveau_display(dev)->priv;
 684 }
 685
 686 #define nv50_mast(d) (&nv50_disp(d)->mast)
 687
 688 /******************************************************************************
 689  * EVO channel helpers
 690  *****************************************************************************/
 691 static u32 *
 692 evo_wait(void *evoc, int nr)
 693 {
 694         struct nv50_dmac *dmac = evoc;
 695         struct nvif_device *device = dmac->base.device;
 696         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 697
 698         mutex_lock(&dmac->lock);
 699         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 700                 dmac->ptr[put] = 0x20000000;
 701
 702                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 703                 if (nvif_msec(device, 2000,
 704                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 705                                 break;
 706                 ) < 0) {
 707                         mutex_unlock(&dmac->lock);
 708                         printk(KERN_ERR "nouveau: evo channel stalled\n");
 709                         return NULL;
 710                 }
 711
 712                 put = 0;
 713         }
 714
 715         return dmac->ptr + put;
 716 }
 717
 718 static void
 719 evo_kick(u32 *push, void *evoc)
 720 {
 721         struct nv50_dmac *dmac = evoc;
 722         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 723         mutex_unlock(&dmac->lock);
 724 }
 725
 726 #define evo_mthd(p,m,s) do {                                                   \
 727         const u32 _m = (m), _s = (s);                                          \
 728         if (drm_debug & DRM_UT_KMS)                                            \
 729                 printk(KERN_ERR "%04x %d %s\n", _m, _s, __func__);             \
 730         *((p)++) = ((_s << 18) | _m);                                          \
 731 } while(0)
 732
 733 #define evo_data(p,d) do {                                                     \
 734         const u32 _d = (d);                                                    \
 735         if (drm_debug & DRM_UT_KMS)                                            \
 736                 printk(KERN_ERR "\t%08x\n", _d);                               \
 737         *((p)++) = _d;                                                         \
 738 } while(0)
 739
 740 /******************************************************************************
 741  * Plane
 742  *****************************************************************************/
 743 #define nv50_wndw(p) container_of((p), struct nv50_wndw, plane)
 744
 745 struct nv50_wndw {
 746         const struct nv50_wndw_func *func;
 747         struct nv50_dmac *dmac;
 748
 749         struct drm_plane plane;
 750
 751         struct nvif_notify notify;
 752         u16 ntfy;
 753         u16 sema;
 754         u32 data;
 755 };
 756
 757 struct nv50_wndw_func {
 758         void *(*dtor)(struct nv50_wndw *);
 759         int (*acquire)(struct nv50_wndw *, struct nv50_wndw_atom *asyw,
 760                        struct nv50_head_atom *asyh);
 761         void (*release)(struct nv50_wndw *, struct nv50_wndw_atom *asyw,
 762                         struct nv50_head_atom *asyh);
 763         void (*prepare)(struct nv50_wndw *, struct nv50_head_atom *asyh,
 764                         struct nv50_wndw_atom *asyw);
 765
 766         void (*sema_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
 767         void (*sema_clr)(struct nv50_wndw *);
 768         void (*ntfy_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
 769         void (*ntfy_clr)(struct nv50_wndw *);
 770         int (*ntfy_wait_begun)(struct nv50_wndw *, struct nv50_wndw_atom *);
 771         void (*image_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
 772         void (*image_clr)(struct nv50_wndw *);
 773         void (*lut)(struct nv50_wndw *, struct nv50_wndw_atom *);
 774         void (*point)(struct nv50_wndw *, struct nv50_wndw_atom *);
 775
 776         u32 (*update)(struct nv50_wndw *, u32 interlock);
 777 };
 778
 779 static int
 780 nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
 781 {
 782         if (asyw->set.ntfy)
 783                 return wndw->func->ntfy_wait_begun(wndw, asyw);
 784         return 0;
 785 }
 786
 787 static u32
 788 nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 interlock, bool flush,
 789                     struct nv50_wndw_atom *asyw)
 790 {
 791         if (asyw->clr.sema && (!asyw->set.sema || flush))
 792                 wndw->func->sema_clr(wndw);
 793         if (asyw->clr.ntfy && (!asyw->set.ntfy || flush))
 794                 wndw->func->ntfy_clr(wndw);
 795         if (asyw->clr.image && (!asyw->set.image || flush))
 796                 wndw->func->image_clr(wndw);
 797
 798         return flush ? wndw->func->update(wndw, interlock) : 0;
 799 }
 800
 801 static u32
 802 nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 interlock,
 803                     struct nv50_wndw_atom *asyw)
 804 {
 805         if (interlock) {
 806                 asyw->image.mode = 0;
 807                 asyw->image.interval = 1;
 808         }
 809
 810         if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw);
 811         if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw);
 812         if (asyw->set.image) wndw->func->image_set(wndw, asyw);
 813         if (asyw->set.lut  ) wndw->func->lut      (wndw, asyw);
 814         if (asyw->set.point) wndw->func->point    (wndw, asyw);
 815
 816         return wndw->func->update(wndw, interlock);
 817 }
 818
 819 static void
 820 nv50_wndw_atomic_check_release(struct nv50_wndw *wndw,
 821                                struct nv50_wndw_atom *asyw,
 822                                struct nv50_head_atom *asyh)
 823 {
 824         struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
 825         NV_ATOMIC(drm, "%s release\n", wndw->plane.name);
 826         wndw->func->release(wndw, asyw, asyh);
 827         asyw->ntfy.handle = 0;
 828         asyw->sema.handle = 0;
 829 }
 830
 831 static int
 832 nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw,
 833                                struct nv50_wndw_atom *asyw,
 834                                struct nv50_head_atom *asyh)
 835 {
 836         struct nouveau_framebuffer *fb = nouveau_framebuffer(asyw->state.fb);
 837         struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
 838         int ret;
 839
 840         NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name);
 841         asyw->clip.x1 = 0;
 842         asyw->clip.y1 = 0;
 843         asyw->clip.x2 = asyh->state.mode.hdisplay;
 844         asyw->clip.y2 = asyh->state.mode.vdisplay;
 845
 846         asyw->image.w = fb->base.width;
 847         asyw->image.h = fb->base.height;
 848         asyw->image.kind = (fb->nvbo->tile_flags & 0x0000ff00) >> 8;
 849         if (asyw->image.kind) {
 850                 asyw->image.layout = 0;
 851                 if (drm->client.device.info.chipset >= 0xc0)
 852                         asyw->image.block = fb->nvbo->tile_mode >> 4;
 853                 else
 854                         asyw->image.block = fb->nvbo->tile_mode;
 855                 asyw->image.pitch = (fb->base.pitches[0] / 4) << 4;
 856         } else {
 857                 asyw->image.layout = 1;
 858                 asyw->image.block  = 0;
 859                 asyw->image.pitch  = fb->base.pitches[0];
 860         }
 861
 862         ret = wndw->func->acquire(wndw, asyw, asyh);
 863         if (ret)
 864                 return ret;
 865
 866         if (asyw->set.image) {
 867                 if (!(asyw->image.mode = asyw->interval ? 0 : 1))
 868                         asyw->image.interval = asyw->interval;
 869                 else
 870                         asyw->image.interval = 0;
 871         }
 872
 873         return 0;
 874 }
 875
 876 static int
 877 nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state)
 878 {
 879         struct nouveau_drm *drm = nouveau_drm(plane->dev);
 880         struct nv50_wndw *wndw = nv50_wndw(plane);
 881         struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state);
 882         struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
 883         struct nv50_head_atom *harm = NULL, *asyh = NULL;
 884         bool varm = false, asyv = false, asym = false;
 885         int ret;
 886
 887         NV_ATOMIC(drm, "%s atomic_check\n", plane->name);
 888         if (asyw->state.crtc) {
 889                 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
 890                 if (IS_ERR(asyh))
 891                         return PTR_ERR(asyh);
 892                 asym = drm_atomic_crtc_needs_modeset(&asyh->state);
 893                 asyv = asyh->state.active;
 894         }
 895
 896         if (armw->state.crtc) {
 897                 harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc);
 898                 if (IS_ERR(harm))
 899                         return PTR_ERR(harm);
 900                 varm = harm->state.crtc->state->active;
 901         }
 902
 903         if (asyv) {
 904                 asyw->point.x = asyw->state.crtc_x;
 905                 asyw->point.y = asyw->state.crtc_y;
 906                 if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point)))
 907                         asyw->set.point = true;
 908
 909                 if (!varm || asym || armw->state.fb != asyw->state.fb) {
 910                         ret = nv50_wndw_atomic_check_acquire(wndw, asyw, asyh);
 911                         if (ret)
 912                                 return ret;
 913                 }
 914         } else
 915         if (varm) {
 916                 nv50_wndw_atomic_check_release(wndw, asyw, harm);
 917         } else {
 918                 return 0;
 919         }
 920
 921         if (!asyv || asym) {
 922                 asyw->clr.ntfy = armw->ntfy.handle != 0;
 923                 asyw->clr.sema = armw->sema.handle != 0;
 924                 if (wndw->func->image_clr)
 925                         asyw->clr.image = armw->image.handle != 0;
 926                 asyw->set.lut = wndw->func->lut && asyv;
 927         }
 928
 929         return 0;
 930 }
 931
 932 static void
 933 nv50_wndw_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state)
 934 {
 935         struct nouveau_framebuffer *fb = nouveau_framebuffer(old_state->fb);
 936         struct nouveau_drm *drm = nouveau_drm(plane->dev);
 937
 938         NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb);
 939         if (!old_state->fb)
 940                 return;
 941
 942         nouveau_bo_unpin(fb->nvbo);
 943 }
 944
 945 static int
 946 nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state)
 947 {
 948         struct nouveau_framebuffer *fb = nouveau_framebuffer(state->fb);
 949         struct nouveau_drm *drm = nouveau_drm(plane->dev);
 950         struct nv50_wndw *wndw = nv50_wndw(plane);
 951         struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
 952         struct nv50_head_atom *asyh;
 953         struct nv50_dmac_ctxdma *ctxdma;
 954         int ret;
 955
 956         NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, state->fb);
 957         if (!asyw->state.fb)
 958                 return 0;
 959
 960         ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM, true);
 961         if (ret)
 962                 return ret;
 963
 964         ctxdma = nv50_dmac_ctxdma_new(wndw->dmac, fb);
 965         if (IS_ERR(ctxdma)) {
 966                 nouveau_bo_unpin(fb->nvbo);
 967                 return PTR_ERR(ctxdma);
 968         }
 969
 970         asyw->state.fence = reservation_object_get_excl_rcu(fb->nvbo->bo.resv);
 971         asyw->image.handle = ctxdma->object.handle;
 972         asyw->image.offset = fb->nvbo->bo.offset;
 973
 974         if (wndw->func->prepare) {
 975                 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
 976                 if (IS_ERR(asyh))
 977                         return PTR_ERR(asyh);
 978
 979                 wndw->func->prepare(wndw, asyh, asyw);
 980         }
 981
 982         return 0;
 983 }
 984
 985 static const struct drm_plane_helper_funcs
 986 nv50_wndw_helper = {
 987         .prepare_fb = nv50_wndw_prepare_fb,
 988         .cleanup_fb = nv50_wndw_cleanup_fb,
 989         .atomic_check = nv50_wndw_atomic_check,
 990 };
 991
 992 static void
 993 nv50_wndw_atomic_destroy_state(struct drm_plane *plane,
 994                                struct drm_plane_state *state)
 995 {
 996         struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
 997         __drm_atomic_helper_plane_destroy_state(&asyw->state);
 998         kfree(asyw);
 999 }
1000
1001 static struct drm_plane_state *
1002 nv50_wndw_atomic_duplicate_state(struct drm_plane *plane)
1003 {
1004         struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state);
1005         struct nv50_wndw_atom *asyw;
1006         if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL)))
1007                 return NULL;
1008         __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state);
1009         asyw->interval = 1;
1010         asyw->sema = armw->sema;
1011         asyw->ntfy = armw->ntfy;
1012         asyw->image = armw->image;
1013         asyw->point = armw->point;
1014         asyw->lut = armw->lut;
1015         asyw->clr.mask = 0;
1016         asyw->set.mask = 0;
1017         return &asyw->state;
1018 }
1019
1020 static void
1021 nv50_wndw_reset(struct drm_plane *plane)
1022 {
1023         struct nv50_wndw_atom *asyw;
1024
1025         if (WARN_ON(!(asyw = kzalloc(sizeof(*asyw), GFP_KERNEL))))
1026                 return;
1027
1028         if (plane->state)
1029                 plane->funcs->atomic_destroy_state(plane, plane->state);
1030         plane->state = &asyw->state;
1031         plane->state->plane = plane;
1032         plane->state->rotation = DRM_ROTATE_0;
1033 }
1034
1035 static void
1036 nv50_wndw_destroy(struct drm_plane *plane)
1037 {
1038         struct nv50_wndw *wndw = nv50_wndw(plane);
1039         void *data;
1040         nvif_notify_fini(&wndw->notify);
1041         data = wndw->func->dtor(wndw);
1042         drm_plane_cleanup(&wndw->plane);
1043         kfree(data);
1044 }
1045
1046 static const struct drm_plane_funcs
1047 nv50_wndw = {
1048         .update_plane = drm_atomic_helper_update_plane,
1049         .disable_plane = drm_atomic_helper_disable_plane,
1050         .destroy = nv50_wndw_destroy,
1051         .reset = nv50_wndw_reset,
1052         .set_property = drm_atomic_helper_plane_set_property,
1053         .atomic_duplicate_state = nv50_wndw_atomic_duplicate_state,
1054         .atomic_destroy_state = nv50_wndw_atomic_destroy_state,
1055 };
1056
1057 static void
1058 nv50_wndw_fini(struct nv50_wndw *wndw)
1059 {
1060         nvif_notify_put(&wndw->notify);
1061 }
1062
1063 static void
1064 nv50_wndw_init(struct nv50_wndw *wndw)
1065 {
1066         nvif_notify_get(&wndw->notify);
1067 }
1068
1069 static int
1070 nv50_wndw_ctor(const struct nv50_wndw_func *func, struct drm_device *dev,
1071                enum drm_plane_type type, const char *name, int index,
1072                struct nv50_dmac *dmac, const u32 *format, int nformat,
1073                struct nv50_wndw *wndw)
1074 {
1075         int ret;
1076
1077         wndw->func = func;
1078         wndw->dmac = dmac;
1079
1080         ret = drm_universal_plane_init(dev, &wndw->plane, 0, &nv50_wndw, format,
1081                                        nformat, type, "%s-%d", name, index);
1082         if (ret)
1083                 return ret;
1084
1085         drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper);
1086         return 0;
1087 }
1088
1089 /******************************************************************************
1090  * Cursor plane
1091  *****************************************************************************/
1092 #define nv50_curs(p) container_of((p), struct nv50_curs, wndw)
1093
1094 struct nv50_curs {
1095         struct nv50_wndw wndw;
1096         struct nvif_object chan;
1097 };
1098
1099 static u32
1100 nv50_curs_update(struct nv50_wndw *wndw, u32 interlock)
1101 {
1102         struct nv50_curs *curs = nv50_curs(wndw);
1103         nvif_wr32(&curs->chan, 0x0080, 0x00000000);
1104         return 0;
1105 }
1106
1107 static void
1108 nv50_curs_point(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1109 {
1110         struct nv50_curs *curs = nv50_curs(wndw);
1111         nvif_wr32(&curs->chan, 0x0084, (asyw->point.y << 16) | asyw->point.x);
1112 }
1113
1114 static void
1115 nv50_curs_prepare(struct nv50_wndw *wndw, struct nv50_head_atom *asyh,
1116                   struct nv50_wndw_atom *asyw)
1117 {
1118         asyh->curs.handle = nv50_disp(wndw->plane.dev)->mast.base.vram.handle;
1119         asyh->curs.offset = asyw->image.offset;
1120         asyh->set.curs = asyh->curs.visible;
1121 }
1122
1123 static void
1124 nv50_curs_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1125                   struct nv50_head_atom *asyh)
1126 {
1127         asyh->curs.visible = false;
1128 }
1129
1130 static int
1131 nv50_curs_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1132                   struct nv50_head_atom *asyh)
1133 {
1134         int ret;
1135
1136         ret = drm_plane_helper_check_state(&asyw->state, &asyw->clip,
1137                                            DRM_PLANE_HELPER_NO_SCALING,
1138                                            DRM_PLANE_HELPER_NO_SCALING,
1139                                            true, true);
1140         asyh->curs.visible = asyw->state.visible;
1141         if (ret || !asyh->curs.visible)
1142                 return ret;
1143
1144         switch (asyw->state.fb->width) {
1145         case 32: asyh->curs.layout = 0; break;
1146         case 64: asyh->curs.layout = 1; break;
1147         default:
1148                 return -EINVAL;
1149         }
1150
1151         if (asyw->state.fb->width != asyw->state.fb->height)
1152                 return -EINVAL;
1153
1154         switch (asyw->state.fb->format->format) {
1155         case DRM_FORMAT_ARGB8888: asyh->curs.format = 1; break;
1156         default:
1157                 WARN_ON(1);
1158                 return -EINVAL;
1159         }
1160
1161         return 0;
1162 }
1163
1164 static void *
1165 nv50_curs_dtor(struct nv50_wndw *wndw)
1166 {
1167         struct nv50_curs *curs = nv50_curs(wndw);
1168         nvif_object_fini(&curs->chan);
1169         return curs;
1170 }
1171
1172 static const u32
1173 nv50_curs_format[] = {
1174         DRM_FORMAT_ARGB8888,
1175 };
1176
1177 static const struct nv50_wndw_func
1178 nv50_curs = {
1179         .dtor = nv50_curs_dtor,
1180         .acquire = nv50_curs_acquire,
1181         .release = nv50_curs_release,
1182         .prepare = nv50_curs_prepare,
1183         .point = nv50_curs_point,
1184         .update = nv50_curs_update,
1185 };
1186
1187 static int
1188 nv50_curs_new(struct nouveau_drm *drm, struct nv50_head *head,
1189               struct nv50_curs **pcurs)
1190 {
1191         static const struct nvif_mclass curses[] = {
1192                 { GK104_DISP_CURSOR, 0 },
1193                 { GF110_DISP_CURSOR, 0 },
1194                 { GT214_DISP_CURSOR, 0 },
1195                 {   G82_DISP_CURSOR, 0 },
1196                 {  NV50_DISP_CURSOR, 0 },
1197                 {}
1198         };
1199         struct nv50_disp_cursor_v0 args = {
1200                 .head = head->base.index,
1201         };
1202         struct nv50_disp *disp = nv50_disp(drm->dev);
1203         struct nv50_curs *curs;
1204         int cid, ret;
1205
1206         cid = nvif_mclass(disp->disp, curses);
1207         if (cid < 0) {
1208                 NV_ERROR(drm, "No supported cursor immediate class\n");
1209                 return cid;
1210         }
1211
1212         if (!(curs = *pcurs = kzalloc(sizeof(*curs), GFP_KERNEL)))
1213                 return -ENOMEM;
1214
1215         ret = nv50_wndw_ctor(&nv50_curs, drm->dev, DRM_PLANE_TYPE_CURSOR,
1216                              "curs", head->base.index, &disp->mast.base,
1217                              nv50_curs_format, ARRAY_SIZE(nv50_curs_format),
1218                              &curs->wndw);
1219         if (ret) {
1220                 kfree(curs);
1221                 return ret;
1222         }
1223
1224         ret = nvif_object_init(disp->disp, 0, curses[cid].oclass, &args,
1225                                sizeof(args), &curs->chan);
1226         if (ret) {
1227                 NV_ERROR(drm, "curs%04x allocation failed: %d\n",
1228                          curses[cid].oclass, ret);
1229                 return ret;
1230         }
1231
1232         return 0;
1233 }
1234
1235 /******************************************************************************
1236  * Primary plane
1237  *****************************************************************************/
1238 #define nv50_base(p) container_of((p), struct nv50_base, wndw)
1239
1240 struct nv50_base {
1241         struct nv50_wndw wndw;
1242         struct nv50_sync chan;
1243         int id;
1244 };
1245
1246 static int
1247 nv50_base_notify(struct nvif_notify *notify)
1248 {
1249         return NVIF_NOTIFY_KEEP;
1250 }
1251
1252 static void
1253 nv50_base_lut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1254 {
1255         struct nv50_base *base = nv50_base(wndw);
1256         u32 *push;
1257         if ((push = evo_wait(&base->chan, 2))) {
1258                 evo_mthd(push, 0x00e0, 1);
1259                 evo_data(push, asyw->lut.enable << 30);
1260                 evo_kick(push, &base->chan);
1261         }
1262 }
1263
1264 static void
1265 nv50_base_image_clr(struct nv50_wndw *wndw)
1266 {
1267         struct nv50_base *base = nv50_base(wndw);
1268         u32 *push;
1269         if ((push = evo_wait(&base->chan, 4))) {
1270                 evo_mthd(push, 0x0084, 1);
1271                 evo_data(push, 0x00000000);
1272                 evo_mthd(push, 0x00c0, 1);
1273                 evo_data(push, 0x00000000);
1274                 evo_kick(push, &base->chan);
1275         }
1276 }
1277
1278 static void
1279 nv50_base_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1280 {
1281         struct nv50_base *base = nv50_base(wndw);
1282         const s32 oclass = base->chan.base.base.user.oclass;
1283         u32 *push;
1284         if ((push = evo_wait(&base->chan, 10))) {
1285                 evo_mthd(push, 0x0084, 1);
1286                 evo_data(push, (asyw->image.mode << 8) |
1287                                (asyw->image.interval << 4));
1288                 evo_mthd(push, 0x00c0, 1);
1289                 evo_data(push, asyw->image.handle);
1290                 if (oclass < G82_DISP_BASE_CHANNEL_DMA) {
1291                         evo_mthd(push, 0x0800, 5);
1292                         evo_data(push, asyw->image.offset >> 8);
1293                         evo_data(push, 0x00000000);
1294                         evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1295                         evo_data(push, (asyw->image.layout << 20) |
1296                                         asyw->image.pitch |
1297                                         asyw->image.block);
1298                         evo_data(push, (asyw->image.kind << 16) |
1299                                        (asyw->image.format << 8));
1300                 } else
1301                 if (oclass < GF110_DISP_BASE_CHANNEL_DMA) {
1302                         evo_mthd(push, 0x0800, 5);
1303                         evo_data(push, asyw->image.offset >> 8);
1304                         evo_data(push, 0x00000000);
1305                         evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1306                         evo_data(push, (asyw->image.layout << 20) |
1307                                         asyw->image.pitch |
1308                                         asyw->image.block);
1309                         evo_data(push, asyw->image.format << 8);
1310                 } else {
1311                         evo_mthd(push, 0x0400, 5);
1312                         evo_data(push, asyw->image.offset >> 8);
1313                         evo_data(push, 0x00000000);
1314                         evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1315                         evo_data(push, (asyw->image.layout << 24) |
1316                                         asyw->image.pitch |
1317                                         asyw->image.block);
1318                         evo_data(push, asyw->image.format << 8);
1319                 }
1320                 evo_kick(push, &base->chan);
1321         }
1322 }
1323
1324 static void
1325 nv50_base_ntfy_clr(struct nv50_wndw *wndw)
1326 {
1327         struct nv50_base *base = nv50_base(wndw);
1328         u32 *push;
1329         if ((push = evo_wait(&base->chan, 2))) {
1330                 evo_mthd(push, 0x00a4, 1);
1331                 evo_data(push, 0x00000000);
1332                 evo_kick(push, &base->chan);
1333         }
1334 }
1335
1336 static void
1337 nv50_base_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1338 {
1339         struct nv50_base *base = nv50_base(wndw);
1340         u32 *push;
1341         if ((push = evo_wait(&base->chan, 3))) {
1342                 evo_mthd(push, 0x00a0, 2);
1343                 evo_data(push, (asyw->ntfy.awaken << 30) | asyw->ntfy.offset);
1344                 evo_data(push, asyw->ntfy.handle);
1345                 evo_kick(push, &base->chan);
1346         }
1347 }
1348
1349 static void
1350 nv50_base_sema_clr(struct nv50_wndw *wndw)
1351 {
1352         struct nv50_base *base = nv50_base(wndw);
1353         u32 *push;
1354         if ((push = evo_wait(&base->chan, 2))) {
1355                 evo_mthd(push, 0x0094, 1);
1356                 evo_data(push, 0x00000000);
1357                 evo_kick(push, &base->chan);
1358         }
1359 }
1360
1361 static void
1362 nv50_base_sema_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1363 {
1364         struct nv50_base *base = nv50_base(wndw);
1365         u32 *push;
1366         if ((push = evo_wait(&base->chan, 5))) {
1367                 evo_mthd(push, 0x0088, 4);
1368                 evo_data(push, asyw->sema.offset);
1369                 evo_data(push, asyw->sema.acquire);
1370                 evo_data(push, asyw->sema.release);
1371                 evo_data(push, asyw->sema.handle);
1372                 evo_kick(push, &base->chan);
1373         }
1374 }
1375
1376 static u32
1377 nv50_base_update(struct nv50_wndw *wndw, u32 interlock)
1378 {
1379         struct nv50_base *base = nv50_base(wndw);
1380         u32 *push;
1381
1382         if (!(push = evo_wait(&base->chan, 2)))
1383                 return 0;
1384         evo_mthd(push, 0x0080, 1);
1385         evo_data(push, interlock);
1386         evo_kick(push, &base->chan);
1387
1388         if (base->chan.base.base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA)
1389                 return interlock ? 2 << (base->id * 8) : 0;
1390         return interlock ? 2 << (base->id * 4) : 0;
1391 }
1392
1393 static int
1394 nv50_base_ntfy_wait_begun(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1395 {
1396         struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
1397         struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
1398         if (nvif_msec(&drm->client.device, 2000ULL,
1399                 u32 data = nouveau_bo_rd32(disp->sync, asyw->ntfy.offset / 4);
1400                 if ((data & 0xc0000000) == 0x40000000)
1401                         break;
1402                 usleep_range(1, 2);
1403         ) < 0)
1404                 return -ETIMEDOUT;
1405         return 0;
1406 }
1407
1408 static void
1409 nv50_base_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1410                   struct nv50_head_atom *asyh)
1411 {
1412         asyh->base.cpp = 0;
1413 }
1414
1415 static int
1416 nv50_base_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1417                   struct nv50_head_atom *asyh)
1418 {
1419         const struct drm_framebuffer *fb = asyw->state.fb;
1420         int ret;
1421
1422         if (!fb->format->depth)
1423                 return -EINVAL;
1424
1425         ret = drm_plane_helper_check_state(&asyw->state, &asyw->clip,
1426                                            DRM_PLANE_HELPER_NO_SCALING,
1427                                            DRM_PLANE_HELPER_NO_SCALING,
1428                                            false, true);
1429         if (ret)
1430                 return ret;
1431
1432         asyh->base.depth = fb->format->depth;
1433         asyh->base.cpp = fb->format->cpp[0];
1434         asyh->base.x = asyw->state.src.x1 >> 16;
1435         asyh->base.y = asyw->state.src.y1 >> 16;
1436         asyh->base.w = asyw->state.fb->width;
1437         asyh->base.h = asyw->state.fb->height;
1438
1439         switch (fb->format->format) {
1440         case DRM_FORMAT_C8         : asyw->image.format = 0x1e; break;
1441         case DRM_FORMAT_RGB565     : asyw->image.format = 0xe8; break;
1442         case DRM_FORMAT_XRGB1555   :
1443         case DRM_FORMAT_ARGB1555   : asyw->image.format = 0xe9; break;
1444         case DRM_FORMAT_XRGB8888   :
1445         case DRM_FORMAT_ARGB8888   : asyw->image.format = 0xcf; break;
1446         case DRM_FORMAT_XBGR2101010:
1447         case DRM_FORMAT_ABGR2101010: asyw->image.format = 0xd1; break;
1448         case DRM_FORMAT_XBGR8888   :
1449         case DRM_FORMAT_ABGR8888   : asyw->image.format = 0xd5; break;
1450         default:
1451                 WARN_ON(1);
1452                 return -EINVAL;
1453         }
1454
1455         asyw->lut.enable = 1;
1456         asyw->set.image = true;
1457         return 0;
1458 }
1459
1460 static void *
1461 nv50_base_dtor(struct nv50_wndw *wndw)
1462 {
1463         struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
1464         struct nv50_base *base = nv50_base(wndw);
1465         nv50_dmac_destroy(&base->chan.base, disp->disp);
1466         return base;
1467 }
1468
1469 static const u32
1470 nv50_base_format[] = {
1471         DRM_FORMAT_C8,
1472         DRM_FORMAT_RGB565,
1473         DRM_FORMAT_XRGB1555,
1474         DRM_FORMAT_ARGB1555,
1475         DRM_FORMAT_XRGB8888,
1476         DRM_FORMAT_ARGB8888,
1477         DRM_FORMAT_XBGR2101010,
1478         DRM_FORMAT_ABGR2101010,
1479         DRM_FORMAT_XBGR8888,
1480         DRM_FORMAT_ABGR8888,
1481 };
1482
1483 static const struct nv50_wndw_func
1484 nv50_base = {
1485         .dtor = nv50_base_dtor,
1486         .acquire = nv50_base_acquire,
1487         .release = nv50_base_release,
1488         .sema_set = nv50_base_sema_set,
1489         .sema_clr = nv50_base_sema_clr,
1490         .ntfy_set = nv50_base_ntfy_set,
1491         .ntfy_clr = nv50_base_ntfy_clr,
1492         .ntfy_wait_begun = nv50_base_ntfy_wait_begun,
1493         .image_set = nv50_base_image_set,
1494         .image_clr = nv50_base_image_clr,
1495         .lut = nv50_base_lut,
1496         .update = nv50_base_update,
1497 };
1498
1499 static int
1500 nv50_base_new(struct nouveau_drm *drm, struct nv50_head *head,
1501               struct nv50_base **pbase)
1502 {
1503         struct nv50_disp *disp = nv50_disp(drm->dev);
1504         struct nv50_base *base;
1505         int ret;
1506
1507         if (!(base = *pbase = kzalloc(sizeof(*base), GFP_KERNEL)))
1508                 return -ENOMEM;
1509         base->id = head->base.index;
1510         base->wndw.ntfy = EVO_FLIP_NTFY0(base->id);
1511         base->wndw.sema = EVO_FLIP_SEM0(base->id);
1512         base->wndw.data = 0x00000000;
1513
1514         ret = nv50_wndw_ctor(&nv50_base, drm->dev, DRM_PLANE_TYPE_PRIMARY,
1515                              "base", base->id, &base->chan.base,
1516                              nv50_base_format, ARRAY_SIZE(nv50_base_format),
1517                              &base->wndw);
1518         if (ret) {
1519                 kfree(base);
1520                 return ret;
1521         }
1522
1523         ret = nv50_base_create(&drm->client.device, disp->disp, base->id,
1524                                disp->sync->bo.offset, &base->chan);
1525         if (ret)
1526                 return ret;
1527
1528         return nvif_notify_init(&base->chan.base.base.user, nv50_base_notify,
1529                                 false,
1530                                 NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT,
1531                                 &(struct nvif_notify_uevent_req) {},
1532                                 sizeof(struct nvif_notify_uevent_req),
1533                                 sizeof(struct nvif_notify_uevent_rep),
1534                                 &base->wndw.notify);
1535 }
1536
1537 /******************************************************************************
1538  * Head
1539  *****************************************************************************/
1540 static void
1541 nv50_head_procamp(struct nv50_head *head, struct nv50_head_atom *asyh)
1542 {
1543         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1544         u32 *push;
1545         if ((push = evo_wait(core, 2))) {
1546                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1547                         evo_mthd(push, 0x08a8 + (head->base.index * 0x400), 1);
1548                 else
1549                         evo_mthd(push, 0x0498 + (head->base.index * 0x300), 1);
1550                 evo_data(push, (asyh->procamp.sat.sin << 20) |
1551                                (asyh->procamp.sat.cos << 8));
1552                 evo_kick(push, core);
1553         }
1554 }
1555
1556 static void
1557 nv50_head_dither(struct nv50_head *head, struct nv50_head_atom *asyh)
1558 {
1559         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1560         u32 *push;
1561         if ((push = evo_wait(core, 2))) {
1562                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1563                         evo_mthd(push, 0x08a0 + (head->base.index * 0x0400), 1);
1564                 else
1565                 if (core->base.user.oclass < GK104_DISP_CORE_CHANNEL_DMA)
1566                         evo_mthd(push, 0x0490 + (head->base.index * 0x0300), 1);
1567                 else
1568                         evo_mthd(push, 0x04a0 + (head->base.index * 0x0300), 1);
1569                 evo_data(push, (asyh->dither.mode << 3) |
1570                                (asyh->dither.bits << 1) |
1571                                 asyh->dither.enable);
1572                 evo_kick(push, core);
1573         }
1574 }
1575
1576 static void
1577 nv50_head_ovly(struct nv50_head *head, struct nv50_head_atom *asyh)
1578 {
1579         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1580         u32 bounds = 0;
1581         u32 *push;
1582
1583         if (asyh->base.cpp) {
1584                 switch (asyh->base.cpp) {
1585                 case 8: bounds |= 0x00000500; break;
1586                 case 4: bounds |= 0x00000300; break;
1587                 case 2: bounds |= 0x00000100; break;
1588                 default:
1589                         WARN_ON(1);
1590                         break;
1591                 }
1592                 bounds |= 0x00000001;
1593         }
1594
1595         if ((push = evo_wait(core, 2))) {
1596                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1597                         evo_mthd(push, 0x0904 + head->base.index * 0x400, 1);
1598                 else
1599                         evo_mthd(push, 0x04d4 + head->base.index * 0x300, 1);
1600                 evo_data(push, bounds);
1601                 evo_kick(push, core);
1602         }
1603 }
1604
1605 static void
1606 nv50_head_base(struct nv50_head *head, struct nv50_head_atom *asyh)
1607 {
1608         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1609         u32 bounds = 0;
1610         u32 *push;
1611
1612         if (asyh->base.cpp) {
1613                 switch (asyh->base.cpp) {
1614                 case 8: bounds |= 0x00000500; break;
1615                 case 4: bounds |= 0x00000300; break;
1616                 case 2: bounds |= 0x00000100; break;
1617                 case 1: bounds |= 0x00000000; break;
1618                 default:
1619                         WARN_ON(1);
1620                         break;
1621                 }
1622                 bounds |= 0x00000001;
1623         }
1624
1625         if ((push = evo_wait(core, 2))) {
1626                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1627                         evo_mthd(push, 0x0900 + head->base.index * 0x400, 1);
1628                 else
1629                         evo_mthd(push, 0x04d0 + head->base.index * 0x300, 1);
1630                 evo_data(push, bounds);
1631                 evo_kick(push, core);
1632         }
1633 }
1634
1635 static void
1636 nv50_head_curs_clr(struct nv50_head *head)
1637 {
1638         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1639         u32 *push;
1640         if ((push = evo_wait(core, 4))) {
1641                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1642                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 1);
1643                         evo_data(push, 0x05000000);
1644                 } else
1645                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1646                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 1);
1647                         evo_data(push, 0x05000000);
1648                         evo_mthd(push, 0x089c + head->base.index * 0x400, 1);
1649                         evo_data(push, 0x00000000);
1650                 } else {
1651                         evo_mthd(push, 0x0480 + head->base.index * 0x300, 1);
1652                         evo_data(push, 0x05000000);
1653                         evo_mthd(push, 0x048c + head->base.index * 0x300, 1);
1654                         evo_data(push, 0x00000000);
1655                 }
1656                 evo_kick(push, core);
1657         }
1658 }
1659
1660 static void
1661 nv50_head_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1662 {
1663         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1664         u32 *push;
1665         if ((push = evo_wait(core, 5))) {
1666                 if (core->base.user.oclass < G82_DISP_BASE_CHANNEL_DMA) {
1667                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 2);
1668                         evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1669                                                     (asyh->curs.format << 24));
1670                         evo_data(push, asyh->curs.offset >> 8);
1671                 } else
1672                 if (core->base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA) {
1673                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 2);
1674                         evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1675                                                     (asyh->curs.format << 24));
1676                         evo_data(push, asyh->curs.offset >> 8);
1677                         evo_mthd(push, 0x089c + head->base.index * 0x400, 1);
1678                         evo_data(push, asyh->curs.handle);
1679                 } else {
1680                         evo_mthd(push, 0x0480 + head->base.index * 0x300, 2);
1681                         evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1682                                                     (asyh->curs.format << 24));
1683                         evo_data(push, asyh->curs.offset >> 8);
1684                         evo_mthd(push, 0x048c + head->base.index * 0x300, 1);
1685                         evo_data(push, asyh->curs.handle);
1686                 }
1687                 evo_kick(push, core);
1688         }
1689 }
1690
1691 static void
1692 nv50_head_core_clr(struct nv50_head *head)
1693 {
1694         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1695         u32 *push;
1696         if ((push = evo_wait(core, 2))) {
1697                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1698                         evo_mthd(push, 0x0874 + head->base.index * 0x400, 1);
1699                 else
1700                         evo_mthd(push, 0x0474 + head->base.index * 0x300, 1);
1701                 evo_data(push, 0x00000000);
1702                 evo_kick(push, core);
1703         }
1704 }
1705
1706 static void
1707 nv50_head_core_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1708 {
1709         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1710         u32 *push;
1711         if ((push = evo_wait(core, 9))) {
1712                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1713                         evo_mthd(push, 0x0860 + head->base.index * 0x400, 1);
1714                         evo_data(push, asyh->core.offset >> 8);
1715                         evo_mthd(push, 0x0868 + head->base.index * 0x400, 4);
1716                         evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1717                         evo_data(push, asyh->core.layout << 20 |
1718                                        (asyh->core.pitch >> 8) << 8 |
1719                                        asyh->core.block);
1720                         evo_data(push, asyh->core.kind << 16 |
1721                                        asyh->core.format << 8);
1722                         evo_data(push, asyh->core.handle);
1723                         evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1);
1724                         evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1725                         /* EVO will complain with INVALID_STATE if we have an
1726                          * active cursor and (re)specify HeadSetContextDmaIso
1727                          * without also updating HeadSetOffsetCursor.
1728                          */
1729                         asyh->set.curs = asyh->curs.visible;
1730                 } else
1731                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1732                         evo_mthd(push, 0x0860 + head->base.index * 0x400, 1);
1733                         evo_data(push, asyh->core.offset >> 8);
1734                         evo_mthd(push, 0x0868 + head->base.index * 0x400, 4);
1735                         evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1736                         evo_data(push, asyh->core.layout << 20 |
1737                                        (asyh->core.pitch >> 8) << 8 |
1738                                        asyh->core.block);
1739                         evo_data(push, asyh->core.format << 8);
1740                         evo_data(push, asyh->core.handle);
1741                         evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1);
1742                         evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1743                 } else {
1744                         evo_mthd(push, 0x0460 + head->base.index * 0x300, 1);
1745                         evo_data(push, asyh->core.offset >> 8);
1746                         evo_mthd(push, 0x0468 + head->base.index * 0x300, 4);
1747                         evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1748                         evo_data(push, asyh->core.layout << 24 |
1749                                        (asyh->core.pitch >> 8) << 8 |
1750                                        asyh->core.block);
1751                         evo_data(push, asyh->core.format << 8);
1752                         evo_data(push, asyh->core.handle);
1753                         evo_mthd(push, 0x04b0 + head->base.index * 0x300, 1);
1754                         evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1755                 }
1756                 evo_kick(push, core);
1757         }
1758 }
1759
1760 static void
1761 nv50_head_lut_clr(struct nv50_head *head)
1762 {
1763         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1764         u32 *push;
1765         if ((push = evo_wait(core, 4))) {
1766                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1767                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1);
1768                         evo_data(push, 0x40000000);
1769                 } else
1770                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1771                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1);
1772                         evo_data(push, 0x40000000);
1773                         evo_mthd(push, 0x085c + (head->base.index * 0x400), 1);
1774                         evo_data(push, 0x00000000);
1775                 } else {
1776                         evo_mthd(push, 0x0440 + (head->base.index * 0x300), 1);
1777                         evo_data(push, 0x03000000);
1778                         evo_mthd(push, 0x045c + (head->base.index * 0x300), 1);
1779                         evo_data(push, 0x00000000);
1780                 }
1781                 evo_kick(push, core);
1782         }
1783 }
1784
1785 static void
1786 nv50_head_lut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1787 {
1788         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1789         u32 *push;
1790         if ((push = evo_wait(core, 7))) {
1791                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1792                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2);
1793                         evo_data(push, 0xc0000000);
1794                         evo_data(push, asyh->lut.offset >> 8);
1795                 } else
1796                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1797                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2);
1798                         evo_data(push, 0xc0000000);
1799                         evo_data(push, asyh->lut.offset >> 8);
1800                         evo_mthd(push, 0x085c + (head->base.index * 0x400), 1);
1801                         evo_data(push, asyh->lut.handle);
1802                 } else {
1803                         evo_mthd(push, 0x0440 + (head->base.index * 0x300), 4);
1804                         evo_data(push, 0x83000000);
1805                         evo_data(push, asyh->lut.offset >> 8);
1806                         evo_data(push, 0x00000000);
1807                         evo_data(push, 0x00000000);
1808                         evo_mthd(push, 0x045c + (head->base.index * 0x300), 1);
1809                         evo_data(push, asyh->lut.handle);
1810                 }
1811                 evo_kick(push, core);
1812         }
1813 }
1814
1815 static void
1816 nv50_head_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
1817 {
1818         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1819         struct nv50_head_mode *m = &asyh->mode;
1820         u32 *push;
1821         if ((push = evo_wait(core, 14))) {
1822                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1823                         evo_mthd(push, 0x0804 + (head->base.index * 0x400), 2);
1824                         evo_data(push, 0x00800000 | m->clock);
1825                         evo_data(push, m->interlace ? 0x00000002 : 0x00000000);
1826                         evo_mthd(push, 0x0810 + (head->base.index * 0x400), 7);
1827                         evo_data(push, 0x00000000);
1828                         evo_data(push, (m->v.active  << 16) | m->h.active );
1829                         evo_data(push, (m->v.synce   << 16) | m->h.synce  );
1830                         evo_data(push, (m->v.blanke  << 16) | m->h.blanke );
1831                         evo_data(push, (m->v.blanks  << 16) | m->h.blanks );
1832                         evo_data(push, (m->v.blank2e << 16) | m->v.blank2s);
1833                         evo_data(push, asyh->mode.v.blankus);
1834                         evo_mthd(push, 0x082c + (head->base.index * 0x400), 1);
1835                         evo_data(push, 0x00000000);
1836                 } else {
1837                         evo_mthd(push, 0x0410 + (head->base.index * 0x300), 6);
1838                         evo_data(push, 0x00000000);
1839                         evo_data(push, (m->v.active  << 16) | m->h.active );
1840                         evo_data(push, (m->v.synce   << 16) | m->h.synce  );
1841                         evo_data(push, (m->v.blanke  << 16) | m->h.blanke );
1842                         evo_data(push, (m->v.blanks  << 16) | m->h.blanks );
1843                         evo_data(push, (m->v.blank2e << 16) | m->v.blank2s);
1844                         evo_mthd(push, 0x042c + (head->base.index * 0x300), 2);
1845                         evo_data(push, 0x00000000); /* ??? */
1846                         evo_data(push, 0xffffff00);
1847                         evo_mthd(push, 0x0450 + (head->base.index * 0x300), 3);
1848                         evo_data(push, m->clock * 1000);
1849                         evo_data(push, 0x00200000); /* ??? */
1850                         evo_data(push, m->clock * 1000);
1851                 }
1852                 evo_kick(push, core);
1853         }
1854 }
1855
1856 static void
1857 nv50_head_view(struct nv50_head *head, struct nv50_head_atom *asyh)
1858 {
1859         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1860         u32 *push;
1861         if ((push = evo_wait(core, 10))) {
1862                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1863                         evo_mthd(push, 0x08a4 + (head->base.index * 0x400), 1);
1864                         evo_data(push, 0x00000000);
1865                         evo_mthd(push, 0x08c8 + (head->base.index * 0x400), 1);
1866                         evo_data(push, (asyh->view.iH << 16) | asyh->view.iW);
1867                         evo_mthd(push, 0x08d8 + (head->base.index * 0x400), 2);
1868                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1869                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1870                 } else {
1871                         evo_mthd(push, 0x0494 + (head->base.index * 0x300), 1);
1872                         evo_data(push, 0x00000000);
1873                         evo_mthd(push, 0x04b8 + (head->base.index * 0x300), 1);
1874                         evo_data(push, (asyh->view.iH << 16) | asyh->view.iW);
1875                         evo_mthd(push, 0x04c0 + (head->base.index * 0x300), 3);
1876                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1877                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1878                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1879                 }
1880                 evo_kick(push, core);
1881         }
1882 }
1883
1884 static void
1885 nv50_head_flush_clr(struct nv50_head *head, struct nv50_head_atom *asyh, bool y)
1886 {
1887         if (asyh->clr.core && (!asyh->set.core || y))
1888                 nv50_head_lut_clr(head);
1889         if (asyh->clr.core && (!asyh->set.core || y))
1890                 nv50_head_core_clr(head);
1891         if (asyh->clr.curs && (!asyh->set.curs || y))
1892                 nv50_head_curs_clr(head);
1893 }
1894
1895 static void
1896 nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1897 {
1898         if (asyh->set.view   ) nv50_head_view    (head, asyh);
1899         if (asyh->set.mode   ) nv50_head_mode    (head, asyh);
1900         if (asyh->set.core   ) nv50_head_lut_set (head, asyh);
1901         if (asyh->set.core   ) nv50_head_core_set(head, asyh);
1902         if (asyh->set.curs   ) nv50_head_curs_set(head, asyh);
1903         if (asyh->set.base   ) nv50_head_base    (head, asyh);
1904         if (asyh->set.ovly   ) nv50_head_ovly    (head, asyh);
1905         if (asyh->set.dither ) nv50_head_dither  (head, asyh);
1906         if (asyh->set.procamp) nv50_head_procamp (head, asyh);
1907 }
1908
1909 static void
1910 nv50_head_atomic_check_procamp(struct nv50_head_atom *armh,
1911                                struct nv50_head_atom *asyh,
1912                                struct nouveau_conn_atom *asyc)
1913 {
1914         const int vib = asyc->procamp.color_vibrance - 100;
1915         const int hue = asyc->procamp.vibrant_hue - 90;
1916         const int adj = (vib > 0) ? 50 : 0;
1917         asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff;
1918         asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff;
1919         asyh->set.procamp = true;
1920 }
1921
1922 static void
1923 nv50_head_atomic_check_dither(struct nv50_head_atom *armh,
1924                               struct nv50_head_atom *asyh,
1925                               struct nouveau_conn_atom *asyc)
1926 {
1927         struct drm_connector *connector = asyc->state.connector;
1928         u32 mode = 0x00;
1929
1930         if (asyc->dither.mode == DITHERING_MODE_AUTO) {
1931                 if (asyh->base.depth > connector->display_info.bpc * 3)
1932                         mode = DITHERING_MODE_DYNAMIC2X2;
1933         } else {
1934                 mode = asyc->dither.mode;
1935         }
1936
1937         if (asyc->dither.depth == DITHERING_DEPTH_AUTO) {
1938                 if (connector->display_info.bpc >= 8)
1939                         mode |= DITHERING_DEPTH_8BPC;
1940         } else {
1941                 mode |= asyc->dither.depth;
1942         }
1943
1944         asyh->dither.enable = mode;
1945         asyh->dither.bits = mode >> 1;
1946         asyh->dither.mode = mode >> 3;
1947         asyh->set.dither = true;
1948 }
1949
1950 static void
1951 nv50_head_atomic_check_view(struct nv50_head_atom *armh,
1952                             struct nv50_head_atom *asyh,
1953                             struct nouveau_conn_atom *asyc)
1954 {
1955         struct drm_connector *connector = asyc->state.connector;
1956         struct drm_display_mode *omode = &asyh->state.adjusted_mode;
1957         struct drm_display_mode *umode = &asyh->state.mode;
1958         int mode = asyc->scaler.mode;
1959         struct edid *edid;
1960
1961         if (connector->edid_blob_ptr)
1962                 edid = (struct edid *)connector->edid_blob_ptr->data;
1963         else
1964                 edid = NULL;
1965
1966         if (!asyc->scaler.full) {
1967                 if (mode == DRM_MODE_SCALE_NONE)
1968                         omode = umode;
1969         } else {
1970                 /* Non-EDID LVDS/eDP mode. */
1971                 mode = DRM_MODE_SCALE_FULLSCREEN;
1972         }
1973
1974         asyh->view.iW = umode->hdisplay;
1975         asyh->view.iH = umode->vdisplay;
1976         asyh->view.oW = omode->hdisplay;
1977         asyh->view.oH = omode->vdisplay;
1978         if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
1979                 asyh->view.oH *= 2;
1980
1981         /* Add overscan compensation if necessary, will keep the aspect
1982          * ratio the same as the backend mode unless overridden by the
1983          * user setting both hborder and vborder properties.
1984          */
1985         if ((asyc->scaler.underscan.mode == UNDERSCAN_ON ||
1986             (asyc->scaler.underscan.mode == UNDERSCAN_AUTO &&
1987              drm_detect_hdmi_monitor(edid)))) {
1988                 u32 bX = asyc->scaler.underscan.hborder;
1989                 u32 bY = asyc->scaler.underscan.vborder;
1990                 u32 r = (asyh->view.oH << 19) / asyh->view.oW;
1991
1992                 if (bX) {
1993                         asyh->view.oW -= (bX * 2);
1994                         if (bY) asyh->view.oH -= (bY * 2);
1995                         else    asyh->view.oH  = ((asyh->view.oW * r) + (r / 2)) >> 19;
1996                 } else {
1997                         asyh->view.oW -= (asyh->view.oW >> 4) + 32;
1998                         if (bY) asyh->view.oH -= (bY * 2);
1999                         else    asyh->view.oH  = ((asyh->view.oW * r) + (r / 2)) >> 19;
2000                 }
2001         }
2002
2003         /* Handle CENTER/ASPECT scaling, taking into account the areas
2004          * removed already for overscan compensation.
2005          */
2006         switch (mode) {
2007         case DRM_MODE_SCALE_CENTER:
2008                 asyh->view.oW = min((u16)umode->hdisplay, asyh->view.oW);
2009                 asyh->view.oH = min((u16)umode->vdisplay, asyh->view.oH);
2010                 /* fall-through */
2011         case DRM_MODE_SCALE_ASPECT:
2012                 if (asyh->view.oH < asyh->view.oW) {
2013                         u32 r = (asyh->view.iW << 19) / asyh->view.iH;
2014                         asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19;
2015                 } else {
2016                         u32 r = (asyh->view.iH << 19) / asyh->view.iW;
2017                         asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
2018                 }
2019                 break;
2020         default:
2021                 break;
2022         }
2023
2024         asyh->set.view = true;
2025 }
2026
2027 static void
2028 nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
2029 {
2030         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
2031         u32 ilace   = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
2032         u32 vscan   = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
2033         u32 hbackp  =  mode->htotal - mode->hsync_end;
2034         u32 vbackp  = (mode->vtotal - mode->vsync_end) * vscan / ilace;
2035         u32 hfrontp =  mode->hsync_start - mode->hdisplay;
2036         u32 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
2037         u32 blankus;
2038         struct nv50_head_mode *m = &asyh->mode;
2039
2040         m->h.active = mode->htotal;
2041         m->h.synce  = mode->hsync_end - mode->hsync_start - 1;
2042         m->h.blanke = m->h.synce + hbackp;
2043         m->h.blanks = mode->htotal - hfrontp - 1;
2044
2045         m->v.active = mode->vtotal * vscan / ilace;
2046         m->v.synce  = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
2047         m->v.blanke = m->v.synce + vbackp;
2048         m->v.blanks = m->v.active - vfrontp - 1;
2049
2050         /*XXX: Safe underestimate, even "0" works */
2051         blankus = (m->v.active - mode->vdisplay - 2) * m->h.active;
2052         blankus *= 1000;
2053         blankus /= mode->clock;
2054         m->v.blankus = blankus;
2055
2056         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2057                 m->v.blank2e =  m->v.active + m->v.synce + vbackp;
2058                 m->v.blank2s =  m->v.blank2e + (mode->vdisplay * vscan / ilace);
2059                 m->v.active  = (m->v.active * 2) + 1;
2060                 m->interlace = true;
2061         } else {
2062                 m->v.blank2e = 0;
2063                 m->v.blank2s = 1;
2064                 m->interlace = false;
2065         }
2066         m->clock = mode->clock;
2067
2068         drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
2069         asyh->set.mode = true;
2070 }
2071
2072 static int
2073 nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state)
2074 {
2075         struct nouveau_drm *drm = nouveau_drm(crtc->dev);
2076         struct nv50_disp *disp = nv50_disp(crtc->dev);
2077         struct nv50_head *head = nv50_head(crtc);
2078         struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
2079         struct nv50_head_atom *asyh = nv50_head_atom(state);
2080         struct nouveau_conn_atom *asyc = NULL;
2081         struct drm_connector_state *conns;
2082         struct drm_connector *conn;
2083         int i;
2084
2085         NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active);
2086         if (asyh->state.active) {
2087                 for_each_connector_in_state(asyh->state.state, conn, conns, i) {
2088                         if (conns->crtc == crtc) {
2089                                 asyc = nouveau_conn_atom(conns);
2090                                 break;
2091                         }
2092                 }
2093
2094                 if (armh->state.active) {
2095                         if (asyc) {
2096                                 if (asyh->state.mode_changed)
2097                                         asyc->set.scaler = true;
2098                                 if (armh->base.depth != asyh->base.depth)
2099                                         asyc->set.dither = true;
2100                         }
2101                 } else {
2102                         asyc->set.mask = ~0;
2103                         asyh->set.mask = ~0;
2104                 }
2105
2106                 if (asyh->state.mode_changed)
2107                         nv50_head_atomic_check_mode(head, asyh);
2108
2109                 if (asyc) {
2110                         if (asyc->set.scaler)
2111                                 nv50_head_atomic_check_view(armh, asyh, asyc);
2112                         if (asyc->set.dither)
2113                                 nv50_head_atomic_check_dither(armh, asyh, asyc);
2114                         if (asyc->set.procamp)
2115                                 nv50_head_atomic_check_procamp(armh, asyh, asyc);
2116                 }
2117
2118                 if ((asyh->core.visible = (asyh->base.cpp != 0))) {
2119                         asyh->core.x = asyh->base.x;
2120                         asyh->core.y = asyh->base.y;
2121                         asyh->core.w = asyh->base.w;
2122                         asyh->core.h = asyh->base.h;
2123                 } else
2124                 if ((asyh->core.visible = asyh->curs.visible)) {
2125                         /*XXX: We need to either find some way of having the
2126                          *     primary base layer appear black, while still
2127                          *     being able to display the other layers, or we
2128                          *     need to allocate a dummy black surface here.
2129                          */
2130                         asyh->core.x = 0;
2131                         asyh->core.y = 0;
2132                         asyh->core.w = asyh->state.mode.hdisplay;
2133                         asyh->core.h = asyh->state.mode.vdisplay;
2134                 }
2135                 asyh->core.handle = disp->mast.base.vram.handle;
2136                 asyh->core.offset = 0;
2137                 asyh->core.format = 0xcf;
2138                 asyh->core.kind = 0;
2139                 asyh->core.layout = 1;
2140                 asyh->core.block = 0;
2141                 asyh->core.pitch = ALIGN(asyh->core.w, 64) * 4;
2142                 asyh->lut.handle = disp->mast.base.vram.handle;
2143                 asyh->lut.offset = head->base.lut.nvbo->bo.offset;
2144                 asyh->set.base = armh->base.cpp != asyh->base.cpp;
2145                 asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp;
2146         } else {
2147                 asyh->core.visible = false;
2148                 asyh->curs.visible = false;
2149                 asyh->base.cpp = 0;
2150                 asyh->ovly.cpp = 0;
2151         }
2152
2153         if (!drm_atomic_crtc_needs_modeset(&asyh->state)) {
2154                 if (asyh->core.visible) {
2155                         if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core)))
2156                                 asyh->set.core = true;
2157                 } else
2158                 if (armh->core.visible) {
2159                         asyh->clr.core = true;
2160                 }
2161
2162                 if (asyh->curs.visible) {
2163                         if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs)))
2164                                 asyh->set.curs = true;
2165                 } else
2166                 if (armh->curs.visible) {
2167                         asyh->clr.curs = true;
2168                 }
2169         } else {
2170                 asyh->clr.core = armh->core.visible;
2171                 asyh->clr.curs = armh->curs.visible;
2172                 asyh->set.core = asyh->core.visible;
2173                 asyh->set.curs = asyh->curs.visible;
2174         }
2175
2176         if (asyh->clr.mask || asyh->set.mask)
2177                 nv50_atom(asyh->state.state)->lock_core = true;
2178         return 0;
2179 }
2180
2181 static void
2182 nv50_head_lut_load(struct drm_crtc *crtc)
2183 {
2184         struct nv50_disp *disp = nv50_disp(crtc->dev);
2185         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
2186         void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
2187         int i;
2188
2189         for (i = 0; i < 256; i++) {
2190                 u16 r = nv_crtc->lut.r[i] >> 2;
2191                 u16 g = nv_crtc->lut.g[i] >> 2;
2192                 u16 b = nv_crtc->lut.b[i] >> 2;
2193
2194                 if (disp->disp->oclass < GF110_DISP) {
2195                         writew(r + 0x0000, lut + (i * 0x08) + 0);
2196                         writew(g + 0x0000, lut + (i * 0x08) + 2);
2197                         writew(b + 0x0000, lut + (i * 0x08) + 4);
2198                 } else {
2199                         writew(r + 0x6000, lut + (i * 0x20) + 0);
2200                         writew(g + 0x6000, lut + (i * 0x20) + 2);
2201                         writew(b + 0x6000, lut + (i * 0x20) + 4);
2202                 }
2203         }
2204 }
2205
2206 static int
2207 nv50_head_mode_set_base_atomic(struct drm_crtc *crtc,
2208                                struct drm_framebuffer *fb, int x, int y,
2209                                enum mode_set_atomic state)
2210 {
2211         WARN_ON(1);
2212         return 0;
2213 }
2214
2215 static const struct drm_crtc_helper_funcs
2216 nv50_head_help = {
2217         .mode_set_base_atomic = nv50_head_mode_set_base_atomic,
2218         .load_lut = nv50_head_lut_load,
2219         .atomic_check = nv50_head_atomic_check,
2220 };
2221
2222 /* This is identical to the version in the atomic helpers, except that
2223  * it supports non-vblanked ("async") page flips.
2224  */
2225 static int
2226 nv50_head_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2227                     struct drm_pending_vblank_event *event, u32 flags)
2228 {
2229         struct drm_plane *plane = crtc->primary;
2230         struct drm_atomic_state *state;
2231         struct drm_plane_state *plane_state;
2232         struct drm_crtc_state *crtc_state;
2233         int ret = 0;
2234
2235         state = drm_atomic_state_alloc(plane->dev);
2236         if (!state)
2237                 return -ENOMEM;
2238
2239         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
2240 retry:
2241         crtc_state = drm_atomic_get_crtc_state(state, crtc);
2242         if (IS_ERR(crtc_state)) {
2243                 ret = PTR_ERR(crtc_state);
2244                 goto fail;
2245         }
2246         crtc_state->event = event;
2247
2248         plane_state = drm_atomic_get_plane_state(state, plane);
2249         if (IS_ERR(plane_state)) {
2250                 ret = PTR_ERR(plane_state);
2251                 goto fail;
2252         }
2253
2254         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
2255         if (ret != 0)
2256                 goto fail;
2257         drm_atomic_set_fb_for_plane(plane_state, fb);
2258
2259         /* Make sure we don't accidentally do a full modeset. */
2260         state->allow_modeset = false;
2261         if (!crtc_state->active) {
2262                 DRM_DEBUG_ATOMIC("[CRTC:%d] disabled, rejecting legacy flip\n",
2263                                  crtc->base.id);
2264                 ret = -EINVAL;
2265                 goto fail;
2266         }
2267
2268         if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
2269                 nv50_wndw_atom(plane_state)->interval = 0;
2270
2271         ret = drm_atomic_nonblocking_commit(state);
2272 fail:
2273         if (ret == -EDEADLK)
2274                 goto backoff;
2275
2276         drm_atomic_state_put(state);
2277         return ret;
2278
2279 backoff:
2280         drm_atomic_state_clear(state);
2281         drm_atomic_legacy_backoff(state);
2282
2283         /*
2284          * Someone might have exchanged the framebuffer while we dropped locks
2285          * in the backoff code. We need to fix up the fb refcount tracking the
2286          * core does for us.
2287          */
2288         plane->old_fb = plane->fb;
2289
2290         goto retry;
2291 }
2292
2293 static int
2294 nv50_head_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
2295                     uint32_t size)
2296 {
2297         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
2298         u32 i;
2299
2300         for (i = 0; i < size; i++) {
2301                 nv_crtc->lut.r[i] = r[i];
2302                 nv_crtc->lut.g[i] = g[i];
2303                 nv_crtc->lut.b[i] = b[i];
2304         }
2305
2306         nv50_head_lut_load(crtc);
2307         return 0;
2308 }
2309
2310 static void
2311 nv50_head_atomic_destroy_state(struct drm_crtc *crtc,
2312                                struct drm_crtc_state *state)
2313 {
2314         struct nv50_head_atom *asyh = nv50_head_atom(state);
2315         __drm_atomic_helper_crtc_destroy_state(&asyh->state);
2316         kfree(asyh);
2317 }
2318
2319 static struct drm_crtc_state *
2320 nv50_head_atomic_duplicate_state(struct drm_crtc *crtc)
2321 {
2322         struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
2323         struct nv50_head_atom *asyh;
2324         if (!(asyh = kmalloc(sizeof(*asyh), GFP_KERNEL)))
2325                 return NULL;
2326         __drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state);
2327         asyh->view = armh->view;
2328         asyh->mode = armh->mode;
2329         asyh->lut  = armh->lut;
2330         asyh->core = armh->core;
2331         asyh->curs = armh->curs;
2332         asyh->base = armh->base;
2333         asyh->ovly = armh->ovly;
2334         asyh->dither = armh->dither;
2335         asyh->procamp = armh->procamp;
2336         asyh->clr.mask = 0;
2337         asyh->set.mask = 0;
2338         return &asyh->state;
2339 }
2340
2341 static void
2342 __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc,
2343                                struct drm_crtc_state *state)
2344 {
2345         if (crtc->state)
2346                 crtc->funcs->atomic_destroy_state(crtc, crtc->state);
2347         crtc->state = state;
2348         crtc->state->crtc = crtc;
2349 }
2350
2351 static void
2352 nv50_head_reset(struct drm_crtc *crtc)
2353 {
2354         struct nv50_head_atom *asyh;
2355
2356         if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL))))
2357                 return;
2358
2359         __drm_atomic_helper_crtc_reset(crtc, &asyh->state);
2360 }
2361
2362 static void
2363 nv50_head_destroy(struct drm_crtc *crtc)
2364 {
2365         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
2366         struct nv50_disp *disp = nv50_disp(crtc->dev);
2367         struct nv50_head *head = nv50_head(crtc);
2368
2369         nv50_dmac_destroy(&head->ovly.base, disp->disp);
2370         nv50_pioc_destroy(&head->oimm.base);
2371
2372         nouveau_bo_unmap(nv_crtc->lut.nvbo);
2373         if (nv_crtc->lut.nvbo)
2374                 nouveau_bo_unpin(nv_crtc->lut.nvbo);
2375         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
2376
2377         drm_crtc_cleanup(crtc);
2378         kfree(crtc);
2379 }
2380
2381 static const struct drm_crtc_funcs
2382 nv50_head_func = {
2383         .reset = nv50_head_reset,
2384         .gamma_set = nv50_head_gamma_set,
2385         .destroy = nv50_head_destroy,
2386         .set_config = drm_atomic_helper_set_config,
2387         .page_flip = nv50_head_page_flip,
2388         .set_property = drm_atomic_helper_crtc_set_property,
2389         .atomic_duplicate_state = nv50_head_atomic_duplicate_state,
2390         .atomic_destroy_state = nv50_head_atomic_destroy_state,
2391 };
2392
2393 static int
2394 nv50_head_create(struct drm_device *dev, int index)
2395 {
2396         struct nouveau_drm *drm = nouveau_drm(dev);
2397         struct nvif_device *device = &drm->client.device;
2398         struct nv50_disp *disp = nv50_disp(dev);
2399         struct nv50_head *head;
2400         struct nv50_base *base;
2401         struct nv50_curs *curs;
2402         struct drm_crtc *crtc;
2403         int ret, i;
2404
2405         head = kzalloc(sizeof(*head), GFP_KERNEL);
2406         if (!head)
2407                 return -ENOMEM;
2408
2409         head->base.index = index;
2410         for (i = 0; i < 256; i++) {
2411                 head->base.lut.r[i] = i << 8;
2412                 head->base.lut.g[i] = i << 8;
2413                 head->base.lut.b[i] = i << 8;
2414         }
2415
2416         ret = nv50_base_new(drm, head, &base);
2417         if (ret == 0)
2418                 ret = nv50_curs_new(drm, head, &curs);
2419         if (ret) {
2420                 kfree(head);
2421                 return ret;
2422         }
2423
2424         crtc = &head->base.base;
2425         drm_crtc_init_with_planes(dev, crtc, &base->wndw.plane,
2426                                   &curs->wndw.plane, &nv50_head_func,
2427                                   "head-%d", head->base.index);
2428         drm_crtc_helper_add(crtc, &nv50_head_help);
2429         drm_mode_crtc_set_gamma_size(crtc, 256);
2430
2431         ret = nouveau_bo_new(&drm->client, 8192, 0x100, TTM_PL_FLAG_VRAM,
2432                              0, 0x0000, NULL, NULL, &head->base.lut.nvbo);
2433         if (!ret) {
2434                 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM, true);
2435                 if (!ret) {
2436                         ret = nouveau_bo_map(head->base.lut.nvbo);
2437                         if (ret)
2438                                 nouveau_bo_unpin(head->base.lut.nvbo);
2439                 }
2440                 if (ret)
2441                         nouveau_bo_ref(NULL, &head->base.lut.nvbo);
2442         }
2443
2444         if (ret)
2445                 goto out;
2446
2447         /* allocate overlay resources */
2448         ret = nv50_oimm_create(device, disp->disp, index, &head->oimm);
2449         if (ret)
2450                 goto out;
2451
2452         ret = nv50_ovly_create(device, disp->disp, index, disp->sync->bo.offset,
2453                                &head->ovly);
2454         if (ret)
2455                 goto out;
2456
2457 out:
2458         if (ret)
2459                 nv50_head_destroy(crtc);
2460         return ret;
2461 }
2462
2463 /******************************************************************************
2464  * Output path helpers
2465  *****************************************************************************/
2466 static int
2467 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
2468                             struct drm_crtc_state *crtc_state,
2469                             struct drm_connector_state *conn_state,
2470                             struct drm_display_mode *native_mode)
2471 {
2472         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
2473         struct drm_display_mode *mode = &crtc_state->mode;
2474         struct drm_connector *connector = conn_state->connector;
2475         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
2476         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
2477
2478         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
2479         asyc->scaler.full = false;
2480         if (!native_mode)
2481                 return 0;
2482
2483         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
2484                 switch (connector->connector_type) {
2485                 case DRM_MODE_CONNECTOR_LVDS:
2486                 case DRM_MODE_CONNECTOR_eDP:
2487                         /* Force use of scaler for non-EDID modes. */
2488                         if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
2489                                 break;
2490                         mode = native_mode;
2491                         asyc->scaler.full = true;
2492                         break;
2493                 default:
2494                         break;
2495                 }
2496         } else {
2497                 mode = native_mode;
2498         }
2499
2500         if (!drm_mode_equal(adjusted_mode, mode)) {
2501                 drm_mode_copy(adjusted_mode, mode);
2502                 crtc_state->mode_changed = true;
2503         }
2504
2505         return 0;
2506 }
2507
2508 static int
2509 nv50_outp_atomic_check(struct drm_encoder *encoder,
2510                        struct drm_crtc_state *crtc_state,
2511                        struct drm_connector_state *conn_state)
2512 {
2513         struct nouveau_connector *nv_connector =
2514                 nouveau_connector(conn_state->connector);
2515         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
2516                                            nv_connector->native_mode);
2517 }
2518
2519 /******************************************************************************
2520  * DAC
2521  *****************************************************************************/
2522 static void
2523 nv50_dac_dpms(struct drm_encoder *encoder, int mode)
2524 {
2525         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2526         struct nv50_disp *disp = nv50_disp(encoder->dev);
2527         struct {
2528                 struct nv50_disp_mthd_v1 base;
2529                 struct nv50_disp_dac_pwr_v0 pwr;
2530         } args = {
2531                 .base.version = 1,
2532                 .base.method = NV50_DISP_MTHD_V1_DAC_PWR,
2533                 .base.hasht  = nv_encoder->dcb->hasht,
2534                 .base.hashm  = nv_encoder->dcb->hashm,
2535                 .pwr.state = 1,
2536                 .pwr.data  = 1,
2537                 .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND &&
2538                               mode != DRM_MODE_DPMS_OFF),
2539                 .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY &&
2540                               mode != DRM_MODE_DPMS_OFF),
2541         };
2542
2543         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2544 }
2545
2546 static void
2547 nv50_dac_disable(struct drm_encoder *encoder)
2548 {
2549         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2550         struct nv50_mast *mast = nv50_mast(encoder->dev);
2551         const int or = nv_encoder->or;
2552         u32 *push;
2553
2554         if (nv_encoder->crtc) {
2555                 push = evo_wait(mast, 4);
2556                 if (push) {
2557                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2558                                 evo_mthd(push, 0x0400 + (or * 0x080), 1);
2559                                 evo_data(push, 0x00000000);
2560                         } else {
2561                                 evo_mthd(push, 0x0180 + (or * 0x020), 1);
2562                                 evo_data(push, 0x00000000);
2563                         }
2564                         evo_kick(push, mast);
2565                 }
2566         }
2567
2568         nv_encoder->crtc = NULL;
2569 }
2570
2571 static void
2572 nv50_dac_enable(struct drm_encoder *encoder)
2573 {
2574         struct nv50_mast *mast = nv50_mast(encoder->dev);
2575         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2576         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2577         struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
2578         u32 *push;
2579
2580         push = evo_wait(mast, 8);
2581         if (push) {
2582                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2583                         u32 syncs = 0x00000000;
2584
2585                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2586                                 syncs |= 0x00000001;
2587                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2588                                 syncs |= 0x00000002;
2589
2590                         evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
2591                         evo_data(push, 1 << nv_crtc->index);
2592                         evo_data(push, syncs);
2593                 } else {
2594                         u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
2595                         u32 syncs = 0x00000001;
2596
2597                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2598                                 syncs |= 0x00000008;
2599                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2600                                 syncs |= 0x00000010;
2601
2602                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2603                                 magic |= 0x00000001;
2604
2605                         evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
2606                         evo_data(push, syncs);
2607                         evo_data(push, magic);
2608                         evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
2609                         evo_data(push, 1 << nv_crtc->index);
2610                 }
2611
2612                 evo_kick(push, mast);
2613         }
2614
2615         nv_encoder->crtc = encoder->crtc;
2616 }
2617
2618 static enum drm_connector_status
2619 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2620 {
2621         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2622         struct nv50_disp *disp = nv50_disp(encoder->dev);
2623         struct {
2624                 struct nv50_disp_mthd_v1 base;
2625                 struct nv50_disp_dac_load_v0 load;
2626         } args = {
2627                 .base.version = 1,
2628                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
2629                 .base.hasht  = nv_encoder->dcb->hasht,
2630                 .base.hashm  = nv_encoder->dcb->hashm,
2631         };
2632         int ret;
2633
2634         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
2635         if (args.load.data == 0)
2636                 args.load.data = 340;
2637
2638         ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
2639         if (ret || !args.load.load)
2640                 return connector_status_disconnected;
2641
2642         return connector_status_connected;
2643 }
2644
2645 static const struct drm_encoder_helper_funcs
2646 nv50_dac_help = {
2647         .dpms = nv50_dac_dpms,
2648         .atomic_check = nv50_outp_atomic_check,
2649         .enable = nv50_dac_enable,
2650         .disable = nv50_dac_disable,
2651         .detect = nv50_dac_detect
2652 };
2653
2654 static void
2655 nv50_dac_destroy(struct drm_encoder *encoder)
2656 {
2657         drm_encoder_cleanup(encoder);
2658         kfree(encoder);
2659 }
2660
2661 static const struct drm_encoder_funcs
2662 nv50_dac_func = {
2663         .destroy = nv50_dac_destroy,
2664 };
2665
2666 static int
2667 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
2668 {
2669         struct nouveau_drm *drm = nouveau_drm(connector->dev);
2670         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
2671         struct nvkm_i2c_bus *bus;
2672         struct nouveau_encoder *nv_encoder;
2673         struct drm_encoder *encoder;
2674         int type = DRM_MODE_ENCODER_DAC;
2675
2676         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2677         if (!nv_encoder)
2678                 return -ENOMEM;
2679         nv_encoder->dcb = dcbe;
2680         nv_encoder->or = ffs(dcbe->or) - 1;
2681
2682         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
2683         if (bus)
2684                 nv_encoder->i2c = &bus->i2c;
2685
2686         encoder = to_drm_encoder(nv_encoder);
2687         encoder->possible_crtcs = dcbe->heads;
2688         encoder->possible_clones = 0;
2689         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
2690                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
2691         drm_encoder_helper_add(encoder, &nv50_dac_help);
2692
2693         drm_mode_connector_attach_encoder(connector, encoder);
2694         return 0;
2695 }
2696
2697 /******************************************************************************
2698  * Audio
2699  *****************************************************************************/
2700 static void
2701 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
2702 {
2703         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2704         struct nv50_disp *disp = nv50_disp(encoder->dev);
2705         struct {
2706                 struct nv50_disp_mthd_v1 base;
2707                 struct nv50_disp_sor_hda_eld_v0 eld;
2708         } args = {
2709                 .base.version = 1,
2710                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
2711                 .base.hasht   = nv_encoder->dcb->hasht,
2712                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
2713                                 (0x0100 << nv_crtc->index),
2714         };
2715
2716         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2717 }
2718
2719 static void
2720 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
2721 {
2722         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2723         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2724         struct nouveau_connector *nv_connector;
2725         struct nv50_disp *disp = nv50_disp(encoder->dev);
2726         struct __packed {
2727                 struct {
2728                         struct nv50_disp_mthd_v1 mthd;
2729                         struct nv50_disp_sor_hda_eld_v0 eld;
2730                 } base;
2731                 u8 data[sizeof(nv_connector->base.eld)];
2732         } args = {
2733                 .base.mthd.version = 1,
2734                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
2735                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
2736                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
2737                                      (0x0100 << nv_crtc->index),
2738         };
2739
2740         nv_connector = nouveau_encoder_connector_get(nv_encoder);
2741         if (!drm_detect_monitor_audio(nv_connector->edid))
2742                 return;
2743
2744         drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
2745         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
2746
2747         nvif_mthd(disp->disp, 0, &args,
2748                   sizeof(args.base) + drm_eld_size(args.data));
2749 }
2750
2751 /******************************************************************************
2752  * HDMI
2753  *****************************************************************************/
2754 static void
2755 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
2756 {
2757         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2758         struct nv50_disp *disp = nv50_disp(encoder->dev);
2759         struct {
2760                 struct nv50_disp_mthd_v1 base;
2761                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
2762         } args = {
2763                 .base.version = 1,
2764                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
2765                 .base.hasht  = nv_encoder->dcb->hasht,
2766                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
2767                                (0x0100 << nv_crtc->index),
2768         };
2769
2770         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2771 }
2772
2773 static void
2774 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
2775 {
2776         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2777         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2778         struct nv50_disp *disp = nv50_disp(encoder->dev);
2779         struct {
2780                 struct nv50_disp_mthd_v1 base;
2781                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
2782         } args = {
2783                 .base.version = 1,
2784                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
2785                 .base.hasht  = nv_encoder->dcb->hasht,
2786                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
2787                                (0x0100 << nv_crtc->index),
2788                 .pwr.state = 1,
2789                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
2790         };
2791         struct nouveau_connector *nv_connector;
2792         u32 max_ac_packet;
2793
2794         nv_connector = nouveau_encoder_connector_get(nv_encoder);
2795         if (!drm_detect_hdmi_monitor(nv_connector->edid))
2796                 return;
2797
2798         max_ac_packet  = mode->htotal - mode->hdisplay;
2799         max_ac_packet -= args.pwr.rekey;
2800         max_ac_packet -= 18; /* constant from tegra */
2801         args.pwr.max_ac_packet = max_ac_packet / 32;
2802
2803         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2804         nv50_audio_enable(encoder, mode);
2805 }
2806
2807 /******************************************************************************
2808  * MST
2809  *****************************************************************************/
2810 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
2811 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
2812 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
2813
2814 struct nv50_mstm {
2815         struct nouveau_encoder *outp;
2816
2817         struct drm_dp_mst_topology_mgr mgr;
2818         struct nv50_msto *msto[4];
2819
2820         bool modified;
2821 };
2822
2823 struct nv50_mstc {
2824         struct nv50_mstm *mstm;
2825         struct drm_dp_mst_port *port;
2826         struct drm_connector connector;
2827
2828         struct drm_display_mode *native;
2829         struct edid *edid;
2830
2831         int pbn;
2832 };
2833
2834 struct nv50_msto {
2835         struct drm_encoder encoder;
2836
2837         struct nv50_head *head;
2838         struct nv50_mstc *mstc;
2839         bool disabled;
2840 };
2841
2842 static struct drm_dp_payload *
2843 nv50_msto_payload(struct nv50_msto *msto)
2844 {
2845         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2846         struct nv50_mstc *mstc = msto->mstc;
2847         struct nv50_mstm *mstm = mstc->mstm;
2848         int vcpi = mstc->port->vcpi.vcpi, i;
2849
2850         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
2851         for (i = 0; i < mstm->mgr.max_payloads; i++) {
2852                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
2853                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
2854                           mstm->outp->base.base.name, i, payload->vcpi,
2855                           payload->start_slot, payload->num_slots);
2856         }
2857
2858         for (i = 0; i < mstm->mgr.max_payloads; i++) {
2859                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
2860                 if (payload->vcpi == vcpi)
2861                         return payload;
2862         }
2863
2864         return NULL;
2865 }
2866
2867 static void
2868 nv50_msto_cleanup(struct nv50_msto *msto)
2869 {
2870         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2871         struct nv50_mstc *mstc = msto->mstc;
2872         struct nv50_mstm *mstm = mstc->mstm;
2873
2874         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
2875         if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto))
2876                 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
2877         if (msto->disabled) {
2878                 msto->mstc = NULL;
2879                 msto->head = NULL;
2880                 msto->disabled = false;
2881         }
2882 }
2883
2884 static void
2885 nv50_msto_prepare(struct nv50_msto *msto)
2886 {
2887         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2888         struct nv50_mstc *mstc = msto->mstc;
2889         struct nv50_mstm *mstm = mstc->mstm;
2890         struct {
2891                 struct nv50_disp_mthd_v1 base;
2892                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
2893         } args = {
2894                 .base.version = 1,
2895                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
2896                 .base.hasht  = mstm->outp->dcb->hasht,
2897                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
2898                                (0x0100 << msto->head->base.index),
2899         };
2900
2901         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
2902         if (mstc->port && mstc->port->vcpi.vcpi > 0) {
2903                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
2904                 if (payload) {
2905                         args.vcpi.start_slot = payload->start_slot;
2906                         args.vcpi.num_slots = payload->num_slots;
2907                         args.vcpi.pbn = mstc->port->vcpi.pbn;
2908                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
2909                 }
2910         }
2911
2912         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
2913                   msto->encoder.name, msto->head->base.base.name,
2914                   args.vcpi.start_slot, args.vcpi.num_slots,
2915                   args.vcpi.pbn, args.vcpi.aligned_pbn);
2916         nvif_mthd(&drm->display->disp, 0, &args, sizeof(args));
2917 }
2918
2919 static int
2920 nv50_msto_atomic_check(struct drm_encoder *encoder,
2921                        struct drm_crtc_state *crtc_state,
2922                        struct drm_connector_state *conn_state)
2923 {
2924         struct nv50_mstc *mstc = nv50_mstc(conn_state->connector);
2925         struct nv50_mstm *mstm = mstc->mstm;
2926         int bpp = conn_state->connector->display_info.bpc * 3;
2927         int slots;
2928
2929         mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp);
2930
2931         slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
2932         if (slots < 0)
2933                 return slots;
2934
2935         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
2936                                            mstc->native);
2937 }
2938
2939 static void
2940 nv50_msto_enable(struct drm_encoder *encoder)
2941 {
2942         struct nv50_head *head = nv50_head(encoder->crtc);
2943         struct nv50_msto *msto = nv50_msto(encoder);
2944         struct nv50_mstc *mstc = NULL;
2945         struct nv50_mstm *mstm = NULL;
2946         struct drm_connector *connector;
2947         u8 proto, depth;
2948         int slots;
2949         bool r;
2950
2951         drm_for_each_connector(connector, encoder->dev) {
2952                 if (connector->state->best_encoder == &msto->encoder) {
2953                         mstc = nv50_mstc(connector);
2954                         mstm = mstc->mstm;
2955                         break;
2956                 }
2957         }
2958
2959         if (WARN_ON(!mstc))
2960                 return;
2961
2962         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, &slots);
2963         WARN_ON(!r);
2964
2965         if (mstm->outp->dcb->sorconf.link & 1)
2966                 proto = 0x8;
2967         else
2968                 proto = 0x9;
2969
2970         switch (mstc->connector.display_info.bpc) {
2971         case  6: depth = 0x2; break;
2972         case  8: depth = 0x5; break;
2973         case 10:
2974         default: depth = 0x6; break;
2975         }
2976
2977         mstm->outp->update(mstm->outp, head->base.index,
2978                            &head->base.base.state->adjusted_mode, proto, depth);
2979
2980         msto->head = head;
2981         msto->mstc = mstc;
2982         mstm->modified = true;
2983 }
2984
2985 static void
2986 nv50_msto_disable(struct drm_encoder *encoder)
2987 {
2988         struct nv50_msto *msto = nv50_msto(encoder);
2989         struct nv50_mstc *mstc = msto->mstc;
2990         struct nv50_mstm *mstm = mstc->mstm;
2991
2992         if (mstc->port)
2993                 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
2994
2995         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
2996         mstm->modified = true;
2997         msto->disabled = true;
2998 }
2999
3000 static const struct drm_encoder_helper_funcs
3001 nv50_msto_help = {
3002         .disable = nv50_msto_disable,
3003         .enable = nv50_msto_enable,
3004         .atomic_check = nv50_msto_atomic_check,
3005 };
3006
3007 static void
3008 nv50_msto_destroy(struct drm_encoder *encoder)
3009 {
3010         struct nv50_msto *msto = nv50_msto(encoder);
3011         drm_encoder_cleanup(&msto->encoder);
3012         kfree(msto);
3013 }
3014
3015 static const struct drm_encoder_funcs
3016 nv50_msto = {
3017         .destroy = nv50_msto_destroy,
3018 };
3019
3020 static int
3021 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
3022               struct nv50_msto **pmsto)
3023 {
3024         struct nv50_msto *msto;
3025         int ret;
3026
3027         if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
3028                 return -ENOMEM;
3029
3030         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
3031                                DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
3032         if (ret) {
3033                 kfree(*pmsto);
3034                 *pmsto = NULL;
3035                 return ret;
3036         }
3037
3038         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
3039         msto->encoder.possible_crtcs = heads;
3040         return 0;
3041 }
3042
3043 static struct drm_encoder *
3044 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
3045                               struct drm_connector_state *connector_state)
3046 {
3047         struct nv50_head *head = nv50_head(connector_state->crtc);
3048         struct nv50_mstc *mstc = nv50_mstc(connector);
3049         if (mstc->port) {
3050                 struct nv50_mstm *mstm = mstc->mstm;
3051                 return &mstm->msto[head->base.index]->encoder;
3052         }
3053         return NULL;
3054 }
3055
3056 static struct drm_encoder *
3057 nv50_mstc_best_encoder(struct drm_connector *connector)
3058 {
3059         struct nv50_mstc *mstc = nv50_mstc(connector);
3060         if (mstc->port) {
3061                 struct nv50_mstm *mstm = mstc->mstm;
3062                 return &mstm->msto[0]->encoder;
3063         }
3064         return NULL;
3065 }
3066
3067 static enum drm_mode_status
3068 nv50_mstc_mode_valid(struct drm_connector *connector,
3069                      struct drm_display_mode *mode)
3070 {
3071         return MODE_OK;
3072 }
3073
3074 static int
3075 nv50_mstc_get_modes(struct drm_connector *connector)
3076 {
3077         struct nv50_mstc *mstc = nv50_mstc(connector);
3078         int ret = 0;
3079
3080         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
3081         drm_mode_connector_update_edid_property(&mstc->connector, mstc->edid);
3082         if (mstc->edid) {
3083                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
3084                 drm_edid_to_eld(&mstc->connector, mstc->edid);
3085         }
3086
3087         if (!mstc->connector.display_info.bpc)
3088                 mstc->connector.display_info.bpc = 8;
3089
3090         if (mstc->native)
3091                 drm_mode_destroy(mstc->connector.dev, mstc->native);
3092         mstc->native = nouveau_conn_native_mode(&mstc->connector);
3093         return ret;
3094 }
3095
3096 static const struct drm_connector_helper_funcs
3097 nv50_mstc_help = {
3098         .get_modes = nv50_mstc_get_modes,
3099         .mode_valid = nv50_mstc_mode_valid,
3100         .best_encoder = nv50_mstc_best_encoder,
3101         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
3102 };
3103
3104 static enum drm_connector_status
3105 nv50_mstc_detect(struct drm_connector *connector, bool force)
3106 {
3107         struct nv50_mstc *mstc = nv50_mstc(connector);
3108         if (!mstc->port)
3109                 return connector_status_disconnected;
3110         return drm_dp_mst_detect_port(connector, mstc->port->mgr, mstc->port);
3111 }
3112
3113 static void
3114 nv50_mstc_destroy(struct drm_connector *connector)
3115 {
3116         struct nv50_mstc *mstc = nv50_mstc(connector);
3117         drm_connector_cleanup(&mstc->connector);
3118         kfree(mstc);
3119 }
3120
3121 static const struct drm_connector_funcs
3122 nv50_mstc = {
3123         .dpms = drm_atomic_helper_connector_dpms,
3124         .reset = nouveau_conn_reset,
3125         .detect = nv50_mstc_detect,
3126         .fill_modes = drm_helper_probe_single_connector_modes,
3127         .set_property = drm_atomic_helper_connector_set_property,
3128         .destroy = nv50_mstc_destroy,
3129         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
3130         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
3131         .atomic_set_property = nouveau_conn_atomic_set_property,
3132         .atomic_get_property = nouveau_conn_atomic_get_property,
3133 };
3134
3135 static int
3136 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
3137               const char *path, struct nv50_mstc **pmstc)
3138 {
3139         struct drm_device *dev = mstm->outp->base.base.dev;
3140         struct nv50_mstc *mstc;
3141         int ret, i;
3142
3143         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
3144                 return -ENOMEM;
3145         mstc->mstm = mstm;
3146         mstc->port = port;
3147
3148         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
3149                                  DRM_MODE_CONNECTOR_DisplayPort);
3150         if (ret) {
3151                 kfree(*pmstc);
3152                 *pmstc = NULL;
3153                 return ret;
3154         }
3155
3156         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
3157
3158         mstc->connector.funcs->reset(&mstc->connector);
3159         nouveau_conn_attach_properties(&mstc->connector);
3160
3161         for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto; i++)
3162                 drm_mode_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
3163
3164         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
3165         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
3166         drm_mode_connector_set_path_property(&mstc->connector, path);
3167         return 0;
3168 }
3169
3170 static void
3171 nv50_mstm_cleanup(struct nv50_mstm *mstm)
3172 {
3173         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
3174         struct drm_encoder *encoder;
3175         int ret;
3176
3177         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
3178         ret = drm_dp_check_act_status(&mstm->mgr);
3179
3180         ret = drm_dp_update_payload_part2(&mstm->mgr);
3181
3182         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
3183                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
3184                         struct nv50_msto *msto = nv50_msto(encoder);
3185                         struct nv50_mstc *mstc = msto->mstc;
3186                         if (mstc && mstc->mstm == mstm)
3187                                 nv50_msto_cleanup(msto);
3188                 }
3189         }
3190
3191         mstm->modified = false;
3192 }
3193
3194 static void
3195 nv50_mstm_prepare(struct nv50_mstm *mstm)
3196 {
3197         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
3198         struct drm_encoder *encoder;
3199         int ret;
3200
3201         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
3202         ret = drm_dp_update_payload_part1(&mstm->mgr);
3203
3204         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
3205                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
3206                         struct nv50_msto *msto = nv50_msto(encoder);
3207                         struct nv50_mstc *mstc = msto->mstc;
3208                         if (mstc && mstc->mstm == mstm)
3209                                 nv50_msto_prepare(msto);
3210                 }
3211         }
3212 }
3213
3214 static void
3215 nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr)
3216 {
3217         struct nv50_mstm *mstm = nv50_mstm(mgr);
3218         drm_kms_helper_hotplug_event(mstm->outp->base.base.dev);
3219 }
3220
3221 static void
3222 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
3223                             struct drm_connector *connector)
3224 {
3225         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3226         struct nv50_mstc *mstc = nv50_mstc(connector);
3227
3228         drm_connector_unregister(&mstc->connector);
3229
3230         drm_modeset_lock_all(drm->dev);
3231         drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
3232         mstc->port = NULL;
3233         drm_modeset_unlock_all(drm->dev);
3234
3235         drm_connector_unreference(&mstc->connector);
3236 }
3237
3238 static void
3239 nv50_mstm_register_connector(struct drm_connector *connector)
3240 {
3241         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3242
3243         drm_modeset_lock_all(drm->dev);
3244         drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
3245         drm_modeset_unlock_all(drm->dev);
3246
3247         drm_connector_register(connector);
3248 }
3249
3250 static struct drm_connector *
3251 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
3252                         struct drm_dp_mst_port *port, const char *path)
3253 {
3254         struct nv50_mstm *mstm = nv50_mstm(mgr);
3255         struct nv50_mstc *mstc;
3256         int ret;
3257
3258         ret = nv50_mstc_new(mstm, port, path, &mstc);
3259         if (ret) {
3260                 if (mstc)
3261                         mstc->connector.funcs->destroy(&mstc->connector);
3262                 return NULL;
3263         }
3264
3265         return &mstc->connector;
3266 }
3267
3268 static const struct drm_dp_mst_topology_cbs
3269 nv50_mstm = {
3270         .add_connector = nv50_mstm_add_connector,
3271         .register_connector = nv50_mstm_register_connector,
3272         .destroy_connector = nv50_mstm_destroy_connector,
3273         .hotplug = nv50_mstm_hotplug,
3274 };
3275
3276 void
3277 nv50_mstm_service(struct nv50_mstm *mstm)
3278 {
3279         struct drm_dp_aux *aux = mstm->mgr.aux;
3280         bool handled = true;
3281         int ret;
3282         u8 esi[8] = {};
3283
3284         while (handled) {
3285                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
3286                 if (ret != 8) {
3287                         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
3288                         return;
3289                 }
3290
3291                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
3292                 if (!handled)
3293                         break;
3294
3295                 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
3296         }
3297 }
3298
3299 void
3300 nv50_mstm_remove(struct nv50_mstm *mstm)
3301 {
3302         if (mstm)
3303                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
3304 }
3305
3306 static int
3307 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
3308 {
3309         struct nouveau_encoder *outp = mstm->outp;
3310         struct {
3311                 struct nv50_disp_mthd_v1 base;
3312                 struct nv50_disp_sor_dp_mst_link_v0 mst;
3313         } args = {
3314                 .base.version = 1,
3315                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
3316                 .base.hasht = outp->dcb->hasht,
3317                 .base.hashm = outp->dcb->hashm,
3318                 .mst.state = state,
3319         };
3320         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
3321         struct nvif_object *disp = &drm->display->disp;
3322         int ret;
3323
3324         if (dpcd >= 0x12) {
3325                 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CTRL, &dpcd);
3326                 if (ret < 0)
3327                         return ret;
3328
3329                 dpcd &= ~DP_MST_EN;
3330                 if (state)
3331                         dpcd |= DP_MST_EN;
3332
3333                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, dpcd);
3334                 if (ret < 0)
3335                         return ret;
3336         }
3337
3338         return nvif_mthd(disp, 0, &args, sizeof(args));
3339 }
3340
3341 int
3342 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
3343 {
3344         int ret, state = 0;
3345
3346         if (!mstm)
3347                 return 0;
3348
3349         if (dpcd[0] >= 0x12) {
3350                 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CAP, &dpcd[1]);
3351                 if (ret < 0)
3352                         return ret;
3353
3354                 if (!(dpcd[1] & DP_MST_CAP))
3355                         dpcd[0] = 0x11;
3356                 else
3357                         state = allow;
3358         }
3359
3360         ret = nv50_mstm_enable(mstm, dpcd[0], state);
3361         if (ret)
3362                 return ret;
3363
3364         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, state);
3365         if (ret)
3366                 return nv50_mstm_enable(mstm, dpcd[0], 0);
3367
3368         return mstm->mgr.mst_state;
3369 }
3370
3371 static void
3372 nv50_mstm_fini(struct nv50_mstm *mstm)
3373 {
3374         if (mstm && mstm->mgr.mst_state)
3375                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
3376 }
3377
3378 static void
3379 nv50_mstm_init(struct nv50_mstm *mstm)
3380 {
3381         if (mstm && mstm->mgr.mst_state)
3382                 drm_dp_mst_topology_mgr_resume(&mstm->mgr);
3383 }
3384
3385 static void
3386 nv50_mstm_del(struct nv50_mstm **pmstm)
3387 {
3388         struct nv50_mstm *mstm = *pmstm;
3389         if (mstm) {
3390                 kfree(*pmstm);
3391                 *pmstm = NULL;
3392         }
3393 }
3394
3395 static int
3396 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
3397               int conn_base_id, struct nv50_mstm **pmstm)
3398 {
3399         const int max_payloads = hweight8(outp->dcb->heads);
3400         struct drm_device *dev = outp->base.base.dev;
3401         struct nv50_mstm *mstm;
3402         int ret, i;
3403         u8 dpcd;
3404
3405         /* This is a workaround for some monitors not functioning
3406          * correctly in MST mode on initial module load.  I think
3407          * some bad interaction with the VBIOS may be responsible.
3408          *
3409          * A good ol' off and on again seems to work here ;)
3410          */
3411         ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
3412         if (ret >= 0 && dpcd >= 0x12)
3413                 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
3414
3415         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
3416                 return -ENOMEM;
3417         mstm->outp = outp;
3418         mstm->mgr.cbs = &nv50_mstm;
3419
3420         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
3421                                            max_payloads, conn_base_id);
3422         if (ret)
3423                 return ret;
3424
3425         for (i = 0; i < max_payloads; i++) {
3426                 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
3427                                     i, &mstm->msto[i]);
3428                 if (ret)
3429                         return ret;
3430         }
3431
3432         return 0;
3433 }
3434
3435 /******************************************************************************
3436  * SOR
3437  *****************************************************************************/
3438 static void
3439 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
3440 {
3441         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3442         struct nv50_disp *disp = nv50_disp(encoder->dev);
3443         struct {
3444                 struct nv50_disp_mthd_v1 base;
3445                 struct nv50_disp_sor_pwr_v0 pwr;
3446         } args = {
3447                 .base.version = 1,
3448                 .base.method = NV50_DISP_MTHD_V1_SOR_PWR,
3449                 .base.hasht  = nv_encoder->dcb->hasht,
3450                 .base.hashm  = nv_encoder->dcb->hashm,
3451                 .pwr.state = mode == DRM_MODE_DPMS_ON,
3452         };
3453
3454         nvif_mthd(disp->disp, 0, &args, sizeof(args));
3455 }
3456
3457 static void
3458 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
3459                 struct drm_display_mode *mode, u8 proto, u8 depth)
3460 {
3461         struct nv50_dmac *core = &nv50_mast(nv_encoder->base.base.dev)->base;
3462         u32 *push;
3463
3464         if (!mode) {
3465                 nv_encoder->ctrl &= ~BIT(head);
3466                 if (!(nv_encoder->ctrl & 0x0000000f))
3467                         nv_encoder->ctrl = 0;
3468         } else {
3469                 nv_encoder->ctrl |= proto << 8;
3470                 nv_encoder->ctrl |= BIT(head);
3471         }
3472
3473         if ((push = evo_wait(core, 6))) {
3474                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
3475                         if (mode) {
3476                                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3477                                         nv_encoder->ctrl |= 0x00001000;
3478                                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3479                                         nv_encoder->ctrl |= 0x00002000;
3480                                 nv_encoder->ctrl |= depth << 16;
3481                         }
3482                         evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
3483                 } else {
3484                         if (mode) {
3485                                 u32 magic = 0x31ec6000 | (head << 25);
3486                                 u32 syncs = 0x00000001;
3487                                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3488                                         syncs |= 0x00000008;
3489                                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3490                                         syncs |= 0x00000010;
3491                                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
3492                                         magic |= 0x00000001;
3493
3494                                 evo_mthd(push, 0x0404 + (head * 0x300), 2);
3495                                 evo_data(push, syncs | (depth << 6));
3496                                 evo_data(push, magic);
3497                         }
3498                         evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
3499                 }
3500                 evo_data(push, nv_encoder->ctrl);
3501                 evo_kick(push, core);
3502         }
3503 }
3504
3505 static void
3506 nv50_sor_disable(struct drm_encoder *encoder)
3507 {
3508         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3509         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
3510
3511         nv_encoder->crtc = NULL;
3512
3513         if (nv_crtc) {
3514                 struct nvkm_i2c_aux *aux = nv_encoder->aux;
3515                 u8 pwr;
3516
3517                 if (aux) {
3518                         int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
3519                         if (ret == 0) {
3520                                 pwr &= ~DP_SET_POWER_MASK;
3521                                 pwr |=  DP_SET_POWER_D3;
3522                                 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
3523                         }
3524                 }
3525
3526                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
3527                 nv50_audio_disable(encoder, nv_crtc);
3528                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
3529         }
3530 }
3531
3532 static void
3533 nv50_sor_enable(struct drm_encoder *encoder)
3534 {
3535         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3536         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
3537         struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
3538         struct {
3539                 struct nv50_disp_mthd_v1 base;
3540                 struct nv50_disp_sor_lvds_script_v0 lvds;
3541         } lvds = {
3542                 .base.version = 1,
3543                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
3544                 .base.hasht   = nv_encoder->dcb->hasht,
3545                 .base.hashm   = nv_encoder->dcb->hashm,
3546         };
3547         struct nv50_disp *disp = nv50_disp(encoder->dev);
3548         struct drm_device *dev = encoder->dev;
3549         struct nouveau_drm *drm = nouveau_drm(dev);
3550         struct nouveau_connector *nv_connector;
3551         struct nvbios *bios = &drm->vbios;
3552         u8 proto = 0xf;
3553         u8 depth = 0x0;
3554
3555         nv_connector = nouveau_encoder_connector_get(nv_encoder);
3556         nv_encoder->crtc = encoder->crtc;
3557
3558         switch (nv_encoder->dcb->type) {
3559         case DCB_OUTPUT_TMDS:
3560                 if (nv_encoder->dcb->sorconf.link & 1) {
3561                         proto = 0x1;
3562                         /* Only enable dual-link if:
3563                          *  - Need to (i.e. rate > 165MHz)
3564                          *  - DCB says we can
3565                          *  - Not an HDMI monitor, since there's no dual-link
3566                          *    on HDMI.
3567                          */
3568                         if (mode->clock >= 165000 &&
3569                             nv_encoder->dcb->duallink_possible &&
3570                             !drm_detect_hdmi_monitor(nv_connector->edid))
3571                                 proto |= 0x4;
3572                 } else {
3573                         proto = 0x2;
3574                 }
3575
3576                 nv50_hdmi_enable(&nv_encoder->base.base, mode);
3577                 break;
3578         case DCB_OUTPUT_LVDS:
3579                 proto = 0x0;
3580
3581                 if (bios->fp_no_ddc) {
3582                         if (bios->fp.dual_link)
3583                                 lvds.lvds.script |= 0x0100;
3584                         if (bios->fp.if_is_24bit)
3585                                 lvds.lvds.script |= 0x0200;
3586                 } else {
3587                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
3588                                 if (((u8 *)nv_connector->edid)[121] == 2)
3589                                         lvds.lvds.script |= 0x0100;
3590                         } else
3591                         if (mode->clock >= bios->fp.duallink_transition_clk) {
3592                                 lvds.lvds.script |= 0x0100;
3593                         }
3594
3595                         if (lvds.lvds.script & 0x0100) {
3596                                 if (bios->fp.strapless_is_24bit & 2)
3597                                         lvds.lvds.script |= 0x0200;
3598                         } else {
3599                                 if (bios->fp.strapless_is_24bit & 1)
3600                                         lvds.lvds.script |= 0x0200;
3601                         }
3602
3603                         if (nv_connector->base.display_info.bpc == 8)
3604                                 lvds.lvds.script |= 0x0200;
3605                 }
3606
3607                 nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds));
3608                 break;
3609         case DCB_OUTPUT_DP:
3610                 if (nv_connector->base.display_info.bpc == 6)
3611                         depth = 0x2;
3612                 else
3613                 if (nv_connector->base.display_info.bpc == 8)
3614                         depth = 0x5;
3615                 else
3616                         depth = 0x6;
3617
3618                 if (nv_encoder->dcb->sorconf.link & 1)
3619                         proto = 0x8;
3620                 else
3621                         proto = 0x9;
3622
3623                 nv50_audio_enable(encoder, mode);
3624                 break;
3625         default:
3626                 BUG();
3627                 break;
3628         }
3629
3630         nv_encoder->update(nv_encoder, nv_crtc->index, mode, proto, depth);
3631 }
3632
3633 static const struct drm_encoder_helper_funcs
3634 nv50_sor_help = {
3635         .dpms = nv50_sor_dpms,
3636         .atomic_check = nv50_outp_atomic_check,
3637         .enable = nv50_sor_enable,
3638         .disable = nv50_sor_disable,
3639 };
3640
3641 static void
3642 nv50_sor_destroy(struct drm_encoder *encoder)
3643 {
3644         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3645         nv50_mstm_del(&nv_encoder->dp.mstm);
3646         drm_encoder_cleanup(encoder);
3647         kfree(encoder);
3648 }
3649
3650 static const struct drm_encoder_funcs
3651 nv50_sor_func = {
3652         .destroy = nv50_sor_destroy,
3653 };
3654
3655 static int
3656 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
3657 {
3658         struct nouveau_connector *nv_connector = nouveau_connector(connector);
3659         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3660         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
3661         struct nouveau_encoder *nv_encoder;
3662         struct drm_encoder *encoder;
3663         int type, ret;
3664
3665         switch (dcbe->type) {
3666         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
3667         case DCB_OUTPUT_TMDS:
3668         case DCB_OUTPUT_DP:
3669         default:
3670                 type = DRM_MODE_ENCODER_TMDS;
3671                 break;
3672         }
3673
3674         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
3675         if (!nv_encoder)
3676                 return -ENOMEM;
3677         nv_encoder->dcb = dcbe;
3678         nv_encoder->or = ffs(dcbe->or) - 1;
3679         nv_encoder->update = nv50_sor_update;
3680
3681         encoder = to_drm_encoder(nv_encoder);
3682         encoder->possible_crtcs = dcbe->heads;
3683         encoder->possible_clones = 0;
3684         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
3685                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
3686         drm_encoder_helper_add(encoder, &nv50_sor_help);
3687
3688         drm_mode_connector_attach_encoder(connector, encoder);
3689
3690         if (dcbe->type == DCB_OUTPUT_DP) {
3691                 struct nvkm_i2c_aux *aux =
3692                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
3693                 if (aux) {
3694                         nv_encoder->i2c = &aux->i2c;
3695                         nv_encoder->aux = aux;
3696                 }
3697
3698                 /*TODO: Use DP Info Table to check for support. */
3699                 if (nv50_disp(encoder->dev)->disp->oclass >= GF110_DISP) {
3700                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
3701                                             nv_connector->base.base.id,
3702                                             &nv_encoder->dp.mstm);
3703                         if (ret)
3704                                 return ret;
3705                 }
3706         } else {
3707                 struct nvkm_i2c_bus *bus =
3708                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
3709                 if (bus)
3710                         nv_encoder->i2c = &bus->i2c;
3711         }
3712
3713         return 0;
3714 }
3715
3716 /******************************************************************************
3717  * PIOR
3718  *****************************************************************************/
3719 static void
3720 nv50_pior_dpms(struct drm_encoder *encoder, int mode)
3721 {
3722         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3723         struct nv50_disp *disp = nv50_disp(encoder->dev);
3724         struct {
3725                 struct nv50_disp_mthd_v1 base;
3726                 struct nv50_disp_pior_pwr_v0 pwr;
3727         } args = {
3728                 .base.version = 1,
3729                 .base.method = NV50_DISP_MTHD_V1_PIOR_PWR,
3730                 .base.hasht  = nv_encoder->dcb->hasht,
3731                 .base.hashm  = nv_encoder->dcb->hashm,
3732                 .pwr.state = mode == DRM_MODE_DPMS_ON,
3733                 .pwr.type = nv_encoder->dcb->type,
3734         };
3735
3736         nvif_mthd(disp->disp, 0, &args, sizeof(args));
3737 }
3738
3739 static int
3740 nv50_pior_atomic_check(struct drm_encoder *encoder,
3741                        struct drm_crtc_state *crtc_state,
3742                        struct drm_connector_state *conn_state)
3743 {
3744         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
3745         if (ret)
3746                 return ret;
3747         crtc_state->adjusted_mode.clock *= 2;
3748         return 0;
3749 }
3750
3751 static void
3752 nv50_pior_disable(struct drm_encoder *encoder)
3753 {
3754         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3755         struct nv50_mast *mast = nv50_mast(encoder->dev);
3756         const int or = nv_encoder->or;
3757         u32 *push;
3758
3759         if (nv_encoder->crtc) {
3760                 push = evo_wait(mast, 4);
3761                 if (push) {
3762                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
3763                                 evo_mthd(push, 0x0700 + (or * 0x040), 1);
3764                                 evo_data(push, 0x00000000);
3765                         }
3766                         evo_kick(push, mast);
3767                 }
3768         }
3769
3770         nv_encoder->crtc = NULL;
3771 }
3772
3773 static void
3774 nv50_pior_enable(struct drm_encoder *encoder)
3775 {
3776         struct nv50_mast *mast = nv50_mast(encoder->dev);
3777         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3778         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
3779         struct nouveau_connector *nv_connector;
3780         struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
3781         u8 owner = 1 << nv_crtc->index;
3782         u8 proto, depth;
3783         u32 *push;
3784
3785         nv_connector = nouveau_encoder_connector_get(nv_encoder);
3786         switch (nv_connector->base.display_info.bpc) {
3787         case 10: depth = 0x6; break;
3788         case  8: depth = 0x5; break;
3789         case  6: depth = 0x2; break;
3790         default: depth = 0x0; break;
3791         }
3792
3793         switch (nv_encoder->dcb->type) {
3794         case DCB_OUTPUT_TMDS:
3795         case DCB_OUTPUT_DP:
3796                 proto = 0x0;
3797                 break;
3798         default:
3799                 BUG();
3800                 break;
3801         }
3802
3803         push = evo_wait(mast, 8);
3804         if (push) {
3805                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
3806                         u32 ctrl = (depth << 16) | (proto << 8) | owner;
3807                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3808                                 ctrl |= 0x00001000;
3809                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3810                                 ctrl |= 0x00002000;
3811                         evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
3812                         evo_data(push, ctrl);
3813                 }
3814
3815                 evo_kick(push, mast);
3816         }
3817
3818         nv_encoder->crtc = encoder->crtc;
3819 }
3820
3821 static const struct drm_encoder_helper_funcs
3822 nv50_pior_help = {
3823         .dpms = nv50_pior_dpms,
3824         .atomic_check = nv50_pior_atomic_check,
3825         .enable = nv50_pior_enable,
3826         .disable = nv50_pior_disable,
3827 };
3828
3829 static void
3830 nv50_pior_destroy(struct drm_encoder *encoder)
3831 {
3832         drm_encoder_cleanup(encoder);
3833         kfree(encoder);
3834 }
3835
3836 static const struct drm_encoder_funcs
3837 nv50_pior_func = {
3838         .destroy = nv50_pior_destroy,
3839 };
3840
3841 static int
3842 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
3843 {
3844         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3845         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
3846         struct nvkm_i2c_bus *bus = NULL;
3847         struct nvkm_i2c_aux *aux = NULL;
3848         struct i2c_adapter *ddc;
3849         struct nouveau_encoder *nv_encoder;
3850         struct drm_encoder *encoder;
3851         int type;
3852
3853         switch (dcbe->type) {
3854         case DCB_OUTPUT_TMDS:
3855                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
3856                 ddc  = bus ? &bus->i2c : NULL;
3857                 type = DRM_MODE_ENCODER_TMDS;
3858                 break;
3859         case DCB_OUTPUT_DP:
3860                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
3861                 ddc  = aux ? &aux->i2c : NULL;
3862                 type = DRM_MODE_ENCODER_TMDS;
3863                 break;
3864         default:
3865                 return -ENODEV;
3866         }
3867
3868         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
3869         if (!nv_encoder)
3870                 return -ENOMEM;
3871         nv_encoder->dcb = dcbe;
3872         nv_encoder->or = ffs(dcbe->or) - 1;
3873         nv_encoder->i2c = ddc;
3874         nv_encoder->aux = aux;
3875
3876         encoder = to_drm_encoder(nv_encoder);
3877         encoder->possible_crtcs = dcbe->heads;
3878         encoder->possible_clones = 0;
3879         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
3880                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
3881         drm_encoder_helper_add(encoder, &nv50_pior_help);
3882
3883         drm_mode_connector_attach_encoder(connector, encoder);
3884         return 0;
3885 }
3886
3887 /******************************************************************************
3888  * Atomic
3889  *****************************************************************************/
3890
3891 static void
3892 nv50_disp_atomic_commit_core(struct nouveau_drm *drm, u32 interlock)
3893 {
3894         struct nv50_disp *disp = nv50_disp(drm->dev);
3895         struct nv50_dmac *core = &disp->mast.base;
3896         struct nv50_mstm *mstm;
3897         struct drm_encoder *encoder;
3898         u32 *push;
3899
3900         NV_ATOMIC(drm, "commit core %08x\n", interlock);
3901
3902         drm_for_each_encoder(encoder, drm->dev) {
3903                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
3904                         mstm = nouveau_encoder(encoder)->dp.mstm;
3905                         if (mstm && mstm->modified)
3906                                 nv50_mstm_prepare(mstm);
3907                 }
3908         }
3909
3910         if ((push = evo_wait(core, 5))) {
3911                 evo_mthd(push, 0x0084, 1);
3912                 evo_data(push, 0x80000000);
3913                 evo_mthd(push, 0x0080, 2);
3914                 evo_data(push, interlock);
3915                 evo_data(push, 0x00000000);
3916                 nouveau_bo_wr32(disp->sync, 0, 0x00000000);
3917                 evo_kick(push, core);
3918                 if (nvif_msec(&drm->client.device, 2000ULL,
3919                         if (nouveau_bo_rd32(disp->sync, 0))
3920                                 break;
3921                         usleep_range(1, 2);
3922                 ) < 0)
3923                         NV_ERROR(drm, "EVO timeout\n");
3924         }
3925
3926         drm_for_each_encoder(encoder, drm->dev) {
3927                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
3928                         mstm = nouveau_encoder(encoder)->dp.mstm;
3929                         if (mstm && mstm->modified)
3930                                 nv50_mstm_cleanup(mstm);
3931                 }
3932         }
3933 }
3934
3935 static void
3936 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
3937 {
3938         struct drm_device *dev = state->dev;
3939         struct drm_crtc_state *crtc_state;
3940         struct drm_crtc *crtc;
3941         struct drm_plane_state *plane_state;
3942         struct drm_plane *plane;
3943         struct nouveau_drm *drm = nouveau_drm(dev);
3944         struct nv50_disp *disp = nv50_disp(dev);
3945         struct nv50_atom *atom = nv50_atom(state);
3946         struct nv50_outp_atom *outp, *outt;
3947         u32 interlock_core = 0;
3948         u32 interlock_chan = 0;
3949         int i;
3950
3951         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
3952         drm_atomic_helper_wait_for_fences(dev, state, false);
3953         drm_atomic_helper_wait_for_dependencies(state);
3954         drm_atomic_helper_update_legacy_modeset_state(dev, state);
3955
3956         if (atom->lock_core)
3957                 mutex_lock(&disp->mutex);
3958
3959         /* Disable head(s). */
3960         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3961                 struct nv50_head_atom *asyh = nv50_head_atom(crtc->state);
3962                 struct nv50_head *head = nv50_head(crtc);
3963
3964                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
3965                           asyh->clr.mask, asyh->set.mask);
3966
3967                 if (asyh->clr.mask) {
3968                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
3969                         interlock_core |= 1;
3970                 }
3971         }
3972
3973         /* Disable plane(s). */
3974         for_each_plane_in_state(state, plane, plane_state, i) {
3975                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state);
3976                 struct nv50_wndw *wndw = nv50_wndw(plane);
3977
3978                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
3979                           asyw->clr.mask, asyw->set.mask);
3980                 if (!asyw->clr.mask)
3981                         continue;
3982
3983                 interlock_chan |= nv50_wndw_flush_clr(wndw, interlock_core,
3984                                                       atom->flush_disable,
3985                                                       asyw);
3986         }
3987
3988         /* Disable output path(s). */
3989         list_for_each_entry(outp, &atom->outp, head) {
3990                 const struct drm_encoder_helper_funcs *help;
3991                 struct drm_encoder *encoder;
3992
3993                 encoder = outp->encoder;
3994                 help = encoder->helper_private;
3995
3996                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
3997                           outp->clr.mask, outp->set.mask);
3998
3999                 if (outp->clr.mask) {
4000                         help->disable(encoder);
4001                         interlock_core |= 1;
4002                         if (outp->flush_disable) {
4003                                 nv50_disp_atomic_commit_core(drm, interlock_chan);
4004                                 interlock_core = 0;
4005                                 interlock_chan = 0;
4006                         }
4007                 }
4008         }
4009
4010         /* Flush disable. */
4011         if (interlock_core) {
4012                 if (atom->flush_disable) {
4013                         nv50_disp_atomic_commit_core(drm, interlock_chan);
4014                         interlock_core = 0;
4015                         interlock_chan = 0;
4016                 }
4017         }
4018
4019         /* Update output path(s). */
4020         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
4021                 const struct drm_encoder_helper_funcs *help;
4022                 struct drm_encoder *encoder;
4023
4024                 encoder = outp->encoder;
4025                 help = encoder->helper_private;
4026
4027                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
4028                           outp->set.mask, outp->clr.mask);
4029
4030                 if (outp->set.mask) {
4031                         help->enable(encoder);
4032                         interlock_core = 1;
4033                 }
4034
4035                 list_del(&outp->head);
4036                 kfree(outp);
4037         }
4038
4039         /* Update head(s). */
4040         for_each_crtc_in_state(state, crtc, crtc_state, i) {
4041                 struct nv50_head_atom *asyh = nv50_head_atom(crtc->state);
4042                 struct nv50_head *head = nv50_head(crtc);
4043
4044                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
4045                           asyh->set.mask, asyh->clr.mask);
4046
4047                 if (asyh->set.mask) {
4048                         nv50_head_flush_set(head, asyh);
4049                         interlock_core = 1;
4050                 }
4051         }
4052
4053         for_each_crtc_in_state(state, crtc, crtc_state, i) {
4054                 if (crtc->state->event)
4055                         drm_crtc_vblank_get(crtc);
4056         }
4057
4058         /* Update plane(s). */
4059         for_each_plane_in_state(state, plane, plane_state, i) {
4060                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state);
4061                 struct nv50_wndw *wndw = nv50_wndw(plane);
4062
4063                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
4064                           asyw->set.mask, asyw->clr.mask);
4065                 if ( !asyw->set.mask &&
4066                     (!asyw->clr.mask || atom->flush_disable))
4067                         continue;
4068
4069                 interlock_chan |= nv50_wndw_flush_set(wndw, interlock_core, asyw);
4070         }
4071
4072         /* Flush update. */
4073         if (interlock_core) {
4074                 if (!interlock_chan && atom->state.legacy_cursor_update) {
4075                         u32 *push = evo_wait(&disp->mast, 2);
4076                         if (push) {
4077                                 evo_mthd(push, 0x0080, 1);
4078                                 evo_data(push, 0x00000000);
4079                                 evo_kick(push, &disp->mast);
4080                         }
4081                 } else {
4082                         nv50_disp_atomic_commit_core(drm, interlock_chan);
4083                 }
4084         }
4085
4086         if (atom->lock_core)
4087                 mutex_unlock(&disp->mutex);
4088
4089         /* Wait for HW to signal completion. */
4090         for_each_plane_in_state(state, plane, plane_state, i) {
4091                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state);
4092                 struct nv50_wndw *wndw = nv50_wndw(plane);
4093                 int ret = nv50_wndw_wait_armed(wndw, asyw);
4094                 if (ret)
4095                         NV_ERROR(drm, "%s: timeout\n", plane->name);
4096         }
4097
4098         for_each_crtc_in_state(state, crtc, crtc_state, i) {
4099                 if (crtc->state->event) {
4100                         unsigned long flags;
4101                         /* Get correct count/ts if racing with vblank irq */
4102                         drm_accurate_vblank_count(crtc);
4103                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
4104                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
4105                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4106                         crtc->state->event = NULL;
4107                         drm_crtc_vblank_put(crtc);
4108                 }
4109         }
4110
4111         drm_atomic_helper_commit_hw_done(state);
4112         drm_atomic_helper_cleanup_planes(dev, state);
4113         drm_atomic_helper_commit_cleanup_done(state);
4114         drm_atomic_state_put(state);
4115 }
4116
4117 static void
4118 nv50_disp_atomic_commit_work(struct work_struct *work)
4119 {
4120         struct drm_atomic_state *state =
4121                 container_of(work, typeof(*state), commit_work);
4122         nv50_disp_atomic_commit_tail(state);
4123 }
4124
4125 static int
4126 nv50_disp_atomic_commit(struct drm_device *dev,
4127                         struct drm_atomic_state *state, bool nonblock)
4128 {
4129         struct nouveau_drm *drm = nouveau_drm(dev);
4130         struct nv50_disp *disp = nv50_disp(dev);
4131         struct drm_plane_state *plane_state;
4132         struct drm_plane *plane;
4133         struct drm_crtc *crtc;
4134         bool active = false;
4135         int ret, i;
4136
4137         ret = pm_runtime_get_sync(dev->dev);
4138         if (ret < 0 && ret != -EACCES)
4139                 return ret;
4140
4141         ret = drm_atomic_helper_setup_commit(state, nonblock);
4142         if (ret)
4143                 goto done;
4144
4145         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
4146
4147         ret = drm_atomic_helper_prepare_planes(dev, state);
4148         if (ret)
4149                 goto done;
4150
4151         if (!nonblock) {
4152                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
4153                 if (ret)
4154                         goto done;
4155         }
4156
4157         for_each_plane_in_state(state, plane, plane_state, i) {
4158                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane_state);
4159                 struct nv50_wndw *wndw = nv50_wndw(plane);
4160                 if (asyw->set.image) {
4161                         asyw->ntfy.handle = wndw->dmac->sync.handle;
4162                         asyw->ntfy.offset = wndw->ntfy;
4163                         asyw->ntfy.awaken = false;
4164                         asyw->set.ntfy = true;
4165                         nouveau_bo_wr32(disp->sync, wndw->ntfy / 4, 0x00000000);
4166                         wndw->ntfy ^= 0x10;
4167                 }
4168         }
4169
4170         drm_atomic_helper_swap_state(state, true);
4171         drm_atomic_state_get(state);
4172
4173         if (nonblock)
4174                 queue_work(system_unbound_wq, &state->commit_work);
4175         else
4176                 nv50_disp_atomic_commit_tail(state);
4177
4178         drm_for_each_crtc(crtc, dev) {
4179                 if (crtc->state->enable) {
4180                         if (!drm->have_disp_power_ref) {
4181                                 drm->have_disp_power_ref = true;
4182                                 return ret;
4183                         }
4184                         active = true;
4185                         break;
4186                 }
4187         }
4188
4189         if (!active && drm->have_disp_power_ref) {
4190                 pm_runtime_put_autosuspend(dev->dev);
4191                 drm->have_disp_power_ref = false;
4192         }
4193
4194 done:
4195         pm_runtime_put_autosuspend(dev->dev);
4196         return ret;
4197 }
4198
4199 static struct nv50_outp_atom *
4200 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
4201 {
4202         struct nv50_outp_atom *outp;
4203
4204         list_for_each_entry(outp, &atom->outp, head) {
4205                 if (outp->encoder == encoder)
4206                         return outp;
4207         }
4208
4209         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
4210         if (!outp)
4211                 return ERR_PTR(-ENOMEM);
4212
4213         list_add(&outp->head, &atom->outp);
4214         outp->encoder = encoder;
4215         return outp;
4216 }
4217
4218 static int
4219 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
4220                                 struct drm_connector *connector)
4221 {
4222         struct drm_encoder *encoder = connector->state->best_encoder;
4223         struct drm_crtc_state *crtc_state;
4224         struct drm_crtc *crtc;
4225         struct nv50_outp_atom *outp;
4226
4227         if (!(crtc = connector->state->crtc))
4228                 return 0;
4229
4230         crtc_state = drm_atomic_get_existing_crtc_state(&atom->state, crtc);
4231         if (crtc->state->active && drm_atomic_crtc_needs_modeset(crtc_state)) {
4232                 outp = nv50_disp_outp_atomic_add(atom, encoder);
4233                 if (IS_ERR(outp))
4234                         return PTR_ERR(outp);
4235
4236                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
4237                         outp->flush_disable = true;
4238                         atom->flush_disable = true;
4239                 }
4240                 outp->clr.ctrl = true;
4241                 atom->lock_core = true;
4242         }
4243
4244         return 0;
4245 }
4246
4247 static int
4248 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
4249                                 struct drm_connector_state *connector_state)
4250 {
4251         struct drm_encoder *encoder = connector_state->best_encoder;
4252         struct drm_crtc_state *crtc_state;
4253         struct drm_crtc *crtc;
4254         struct nv50_outp_atom *outp;
4255
4256         if (!(crtc = connector_state->crtc))
4257                 return 0;
4258
4259         crtc_state = drm_atomic_get_existing_crtc_state(&atom->state, crtc);
4260         if (crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state)) {
4261                 outp = nv50_disp_outp_atomic_add(atom, encoder);
4262                 if (IS_ERR(outp))
4263                         return PTR_ERR(outp);
4264
4265                 outp->set.ctrl = true;
4266                 atom->lock_core = true;
4267         }
4268
4269         return 0;
4270 }
4271
4272 static int
4273 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
4274 {
4275         struct nv50_atom *atom = nv50_atom(state);
4276         struct drm_connector_state *connector_state;
4277         struct drm_connector *connector;
4278         int ret, i;
4279
4280         ret = drm_atomic_helper_check(dev, state);
4281         if (ret)
4282                 return ret;
4283
4284         for_each_connector_in_state(state, connector, connector_state, i) {
4285                 ret = nv50_disp_outp_atomic_check_clr(atom, connector);
4286                 if (ret)
4287                         return ret;
4288
4289                 ret = nv50_disp_outp_atomic_check_set(atom, connector_state);
4290                 if (ret)
4291                         return ret;
4292         }
4293
4294         return 0;
4295 }
4296
4297 static void
4298 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
4299 {
4300         struct nv50_atom *atom = nv50_atom(state);
4301         struct nv50_outp_atom *outp, *outt;
4302
4303         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
4304                 list_del(&outp->head);
4305                 kfree(outp);
4306         }
4307
4308         drm_atomic_state_default_clear(state);
4309 }
4310
4311 static void
4312 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
4313 {
4314         struct nv50_atom *atom = nv50_atom(state);
4315         drm_atomic_state_default_release(&atom->state);
4316         kfree(atom);
4317 }
4318
4319 static struct drm_atomic_state *
4320 nv50_disp_atomic_state_alloc(struct drm_device *dev)
4321 {
4322         struct nv50_atom *atom;
4323         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
4324             drm_atomic_state_init(dev, &atom->state) < 0) {
4325                 kfree(atom);
4326                 return NULL;
4327         }
4328         INIT_LIST_HEAD(&atom->outp);
4329         return &atom->state;
4330 }
4331
4332 static const struct drm_mode_config_funcs
4333 nv50_disp_func = {
4334         .fb_create = nouveau_user_framebuffer_create,
4335         .output_poll_changed = nouveau_fbcon_output_poll_changed,
4336         .atomic_check = nv50_disp_atomic_check,
4337         .atomic_commit = nv50_disp_atomic_commit,
4338         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
4339         .atomic_state_clear = nv50_disp_atomic_state_clear,
4340         .atomic_state_free = nv50_disp_atomic_state_free,
4341 };
4342
4343 /******************************************************************************
4344  * Init
4345  *****************************************************************************/
4346
4347 void
4348 nv50_display_fini(struct drm_device *dev)
4349 {
4350         struct nouveau_encoder *nv_encoder;
4351         struct drm_encoder *encoder;
4352         struct drm_plane *plane;
4353
4354         drm_for_each_plane(plane, dev) {
4355                 struct nv50_wndw *wndw = nv50_wndw(plane);
4356                 if (plane->funcs != &nv50_wndw)
4357                         continue;
4358                 nv50_wndw_fini(wndw);
4359         }
4360
4361         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4362                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
4363                         nv_encoder = nouveau_encoder(encoder);
4364                         nv50_mstm_fini(nv_encoder->dp.mstm);
4365                 }
4366         }
4367 }
4368
4369 int
4370 nv50_display_init(struct drm_device *dev)
4371 {
4372         struct drm_encoder *encoder;
4373         struct drm_plane *plane;
4374         struct drm_crtc *crtc;
4375         u32 *push;
4376
4377         push = evo_wait(nv50_mast(dev), 32);
4378         if (!push)
4379                 return -EBUSY;
4380
4381         evo_mthd(push, 0x0088, 1);
4382         evo_data(push, nv50_mast(dev)->base.sync.handle);
4383         evo_kick(push, nv50_mast(dev));
4384
4385         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4386                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
4387                         const struct drm_encoder_helper_funcs *help;
4388                         struct nouveau_encoder *nv_encoder;
4389
4390                         nv_encoder = nouveau_encoder(encoder);
4391                         help = encoder->helper_private;
4392                         if (help && help->dpms)
4393                                 help->dpms(encoder, DRM_MODE_DPMS_ON);
4394
4395                         nv50_mstm_init(nv_encoder->dp.mstm);
4396                 }
4397         }
4398
4399         drm_for_each_crtc(crtc, dev) {
4400                 nv50_head_lut_load(crtc);
4401         }
4402
4403         drm_for_each_plane(plane, dev) {
4404                 struct nv50_wndw *wndw = nv50_wndw(plane);
4405                 if (plane->funcs != &nv50_wndw)
4406                         continue;
4407                 nv50_wndw_init(wndw);
4408         }
4409
4410         return 0;
4411 }
4412
4413 void
4414 nv50_display_destroy(struct drm_device *dev)
4415 {
4416         struct nv50_disp *disp = nv50_disp(dev);
4417
4418         nv50_dmac_destroy(&disp->mast.base, disp->disp);
4419
4420         nouveau_bo_unmap(disp->sync);
4421         if (disp->sync)
4422                 nouveau_bo_unpin(disp->sync);
4423         nouveau_bo_ref(NULL, &disp->sync);
4424
4425         nouveau_display(dev)->priv = NULL;
4426         kfree(disp);
4427 }
4428
4429 MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
4430 static int nouveau_atomic = 0;
4431 module_param_named(atomic, nouveau_atomic, int, 0400);
4432
4433 int
4434 nv50_display_create(struct drm_device *dev)
4435 {
4436         struct nvif_device *device = &nouveau_drm(dev)->client.device;
4437         struct nouveau_drm *drm = nouveau_drm(dev);
4438         struct dcb_table *dcb = &drm->vbios.dcb;
4439         struct drm_connector *connector, *tmp;
4440         struct nv50_disp *disp;
4441         struct dcb_output *dcbe;
4442         int crtcs, ret, i;
4443
4444         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
4445         if (!disp)
4446                 return -ENOMEM;
4447
4448         mutex_init(&disp->mutex);
4449
4450         nouveau_display(dev)->priv = disp;
4451         nouveau_display(dev)->dtor = nv50_display_destroy;
4452         nouveau_display(dev)->init = nv50_display_init;
4453         nouveau_display(dev)->fini = nv50_display_fini;
4454         disp->disp = &nouveau_display(dev)->disp;
4455         dev->mode_config.funcs = &nv50_disp_func;
4456         if (nouveau_atomic)
4457                 dev->driver->driver_features |= DRIVER_ATOMIC;
4458
4459         /* small shared memory area we use for notifiers and semaphores */
4460         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
4461                              0, 0x0000, NULL, NULL, &disp->sync);
4462         if (!ret) {
4463                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
4464                 if (!ret) {
4465                         ret = nouveau_bo_map(disp->sync);
4466                         if (ret)
4467                                 nouveau_bo_unpin(disp->sync);
4468                 }
4469                 if (ret)
4470                         nouveau_bo_ref(NULL, &disp->sync);
4471         }
4472
4473         if (ret)
4474                 goto out;
4475
4476         /* allocate master evo channel */
4477         ret = nv50_core_create(device, disp->disp, disp->sync->bo.offset,
4478                               &disp->mast);
4479         if (ret)
4480                 goto out;
4481
4482         /* create crtc objects to represent the hw heads */
4483         if (disp->disp->oclass >= GF110_DISP)
4484                 crtcs = nvif_rd32(&device->object, 0x022448);
4485         else
4486                 crtcs = 2;
4487
4488         for (i = 0; i < crtcs; i++) {
4489                 ret = nv50_head_create(dev, i);
4490                 if (ret)
4491                         goto out;
4492         }
4493
4494         /* create encoder/connector objects based on VBIOS DCB table */
4495         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
4496                 connector = nouveau_connector_create(dev, dcbe->connector);
4497                 if (IS_ERR(connector))
4498                         continue;
4499
4500                 if (dcbe->location == DCB_LOC_ON_CHIP) {
4501                         switch (dcbe->type) {
4502                         case DCB_OUTPUT_TMDS:
4503                         case DCB_OUTPUT_LVDS:
4504                         case DCB_OUTPUT_DP:
4505                                 ret = nv50_sor_create(connector, dcbe);
4506                                 break;
4507                         case DCB_OUTPUT_ANALOG:
4508                                 ret = nv50_dac_create(connector, dcbe);
4509                                 break;
4510                         default:
4511                                 ret = -ENODEV;
4512                                 break;
4513                         }
4514                 } else {
4515                         ret = nv50_pior_create(connector, dcbe);
4516                 }
4517
4518                 if (ret) {
4519                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
4520                                      dcbe->location, dcbe->type,
4521                                      ffs(dcbe->or) - 1, ret);
4522                         ret = 0;
4523                 }
4524         }
4525
4526         /* cull any connectors we created that don't have an encoder */
4527         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
4528                 if (connector->encoder_ids[0])
4529                         continue;
4530
4531                 NV_WARN(drm, "%s has no encoders, removing\n",
4532                         connector->name);
4533                 connector->funcs->destroy(connector);
4534         }
4535
4536 out:
4537         if (ret)
4538                 nv50_display_destroy(dev);
4539         return ret;
4540 }