drivers/gpu/drm/nouveau/nv04_dfp.c

   1 /*
   2  * Copyright 2003 NVIDIA, Corporation
   3  * Copyright 2006 Dave Airlie
   4  * Copyright 2007 Maarten Maathuis
   5  * Copyright 2007-2009 Stuart Bennett
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  23  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm_crtc_helper.h"
  29
  30 #include "nouveau_drv.h"
  31 #include "nouveau_encoder.h"
  32 #include "nouveau_connector.h"
  33 #include "nouveau_crtc.h"
  34 #include "nouveau_hw.h"
  35 #include "nvreg.h"
  36
  37 #define FP_TG_CONTROL_ON  (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |        \
  38                            NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS |         \
  39                            NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS)
  40 #define FP_TG_CONTROL_OFF (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE |    \
  41                            NV_PRAMDAC_FP_TG_CONTROL_HSYNC_DISABLE |     \
  42                            NV_PRAMDAC_FP_TG_CONTROL_VSYNC_DISABLE)
  43
  44 static inline bool is_fpc_off(uint32_t fpc)
  45 {
  46         return ((fpc & (FP_TG_CONTROL_ON | FP_TG_CONTROL_OFF)) ==
  47                         FP_TG_CONTROL_OFF);
  48 }
  49
  50 int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent)
  51 {
  52         /* special case of nv_read_tmds to find crtc associated with an output.
  53          * this does not give a correct answer for off-chip dvi, but there's no
  54          * use for such an answer anyway
  55          */
  56         int ramdac = (dcbent->or & OUTPUT_C) >> 2;
  57
  58         NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL,
  59         NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | 0x4);
  60         return ((NVReadRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA) & 0x8) >> 3) ^ ramdac;
  61 }
  62
  63 void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
  64                         int head, bool dl)
  65 {
  66         /* The BIOS scripts don't do this for us, sadly
  67          * Luckily we do know the values ;-)
  68          *
  69          * head < 0 indicates we wish to force a setting with the overrideval
  70          * (for VT restore etc.)
  71          */
  72
  73         int ramdac = (dcbent->or & OUTPUT_C) >> 2;
  74         uint8_t tmds04 = 0x80;
  75
  76         if (head != ramdac)
  77                 tmds04 = 0x88;
  78
  79         if (dcbent->type == OUTPUT_LVDS)
  80                 tmds04 |= 0x01;
  81
  82         nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04);
  83
  84         if (dl) /* dual link */
  85                 nv_write_tmds(dev, dcbent->or, 1, 0x04, tmds04 ^ 0x08);
  86 }
  87
  88 void nv04_dfp_disable(struct drm_device *dev, int head)
  89 {
  90         struct drm_nouveau_private *dev_priv = dev->dev_private;
  91         struct nv04_crtc_reg *crtcstate = dev_priv->mode_reg.crtc_reg;
  92
  93         if (NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL) &
  94             FP_TG_CONTROL_ON) {
  95                 /* digital remnants must be cleaned before new crtc
  96                  * values programmed.  delay is time for the vga stuff
  97                  * to realise it's in control again
  98                  */
  99                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
 100                               FP_TG_CONTROL_OFF);
 101                 msleep(50);
 102         }
 103         /* don't inadvertently turn it on when state written later */
 104         crtcstate[head].fp_control = FP_TG_CONTROL_OFF;
 105 }
 106
 107 void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode)
 108 {
 109         struct drm_device *dev = encoder->dev;
 110         struct drm_nouveau_private *dev_priv = dev->dev_private;
 111         struct drm_crtc *crtc;
 112         struct nouveau_crtc *nv_crtc;
 113         uint32_t *fpc;
 114
 115         if (mode == DRM_MODE_DPMS_ON) {
 116                 nv_crtc = nouveau_crtc(encoder->crtc);
 117                 fpc = &dev_priv->mode_reg.crtc_reg[nv_crtc->index].fp_control;
 118
 119                 if (is_fpc_off(*fpc)) {
 120                         /* using saved value is ok, as (is_digital && dpms_on &&
 121                          * fp_control==OFF) is (at present) *only* true when
 122                          * fpc's most recent change was by below "off" code
 123                          */
 124                         *fpc = nv_crtc->dpms_saved_fp_control;
 125                 }
 126
 127                 nv_crtc->fp_users |= 1 << nouveau_encoder(encoder)->dcb->index;
 128                 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_FP_TG_CONTROL, *fpc);
 129         } else {
 130                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 131                         nv_crtc = nouveau_crtc(crtc);
 132                         fpc = &dev_priv->mode_reg.crtc_reg[nv_crtc->index].fp_control;
 133
 134                         nv_crtc->fp_users &= ~(1 << nouveau_encoder(encoder)->dcb->index);
 135                         if (!is_fpc_off(*fpc) && !nv_crtc->fp_users) {
 136                                 nv_crtc->dpms_saved_fp_control = *fpc;
 137                                 /* cut the FP output */
 138                                 *fpc &= ~FP_TG_CONTROL_ON;
 139                                 *fpc |= FP_TG_CONTROL_OFF;
 140                                 NVWriteRAMDAC(dev, nv_crtc->index,
 141                                               NV_PRAMDAC_FP_TG_CONTROL, *fpc);
 142                         }
 143                 }
 144         }
 145 }
 146
 147 static bool nv04_dfp_mode_fixup(struct drm_encoder *encoder,
 148                                 struct drm_display_mode *mode,
 149                                 struct drm_display_mode *adjusted_mode)
 150 {
 151         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 152         struct nouveau_connector *nv_connector = nouveau_encoder_connector_get(nv_encoder);
 153
 154         /* For internal panels and gpu scaling on DVI we need the native mode */
 155         if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
 156                 if (!nv_connector->native_mode)
 157                         return false;
 158                 nv_encoder->mode = *nv_connector->native_mode;
 159                 adjusted_mode->clock = nv_connector->native_mode->clock;
 160         } else {
 161                 nv_encoder->mode = *adjusted_mode;
 162         }
 163
 164         return true;
 165 }
 166
 167 static void nv04_dfp_prepare_sel_clk(struct drm_device *dev,
 168                                      struct nouveau_encoder *nv_encoder, int head)
 169 {
 170         struct drm_nouveau_private *dev_priv = dev->dev_private;
 171         struct nv04_mode_state *state = &dev_priv->mode_reg;
 172         uint32_t bits1618 = nv_encoder->dcb->or & OUTPUT_A ? 0x10000 : 0x40000;
 173
 174         if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP)
 175                 return;
 176
 177         /* SEL_CLK is only used on the primary ramdac
 178          * It toggles spread spectrum PLL output and sets the bindings of PLLs
 179          * to heads on digital outputs
 180          */
 181         if (head)
 182                 state->sel_clk |= bits1618;
 183         else
 184                 state->sel_clk &= ~bits1618;
 185
 186         /* nv30:
 187          *      bit 0           NVClk spread spectrum on/off
 188          *      bit 2           MemClk spread spectrum on/off
 189          *      bit 4           PixClk1 spread spectrum on/off toggle
 190          *      bit 6           PixClk2 spread spectrum on/off toggle
 191          *
 192          * nv40 (observations from bios behaviour and mmio traces):
 193          *      bits 4&6        as for nv30
 194          *      bits 5&7        head dependent as for bits 4&6, but do not appear with 4&6;
 195          *                      maybe a different spread mode
 196          *      bits 8&10       seen on dual-link dvi outputs, purpose unknown (set by POST scripts)
 197          *      The logic behind turning spread spectrum on/off in the first place,
 198          *      and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table
 199          *      entry has the necessary info)
 200          */
 201         if (nv_encoder->dcb->type == OUTPUT_LVDS && dev_priv->saved_reg.sel_clk & 0xf0) {
 202                 int shift = (dev_priv->saved_reg.sel_clk & 0x50) ? 0 : 1;
 203
 204                 state->sel_clk &= ~0xf0;
 205                 state->sel_clk |= (head ? 0x40 : 0x10) << shift;
 206         }
 207 }
 208
 209 static void nv04_dfp_prepare(struct drm_encoder *encoder)
 210 {
 211         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 212         struct drm_encoder_helper_funcs *helper = encoder->helper_private;
 213         struct drm_device *dev = encoder->dev;
 214         struct drm_nouveau_private *dev_priv = dev->dev_private;
 215         int head = nouveau_crtc(encoder->crtc)->index;
 216         struct nv04_crtc_reg *crtcstate = dev_priv->mode_reg.crtc_reg;
 217         uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX];
 218         uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX];
 219
 220         helper->dpms(encoder, DRM_MODE_DPMS_OFF);
 221
 222         nv04_dfp_prepare_sel_clk(dev, nv_encoder, head);
 223
 224         /* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f)
 225          * at LCD__INDEX which we don't alter
 226          */
 227         if (!(*cr_lcd & 0x44)) {
 228                 *cr_lcd = 0x3;
 229
 230                 if (nv_two_heads(dev)) {
 231                         if (nv_encoder->dcb->location == DCB_LOC_ON_CHIP)
 232                                 *cr_lcd |= head ? 0x0 : 0x8;
 233                         else {
 234                                 *cr_lcd |= (nv_encoder->dcb->or << 4) & 0x30;
 235                                 if (nv_encoder->dcb->type == OUTPUT_LVDS)
 236                                         *cr_lcd |= 0x30;
 237                                 if ((*cr_lcd & 0x30) == (*cr_lcd_oth & 0x30)) {
 238                                         /* avoid being connected to both crtcs */
 239                                         *cr_lcd_oth &= ~0x30;
 240                                         NVWriteVgaCrtc(dev, head ^ 1,
 241                                                        NV_CIO_CRE_LCD__INDEX,
 242                                                        *cr_lcd_oth);
 243                                 }
 244                         }
 245                 }
 246         }
 247 }
 248
 249
 250 static void nv04_dfp_mode_set(struct drm_encoder *encoder,
 251                               struct drm_display_mode *mode,
 252                               struct drm_display_mode *adjusted_mode)
 253 {
 254         struct drm_device *dev = encoder->dev;
 255         struct drm_nouveau_private *dev_priv = dev->dev_private;
 256         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 257         struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
 258         struct nv04_crtc_reg *savep = &dev_priv->saved_reg.crtc_reg[nv_crtc->index];
 259         struct nouveau_connector *nv_connector = nouveau_crtc_connector_get(nv_crtc);
 260         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 261         struct drm_display_mode *output_mode = &nv_encoder->mode;
 262         uint32_t mode_ratio, panel_ratio;
 263
 264         NV_DEBUG_KMS(dev, "Output mode on CRTC %d:\n", nv_crtc->index);
 265         drm_mode_debug_printmodeline(output_mode);
 266
 267         /* Initialize the FP registers in this CRTC. */
 268         regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
 269         regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
 270         if (!nv_gf4_disp_arch(dev) ||
 271             (output_mode->hsync_start - output_mode->hdisplay) >=
 272                                         dev_priv->vbios.digital_min_front_porch)
 273                 regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay;
 274         else
 275                 regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - dev_priv->vbios.digital_min_front_porch - 1;
 276         regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1;
 277         regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
 278         regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew;
 279         regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1;
 280
 281         regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
 282         regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
 283         regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1;
 284         regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1;
 285         regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
 286         regp->fp_vert_regs[FP_VALID_START] = 0;
 287         regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1;
 288
 289         /* bit26: a bit seen on some g7x, no as yet discernable purpose */
 290         regp->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
 291                            (savep->fp_control & (1 << 26 | NV_PRAMDAC_FP_TG_CONTROL_READ_PROG));
 292         /* Deal with vsync/hsync polarity */
 293         /* LVDS screens do set this, but modes with +ve syncs are very rare */
 294         if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
 295                 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
 296         if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
 297                 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
 298         /* panel scaling first, as native would get set otherwise */
 299         if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE ||
 300             nv_connector->scaling_mode == DRM_MODE_SCALE_CENTER)        /* panel handles it */
 301                 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER;
 302         else if (adjusted_mode->hdisplay == output_mode->hdisplay &&
 303                  adjusted_mode->vdisplay == output_mode->vdisplay) /* native mode */
 304                 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE;
 305         else /* gpu needs to scale */
 306                 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE;
 307         if (nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
 308                 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
 309         if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP &&
 310             output_mode->clock > 165000)
 311                 regp->fp_control |= (2 << 24);
 312         if (nv_encoder->dcb->type == OUTPUT_LVDS) {
 313                 bool duallink, dummy;
 314
 315                 nouveau_bios_parse_lvds_table(dev, nv_connector->native_mode->
 316                                               clock, &duallink, &dummy);
 317                 if (duallink)
 318                         regp->fp_control |= (8 << 28);
 319         } else
 320         if (output_mode->clock > 165000)
 321                 regp->fp_control |= (8 << 28);
 322
 323         regp->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
 324                            NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
 325                            NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
 326                            NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
 327                            NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
 328                            NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
 329                            NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
 330
 331         /* We want automatic scaling */
 332         regp->fp_debug_1 = 0;
 333         /* This can override HTOTAL and VTOTAL */
 334         regp->fp_debug_2 = 0;
 335
 336         /* Use 20.12 fixed point format to avoid floats */
 337         mode_ratio = (1 << 12) * adjusted_mode->hdisplay / adjusted_mode->vdisplay;
 338         panel_ratio = (1 << 12) * output_mode->hdisplay / output_mode->vdisplay;
 339         /* if ratios are equal, SCALE_ASPECT will automatically (and correctly)
 340          * get treated the same as SCALE_FULLSCREEN */
 341         if (nv_connector->scaling_mode == DRM_MODE_SCALE_ASPECT &&
 342             mode_ratio != panel_ratio) {
 343                 uint32_t diff, scale;
 344                 bool divide_by_2 = nv_gf4_disp_arch(dev);
 345
 346                 if (mode_ratio < panel_ratio) {
 347                         /* vertical needs to expand to glass size (automatic)
 348                          * horizontal needs to be scaled at vertical scale factor
 349                          * to maintain aspect */
 350
 351                         scale = (1 << 12) * adjusted_mode->vdisplay / output_mode->vdisplay;
 352                         regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE |
 353                                            XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE);
 354
 355                         /* restrict area of screen used, horizontally */
 356                         diff = output_mode->hdisplay -
 357                                output_mode->vdisplay * mode_ratio / (1 << 12);
 358                         regp->fp_horiz_regs[FP_VALID_START] += diff / 2;
 359                         regp->fp_horiz_regs[FP_VALID_END] -= diff / 2;
 360                 }
 361
 362                 if (mode_ratio > panel_ratio) {
 363                         /* horizontal needs to expand to glass size (automatic)
 364                          * vertical needs to be scaled at horizontal scale factor
 365                          * to maintain aspect */
 366
 367                         scale = (1 << 12) * adjusted_mode->hdisplay / output_mode->hdisplay;
 368                         regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE |
 369                                            XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE);
 370
 371                         /* restrict area of screen used, vertically */
 372                         diff = output_mode->vdisplay -
 373                                (1 << 12) * output_mode->hdisplay / mode_ratio;
 374                         regp->fp_vert_regs[FP_VALID_START] += diff / 2;
 375                         regp->fp_vert_regs[FP_VALID_END] -= diff / 2;
 376                 }
 377         }
 378
 379         /* Output property. */
 380         if (nv_connector->use_dithering) {
 381                 if (dev_priv->chipset == 0x11)
 382                         regp->dither = savep->dither | 0x00010000;
 383                 else {
 384                         int i;
 385                         regp->dither = savep->dither | 0x00000001;
 386                         for (i = 0; i < 3; i++) {
 387                                 regp->dither_regs[i] = 0xe4e4e4e4;
 388                                 regp->dither_regs[i + 3] = 0x44444444;
 389                         }
 390                 }
 391         } else {
 392                 if (dev_priv->chipset != 0x11) {
 393                         /* reset them */
 394                         int i;
 395                         for (i = 0; i < 3; i++) {
 396                                 regp->dither_regs[i] = savep->dither_regs[i];
 397                                 regp->dither_regs[i + 3] = savep->dither_regs[i + 3];
 398                         }
 399                 }
 400                 regp->dither = savep->dither;
 401         }
 402
 403         regp->fp_margin_color = 0;
 404 }
 405
 406 static void nv04_dfp_commit(struct drm_encoder *encoder)
 407 {
 408         struct drm_device *dev = encoder->dev;
 409         struct drm_nouveau_private *dev_priv = dev->dev_private;
 410         struct drm_encoder_helper_funcs *helper = encoder->helper_private;
 411         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 412         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 413         struct dcb_entry *dcbe = nv_encoder->dcb;
 414         int head = nouveau_crtc(encoder->crtc)->index;
 415
 416         NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
 417                 drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base),
 418                 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
 419
 420         if (dcbe->type == OUTPUT_TMDS)
 421                 run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock);
 422         else if (dcbe->type == OUTPUT_LVDS)
 423                 call_lvds_script(dev, dcbe, head, LVDS_RESET, nv_encoder->mode.clock);
 424
 425         /* update fp_control state for any changes made by scripts,
 426          * so correct value is written at DPMS on */
 427         dev_priv->mode_reg.crtc_reg[head].fp_control =
 428                 NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
 429
 430         /* This could use refinement for flatpanels, but it should work this way */
 431         if (dev_priv->chipset < 0x44)
 432                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000);
 433         else
 434                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
 435
 436         helper->dpms(encoder, DRM_MODE_DPMS_ON);
 437
 438         NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
 439                 drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base),
 440                 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
 441 }
 442
 443 static inline bool is_powersaving_dpms(int mode)
 444 {
 445         return (mode != DRM_MODE_DPMS_ON);
 446 }
 447
 448 static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode)
 449 {
 450         struct drm_device *dev = encoder->dev;
 451         struct drm_crtc *crtc = encoder->crtc;
 452         struct drm_nouveau_private *dev_priv = dev->dev_private;
 453         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 454         bool was_powersaving = is_powersaving_dpms(nv_encoder->last_dpms);
 455
 456         if (nv_encoder->last_dpms == mode)
 457                 return;
 458         nv_encoder->last_dpms = mode;
 459
 460         NV_INFO(dev, "Setting dpms mode %d on lvds encoder (output %d)\n",
 461                      mode, nv_encoder->dcb->index);
 462
 463         if (was_powersaving && is_powersaving_dpms(mode))
 464                 return;
 465
 466         if (nv_encoder->dcb->lvdsconf.use_power_scripts) {
 467                 struct nouveau_connector *nv_connector = nouveau_encoder_connector_get(nv_encoder);
 468
 469                 /* when removing an output, crtc may not be set, but PANEL_OFF
 470                  * must still be run
 471                  */
 472                 int head = crtc ? nouveau_crtc(crtc)->index :
 473                            nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
 474
 475                 if (mode == DRM_MODE_DPMS_ON) {
 476                         if (!nv_connector->native_mode) {
 477                                 NV_ERROR(dev, "Not turning on LVDS without native mode\n");
 478                                 return;
 479                         }
 480                         call_lvds_script(dev, nv_encoder->dcb, head,
 481                                          LVDS_PANEL_ON, nv_connector->native_mode->clock);
 482                 } else
 483                         /* pxclk of 0 is fine for PANEL_OFF, and for a
 484                          * disconnected LVDS encoder there is no native_mode
 485                          */
 486                         call_lvds_script(dev, nv_encoder->dcb, head,
 487                                          LVDS_PANEL_OFF, 0);
 488         }
 489
 490         nv04_dfp_update_fp_control(encoder, mode);
 491
 492         if (mode == DRM_MODE_DPMS_ON)
 493                 nv04_dfp_prepare_sel_clk(dev, nv_encoder, nouveau_crtc(crtc)->index);
 494         else {
 495                 dev_priv->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
 496                 dev_priv->mode_reg.sel_clk &= ~0xf0;
 497         }
 498         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, dev_priv->mode_reg.sel_clk);
 499 }
 500
 501 static void nv04_tmds_dpms(struct drm_encoder *encoder, int mode)
 502 {
 503         struct drm_device *dev = encoder->dev;
 504         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 505
 506         if (nv_encoder->last_dpms == mode)
 507                 return;
 508         nv_encoder->last_dpms = mode;
 509
 510         NV_INFO(dev, "Setting dpms mode %d on tmds encoder (output %d)\n",
 511                      mode, nv_encoder->dcb->index);
 512
 513         nv04_dfp_update_fp_control(encoder, mode);
 514 }
 515
 516 static void nv04_dfp_save(struct drm_encoder *encoder)
 517 {
 518         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 519         struct drm_device *dev = encoder->dev;
 520
 521         if (nv_two_heads(dev))
 522                 nv_encoder->restore.head =
 523                         nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
 524 }
 525
 526 static void nv04_dfp_restore(struct drm_encoder *encoder)
 527 {
 528         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 529         struct drm_device *dev = encoder->dev;
 530         struct drm_nouveau_private *dev_priv = dev->dev_private;
 531         int head = nv_encoder->restore.head;
 532
 533         if (nv_encoder->dcb->type == OUTPUT_LVDS) {
 534                 struct drm_display_mode *native_mode = nouveau_encoder_connector_get(nv_encoder)->native_mode;
 535                 if (native_mode)
 536                         call_lvds_script(dev, nv_encoder->dcb, head, LVDS_PANEL_ON,
 537                                          native_mode->clock);
 538                 else
 539                         NV_ERROR(dev, "Not restoring LVDS without native mode\n");
 540
 541         } else if (nv_encoder->dcb->type == OUTPUT_TMDS) {
 542                 int clock = nouveau_hw_pllvals_to_clk
 543                                         (&dev_priv->saved_reg.crtc_reg[head].pllvals);
 544
 545                 run_tmds_table(dev, nv_encoder->dcb, head, clock);
 546         }
 547
 548         nv_encoder->last_dpms = NV_DPMS_CLEARED;
 549 }
 550
 551 static void nv04_dfp_destroy(struct drm_encoder *encoder)
 552 {
 553         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 554
 555         NV_DEBUG_KMS(encoder->dev, "\n");
 556
 557         drm_encoder_cleanup(encoder);
 558         kfree(nv_encoder);
 559 }
 560
 561 static const struct drm_encoder_helper_funcs nv04_lvds_helper_funcs = {
 562         .dpms = nv04_lvds_dpms,
 563         .save = nv04_dfp_save,
 564         .restore = nv04_dfp_restore,
 565         .mode_fixup = nv04_dfp_mode_fixup,
 566         .prepare = nv04_dfp_prepare,
 567         .commit = nv04_dfp_commit,
 568         .mode_set = nv04_dfp_mode_set,
 569         .detect = NULL,
 570 };
 571
 572 static const struct drm_encoder_helper_funcs nv04_tmds_helper_funcs = {
 573         .dpms = nv04_tmds_dpms,
 574         .save = nv04_dfp_save,
 575         .restore = nv04_dfp_restore,
 576         .mode_fixup = nv04_dfp_mode_fixup,
 577         .prepare = nv04_dfp_prepare,
 578         .commit = nv04_dfp_commit,
 579         .mode_set = nv04_dfp_mode_set,
 580         .detect = NULL,
 581 };
 582
 583 static const struct drm_encoder_funcs nv04_dfp_funcs = {
 584         .destroy = nv04_dfp_destroy,
 585 };
 586
 587 int nv04_dfp_create(struct drm_device *dev, struct dcb_entry *entry)
 588 {
 589         const struct drm_encoder_helper_funcs *helper;
 590         struct drm_encoder *encoder;
 591         struct nouveau_encoder *nv_encoder = NULL;
 592         int type;
 593
 594         switch (entry->type) {
 595         case OUTPUT_TMDS:
 596                 type = DRM_MODE_ENCODER_TMDS;
 597                 helper = &nv04_tmds_helper_funcs;
 598                 break;
 599         case OUTPUT_LVDS:
 600                 type = DRM_MODE_ENCODER_LVDS;
 601                 helper = &nv04_lvds_helper_funcs;
 602                 break;
 603         default:
 604                 return -EINVAL;
 605         }
 606
 607         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 608         if (!nv_encoder)
 609                 return -ENOMEM;
 610
 611         encoder = to_drm_encoder(nv_encoder);
 612
 613         nv_encoder->dcb = entry;
 614         nv_encoder->or = ffs(entry->or) - 1;
 615
 616         drm_encoder_init(dev, encoder, &nv04_dfp_funcs, type);
 617         drm_encoder_helper_add(encoder, helper);
 618
 619         encoder->possible_crtcs = entry->heads;
 620         encoder->possible_clones = 0;
 621
 622         return 0;
 623 }