drm/radeon: bump the UMS driver version number to indicate rv740 fix
[sfrench/cifs-2.6.git] / drivers / gpu / drm / nouveau / nouveau_mem.c
1 /*
2  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
3  * Copyright 2005 Stephane Marchesin
4  *
5  * The Weather Channel (TM) funded Tungsten Graphics to develop the
6  * initial release of the Radeon 8500 driver under the XFree86 license.
7  * This notice must be preserved.
8  *
9  * Permission is hereby granted, free of charge, to any person obtaining a
10  * copy of this software and associated documentation files (the "Software"),
11  * to deal in the Software without restriction, including without limitation
12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13  * and/or sell copies of the Software, and to permit persons to whom the
14  * Software is furnished to do so, subject to the following conditions:
15  *
16  * The above copyright notice and this permission notice (including the next
17  * paragraph) shall be included in all copies or substantial portions of the
18  * Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
23  * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26  * DEALINGS IN THE SOFTWARE.
27  *
28  * Authors:
29  *    Keith Whitwell <keith@tungstengraphics.com>
30  */
31
32
33 #include "drmP.h"
34 #include "drm.h"
35 #include "drm_sarea.h"
36 #include "nouveau_drv.h"
37
38 static struct mem_block *
39 split_block(struct mem_block *p, uint64_t start, uint64_t size,
40             struct drm_file *file_priv)
41 {
42         /* Maybe cut off the start of an existing block */
43         if (start > p->start) {
44                 struct mem_block *newblock =
45                         kmalloc(sizeof(*newblock), GFP_KERNEL);
46                 if (!newblock)
47                         goto out;
48                 newblock->start = start;
49                 newblock->size = p->size - (start - p->start);
50                 newblock->file_priv = NULL;
51                 newblock->next = p->next;
52                 newblock->prev = p;
53                 p->next->prev = newblock;
54                 p->next = newblock;
55                 p->size -= newblock->size;
56                 p = newblock;
57         }
58
59         /* Maybe cut off the end of an existing block */
60         if (size < p->size) {
61                 struct mem_block *newblock =
62                         kmalloc(sizeof(*newblock), GFP_KERNEL);
63                 if (!newblock)
64                         goto out;
65                 newblock->start = start + size;
66                 newblock->size = p->size - size;
67                 newblock->file_priv = NULL;
68                 newblock->next = p->next;
69                 newblock->prev = p;
70                 p->next->prev = newblock;
71                 p->next = newblock;
72                 p->size = size;
73         }
74
75 out:
76         /* Our block is in the middle */
77         p->file_priv = file_priv;
78         return p;
79 }
80
81 struct mem_block *
82 nouveau_mem_alloc_block(struct mem_block *heap, uint64_t size,
83                         int align2, struct drm_file *file_priv, int tail)
84 {
85         struct mem_block *p;
86         uint64_t mask = (1 << align2) - 1;
87
88         if (!heap)
89                 return NULL;
90
91         if (tail) {
92                 list_for_each_prev(p, heap) {
93                         uint64_t start = ((p->start + p->size) - size) & ~mask;
94
95                         if (p->file_priv == NULL && start >= p->start &&
96                             start + size <= p->start + p->size)
97                                 return split_block(p, start, size, file_priv);
98                 }
99         } else {
100                 list_for_each(p, heap) {
101                         uint64_t start = (p->start + mask) & ~mask;
102
103                         if (p->file_priv == NULL &&
104                             start + size <= p->start + p->size)
105                                 return split_block(p, start, size, file_priv);
106                 }
107         }
108
109         return NULL;
110 }
111
112 void nouveau_mem_free_block(struct mem_block *p)
113 {
114         p->file_priv = NULL;
115
116         /* Assumes a single contiguous range.  Needs a special file_priv in
117          * 'heap' to stop it being subsumed.
118          */
119         if (p->next->file_priv == NULL) {
120                 struct mem_block *q = p->next;
121                 p->size += q->size;
122                 p->next = q->next;
123                 p->next->prev = p;
124                 kfree(q);
125         }
126
127         if (p->prev->file_priv == NULL) {
128                 struct mem_block *q = p->prev;
129                 q->size += p->size;
130                 q->next = p->next;
131                 q->next->prev = q;
132                 kfree(p);
133         }
134 }
135
136 /* Initialize.  How to check for an uninitialized heap?
137  */
138 int nouveau_mem_init_heap(struct mem_block **heap, uint64_t start,
139                           uint64_t size)
140 {
141         struct mem_block *blocks = kmalloc(sizeof(*blocks), GFP_KERNEL);
142
143         if (!blocks)
144                 return -ENOMEM;
145
146         *heap = kmalloc(sizeof(**heap), GFP_KERNEL);
147         if (!*heap) {
148                 kfree(blocks);
149                 return -ENOMEM;
150         }
151
152         blocks->start = start;
153         blocks->size = size;
154         blocks->file_priv = NULL;
155         blocks->next = blocks->prev = *heap;
156
157         memset(*heap, 0, sizeof(**heap));
158         (*heap)->file_priv = (struct drm_file *) -1;
159         (*heap)->next = (*heap)->prev = blocks;
160         return 0;
161 }
162
163 /*
164  * Free all blocks associated with the releasing file_priv
165  */
166 void nouveau_mem_release(struct drm_file *file_priv, struct mem_block *heap)
167 {
168         struct mem_block *p;
169
170         if (!heap || !heap->next)
171                 return;
172
173         list_for_each(p, heap) {
174                 if (p->file_priv == file_priv)
175                         p->file_priv = NULL;
176         }
177
178         /* Assumes a single contiguous range.  Needs a special file_priv in
179          * 'heap' to stop it being subsumed.
180          */
181         list_for_each(p, heap) {
182                 while ((p->file_priv == NULL) &&
183                                         (p->next->file_priv == NULL) &&
184                                         (p->next != heap)) {
185                         struct mem_block *q = p->next;
186                         p->size += q->size;
187                         p->next = q->next;
188                         p->next->prev = p;
189                         kfree(q);
190                 }
191         }
192 }
193
194 /*
195  * NV10-NV40 tiling helpers
196  */
197
198 static void
199 nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
200                            uint32_t size, uint32_t pitch)
201 {
202         struct drm_nouveau_private *dev_priv = dev->dev_private;
203         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
204         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
205         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
206         struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
207
208         tile->addr = addr;
209         tile->size = size;
210         tile->used = !!pitch;
211         nouveau_fence_unref((void **)&tile->fence);
212
213         if (!pfifo->cache_flush(dev))
214                 return;
215
216         pfifo->reassign(dev, false);
217         pfifo->cache_flush(dev);
218         pfifo->cache_pull(dev, false);
219
220         nouveau_wait_for_idle(dev);
221
222         pgraph->set_region_tiling(dev, i, addr, size, pitch);
223         pfb->set_region_tiling(dev, i, addr, size, pitch);
224
225         pfifo->cache_pull(dev, true);
226         pfifo->reassign(dev, true);
227 }
228
229 struct nouveau_tile_reg *
230 nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
231                     uint32_t pitch)
232 {
233         struct drm_nouveau_private *dev_priv = dev->dev_private;
234         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
235         struct nouveau_tile_reg *tile = dev_priv->tile.reg, *found = NULL;
236         int i;
237
238         spin_lock(&dev_priv->tile.lock);
239
240         for (i = 0; i < pfb->num_tiles; i++) {
241                 if (tile[i].used)
242                         /* Tile region in use. */
243                         continue;
244
245                 if (tile[i].fence &&
246                     !nouveau_fence_signalled(tile[i].fence, NULL))
247                         /* Pending tile region. */
248                         continue;
249
250                 if (max(tile[i].addr, addr) <
251                     min(tile[i].addr + tile[i].size, addr + size))
252                         /* Kill an intersecting tile region. */
253                         nv10_mem_set_region_tiling(dev, i, 0, 0, 0);
254
255                 if (pitch && !found) {
256                         /* Free tile region. */
257                         nv10_mem_set_region_tiling(dev, i, addr, size, pitch);
258                         found = &tile[i];
259                 }
260         }
261
262         spin_unlock(&dev_priv->tile.lock);
263
264         return found;
265 }
266
267 void
268 nv10_mem_expire_tiling(struct drm_device *dev, struct nouveau_tile_reg *tile,
269                        struct nouveau_fence *fence)
270 {
271         if (fence) {
272                 /* Mark it as pending. */
273                 tile->fence = fence;
274                 nouveau_fence_ref(fence);
275         }
276
277         tile->used = false;
278 }
279
280 /*
281  * NV50 VM helpers
282  */
283 int
284 nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
285                         uint32_t flags, uint64_t phys)
286 {
287         struct drm_nouveau_private *dev_priv = dev->dev_private;
288         struct nouveau_gpuobj **pgt;
289         unsigned psz, pfl, pages;
290
291         if (virt >= dev_priv->vm_gart_base &&
292             (virt + size) < (dev_priv->vm_gart_base + dev_priv->vm_gart_size)) {
293                 psz = 12;
294                 pgt = &dev_priv->gart_info.sg_ctxdma;
295                 pfl = 0x21;
296                 virt -= dev_priv->vm_gart_base;
297         } else
298         if (virt >= dev_priv->vm_vram_base &&
299             (virt + size) < (dev_priv->vm_vram_base + dev_priv->vm_vram_size)) {
300                 psz = 16;
301                 pgt = dev_priv->vm_vram_pt;
302                 pfl = 0x01;
303                 virt -= dev_priv->vm_vram_base;
304         } else {
305                 NV_ERROR(dev, "Invalid address: 0x%16llx-0x%16llx\n",
306                          virt, virt + size - 1);
307                 return -EINVAL;
308         }
309
310         pages = size >> psz;
311
312         dev_priv->engine.instmem.prepare_access(dev, true);
313         if (flags & 0x80000000) {
314                 while (pages--) {
315                         struct nouveau_gpuobj *pt = pgt[virt >> 29];
316                         unsigned pte = ((virt & 0x1fffffffULL) >> psz) << 1;
317
318                         nv_wo32(dev, pt, pte++, 0x00000000);
319                         nv_wo32(dev, pt, pte++, 0x00000000);
320
321                         virt += (1 << psz);
322                 }
323         } else {
324                 while (pages--) {
325                         struct nouveau_gpuobj *pt = pgt[virt >> 29];
326                         unsigned pte = ((virt & 0x1fffffffULL) >> psz) << 1;
327                         unsigned offset_h = upper_32_bits(phys) & 0xff;
328                         unsigned offset_l = lower_32_bits(phys);
329
330                         nv_wo32(dev, pt, pte++, offset_l | pfl);
331                         nv_wo32(dev, pt, pte++, offset_h | flags);
332
333                         phys += (1 << psz);
334                         virt += (1 << psz);
335                 }
336         }
337         dev_priv->engine.instmem.finish_access(dev);
338
339         nv_wr32(dev, 0x100c80, 0x00050001);
340         if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
341                 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
342                 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
343                 return -EBUSY;
344         }
345
346         nv_wr32(dev, 0x100c80, 0x00000001);
347         if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
348                 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
349                 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
350                 return -EBUSY;
351         }
352
353         return 0;
354 }
355
356 void
357 nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
358 {
359         nv50_mem_vm_bind_linear(dev, virt, size, 0x80000000, 0);
360 }
361
362 /*
363  * Cleanup everything
364  */
365 void nouveau_mem_takedown(struct mem_block **heap)
366 {
367         struct mem_block *p;
368
369         if (!*heap)
370                 return;
371
372         for (p = (*heap)->next; p != *heap;) {
373                 struct mem_block *q = p;
374                 p = p->next;
375                 kfree(q);
376         }
377
378         kfree(*heap);
379         *heap = NULL;
380 }
381
382 void nouveau_mem_close(struct drm_device *dev)
383 {
384         struct drm_nouveau_private *dev_priv = dev->dev_private;
385
386         nouveau_bo_unpin(dev_priv->vga_ram);
387         nouveau_bo_ref(NULL, &dev_priv->vga_ram);
388
389         ttm_bo_device_release(&dev_priv->ttm.bdev);
390
391         nouveau_ttm_global_release(dev_priv);
392
393         if (drm_core_has_AGP(dev) && dev->agp &&
394             drm_core_check_feature(dev, DRIVER_MODESET)) {
395                 struct drm_agp_mem *entry, *tempe;
396
397                 /* Remove AGP resources, but leave dev->agp
398                    intact until drv_cleanup is called. */
399                 list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
400                         if (entry->bound)
401                                 drm_unbind_agp(entry->memory);
402                         drm_free_agp(entry->memory, entry->pages);
403                         kfree(entry);
404                 }
405                 INIT_LIST_HEAD(&dev->agp->memory);
406
407                 if (dev->agp->acquired)
408                         drm_agp_release(dev);
409
410                 dev->agp->acquired = 0;
411                 dev->agp->enabled = 0;
412         }
413
414         if (dev_priv->fb_mtrr) {
415                 drm_mtrr_del(dev_priv->fb_mtrr, drm_get_resource_start(dev, 1),
416                              drm_get_resource_len(dev, 1), DRM_MTRR_WC);
417                 dev_priv->fb_mtrr = 0;
418         }
419 }
420
421 /*XXX won't work on BSD because of pci_read_config_dword */
422 static uint32_t
423 nouveau_mem_fb_amount_igp(struct drm_device *dev)
424 {
425         struct drm_nouveau_private *dev_priv = dev->dev_private;
426         struct pci_dev *bridge;
427         uint32_t mem;
428
429         bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
430         if (!bridge) {
431                 NV_ERROR(dev, "no bridge device\n");
432                 return 0;
433         }
434
435         if (dev_priv->flags&NV_NFORCE) {
436                 pci_read_config_dword(bridge, 0x7C, &mem);
437                 return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
438         } else
439         if (dev_priv->flags&NV_NFORCE2) {
440                 pci_read_config_dword(bridge, 0x84, &mem);
441                 return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
442         }
443
444         NV_ERROR(dev, "impossible!\n");
445         return 0;
446 }
447
448 /* returns the amount of FB ram in bytes */
449 uint64_t nouveau_mem_fb_amount(struct drm_device *dev)
450 {
451         struct drm_nouveau_private *dev_priv = dev->dev_private;
452         uint32_t boot0;
453
454         switch (dev_priv->card_type) {
455         case NV_04:
456                 boot0 = nv_rd32(dev, NV03_BOOT_0);
457                 if (boot0 & 0x00000100)
458                         return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
459
460                 switch (boot0 & NV03_BOOT_0_RAM_AMOUNT) {
461                 case NV04_BOOT_0_RAM_AMOUNT_32MB:
462                         return 32 * 1024 * 1024;
463                 case NV04_BOOT_0_RAM_AMOUNT_16MB:
464                         return 16 * 1024 * 1024;
465                 case NV04_BOOT_0_RAM_AMOUNT_8MB:
466                         return 8 * 1024 * 1024;
467                 case NV04_BOOT_0_RAM_AMOUNT_4MB:
468                         return 4 * 1024 * 1024;
469                 }
470                 break;
471         case NV_10:
472         case NV_20:
473         case NV_30:
474         case NV_40:
475         case NV_50:
476         default:
477                 if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
478                         return nouveau_mem_fb_amount_igp(dev);
479                 } else {
480                         uint64_t mem;
481                         mem = (nv_rd32(dev, NV04_FIFO_DATA) &
482                                         NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK) >>
483                                         NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT;
484                         return mem * 1024 * 1024;
485                 }
486                 break;
487         }
488
489         NV_ERROR(dev,
490                 "Unable to detect video ram size. Please report your setup to "
491                                                         DRIVER_EMAIL "\n");
492         return 0;
493 }
494
495 #if __OS_HAS_AGP
496 static void nouveau_mem_reset_agp(struct drm_device *dev)
497 {
498         uint32_t saved_pci_nv_1, saved_pci_nv_19, pmc_enable;
499
500         saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
501         saved_pci_nv_19 = nv_rd32(dev, NV04_PBUS_PCI_NV_19);
502
503         /* clear busmaster bit */
504         nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
505         /* clear SBA and AGP bits */
506         nv_wr32(dev, NV04_PBUS_PCI_NV_19, saved_pci_nv_19 & 0xfffff0ff);
507
508         /* power cycle pgraph, if enabled */
509         pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
510         if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
511                 nv_wr32(dev, NV03_PMC_ENABLE,
512                                 pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
513                 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
514                                 NV_PMC_ENABLE_PGRAPH);
515         }
516
517         /* and restore (gives effect of resetting AGP) */
518         nv_wr32(dev, NV04_PBUS_PCI_NV_19, saved_pci_nv_19);
519         nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
520 }
521 #endif
522
523 int
524 nouveau_mem_init_agp(struct drm_device *dev)
525 {
526 #if __OS_HAS_AGP
527         struct drm_nouveau_private *dev_priv = dev->dev_private;
528         struct drm_agp_info info;
529         struct drm_agp_mode mode;
530         int ret;
531
532         if (nouveau_noagp)
533                 return 0;
534
535         nouveau_mem_reset_agp(dev);
536
537         if (!dev->agp->acquired) {
538                 ret = drm_agp_acquire(dev);
539                 if (ret) {
540                         NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
541                         return ret;
542                 }
543         }
544
545         ret = drm_agp_info(dev, &info);
546         if (ret) {
547                 NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
548                 return ret;
549         }
550
551         /* see agp.h for the AGPSTAT_* modes available */
552         mode.mode = info.mode;
553         ret = drm_agp_enable(dev, mode);
554         if (ret) {
555                 NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
556                 return ret;
557         }
558
559         dev_priv->gart_info.type        = NOUVEAU_GART_AGP;
560         dev_priv->gart_info.aper_base   = info.aperture_base;
561         dev_priv->gart_info.aper_size   = info.aperture_size;
562 #endif
563         return 0;
564 }
565
566 int
567 nouveau_mem_init(struct drm_device *dev)
568 {
569         struct drm_nouveau_private *dev_priv = dev->dev_private;
570         struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
571         int ret, dma_bits = 32;
572
573         dev_priv->fb_phys = drm_get_resource_start(dev, 1);
574         dev_priv->gart_info.type = NOUVEAU_GART_NONE;
575
576         if (dev_priv->card_type >= NV_50 &&
577             pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
578                 dma_bits = 40;
579
580         ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
581         if (ret) {
582                 NV_ERROR(dev, "Error setting DMA mask: %d\n", ret);
583                 return ret;
584         }
585
586         ret = nouveau_ttm_global_init(dev_priv);
587         if (ret)
588                 return ret;
589
590         ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
591                                  dev_priv->ttm.bo_global_ref.ref.object,
592                                  &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
593                                  dma_bits <= 32 ? true : false);
594         if (ret) {
595                 NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
596                 return ret;
597         }
598
599         INIT_LIST_HEAD(&dev_priv->ttm.bo_list);
600         spin_lock_init(&dev_priv->ttm.bo_list_lock);
601         spin_lock_init(&dev_priv->tile.lock);
602
603         dev_priv->fb_available_size = nouveau_mem_fb_amount(dev);
604
605         dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
606         if (dev_priv->fb_mappable_pages > drm_get_resource_len(dev, 1))
607                 dev_priv->fb_mappable_pages = drm_get_resource_len(dev, 1);
608         dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
609
610         NV_INFO(dev, "%d MiB VRAM\n", (int)(dev_priv->fb_available_size >> 20));
611
612         /* remove reserved space at end of vram from available amount */
613         dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
614         dev_priv->fb_aper_free = dev_priv->fb_available_size;
615
616         /* mappable vram */
617         ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
618                              dev_priv->fb_available_size >> PAGE_SHIFT);
619         if (ret) {
620                 NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
621                 return ret;
622         }
623
624         ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
625                              0, 0, true, true, &dev_priv->vga_ram);
626         if (ret == 0)
627                 ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM);
628         if (ret) {
629                 NV_WARN(dev, "failed to reserve VGA memory\n");
630                 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
631         }
632
633         /* GART */
634 #if !defined(__powerpc__) && !defined(__ia64__)
635         if (drm_device_is_agp(dev) && dev->agp) {
636                 ret = nouveau_mem_init_agp(dev);
637                 if (ret)
638                         NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
639         }
640 #endif
641
642         if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
643                 ret = nouveau_sgdma_init(dev);
644                 if (ret) {
645                         NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
646                         return ret;
647                 }
648         }
649
650         NV_INFO(dev, "%d MiB GART (aperture)\n",
651                 (int)(dev_priv->gart_info.aper_size >> 20));
652         dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
653
654         ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
655                              dev_priv->gart_info.aper_size >> PAGE_SHIFT);
656         if (ret) {
657                 NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
658                 return ret;
659         }
660
661         dev_priv->fb_mtrr = drm_mtrr_add(drm_get_resource_start(dev, 1),
662                                          drm_get_resource_len(dev, 1),
663                                          DRM_MTRR_WC);
664
665         return 0;
666 }
667
668