drivers/gpu/drm/nouveau/nouveau_drv.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include <linux/console.h>
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "drm_crtc_helper.h"
  30 #include "nouveau_drv.h"
  31 #include "nouveau_hw.h"
  32 #include "nouveau_fb.h"
  33 #include "nouveau_fbcon.h"
  34 #include "nv50_display.h"
  35
  36 #include "drm_pciids.h"
  37
  38 MODULE_PARM_DESC(ctxfw, "Use external firmware blob for grctx init (NV40)");
  39 int nouveau_ctxfw = 0;
  40 module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
  41
  42 MODULE_PARM_DESC(noagp, "Disable AGP");
  43 int nouveau_noagp;
  44 module_param_named(noagp, nouveau_noagp, int, 0400);
  45
  46 MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
  47 static int nouveau_modeset = -1; /* kms */
  48 module_param_named(modeset, nouveau_modeset, int, 0400);
  49
  50 MODULE_PARM_DESC(vbios, "Override default VBIOS location");
  51 char *nouveau_vbios;
  52 module_param_named(vbios, nouveau_vbios, charp, 0400);
  53
  54 MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
  55 int nouveau_vram_pushbuf;
  56 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
  57
  58 MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
  59 int nouveau_vram_notify;
  60 module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
  61
  62 MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
  63 int nouveau_duallink = 1;
  64 module_param_named(duallink, nouveau_duallink, int, 0400);
  65
  66 MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
  67 int nouveau_uscript_lvds = -1;
  68 module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);
  69
  70 MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
  71 int nouveau_uscript_tmds = -1;
  72 module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
  73
  74 MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
  75                  "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
  76                  "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
  77                  "\t\tDefault: PAL\n"
  78                  "\t\t*NOTE* Ignored for cards with external TV encoders.");
  79 char *nouveau_tv_norm;
  80 module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
  81
  82 MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
  83                 "\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
  84                 "\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
  85                 "\t\t0x100 vgaattr, 0x200 EVO (G80+). ");
  86 int nouveau_reg_debug;
  87 module_param_named(reg_debug, nouveau_reg_debug, int, 0600);
  88
  89 int nouveau_fbpercrtc;
  90 #if 0
  91 module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
  92 #endif
  93
  94 static struct pci_device_id pciidlist[] = {
  95         {
  96                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
  97                 .class = PCI_BASE_CLASS_DISPLAY << 16,
  98                 .class_mask  = 0xff << 16,
  99         },
 100         {
 101                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
 102                 .class = PCI_BASE_CLASS_DISPLAY << 16,
 103                 .class_mask  = 0xff << 16,
 104         },
 105         {}
 106 };
 107
 108 MODULE_DEVICE_TABLE(pci, pciidlist);
 109
 110 static struct drm_driver driver;
 111
 112 static int __devinit
 113 nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 114 {
 115         return drm_get_dev(pdev, ent, &driver);
 116 }
 117
 118 static void
 119 nouveau_pci_remove(struct pci_dev *pdev)
 120 {
 121         struct drm_device *dev = pci_get_drvdata(pdev);
 122
 123         drm_put_dev(dev);
 124 }
 125
 126 static int
 127 nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
 128 {
 129         struct drm_device *dev = pci_get_drvdata(pdev);
 130         struct drm_nouveau_private *dev_priv = dev->dev_private;
 131         struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
 132         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
 133         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 134         struct nouveau_channel *chan;
 135         struct drm_crtc *crtc;
 136         uint32_t fbdev_flags;
 137         int ret, i;
 138
 139         if (!drm_core_check_feature(dev, DRIVER_MODESET))
 140                 return -ENODEV;
 141
 142         if (pm_state.event == PM_EVENT_PRETHAW)
 143                 return 0;
 144
 145         fbdev_flags = dev_priv->fbdev_info->flags;
 146         dev_priv->fbdev_info->flags |= FBINFO_HWACCEL_DISABLED;
 147
 148         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 149                 struct nouveau_framebuffer *nouveau_fb;
 150
 151                 nouveau_fb = nouveau_framebuffer(crtc->fb);
 152                 if (!nouveau_fb || !nouveau_fb->nvbo)
 153                         continue;
 154
 155                 nouveau_bo_unpin(nouveau_fb->nvbo);
 156         }
 157
 158         NV_INFO(dev, "Evicting buffers...\n");
 159         ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 160
 161         NV_INFO(dev, "Idling channels...\n");
 162         for (i = 0; i < pfifo->channels; i++) {
 163                 struct nouveau_fence *fence = NULL;
 164
 165                 chan = dev_priv->fifos[i];
 166                 if (!chan || (dev_priv->card_type >= NV_50 &&
 167                               chan == dev_priv->fifos[0]))
 168                         continue;
 169
 170                 ret = nouveau_fence_new(chan, &fence, true);
 171                 if (ret == 0) {
 172                         ret = nouveau_fence_wait(fence, NULL, false, false);
 173                         nouveau_fence_unref((void *)&fence);
 174                 }
 175
 176                 if (ret) {
 177                         NV_ERROR(dev, "Failed to idle channel %d for suspend\n",
 178                                  chan->id);
 179                 }
 180         }
 181
 182         pgraph->fifo_access(dev, false);
 183         nouveau_wait_for_idle(dev);
 184         pfifo->reassign(dev, false);
 185         pfifo->disable(dev);
 186         pfifo->unload_context(dev);
 187         pgraph->unload_context(dev);
 188
 189         NV_INFO(dev, "Suspending GPU objects...\n");
 190         ret = nouveau_gpuobj_suspend(dev);
 191         if (ret) {
 192                 NV_ERROR(dev, "... failed: %d\n", ret);
 193                 goto out_abort;
 194         }
 195
 196         ret = pinstmem->suspend(dev);
 197         if (ret) {
 198                 NV_ERROR(dev, "... failed: %d\n", ret);
 199                 nouveau_gpuobj_suspend_cleanup(dev);
 200                 goto out_abort;
 201         }
 202
 203         NV_INFO(dev, "And we're gone!\n");
 204         pci_save_state(pdev);
 205         if (pm_state.event == PM_EVENT_SUSPEND) {
 206                 pci_disable_device(pdev);
 207                 pci_set_power_state(pdev, PCI_D3hot);
 208         }
 209
 210         acquire_console_sem();
 211         fb_set_suspend(dev_priv->fbdev_info, 1);
 212         release_console_sem();
 213         dev_priv->fbdev_info->flags = fbdev_flags;
 214         return 0;
 215
 216 out_abort:
 217         NV_INFO(dev, "Re-enabling acceleration..\n");
 218         pfifo->enable(dev);
 219         pfifo->reassign(dev, true);
 220         pgraph->fifo_access(dev, true);
 221         return ret;
 222 }
 223
 224 static int
 225 nouveau_pci_resume(struct pci_dev *pdev)
 226 {
 227         struct drm_device *dev = pci_get_drvdata(pdev);
 228         struct drm_nouveau_private *dev_priv = dev->dev_private;
 229         struct nouveau_engine *engine = &dev_priv->engine;
 230         struct drm_crtc *crtc;
 231         uint32_t fbdev_flags;
 232         int ret, i;
 233
 234         if (!drm_core_check_feature(dev, DRIVER_MODESET))
 235                 return -ENODEV;
 236
 237         fbdev_flags = dev_priv->fbdev_info->flags;
 238         dev_priv->fbdev_info->flags |= FBINFO_HWACCEL_DISABLED;
 239
 240         NV_INFO(dev, "We're back, enabling device...\n");
 241         pci_set_power_state(pdev, PCI_D0);
 242         pci_restore_state(pdev);
 243         if (pci_enable_device(pdev))
 244                 return -1;
 245         pci_set_master(dev->pdev);
 246
 247         NV_INFO(dev, "POSTing device...\n");
 248         ret = nouveau_run_vbios_init(dev);
 249         if (ret)
 250                 return ret;
 251
 252         if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
 253                 ret = nouveau_mem_init_agp(dev);
 254                 if (ret) {
 255                         NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
 256                         return ret;
 257                 }
 258         }
 259
 260         NV_INFO(dev, "Reinitialising engines...\n");
 261         engine->instmem.resume(dev);
 262         engine->mc.init(dev);
 263         engine->timer.init(dev);
 264         engine->fb.init(dev);
 265         engine->graph.init(dev);
 266         engine->fifo.init(dev);
 267
 268         NV_INFO(dev, "Restoring GPU objects...\n");
 269         nouveau_gpuobj_resume(dev);
 270
 271         nouveau_irq_postinstall(dev);
 272
 273         /* Re-write SKIPS, they'll have been lost over the suspend */
 274         if (nouveau_vram_pushbuf) {
 275                 struct nouveau_channel *chan;
 276                 int j;
 277
 278                 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 279                         chan = dev_priv->fifos[i];
 280                         if (!chan || !chan->pushbuf_bo)
 281                                 continue;
 282
 283                         for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
 284                                 nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
 285                 }
 286         }
 287
 288         NV_INFO(dev, "Restoring mode...\n");
 289         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 290                 struct nouveau_framebuffer *nouveau_fb;
 291
 292                 nouveau_fb = nouveau_framebuffer(crtc->fb);
 293                 if (!nouveau_fb || !nouveau_fb->nvbo)
 294                         continue;
 295
 296                 nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
 297         }
 298
 299         if (dev_priv->card_type < NV_50) {
 300                 nv04_display_restore(dev);
 301                 NVLockVgaCrtcs(dev, false);
 302         } else
 303                 nv50_display_init(dev);
 304
 305         /* Force CLUT to get re-loaded during modeset */
 306         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 307                 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 308
 309                 nv_crtc->lut.depth = 0;
 310         }
 311
 312         acquire_console_sem();
 313         fb_set_suspend(dev_priv->fbdev_info, 0);
 314         release_console_sem();
 315
 316         nouveau_fbcon_zfill(dev);
 317
 318         drm_helper_resume_force_mode(dev);
 319         dev_priv->fbdev_info->flags = fbdev_flags;
 320         return 0;
 321 }
 322
 323 static struct drm_driver driver = {
 324         .driver_features =
 325                 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
 326                 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
 327         .load = nouveau_load,
 328         .firstopen = nouveau_firstopen,
 329         .lastclose = nouveau_lastclose,
 330         .unload = nouveau_unload,
 331         .preclose = nouveau_preclose,
 332 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
 333         .debugfs_init = nouveau_debugfs_init,
 334         .debugfs_cleanup = nouveau_debugfs_takedown,
 335 #endif
 336         .irq_preinstall = nouveau_irq_preinstall,
 337         .irq_postinstall = nouveau_irq_postinstall,
 338         .irq_uninstall = nouveau_irq_uninstall,
 339         .irq_handler = nouveau_irq_handler,
 340         .reclaim_buffers = drm_core_reclaim_buffers,
 341         .get_map_ofs = drm_core_get_map_ofs,
 342         .get_reg_ofs = drm_core_get_reg_ofs,
 343         .ioctls = nouveau_ioctls,
 344         .fops = {
 345                 .owner = THIS_MODULE,
 346                 .open = drm_open,
 347                 .release = drm_release,
 348                 .unlocked_ioctl = drm_ioctl,
 349                 .mmap = nouveau_ttm_mmap,
 350                 .poll = drm_poll,
 351                 .fasync = drm_fasync,
 352 #if defined(CONFIG_COMPAT)
 353                 .compat_ioctl = nouveau_compat_ioctl,
 354 #endif
 355         },
 356         .pci_driver = {
 357                 .name = DRIVER_NAME,
 358                 .id_table = pciidlist,
 359                 .probe = nouveau_pci_probe,
 360                 .remove = nouveau_pci_remove,
 361                 .suspend = nouveau_pci_suspend,
 362                 .resume = nouveau_pci_resume
 363         },
 364
 365         .gem_init_object = nouveau_gem_object_new,
 366         .gem_free_object = nouveau_gem_object_del,
 367
 368         .name = DRIVER_NAME,
 369         .desc = DRIVER_DESC,
 370 #ifdef GIT_REVISION
 371         .date = GIT_REVISION,
 372 #else
 373         .date = DRIVER_DATE,
 374 #endif
 375         .major = DRIVER_MAJOR,
 376         .minor = DRIVER_MINOR,
 377         .patchlevel = DRIVER_PATCHLEVEL,
 378 };
 379
 380 static int __init nouveau_init(void)
 381 {
 382         driver.num_ioctls = nouveau_max_ioctl;
 383
 384         if (nouveau_modeset == -1) {
 385 #ifdef CONFIG_VGA_CONSOLE
 386                 if (vgacon_text_force())
 387                         nouveau_modeset = 0;
 388                 else
 389 #endif
 390                         nouveau_modeset = 1;
 391         }
 392
 393         if (nouveau_modeset == 1)
 394                 driver.driver_features |= DRIVER_MODESET;
 395
 396         return drm_init(&driver);
 397 }
 398
 399 static void __exit nouveau_exit(void)
 400 {
 401         drm_exit(&driver);
 402 }
 403
 404 module_init(nouveau_init);
 405 module_exit(nouveau_exit);
 406
 407 MODULE_AUTHOR(DRIVER_AUTHOR);
 408 MODULE_DESCRIPTION(DRIVER_DESC);
 409 MODULE_LICENSE("GPL and additional rights");