8497768f1b4102ac76d7e5d45257aec2bb72a82b
[sfrench/cifs-2.6.git] / drivers / gpu / drm / nouveau / dispnv50 / disp.c
1 /*
2  * Copyright 2011 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include "disp.h"
25 #include "atom.h"
26 #include "core.h"
27 #include "head.h"
28 #include "wndw.h"
29
30 #include <linux/dma-mapping.h>
31 #include <linux/hdmi.h>
32
33 #include <drm/drmP.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_dp_helper.h>
36 #include <drm/drm_fb_helper.h>
37 #include <drm/drm_plane_helper.h>
38 #include <drm/drm_probe_helper.h>
39 #include <drm/drm_scdc_helper.h>
40 #include <drm/drm_edid.h>
41
42 #include <nvif/class.h>
43 #include <nvif/cl0002.h>
44 #include <nvif/cl5070.h>
45 #include <nvif/cl507d.h>
46 #include <nvif/event.h>
47
48 #include "nouveau_drv.h"
49 #include "nouveau_dma.h"
50 #include "nouveau_gem.h"
51 #include "nouveau_connector.h"
52 #include "nouveau_encoder.h"
53 #include "nouveau_fence.h"
54 #include "nouveau_fbcon.h"
55
56 #include <subdev/bios/dp.h>
57
58 /******************************************************************************
59  * Atomic state
60  *****************************************************************************/
61
62 struct nv50_outp_atom {
63         struct list_head head;
64
65         struct drm_encoder *encoder;
66         bool flush_disable;
67
68         union nv50_outp_atom_mask {
69                 struct {
70                         bool ctrl:1;
71                 };
72                 u8 mask;
73         } set, clr;
74 };
75
76 /******************************************************************************
77  * EVO channel
78  *****************************************************************************/
79
80 static int
81 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
82                  const s32 *oclass, u8 head, void *data, u32 size,
83                  struct nv50_chan *chan)
84 {
85         struct nvif_sclass *sclass;
86         int ret, i, n;
87
88         chan->device = device;
89
90         ret = n = nvif_object_sclass_get(disp, &sclass);
91         if (ret < 0)
92                 return ret;
93
94         while (oclass[0]) {
95                 for (i = 0; i < n; i++) {
96                         if (sclass[i].oclass == oclass[0]) {
97                                 ret = nvif_object_init(disp, 0, oclass[0],
98                                                        data, size, &chan->user);
99                                 if (ret == 0)
100                                         nvif_object_map(&chan->user, NULL, 0);
101                                 nvif_object_sclass_put(&sclass);
102                                 return ret;
103                         }
104                 }
105                 oclass++;
106         }
107
108         nvif_object_sclass_put(&sclass);
109         return -ENOSYS;
110 }
111
112 static void
113 nv50_chan_destroy(struct nv50_chan *chan)
114 {
115         nvif_object_fini(&chan->user);
116 }
117
118 /******************************************************************************
119  * DMA EVO channel
120  *****************************************************************************/
121
122 void
123 nv50_dmac_destroy(struct nv50_dmac *dmac)
124 {
125         nvif_object_fini(&dmac->vram);
126         nvif_object_fini(&dmac->sync);
127
128         nv50_chan_destroy(&dmac->base);
129
130         nvif_mem_fini(&dmac->push);
131 }
132
133 int
134 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
135                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
136                  struct nv50_dmac *dmac)
137 {
138         struct nouveau_cli *cli = (void *)device->object.client;
139         struct nv50_disp_core_channel_dma_v0 *args = data;
140         u8 type = NVIF_MEM_COHERENT;
141         int ret;
142
143         mutex_init(&dmac->lock);
144
145         /* Pascal added support for 47-bit physical addresses, but some
146          * parts of EVO still only accept 40-bit PAs.
147          *
148          * To avoid issues on systems with large amounts of RAM, and on
149          * systems where an IOMMU maps pages at a high address, we need
150          * to allocate push buffers in VRAM instead.
151          *
152          * This appears to match NVIDIA's behaviour on Pascal.
153          */
154         if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
155                 type |= NVIF_MEM_VRAM;
156
157         ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push);
158         if (ret)
159                 return ret;
160
161         dmac->ptr = dmac->push.object.map.ptr;
162
163         args->pushbuf = nvif_handle(&dmac->push.object);
164
165         ret = nv50_chan_create(device, disp, oclass, head, data, size,
166                                &dmac->base);
167         if (ret)
168                 return ret;
169
170         if (!syncbuf)
171                 return 0;
172
173         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
174                                &(struct nv_dma_v0) {
175                                         .target = NV_DMA_V0_TARGET_VRAM,
176                                         .access = NV_DMA_V0_ACCESS_RDWR,
177                                         .start = syncbuf + 0x0000,
178                                         .limit = syncbuf + 0x0fff,
179                                }, sizeof(struct nv_dma_v0),
180                                &dmac->sync);
181         if (ret)
182                 return ret;
183
184         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
185                                &(struct nv_dma_v0) {
186                                         .target = NV_DMA_V0_TARGET_VRAM,
187                                         .access = NV_DMA_V0_ACCESS_RDWR,
188                                         .start = 0,
189                                         .limit = device->info.ram_user - 1,
190                                }, sizeof(struct nv_dma_v0),
191                                &dmac->vram);
192         if (ret)
193                 return ret;
194
195         return ret;
196 }
197
198 /******************************************************************************
199  * EVO channel helpers
200  *****************************************************************************/
201 static void
202 evo_flush(struct nv50_dmac *dmac)
203 {
204         /* Push buffer fetches are not coherent with BAR1, we need to ensure
205          * writes have been flushed right through to VRAM before writing PUT.
206          */
207         if (dmac->push.type & NVIF_MEM_VRAM) {
208                 struct nvif_device *device = dmac->base.device;
209                 nvif_wr32(&device->object, 0x070000, 0x00000001);
210                 nvif_msec(device, 2000,
211                         if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
212                                 break;
213                 );
214         }
215 }
216
217 u32 *
218 evo_wait(struct nv50_dmac *evoc, int nr)
219 {
220         struct nv50_dmac *dmac = evoc;
221         struct nvif_device *device = dmac->base.device;
222         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
223
224         mutex_lock(&dmac->lock);
225         if (put + nr >= (PAGE_SIZE / 4) - 8) {
226                 dmac->ptr[put] = 0x20000000;
227                 evo_flush(dmac);
228
229                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
230                 if (nvif_msec(device, 2000,
231                         if (!nvif_rd32(&dmac->base.user, 0x0004))
232                                 break;
233                 ) < 0) {
234                         mutex_unlock(&dmac->lock);
235                         pr_err("nouveau: evo channel stalled\n");
236                         return NULL;
237                 }
238
239                 put = 0;
240         }
241
242         return dmac->ptr + put;
243 }
244
245 void
246 evo_kick(u32 *push, struct nv50_dmac *evoc)
247 {
248         struct nv50_dmac *dmac = evoc;
249
250         evo_flush(dmac);
251
252         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
253         mutex_unlock(&dmac->lock);
254 }
255
256 /******************************************************************************
257  * Output path helpers
258  *****************************************************************************/
259 static void
260 nv50_outp_release(struct nouveau_encoder *nv_encoder)
261 {
262         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
263         struct {
264                 struct nv50_disp_mthd_v1 base;
265         } args = {
266                 .base.version = 1,
267                 .base.method = NV50_DISP_MTHD_V1_RELEASE,
268                 .base.hasht  = nv_encoder->dcb->hasht,
269                 .base.hashm  = nv_encoder->dcb->hashm,
270         };
271
272         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
273         nv_encoder->or = -1;
274         nv_encoder->link = 0;
275 }
276
277 static int
278 nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
279 {
280         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
281         struct nv50_disp *disp = nv50_disp(drm->dev);
282         struct {
283                 struct nv50_disp_mthd_v1 base;
284                 struct nv50_disp_acquire_v0 info;
285         } args = {
286                 .base.version = 1,
287                 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
288                 .base.hasht  = nv_encoder->dcb->hasht,
289                 .base.hashm  = nv_encoder->dcb->hashm,
290         };
291         int ret;
292
293         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
294         if (ret) {
295                 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
296                 return ret;
297         }
298
299         nv_encoder->or = args.info.or;
300         nv_encoder->link = args.info.link;
301         return 0;
302 }
303
304 static int
305 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
306                             struct drm_crtc_state *crtc_state,
307                             struct drm_connector_state *conn_state,
308                             struct drm_display_mode *native_mode)
309 {
310         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
311         struct drm_display_mode *mode = &crtc_state->mode;
312         struct drm_connector *connector = conn_state->connector;
313         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
314         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
315
316         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
317         asyc->scaler.full = false;
318         if (!native_mode)
319                 return 0;
320
321         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
322                 switch (connector->connector_type) {
323                 case DRM_MODE_CONNECTOR_LVDS:
324                 case DRM_MODE_CONNECTOR_eDP:
325                         /* Don't force scaler for EDID modes with
326                          * same size as the native one (e.g. different
327                          * refresh rate)
328                          */
329                         if (adjusted_mode->hdisplay == native_mode->hdisplay &&
330                             adjusted_mode->vdisplay == native_mode->vdisplay &&
331                             adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
332                                 break;
333                         mode = native_mode;
334                         asyc->scaler.full = true;
335                         break;
336                 default:
337                         break;
338                 }
339         } else {
340                 mode = native_mode;
341         }
342
343         if (!drm_mode_equal(adjusted_mode, mode)) {
344                 drm_mode_copy(adjusted_mode, mode);
345                 crtc_state->mode_changed = true;
346         }
347
348         return 0;
349 }
350
351 static int
352 nv50_outp_atomic_check(struct drm_encoder *encoder,
353                        struct drm_crtc_state *crtc_state,
354                        struct drm_connector_state *conn_state)
355 {
356         struct nouveau_connector *nv_connector =
357                 nouveau_connector(conn_state->connector);
358         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
359                                            nv_connector->native_mode);
360 }
361
362 /******************************************************************************
363  * DAC
364  *****************************************************************************/
365 static void
366 nv50_dac_disable(struct drm_encoder *encoder)
367 {
368         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
369         struct nv50_core *core = nv50_disp(encoder->dev)->core;
370         if (nv_encoder->crtc)
371                 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL);
372         nv_encoder->crtc = NULL;
373         nv50_outp_release(nv_encoder);
374 }
375
376 static void
377 nv50_dac_enable(struct drm_encoder *encoder)
378 {
379         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
380         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
381         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
382         struct nv50_core *core = nv50_disp(encoder->dev)->core;
383
384         nv50_outp_acquire(nv_encoder);
385
386         core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);
387         asyh->or.depth = 0;
388
389         nv_encoder->crtc = encoder->crtc;
390 }
391
392 static enum drm_connector_status
393 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
394 {
395         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
396         struct nv50_disp *disp = nv50_disp(encoder->dev);
397         struct {
398                 struct nv50_disp_mthd_v1 base;
399                 struct nv50_disp_dac_load_v0 load;
400         } args = {
401                 .base.version = 1,
402                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
403                 .base.hasht  = nv_encoder->dcb->hasht,
404                 .base.hashm  = nv_encoder->dcb->hashm,
405         };
406         int ret;
407
408         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
409         if (args.load.data == 0)
410                 args.load.data = 340;
411
412         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
413         if (ret || !args.load.load)
414                 return connector_status_disconnected;
415
416         return connector_status_connected;
417 }
418
419 static const struct drm_encoder_helper_funcs
420 nv50_dac_help = {
421         .atomic_check = nv50_outp_atomic_check,
422         .enable = nv50_dac_enable,
423         .disable = nv50_dac_disable,
424         .detect = nv50_dac_detect
425 };
426
427 static void
428 nv50_dac_destroy(struct drm_encoder *encoder)
429 {
430         drm_encoder_cleanup(encoder);
431         kfree(encoder);
432 }
433
434 static const struct drm_encoder_funcs
435 nv50_dac_func = {
436         .destroy = nv50_dac_destroy,
437 };
438
439 static int
440 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
441 {
442         struct nouveau_drm *drm = nouveau_drm(connector->dev);
443         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
444         struct nvkm_i2c_bus *bus;
445         struct nouveau_encoder *nv_encoder;
446         struct drm_encoder *encoder;
447         int type = DRM_MODE_ENCODER_DAC;
448
449         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
450         if (!nv_encoder)
451                 return -ENOMEM;
452         nv_encoder->dcb = dcbe;
453
454         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
455         if (bus)
456                 nv_encoder->i2c = &bus->i2c;
457
458         encoder = to_drm_encoder(nv_encoder);
459         encoder->possible_crtcs = dcbe->heads;
460         encoder->possible_clones = 0;
461         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
462                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
463         drm_encoder_helper_add(encoder, &nv50_dac_help);
464
465         drm_connector_attach_encoder(connector, encoder);
466         return 0;
467 }
468
469 /******************************************************************************
470  * Audio
471  *****************************************************************************/
472 static void
473 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
474 {
475         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
476         struct nv50_disp *disp = nv50_disp(encoder->dev);
477         struct {
478                 struct nv50_disp_mthd_v1 base;
479                 struct nv50_disp_sor_hda_eld_v0 eld;
480         } args = {
481                 .base.version = 1,
482                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
483                 .base.hasht   = nv_encoder->dcb->hasht,
484                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
485                                 (0x0100 << nv_crtc->index),
486         };
487
488         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
489 }
490
491 static void
492 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
493 {
494         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
495         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
496         struct nouveau_connector *nv_connector;
497         struct nv50_disp *disp = nv50_disp(encoder->dev);
498         struct __packed {
499                 struct {
500                         struct nv50_disp_mthd_v1 mthd;
501                         struct nv50_disp_sor_hda_eld_v0 eld;
502                 } base;
503                 u8 data[sizeof(nv_connector->base.eld)];
504         } args = {
505                 .base.mthd.version = 1,
506                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
507                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
508                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
509                                      (0x0100 << nv_crtc->index),
510         };
511
512         nv_connector = nouveau_encoder_connector_get(nv_encoder);
513         if (!drm_detect_monitor_audio(nv_connector->edid))
514                 return;
515
516         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
517
518         nvif_mthd(&disp->disp->object, 0, &args,
519                   sizeof(args.base) + drm_eld_size(args.data));
520 }
521
522 /******************************************************************************
523  * HDMI
524  *****************************************************************************/
525 static void
526 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
527 {
528         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
529         struct nv50_disp *disp = nv50_disp(encoder->dev);
530         struct {
531                 struct nv50_disp_mthd_v1 base;
532                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
533         } args = {
534                 .base.version = 1,
535                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
536                 .base.hasht  = nv_encoder->dcb->hasht,
537                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
538                                (0x0100 << nv_crtc->index),
539         };
540
541         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
542 }
543
544 static void
545 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
546 {
547         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
548         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
549         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
550         struct nv50_disp *disp = nv50_disp(encoder->dev);
551         struct {
552                 struct nv50_disp_mthd_v1 base;
553                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
554                 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
555         } args = {
556                 .base.version = 1,
557                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
558                 .base.hasht  = nv_encoder->dcb->hasht,
559                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
560                                (0x0100 << nv_crtc->index),
561                 .pwr.state = 1,
562                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
563         };
564         struct nouveau_connector *nv_connector;
565         struct drm_hdmi_info *hdmi;
566         u32 max_ac_packet;
567         union hdmi_infoframe avi_frame;
568         union hdmi_infoframe vendor_frame;
569         bool high_tmds_clock_ratio = false, scrambling = false;
570         u8 config;
571         int ret;
572         int size;
573
574         nv_connector = nouveau_encoder_connector_get(nv_encoder);
575         if (!drm_detect_hdmi_monitor(nv_connector->edid))
576                 return;
577
578         hdmi = &nv_connector->base.display_info.hdmi;
579
580         ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi,
581                                                        &nv_connector->base, mode);
582         if (!ret) {
583                 /* We have an AVI InfoFrame, populate it to the display */
584                 args.pwr.avi_infoframe_length
585                         = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
586         }
587
588         ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
589                                                           &nv_connector->base, mode);
590         if (!ret) {
591                 /* We have a Vendor InfoFrame, populate it to the display */
592                 args.pwr.vendor_infoframe_length
593                         = hdmi_infoframe_pack(&vendor_frame,
594                                               args.infoframes
595                                               + args.pwr.avi_infoframe_length,
596                                               17);
597         }
598
599         max_ac_packet  = mode->htotal - mode->hdisplay;
600         max_ac_packet -= args.pwr.rekey;
601         max_ac_packet -= 18; /* constant from tegra */
602         args.pwr.max_ac_packet = max_ac_packet / 32;
603
604         if (hdmi->scdc.scrambling.supported) {
605                 high_tmds_clock_ratio = mode->clock > 340000;
606                 scrambling = high_tmds_clock_ratio ||
607                         hdmi->scdc.scrambling.low_rates;
608         }
609
610         args.pwr.scdc =
611                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
612                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
613
614         size = sizeof(args.base)
615                 + sizeof(args.pwr)
616                 + args.pwr.avi_infoframe_length
617                 + args.pwr.vendor_infoframe_length;
618         nvif_mthd(&disp->disp->object, 0, &args, size);
619
620         nv50_audio_enable(encoder, mode);
621
622         /* If SCDC is supported by the downstream monitor, update
623          * divider / scrambling settings to what we programmed above.
624          */
625         if (!hdmi->scdc.scrambling.supported)
626                 return;
627
628         ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
629         if (ret < 0) {
630                 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
631                 return;
632         }
633         config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
634         config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
635         config |= SCDC_SCRAMBLING_ENABLE * scrambling;
636         ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
637         if (ret < 0)
638                 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
639                          config, ret);
640 }
641
642 /******************************************************************************
643  * MST
644  *****************************************************************************/
645 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
646 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
647 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
648
649 struct nv50_mstm {
650         struct nouveau_encoder *outp;
651
652         struct drm_dp_mst_topology_mgr mgr;
653         struct nv50_msto *msto[4];
654
655         bool modified;
656         bool disabled;
657         int links;
658 };
659
660 struct nv50_mstc {
661         struct nv50_mstm *mstm;
662         struct drm_dp_mst_port *port;
663         struct drm_connector connector;
664
665         struct drm_display_mode *native;
666         struct edid *edid;
667 };
668
669 struct nv50_msto {
670         struct drm_encoder encoder;
671
672         struct nv50_head *head;
673         struct nv50_mstc *mstc;
674         bool disabled;
675 };
676
677 static struct drm_dp_payload *
678 nv50_msto_payload(struct nv50_msto *msto)
679 {
680         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
681         struct nv50_mstc *mstc = msto->mstc;
682         struct nv50_mstm *mstm = mstc->mstm;
683         int vcpi = mstc->port->vcpi.vcpi, i;
684
685         WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock));
686
687         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
688         for (i = 0; i < mstm->mgr.max_payloads; i++) {
689                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
690                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
691                           mstm->outp->base.base.name, i, payload->vcpi,
692                           payload->start_slot, payload->num_slots);
693         }
694
695         for (i = 0; i < mstm->mgr.max_payloads; i++) {
696                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
697                 if (payload->vcpi == vcpi)
698                         return payload;
699         }
700
701         return NULL;
702 }
703
704 static void
705 nv50_msto_cleanup(struct nv50_msto *msto)
706 {
707         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
708         struct nv50_mstc *mstc = msto->mstc;
709         struct nv50_mstm *mstm = mstc->mstm;
710
711         if (!msto->disabled)
712                 return;
713
714         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
715
716         drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
717
718         msto->mstc = NULL;
719         msto->head = NULL;
720         msto->disabled = false;
721 }
722
723 static void
724 nv50_msto_prepare(struct nv50_msto *msto)
725 {
726         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
727         struct nv50_mstc *mstc = msto->mstc;
728         struct nv50_mstm *mstm = mstc->mstm;
729         struct {
730                 struct nv50_disp_mthd_v1 base;
731                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
732         } args = {
733                 .base.version = 1,
734                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
735                 .base.hasht  = mstm->outp->dcb->hasht,
736                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
737                                (0x0100 << msto->head->base.index),
738         };
739
740         mutex_lock(&mstm->mgr.payload_lock);
741
742         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
743         if (mstc->port->vcpi.vcpi > 0) {
744                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
745                 if (payload) {
746                         args.vcpi.start_slot = payload->start_slot;
747                         args.vcpi.num_slots = payload->num_slots;
748                         args.vcpi.pbn = mstc->port->vcpi.pbn;
749                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
750                 }
751         }
752
753         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
754                   msto->encoder.name, msto->head->base.base.name,
755                   args.vcpi.start_slot, args.vcpi.num_slots,
756                   args.vcpi.pbn, args.vcpi.aligned_pbn);
757
758         nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
759         mutex_unlock(&mstm->mgr.payload_lock);
760 }
761
762 static int
763 nv50_msto_atomic_check(struct drm_encoder *encoder,
764                        struct drm_crtc_state *crtc_state,
765                        struct drm_connector_state *conn_state)
766 {
767         struct drm_atomic_state *state = crtc_state->state;
768         struct drm_connector *connector = conn_state->connector;
769         struct nv50_mstc *mstc = nv50_mstc(connector);
770         struct nv50_mstm *mstm = mstc->mstm;
771         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
772         int slots;
773
774         /* When restoring duplicated states, we need to make sure that the
775          * bw remains the same and avoid recalculating it, as the connector's
776          * bpc may have changed after the state was duplicated
777          */
778         if (!state->duplicated)
779                 asyh->dp.pbn =
780                         drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock,
781                                              connector->display_info.bpc * 3);
782
783         if (drm_atomic_crtc_needs_modeset(crtc_state)) {
784                 slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr,
785                                                       mstc->port,
786                                                       asyh->dp.pbn);
787                 if (slots < 0)
788                         return slots;
789
790                 asyh->dp.tu = slots;
791         }
792
793         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
794                                            mstc->native);
795 }
796
797 static void
798 nv50_msto_enable(struct drm_encoder *encoder)
799 {
800         struct nv50_head *head = nv50_head(encoder->crtc);
801         struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state);
802         struct nv50_msto *msto = nv50_msto(encoder);
803         struct nv50_mstc *mstc = NULL;
804         struct nv50_mstm *mstm = NULL;
805         struct drm_connector *connector;
806         struct drm_connector_list_iter conn_iter;
807         u8 proto, depth;
808         bool r;
809
810         drm_connector_list_iter_begin(encoder->dev, &conn_iter);
811         drm_for_each_connector_iter(connector, &conn_iter) {
812                 if (connector->state->best_encoder == &msto->encoder) {
813                         mstc = nv50_mstc(connector);
814                         mstm = mstc->mstm;
815                         break;
816                 }
817         }
818         drm_connector_list_iter_end(&conn_iter);
819
820         if (WARN_ON(!mstc))
821                 return;
822
823         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn,
824                                      armh->dp.tu);
825         if (!r)
826                 DRM_DEBUG_KMS("Failed to allocate VCPI\n");
827
828         if (!mstm->links++)
829                 nv50_outp_acquire(mstm->outp);
830
831         if (mstm->outp->link & 1)
832                 proto = 0x8;
833         else
834                 proto = 0x9;
835
836         switch (mstc->connector.display_info.bpc) {
837         case  6: depth = 0x2; break;
838         case  8: depth = 0x5; break;
839         case 10:
840         default: depth = 0x6; break;
841         }
842
843         mstm->outp->update(mstm->outp, head->base.index, armh, proto, depth);
844
845         msto->head = head;
846         msto->mstc = mstc;
847         mstm->modified = true;
848 }
849
850 static void
851 nv50_msto_disable(struct drm_encoder *encoder)
852 {
853         struct nv50_msto *msto = nv50_msto(encoder);
854         struct nv50_mstc *mstc = msto->mstc;
855         struct nv50_mstm *mstm = mstc->mstm;
856
857         drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
858
859         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
860         mstm->modified = true;
861         if (!--mstm->links)
862                 mstm->disabled = true;
863         msto->disabled = true;
864 }
865
866 static const struct drm_encoder_helper_funcs
867 nv50_msto_help = {
868         .disable = nv50_msto_disable,
869         .enable = nv50_msto_enable,
870         .atomic_check = nv50_msto_atomic_check,
871 };
872
873 static void
874 nv50_msto_destroy(struct drm_encoder *encoder)
875 {
876         struct nv50_msto *msto = nv50_msto(encoder);
877         drm_encoder_cleanup(&msto->encoder);
878         kfree(msto);
879 }
880
881 static const struct drm_encoder_funcs
882 nv50_msto = {
883         .destroy = nv50_msto_destroy,
884 };
885
886 static int
887 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
888               struct nv50_msto **pmsto)
889 {
890         struct nv50_msto *msto;
891         int ret;
892
893         if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
894                 return -ENOMEM;
895
896         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
897                                DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
898         if (ret) {
899                 kfree(*pmsto);
900                 *pmsto = NULL;
901                 return ret;
902         }
903
904         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
905         msto->encoder.possible_crtcs = heads;
906         return 0;
907 }
908
909 static struct drm_encoder *
910 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
911                               struct drm_connector_state *connector_state)
912 {
913         struct nv50_head *head = nv50_head(connector_state->crtc);
914         struct nv50_mstc *mstc = nv50_mstc(connector);
915
916         return &mstc->mstm->msto[head->base.index]->encoder;
917 }
918
919 static struct drm_encoder *
920 nv50_mstc_best_encoder(struct drm_connector *connector)
921 {
922         struct nv50_mstc *mstc = nv50_mstc(connector);
923
924         return &mstc->mstm->msto[0]->encoder;
925 }
926
927 static enum drm_mode_status
928 nv50_mstc_mode_valid(struct drm_connector *connector,
929                      struct drm_display_mode *mode)
930 {
931         return MODE_OK;
932 }
933
934 static int
935 nv50_mstc_get_modes(struct drm_connector *connector)
936 {
937         struct nv50_mstc *mstc = nv50_mstc(connector);
938         int ret = 0;
939
940         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
941         drm_connector_update_edid_property(&mstc->connector, mstc->edid);
942         if (mstc->edid)
943                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
944
945         if (!mstc->connector.display_info.bpc)
946                 mstc->connector.display_info.bpc = 8;
947
948         if (mstc->native)
949                 drm_mode_destroy(mstc->connector.dev, mstc->native);
950         mstc->native = nouveau_conn_native_mode(&mstc->connector);
951         return ret;
952 }
953
954 static int
955 nv50_mstc_atomic_check(struct drm_connector *connector,
956                        struct drm_atomic_state *state)
957 {
958         struct nv50_mstc *mstc = nv50_mstc(connector);
959         struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
960         struct drm_connector_state *new_conn_state =
961                 drm_atomic_get_new_connector_state(state, connector);
962         struct drm_connector_state *old_conn_state =
963                 drm_atomic_get_old_connector_state(state, connector);
964         struct drm_crtc_state *crtc_state;
965         struct drm_crtc *new_crtc = new_conn_state->crtc;
966
967         if (!old_conn_state->crtc)
968                 return 0;
969
970         /* We only want to free VCPI if this state disables the CRTC on this
971          * connector
972          */
973         if (new_crtc) {
974                 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
975
976                 if (!crtc_state ||
977                     !drm_atomic_crtc_needs_modeset(crtc_state) ||
978                     crtc_state->enable)
979                         return 0;
980         }
981
982         return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port);
983 }
984
985 static const struct drm_connector_helper_funcs
986 nv50_mstc_help = {
987         .get_modes = nv50_mstc_get_modes,
988         .mode_valid = nv50_mstc_mode_valid,
989         .best_encoder = nv50_mstc_best_encoder,
990         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
991         .atomic_check = nv50_mstc_atomic_check,
992 };
993
994 static enum drm_connector_status
995 nv50_mstc_detect(struct drm_connector *connector, bool force)
996 {
997         struct nv50_mstc *mstc = nv50_mstc(connector);
998         enum drm_connector_status conn_status;
999         int ret;
1000
1001         if (drm_connector_is_unregistered(connector))
1002                 return connector_status_disconnected;
1003
1004         ret = pm_runtime_get_sync(connector->dev->dev);
1005         if (ret < 0 && ret != -EACCES)
1006                 return connector_status_disconnected;
1007
1008         conn_status = drm_dp_mst_detect_port(connector, mstc->port->mgr,
1009                                              mstc->port);
1010
1011         pm_runtime_mark_last_busy(connector->dev->dev);
1012         pm_runtime_put_autosuspend(connector->dev->dev);
1013         return conn_status;
1014 }
1015
1016 static void
1017 nv50_mstc_destroy(struct drm_connector *connector)
1018 {
1019         struct nv50_mstc *mstc = nv50_mstc(connector);
1020
1021         drm_connector_cleanup(&mstc->connector);
1022         drm_dp_mst_put_port_malloc(mstc->port);
1023
1024         kfree(mstc);
1025 }
1026
1027 static const struct drm_connector_funcs
1028 nv50_mstc = {
1029         .reset = nouveau_conn_reset,
1030         .detect = nv50_mstc_detect,
1031         .fill_modes = drm_helper_probe_single_connector_modes,
1032         .destroy = nv50_mstc_destroy,
1033         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1034         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1035         .atomic_set_property = nouveau_conn_atomic_set_property,
1036         .atomic_get_property = nouveau_conn_atomic_get_property,
1037 };
1038
1039 static int
1040 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1041               const char *path, struct nv50_mstc **pmstc)
1042 {
1043         struct drm_device *dev = mstm->outp->base.base.dev;
1044         struct nv50_mstc *mstc;
1045         int ret, i;
1046
1047         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1048                 return -ENOMEM;
1049         mstc->mstm = mstm;
1050         mstc->port = port;
1051
1052         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1053                                  DRM_MODE_CONNECTOR_DisplayPort);
1054         if (ret) {
1055                 kfree(*pmstc);
1056                 *pmstc = NULL;
1057                 return ret;
1058         }
1059
1060         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1061
1062         mstc->connector.funcs->reset(&mstc->connector);
1063         nouveau_conn_attach_properties(&mstc->connector);
1064
1065         for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++)
1066                 drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
1067
1068         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1069         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1070         drm_connector_set_path_property(&mstc->connector, path);
1071         drm_dp_mst_get_port_malloc(port);
1072         return 0;
1073 }
1074
1075 static void
1076 nv50_mstm_cleanup(struct nv50_mstm *mstm)
1077 {
1078         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1079         struct drm_encoder *encoder;
1080         int ret;
1081
1082         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1083         ret = drm_dp_check_act_status(&mstm->mgr);
1084
1085         ret = drm_dp_update_payload_part2(&mstm->mgr);
1086
1087         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1088                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1089                         struct nv50_msto *msto = nv50_msto(encoder);
1090                         struct nv50_mstc *mstc = msto->mstc;
1091                         if (mstc && mstc->mstm == mstm)
1092                                 nv50_msto_cleanup(msto);
1093                 }
1094         }
1095
1096         mstm->modified = false;
1097 }
1098
1099 static void
1100 nv50_mstm_prepare(struct nv50_mstm *mstm)
1101 {
1102         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1103         struct drm_encoder *encoder;
1104         int ret;
1105
1106         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1107         ret = drm_dp_update_payload_part1(&mstm->mgr);
1108
1109         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1110                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1111                         struct nv50_msto *msto = nv50_msto(encoder);
1112                         struct nv50_mstc *mstc = msto->mstc;
1113                         if (mstc && mstc->mstm == mstm)
1114                                 nv50_msto_prepare(msto);
1115                 }
1116         }
1117
1118         if (mstm->disabled) {
1119                 if (!mstm->links)
1120                         nv50_outp_release(mstm->outp);
1121                 mstm->disabled = false;
1122         }
1123 }
1124
1125 static void
1126 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
1127                             struct drm_connector *connector)
1128 {
1129         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1130         struct nv50_mstc *mstc = nv50_mstc(connector);
1131
1132         drm_connector_unregister(&mstc->connector);
1133
1134         drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
1135
1136         drm_connector_put(&mstc->connector);
1137 }
1138
1139 static void
1140 nv50_mstm_register_connector(struct drm_connector *connector)
1141 {
1142         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1143
1144         drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
1145
1146         drm_connector_register(connector);
1147 }
1148
1149 static struct drm_connector *
1150 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1151                         struct drm_dp_mst_port *port, const char *path)
1152 {
1153         struct nv50_mstm *mstm = nv50_mstm(mgr);
1154         struct nv50_mstc *mstc;
1155         int ret;
1156
1157         ret = nv50_mstc_new(mstm, port, path, &mstc);
1158         if (ret)
1159                 return NULL;
1160
1161         return &mstc->connector;
1162 }
1163
1164 static const struct drm_dp_mst_topology_cbs
1165 nv50_mstm = {
1166         .add_connector = nv50_mstm_add_connector,
1167         .register_connector = nv50_mstm_register_connector,
1168         .destroy_connector = nv50_mstm_destroy_connector,
1169 };
1170
1171 void
1172 nv50_mstm_service(struct nv50_mstm *mstm)
1173 {
1174         struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1175         bool handled = true;
1176         int ret;
1177         u8 esi[8] = {};
1178
1179         if (!aux)
1180                 return;
1181
1182         while (handled) {
1183                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1184                 if (ret != 8) {
1185                         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1186                         return;
1187                 }
1188
1189                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1190                 if (!handled)
1191                         break;
1192
1193                 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
1194         }
1195 }
1196
1197 void
1198 nv50_mstm_remove(struct nv50_mstm *mstm)
1199 {
1200         if (mstm)
1201                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1202 }
1203
1204 static int
1205 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1206 {
1207         struct nouveau_encoder *outp = mstm->outp;
1208         struct {
1209                 struct nv50_disp_mthd_v1 base;
1210                 struct nv50_disp_sor_dp_mst_link_v0 mst;
1211         } args = {
1212                 .base.version = 1,
1213                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1214                 .base.hasht = outp->dcb->hasht,
1215                 .base.hashm = outp->dcb->hashm,
1216                 .mst.state = state,
1217         };
1218         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1219         struct nvif_object *disp = &drm->display->disp.object;
1220         int ret;
1221
1222         if (dpcd >= 0x12) {
1223                 /* Even if we're enabling MST, start with disabling the
1224                  * branching unit to clear any sink-side MST topology state
1225                  * that wasn't set by us
1226                  */
1227                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1228                 if (ret < 0)
1229                         return ret;
1230
1231                 if (state) {
1232                         /* Now, start initializing */
1233                         ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1234                                                  DP_MST_EN);
1235                         if (ret < 0)
1236                                 return ret;
1237                 }
1238         }
1239
1240         return nvif_mthd(disp, 0, &args, sizeof(args));
1241 }
1242
1243 int
1244 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1245 {
1246         struct drm_dp_aux *aux;
1247         int ret;
1248         bool old_state, new_state;
1249         u8 mstm_ctrl;
1250
1251         if (!mstm)
1252                 return 0;
1253
1254         mutex_lock(&mstm->mgr.lock);
1255
1256         old_state = mstm->mgr.mst_state;
1257         new_state = old_state;
1258         aux = mstm->mgr.aux;
1259
1260         if (old_state) {
1261                 /* Just check that the MST hub is still as we expect it */
1262                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1263                 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) {
1264                         DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1265                         new_state = false;
1266                 }
1267         } else if (dpcd[0] >= 0x12) {
1268                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1269                 if (ret < 0)
1270                         goto probe_error;
1271
1272                 if (!(dpcd[1] & DP_MST_CAP))
1273                         dpcd[0] = 0x11;
1274                 else
1275                         new_state = allow;
1276         }
1277
1278         if (new_state == old_state) {
1279                 mutex_unlock(&mstm->mgr.lock);
1280                 return new_state;
1281         }
1282
1283         ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1284         if (ret)
1285                 goto probe_error;
1286
1287         mutex_unlock(&mstm->mgr.lock);
1288
1289         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1290         if (ret)
1291                 return nv50_mstm_enable(mstm, dpcd[0], 0);
1292
1293         return new_state;
1294
1295 probe_error:
1296         mutex_unlock(&mstm->mgr.lock);
1297         return ret;
1298 }
1299
1300 static void
1301 nv50_mstm_fini(struct nv50_mstm *mstm)
1302 {
1303         if (mstm && mstm->mgr.mst_state)
1304                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1305 }
1306
1307 static void
1308 nv50_mstm_init(struct nv50_mstm *mstm)
1309 {
1310         int ret;
1311
1312         if (!mstm || !mstm->mgr.mst_state)
1313                 return;
1314
1315         ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr);
1316         if (ret == -1) {
1317                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1318                 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1319         }
1320 }
1321
1322 static void
1323 nv50_mstm_del(struct nv50_mstm **pmstm)
1324 {
1325         struct nv50_mstm *mstm = *pmstm;
1326         if (mstm) {
1327                 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1328                 kfree(*pmstm);
1329                 *pmstm = NULL;
1330         }
1331 }
1332
1333 static int
1334 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1335               int conn_base_id, struct nv50_mstm **pmstm)
1336 {
1337         const int max_payloads = hweight8(outp->dcb->heads);
1338         struct drm_device *dev = outp->base.base.dev;
1339         struct nv50_mstm *mstm;
1340         int ret, i;
1341         u8 dpcd;
1342
1343         /* This is a workaround for some monitors not functioning
1344          * correctly in MST mode on initial module load.  I think
1345          * some bad interaction with the VBIOS may be responsible.
1346          *
1347          * A good ol' off and on again seems to work here ;)
1348          */
1349         ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1350         if (ret >= 0 && dpcd >= 0x12)
1351                 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1352
1353         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1354                 return -ENOMEM;
1355         mstm->outp = outp;
1356         mstm->mgr.cbs = &nv50_mstm;
1357
1358         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1359                                            max_payloads, conn_base_id);
1360         if (ret)
1361                 return ret;
1362
1363         for (i = 0; i < max_payloads; i++) {
1364                 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
1365                                     i, &mstm->msto[i]);
1366                 if (ret)
1367                         return ret;
1368         }
1369
1370         return 0;
1371 }
1372
1373 /******************************************************************************
1374  * SOR
1375  *****************************************************************************/
1376 static void
1377 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1378                 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1379 {
1380         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1381         struct nv50_core *core = disp->core;
1382
1383         if (!asyh) {
1384                 nv_encoder->ctrl &= ~BIT(head);
1385                 if (!(nv_encoder->ctrl & 0x0000000f))
1386                         nv_encoder->ctrl = 0;
1387         } else {
1388                 nv_encoder->ctrl |= proto << 8;
1389                 nv_encoder->ctrl |= BIT(head);
1390                 asyh->or.depth = depth;
1391         }
1392
1393         core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1394 }
1395
1396 static void
1397 nv50_sor_disable(struct drm_encoder *encoder)
1398 {
1399         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1400         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1401
1402         nv_encoder->crtc = NULL;
1403
1404         if (nv_crtc) {
1405                 struct nvkm_i2c_aux *aux = nv_encoder->aux;
1406                 u8 pwr;
1407
1408                 if (aux) {
1409                         int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
1410                         if (ret == 0) {
1411                                 pwr &= ~DP_SET_POWER_MASK;
1412                                 pwr |=  DP_SET_POWER_D3;
1413                                 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
1414                         }
1415                 }
1416
1417                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1418                 nv50_audio_disable(encoder, nv_crtc);
1419                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1420                 nv50_outp_release(nv_encoder);
1421         }
1422 }
1423
1424 static void
1425 nv50_sor_enable(struct drm_encoder *encoder)
1426 {
1427         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1428         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1429         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1430         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1431         struct {
1432                 struct nv50_disp_mthd_v1 base;
1433                 struct nv50_disp_sor_lvds_script_v0 lvds;
1434         } lvds = {
1435                 .base.version = 1,
1436                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1437                 .base.hasht   = nv_encoder->dcb->hasht,
1438                 .base.hashm   = nv_encoder->dcb->hashm,
1439         };
1440         struct nv50_disp *disp = nv50_disp(encoder->dev);
1441         struct drm_device *dev = encoder->dev;
1442         struct nouveau_drm *drm = nouveau_drm(dev);
1443         struct nouveau_connector *nv_connector;
1444         struct nvbios *bios = &drm->vbios;
1445         u8 proto = 0xf;
1446         u8 depth = 0x0;
1447
1448         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1449         nv_encoder->crtc = encoder->crtc;
1450         nv50_outp_acquire(nv_encoder);
1451
1452         switch (nv_encoder->dcb->type) {
1453         case DCB_OUTPUT_TMDS:
1454                 if (nv_encoder->link & 1) {
1455                         proto = 0x1;
1456                         /* Only enable dual-link if:
1457                          *  - Need to (i.e. rate > 165MHz)
1458                          *  - DCB says we can
1459                          *  - Not an HDMI monitor, since there's no dual-link
1460                          *    on HDMI.
1461                          */
1462                         if (mode->clock >= 165000 &&
1463                             nv_encoder->dcb->duallink_possible &&
1464                             !drm_detect_hdmi_monitor(nv_connector->edid))
1465                                 proto |= 0x4;
1466                 } else {
1467                         proto = 0x2;
1468                 }
1469
1470                 nv50_hdmi_enable(&nv_encoder->base.base, mode);
1471                 break;
1472         case DCB_OUTPUT_LVDS:
1473                 proto = 0x0;
1474
1475                 if (bios->fp_no_ddc) {
1476                         if (bios->fp.dual_link)
1477                                 lvds.lvds.script |= 0x0100;
1478                         if (bios->fp.if_is_24bit)
1479                                 lvds.lvds.script |= 0x0200;
1480                 } else {
1481                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1482                                 if (((u8 *)nv_connector->edid)[121] == 2)
1483                                         lvds.lvds.script |= 0x0100;
1484                         } else
1485                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1486                                 lvds.lvds.script |= 0x0100;
1487                         }
1488
1489                         if (lvds.lvds.script & 0x0100) {
1490                                 if (bios->fp.strapless_is_24bit & 2)
1491                                         lvds.lvds.script |= 0x0200;
1492                         } else {
1493                                 if (bios->fp.strapless_is_24bit & 1)
1494                                         lvds.lvds.script |= 0x0200;
1495                         }
1496
1497                         if (nv_connector->base.display_info.bpc == 8)
1498                                 lvds.lvds.script |= 0x0200;
1499                 }
1500
1501                 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1502                 break;
1503         case DCB_OUTPUT_DP:
1504                 if (nv_connector->base.display_info.bpc == 6)
1505                         depth = 0x2;
1506                 else
1507                 if (nv_connector->base.display_info.bpc == 8)
1508                         depth = 0x5;
1509                 else
1510                         depth = 0x6;
1511
1512                 if (nv_encoder->link & 1)
1513                         proto = 0x8;
1514                 else
1515                         proto = 0x9;
1516
1517                 nv50_audio_enable(encoder, mode);
1518                 break;
1519         default:
1520                 BUG();
1521                 break;
1522         }
1523
1524         nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1525 }
1526
1527 static const struct drm_encoder_helper_funcs
1528 nv50_sor_help = {
1529         .atomic_check = nv50_outp_atomic_check,
1530         .enable = nv50_sor_enable,
1531         .disable = nv50_sor_disable,
1532 };
1533
1534 static void
1535 nv50_sor_destroy(struct drm_encoder *encoder)
1536 {
1537         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1538         nv50_mstm_del(&nv_encoder->dp.mstm);
1539         drm_encoder_cleanup(encoder);
1540         kfree(encoder);
1541 }
1542
1543 static const struct drm_encoder_funcs
1544 nv50_sor_func = {
1545         .destroy = nv50_sor_destroy,
1546 };
1547
1548 static int
1549 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1550 {
1551         struct nouveau_connector *nv_connector = nouveau_connector(connector);
1552         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1553         struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1554         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1555         struct nouveau_encoder *nv_encoder;
1556         struct drm_encoder *encoder;
1557         u8 ver, hdr, cnt, len;
1558         u32 data;
1559         int type, ret;
1560
1561         switch (dcbe->type) {
1562         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1563         case DCB_OUTPUT_TMDS:
1564         case DCB_OUTPUT_DP:
1565         default:
1566                 type = DRM_MODE_ENCODER_TMDS;
1567                 break;
1568         }
1569
1570         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1571         if (!nv_encoder)
1572                 return -ENOMEM;
1573         nv_encoder->dcb = dcbe;
1574         nv_encoder->update = nv50_sor_update;
1575
1576         encoder = to_drm_encoder(nv_encoder);
1577         encoder->possible_crtcs = dcbe->heads;
1578         encoder->possible_clones = 0;
1579         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1580                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1581         drm_encoder_helper_add(encoder, &nv50_sor_help);
1582
1583         drm_connector_attach_encoder(connector, encoder);
1584
1585         if (dcbe->type == DCB_OUTPUT_DP) {
1586                 struct nv50_disp *disp = nv50_disp(encoder->dev);
1587                 struct nvkm_i2c_aux *aux =
1588                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1589                 if (aux) {
1590                         if (disp->disp->object.oclass < GF110_DISP) {
1591                                 /* HW has no support for address-only
1592                                  * transactions, so we're required to
1593                                  * use custom I2C-over-AUX code.
1594                                  */
1595                                 nv_encoder->i2c = &aux->i2c;
1596                         } else {
1597                                 nv_encoder->i2c = &nv_connector->aux.ddc;
1598                         }
1599                         nv_encoder->aux = aux;
1600                 }
1601
1602                 if ((data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) &&
1603                     ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) {
1604                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
1605                                             nv_connector->base.base.id,
1606                                             &nv_encoder->dp.mstm);
1607                         if (ret)
1608                                 return ret;
1609                 }
1610         } else {
1611                 struct nvkm_i2c_bus *bus =
1612                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1613                 if (bus)
1614                         nv_encoder->i2c = &bus->i2c;
1615         }
1616
1617         return 0;
1618 }
1619
1620 /******************************************************************************
1621  * PIOR
1622  *****************************************************************************/
1623 static int
1624 nv50_pior_atomic_check(struct drm_encoder *encoder,
1625                        struct drm_crtc_state *crtc_state,
1626                        struct drm_connector_state *conn_state)
1627 {
1628         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1629         if (ret)
1630                 return ret;
1631         crtc_state->adjusted_mode.clock *= 2;
1632         return 0;
1633 }
1634
1635 static void
1636 nv50_pior_disable(struct drm_encoder *encoder)
1637 {
1638         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1639         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1640         if (nv_encoder->crtc)
1641                 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL);
1642         nv_encoder->crtc = NULL;
1643         nv50_outp_release(nv_encoder);
1644 }
1645
1646 static void
1647 nv50_pior_enable(struct drm_encoder *encoder)
1648 {
1649         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1650         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1651         struct nouveau_connector *nv_connector;
1652         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1653         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1654         u8 owner = 1 << nv_crtc->index;
1655         u8 proto;
1656
1657         nv50_outp_acquire(nv_encoder);
1658
1659         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1660         switch (nv_connector->base.display_info.bpc) {
1661         case 10: asyh->or.depth = 0x6; break;
1662         case  8: asyh->or.depth = 0x5; break;
1663         case  6: asyh->or.depth = 0x2; break;
1664         default: asyh->or.depth = 0x0; break;
1665         }
1666
1667         switch (nv_encoder->dcb->type) {
1668         case DCB_OUTPUT_TMDS:
1669         case DCB_OUTPUT_DP:
1670                 proto = 0x0;
1671                 break;
1672         default:
1673                 BUG();
1674                 break;
1675         }
1676
1677         core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh);
1678         nv_encoder->crtc = encoder->crtc;
1679 }
1680
1681 static const struct drm_encoder_helper_funcs
1682 nv50_pior_help = {
1683         .atomic_check = nv50_pior_atomic_check,
1684         .enable = nv50_pior_enable,
1685         .disable = nv50_pior_disable,
1686 };
1687
1688 static void
1689 nv50_pior_destroy(struct drm_encoder *encoder)
1690 {
1691         drm_encoder_cleanup(encoder);
1692         kfree(encoder);
1693 }
1694
1695 static const struct drm_encoder_funcs
1696 nv50_pior_func = {
1697         .destroy = nv50_pior_destroy,
1698 };
1699
1700 static int
1701 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1702 {
1703         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1704         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1705         struct nvkm_i2c_bus *bus = NULL;
1706         struct nvkm_i2c_aux *aux = NULL;
1707         struct i2c_adapter *ddc;
1708         struct nouveau_encoder *nv_encoder;
1709         struct drm_encoder *encoder;
1710         int type;
1711
1712         switch (dcbe->type) {
1713         case DCB_OUTPUT_TMDS:
1714                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1715                 ddc  = bus ? &bus->i2c : NULL;
1716                 type = DRM_MODE_ENCODER_TMDS;
1717                 break;
1718         case DCB_OUTPUT_DP:
1719                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1720                 ddc  = aux ? &aux->i2c : NULL;
1721                 type = DRM_MODE_ENCODER_TMDS;
1722                 break;
1723         default:
1724                 return -ENODEV;
1725         }
1726
1727         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1728         if (!nv_encoder)
1729                 return -ENOMEM;
1730         nv_encoder->dcb = dcbe;
1731         nv_encoder->i2c = ddc;
1732         nv_encoder->aux = aux;
1733
1734         encoder = to_drm_encoder(nv_encoder);
1735         encoder->possible_crtcs = dcbe->heads;
1736         encoder->possible_clones = 0;
1737         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1738                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1739         drm_encoder_helper_add(encoder, &nv50_pior_help);
1740
1741         drm_connector_attach_encoder(connector, encoder);
1742         return 0;
1743 }
1744
1745 /******************************************************************************
1746  * Atomic
1747  *****************************************************************************/
1748
1749 static void
1750 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1751 {
1752         struct nouveau_drm *drm = nouveau_drm(state->dev);
1753         struct nv50_disp *disp = nv50_disp(drm->dev);
1754         struct nv50_core *core = disp->core;
1755         struct nv50_mstm *mstm;
1756         struct drm_encoder *encoder;
1757
1758         NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1759
1760         drm_for_each_encoder(encoder, drm->dev) {
1761                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1762                         mstm = nouveau_encoder(encoder)->dp.mstm;
1763                         if (mstm && mstm->modified)
1764                                 nv50_mstm_prepare(mstm);
1765                 }
1766         }
1767
1768         core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1769         core->func->update(core, interlock, true);
1770         if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1771                                        disp->core->chan.base.device))
1772                 NV_ERROR(drm, "core notifier timeout\n");
1773
1774         drm_for_each_encoder(encoder, drm->dev) {
1775                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1776                         mstm = nouveau_encoder(encoder)->dp.mstm;
1777                         if (mstm && mstm->modified)
1778                                 nv50_mstm_cleanup(mstm);
1779                 }
1780         }
1781 }
1782
1783 static void
1784 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1785 {
1786         struct drm_plane_state *new_plane_state;
1787         struct drm_plane *plane;
1788         int i;
1789
1790         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1791                 struct nv50_wndw *wndw = nv50_wndw(plane);
1792                 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1793                         if (wndw->func->update)
1794                                 wndw->func->update(wndw, interlock);
1795                 }
1796         }
1797 }
1798
1799 static void
1800 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1801 {
1802         struct drm_device *dev = state->dev;
1803         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
1804         struct drm_crtc *crtc;
1805         struct drm_plane_state *new_plane_state;
1806         struct drm_plane *plane;
1807         struct nouveau_drm *drm = nouveau_drm(dev);
1808         struct nv50_disp *disp = nv50_disp(dev);
1809         struct nv50_atom *atom = nv50_atom(state);
1810         struct nv50_outp_atom *outp, *outt;
1811         u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
1812         int i;
1813
1814         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
1815         drm_atomic_helper_wait_for_fences(dev, state, false);
1816         drm_atomic_helper_wait_for_dependencies(state);
1817         drm_atomic_helper_update_legacy_modeset_state(dev, state);
1818
1819         if (atom->lock_core)
1820                 mutex_lock(&disp->mutex);
1821
1822         /* Disable head(s). */
1823         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1824                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1825                 struct nv50_head *head = nv50_head(crtc);
1826
1827                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
1828                           asyh->clr.mask, asyh->set.mask);
1829                 if (old_crtc_state->active && !new_crtc_state->active)
1830                         drm_crtc_vblank_off(crtc);
1831
1832                 if (asyh->clr.mask) {
1833                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
1834                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1835                 }
1836         }
1837
1838         /* Disable plane(s). */
1839         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1840                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1841                 struct nv50_wndw *wndw = nv50_wndw(plane);
1842
1843                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
1844                           asyw->clr.mask, asyw->set.mask);
1845                 if (!asyw->clr.mask)
1846                         continue;
1847
1848                 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
1849         }
1850
1851         /* Disable output path(s). */
1852         list_for_each_entry(outp, &atom->outp, head) {
1853                 const struct drm_encoder_helper_funcs *help;
1854                 struct drm_encoder *encoder;
1855
1856                 encoder = outp->encoder;
1857                 help = encoder->helper_private;
1858
1859                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
1860                           outp->clr.mask, outp->set.mask);
1861
1862                 if (outp->clr.mask) {
1863                         help->disable(encoder);
1864                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1865                         if (outp->flush_disable) {
1866                                 nv50_disp_atomic_commit_wndw(state, interlock);
1867                                 nv50_disp_atomic_commit_core(state, interlock);
1868                                 memset(interlock, 0x00, sizeof(interlock));
1869                         }
1870                 }
1871         }
1872
1873         /* Flush disable. */
1874         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1875                 if (atom->flush_disable) {
1876                         nv50_disp_atomic_commit_wndw(state, interlock);
1877                         nv50_disp_atomic_commit_core(state, interlock);
1878                         memset(interlock, 0x00, sizeof(interlock));
1879                 }
1880         }
1881
1882         /* Update output path(s). */
1883         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
1884                 const struct drm_encoder_helper_funcs *help;
1885                 struct drm_encoder *encoder;
1886
1887                 encoder = outp->encoder;
1888                 help = encoder->helper_private;
1889
1890                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
1891                           outp->set.mask, outp->clr.mask);
1892
1893                 if (outp->set.mask) {
1894                         help->enable(encoder);
1895                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1896                 }
1897
1898                 list_del(&outp->head);
1899                 kfree(outp);
1900         }
1901
1902         /* Update head(s). */
1903         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1904                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1905                 struct nv50_head *head = nv50_head(crtc);
1906
1907                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
1908                           asyh->set.mask, asyh->clr.mask);
1909
1910                 if (asyh->set.mask) {
1911                         nv50_head_flush_set(head, asyh);
1912                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1913                 }
1914
1915                 if (new_crtc_state->active) {
1916                         if (!old_crtc_state->active)
1917                                 drm_crtc_vblank_on(crtc);
1918                         if (new_crtc_state->event)
1919                                 drm_crtc_vblank_get(crtc);
1920                 }
1921         }
1922
1923         /* Update plane(s). */
1924         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1925                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1926                 struct nv50_wndw *wndw = nv50_wndw(plane);
1927
1928                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
1929                           asyw->set.mask, asyw->clr.mask);
1930                 if ( !asyw->set.mask &&
1931                     (!asyw->clr.mask || atom->flush_disable))
1932                         continue;
1933
1934                 nv50_wndw_flush_set(wndw, interlock, asyw);
1935         }
1936
1937         /* Flush update. */
1938         nv50_disp_atomic_commit_wndw(state, interlock);
1939
1940         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1941                 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
1942                     interlock[NV50_DISP_INTERLOCK_OVLY] ||
1943                     interlock[NV50_DISP_INTERLOCK_WNDW] ||
1944                     !atom->state.legacy_cursor_update)
1945                         nv50_disp_atomic_commit_core(state, interlock);
1946                 else
1947                         disp->core->func->update(disp->core, interlock, false);
1948         }
1949
1950         if (atom->lock_core)
1951                 mutex_unlock(&disp->mutex);
1952
1953         /* Wait for HW to signal completion. */
1954         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1955                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1956                 struct nv50_wndw *wndw = nv50_wndw(plane);
1957                 int ret = nv50_wndw_wait_armed(wndw, asyw);
1958                 if (ret)
1959                         NV_ERROR(drm, "%s: timeout\n", plane->name);
1960         }
1961
1962         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
1963                 if (new_crtc_state->event) {
1964                         unsigned long flags;
1965                         /* Get correct count/ts if racing with vblank irq */
1966                         if (new_crtc_state->active)
1967                                 drm_crtc_accurate_vblank_count(crtc);
1968                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
1969                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
1970                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1971
1972                         new_crtc_state->event = NULL;
1973                         if (new_crtc_state->active)
1974                                 drm_crtc_vblank_put(crtc);
1975                 }
1976         }
1977
1978         drm_atomic_helper_commit_hw_done(state);
1979         drm_atomic_helper_cleanup_planes(dev, state);
1980         drm_atomic_helper_commit_cleanup_done(state);
1981         drm_atomic_state_put(state);
1982 }
1983
1984 static void
1985 nv50_disp_atomic_commit_work(struct work_struct *work)
1986 {
1987         struct drm_atomic_state *state =
1988                 container_of(work, typeof(*state), commit_work);
1989         nv50_disp_atomic_commit_tail(state);
1990 }
1991
1992 static int
1993 nv50_disp_atomic_commit(struct drm_device *dev,
1994                         struct drm_atomic_state *state, bool nonblock)
1995 {
1996         struct nouveau_drm *drm = nouveau_drm(dev);
1997         struct drm_plane_state *new_plane_state;
1998         struct drm_plane *plane;
1999         struct drm_crtc *crtc;
2000         bool active = false;
2001         int ret, i;
2002
2003         ret = pm_runtime_get_sync(dev->dev);
2004         if (ret < 0 && ret != -EACCES)
2005                 return ret;
2006
2007         ret = drm_atomic_helper_setup_commit(state, nonblock);
2008         if (ret)
2009                 goto done;
2010
2011         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2012
2013         ret = drm_atomic_helper_prepare_planes(dev, state);
2014         if (ret)
2015                 goto done;
2016
2017         if (!nonblock) {
2018                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2019                 if (ret)
2020                         goto err_cleanup;
2021         }
2022
2023         ret = drm_atomic_helper_swap_state(state, true);
2024         if (ret)
2025                 goto err_cleanup;
2026
2027         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2028                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2029                 struct nv50_wndw *wndw = nv50_wndw(plane);
2030
2031                 if (asyw->set.image)
2032                         nv50_wndw_ntfy_enable(wndw, asyw);
2033         }
2034
2035         drm_atomic_state_get(state);
2036
2037         if (nonblock)
2038                 queue_work(system_unbound_wq, &state->commit_work);
2039         else
2040                 nv50_disp_atomic_commit_tail(state);
2041
2042         drm_for_each_crtc(crtc, dev) {
2043                 if (crtc->state->active) {
2044                         if (!drm->have_disp_power_ref) {
2045                                 drm->have_disp_power_ref = true;
2046                                 return 0;
2047                         }
2048                         active = true;
2049                         break;
2050                 }
2051         }
2052
2053         if (!active && drm->have_disp_power_ref) {
2054                 pm_runtime_put_autosuspend(dev->dev);
2055                 drm->have_disp_power_ref = false;
2056         }
2057
2058 err_cleanup:
2059         if (ret)
2060                 drm_atomic_helper_cleanup_planes(dev, state);
2061 done:
2062         pm_runtime_put_autosuspend(dev->dev);
2063         return ret;
2064 }
2065
2066 static struct nv50_outp_atom *
2067 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2068 {
2069         struct nv50_outp_atom *outp;
2070
2071         list_for_each_entry(outp, &atom->outp, head) {
2072                 if (outp->encoder == encoder)
2073                         return outp;
2074         }
2075
2076         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2077         if (!outp)
2078                 return ERR_PTR(-ENOMEM);
2079
2080         list_add(&outp->head, &atom->outp);
2081         outp->encoder = encoder;
2082         return outp;
2083 }
2084
2085 static int
2086 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2087                                 struct drm_connector_state *old_connector_state)
2088 {
2089         struct drm_encoder *encoder = old_connector_state->best_encoder;
2090         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2091         struct drm_crtc *crtc;
2092         struct nv50_outp_atom *outp;
2093
2094         if (!(crtc = old_connector_state->crtc))
2095                 return 0;
2096
2097         old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2098         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2099         if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2100                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2101                 if (IS_ERR(outp))
2102                         return PTR_ERR(outp);
2103
2104                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2105                         outp->flush_disable = true;
2106                         atom->flush_disable = true;
2107                 }
2108                 outp->clr.ctrl = true;
2109                 atom->lock_core = true;
2110         }
2111
2112         return 0;
2113 }
2114
2115 static int
2116 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2117                                 struct drm_connector_state *connector_state)
2118 {
2119         struct drm_encoder *encoder = connector_state->best_encoder;
2120         struct drm_crtc_state *new_crtc_state;
2121         struct drm_crtc *crtc;
2122         struct nv50_outp_atom *outp;
2123
2124         if (!(crtc = connector_state->crtc))
2125                 return 0;
2126
2127         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2128         if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2129                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2130                 if (IS_ERR(outp))
2131                         return PTR_ERR(outp);
2132
2133                 outp->set.ctrl = true;
2134                 atom->lock_core = true;
2135         }
2136
2137         return 0;
2138 }
2139
2140 static int
2141 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2142 {
2143         struct nv50_atom *atom = nv50_atom(state);
2144         struct drm_connector_state *old_connector_state, *new_connector_state;
2145         struct drm_connector *connector;
2146         struct drm_crtc_state *new_crtc_state;
2147         struct drm_crtc *crtc;
2148         int ret, i;
2149
2150         /* We need to handle colour management on a per-plane basis. */
2151         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2152                 if (new_crtc_state->color_mgmt_changed) {
2153                         ret = drm_atomic_add_affected_planes(state, crtc);
2154                         if (ret)
2155                                 return ret;
2156                 }
2157         }
2158
2159         ret = drm_atomic_helper_check(dev, state);
2160         if (ret)
2161                 return ret;
2162
2163         for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2164                 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2165                 if (ret)
2166                         return ret;
2167
2168                 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2169                 if (ret)
2170                         return ret;
2171         }
2172
2173         ret = drm_dp_mst_atomic_check(state);
2174         if (ret)
2175                 return ret;
2176
2177         return 0;
2178 }
2179
2180 static void
2181 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2182 {
2183         struct nv50_atom *atom = nv50_atom(state);
2184         struct nv50_outp_atom *outp, *outt;
2185
2186         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2187                 list_del(&outp->head);
2188                 kfree(outp);
2189         }
2190
2191         drm_atomic_state_default_clear(state);
2192 }
2193
2194 static void
2195 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2196 {
2197         struct nv50_atom *atom = nv50_atom(state);
2198         drm_atomic_state_default_release(&atom->state);
2199         kfree(atom);
2200 }
2201
2202 static struct drm_atomic_state *
2203 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2204 {
2205         struct nv50_atom *atom;
2206         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2207             drm_atomic_state_init(dev, &atom->state) < 0) {
2208                 kfree(atom);
2209                 return NULL;
2210         }
2211         INIT_LIST_HEAD(&atom->outp);
2212         return &atom->state;
2213 }
2214
2215 static const struct drm_mode_config_funcs
2216 nv50_disp_func = {
2217         .fb_create = nouveau_user_framebuffer_create,
2218         .output_poll_changed = nouveau_fbcon_output_poll_changed,
2219         .atomic_check = nv50_disp_atomic_check,
2220         .atomic_commit = nv50_disp_atomic_commit,
2221         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2222         .atomic_state_clear = nv50_disp_atomic_state_clear,
2223         .atomic_state_free = nv50_disp_atomic_state_free,
2224 };
2225
2226 /******************************************************************************
2227  * Init
2228  *****************************************************************************/
2229
2230 static void
2231 nv50_display_fini(struct drm_device *dev, bool suspend)
2232 {
2233         struct nouveau_encoder *nv_encoder;
2234         struct drm_encoder *encoder;
2235         struct drm_plane *plane;
2236
2237         drm_for_each_plane(plane, dev) {
2238                 struct nv50_wndw *wndw = nv50_wndw(plane);
2239                 if (plane->funcs != &nv50_wndw)
2240                         continue;
2241                 nv50_wndw_fini(wndw);
2242         }
2243
2244         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2245                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2246                         nv_encoder = nouveau_encoder(encoder);
2247                         nv50_mstm_fini(nv_encoder->dp.mstm);
2248                 }
2249         }
2250 }
2251
2252 static int
2253 nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2254 {
2255         struct nv50_core *core = nv50_disp(dev)->core;
2256         struct drm_encoder *encoder;
2257         struct drm_plane *plane;
2258
2259         core->func->init(core);
2260
2261         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2262                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2263                         struct nouveau_encoder *nv_encoder =
2264                                 nouveau_encoder(encoder);
2265                         nv50_mstm_init(nv_encoder->dp.mstm);
2266                 }
2267         }
2268
2269         drm_for_each_plane(plane, dev) {
2270                 struct nv50_wndw *wndw = nv50_wndw(plane);
2271                 if (plane->funcs != &nv50_wndw)
2272                         continue;
2273                 nv50_wndw_init(wndw);
2274         }
2275
2276         return 0;
2277 }
2278
2279 static void
2280 nv50_display_destroy(struct drm_device *dev)
2281 {
2282         struct nv50_disp *disp = nv50_disp(dev);
2283
2284         nv50_core_del(&disp->core);
2285
2286         nouveau_bo_unmap(disp->sync);
2287         if (disp->sync)
2288                 nouveau_bo_unpin(disp->sync);
2289         nouveau_bo_ref(NULL, &disp->sync);
2290
2291         nouveau_display(dev)->priv = NULL;
2292         kfree(disp);
2293 }
2294
2295 int
2296 nv50_display_create(struct drm_device *dev)
2297 {
2298         struct nvif_device *device = &nouveau_drm(dev)->client.device;
2299         struct nouveau_drm *drm = nouveau_drm(dev);
2300         struct dcb_table *dcb = &drm->vbios.dcb;
2301         struct drm_connector *connector, *tmp;
2302         struct nv50_disp *disp;
2303         struct dcb_output *dcbe;
2304         int crtcs, ret, i;
2305
2306         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2307         if (!disp)
2308                 return -ENOMEM;
2309
2310         mutex_init(&disp->mutex);
2311
2312         nouveau_display(dev)->priv = disp;
2313         nouveau_display(dev)->dtor = nv50_display_destroy;
2314         nouveau_display(dev)->init = nv50_display_init;
2315         nouveau_display(dev)->fini = nv50_display_fini;
2316         disp->disp = &nouveau_display(dev)->disp;
2317         dev->mode_config.funcs = &nv50_disp_func;
2318         dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2319
2320         /* small shared memory area we use for notifiers and semaphores */
2321         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2322                              0, 0x0000, NULL, NULL, &disp->sync);
2323         if (!ret) {
2324                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2325                 if (!ret) {
2326                         ret = nouveau_bo_map(disp->sync);
2327                         if (ret)
2328                                 nouveau_bo_unpin(disp->sync);
2329                 }
2330                 if (ret)
2331                         nouveau_bo_ref(NULL, &disp->sync);
2332         }
2333
2334         if (ret)
2335                 goto out;
2336
2337         /* allocate master evo channel */
2338         ret = nv50_core_new(drm, &disp->core);
2339         if (ret)
2340                 goto out;
2341
2342         /* create crtc objects to represent the hw heads */
2343         if (disp->disp->object.oclass >= GV100_DISP)
2344                 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2345         else
2346         if (disp->disp->object.oclass >= GF110_DISP)
2347                 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2348         else
2349                 crtcs = 0x3;
2350
2351         for (i = 0; i < fls(crtcs); i++) {
2352                 if (!(crtcs & (1 << i)))
2353                         continue;
2354                 ret = nv50_head_create(dev, i);
2355                 if (ret)
2356                         goto out;
2357         }
2358
2359         /* create encoder/connector objects based on VBIOS DCB table */
2360         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2361                 connector = nouveau_connector_create(dev, dcbe);
2362                 if (IS_ERR(connector))
2363                         continue;
2364
2365                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2366                         switch (dcbe->type) {
2367                         case DCB_OUTPUT_TMDS:
2368                         case DCB_OUTPUT_LVDS:
2369                         case DCB_OUTPUT_DP:
2370                                 ret = nv50_sor_create(connector, dcbe);
2371                                 break;
2372                         case DCB_OUTPUT_ANALOG:
2373                                 ret = nv50_dac_create(connector, dcbe);
2374                                 break;
2375                         default:
2376                                 ret = -ENODEV;
2377                                 break;
2378                         }
2379                 } else {
2380                         ret = nv50_pior_create(connector, dcbe);
2381                 }
2382
2383                 if (ret) {
2384                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2385                                      dcbe->location, dcbe->type,
2386                                      ffs(dcbe->or) - 1, ret);
2387                         ret = 0;
2388                 }
2389         }
2390
2391         /* cull any connectors we created that don't have an encoder */
2392         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2393                 if (connector->encoder_ids[0])
2394                         continue;
2395
2396                 NV_WARN(drm, "%s has no encoders, removing\n",
2397                         connector->name);
2398                 connector->funcs->destroy(connector);
2399         }
2400
2401         /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2402         dev->vblank_disable_immediate = true;
2403
2404 out:
2405         if (ret)
2406                 nv50_display_destroy(dev);
2407         return ret;
2408 }