drivers/gpu/drm/nouveau/core/engine/disp/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <subdev/bar.h>
  26
  27 #include <engine/software.h>
  28 #include <engine/disp.h>
  29
  30 struct nv50_disp_priv {
  31         struct nouveau_disp base;
  32 };
  33
  34 static struct nouveau_oclass
  35 nv50_disp_sclass[] = {
  36         {},
  37 };
  38
  39 static void
  40 nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc)
  41 {
  42         struct nouveau_bar *bar = nouveau_bar(priv);
  43         struct nouveau_disp *disp = &priv->base;
  44         struct nouveau_software_chan *chan, *temp;
  45         unsigned long flags;
  46
  47         spin_lock_irqsave(&disp->vblank.lock, flags);
  48         list_for_each_entry_safe(chan, temp, &disp->vblank.list, vblank.head) {
  49                 if (chan->vblank.crtc != crtc)
  50                         continue;
  51
  52                 if (nv_device(priv)->chipset == 0x50) {
  53                         nv_wr32(priv, 0x001704, chan->vblank.channel);
  54                         nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
  55                         bar->flush(bar);
  56                         nv_wr32(priv, 0x001570, chan->vblank.offset);
  57                         nv_wr32(priv, 0x001574, chan->vblank.value);
  58                 } else {
  59                         nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);
  60                         bar->flush(bar);
  61                         nv_wr32(priv, 0x06000c,
  62                                 upper_32_bits(chan->vblank.offset));
  63                         nv_wr32(priv, 0x060010,
  64                                 lower_32_bits(chan->vblank.offset));
  65                         nv_wr32(priv, 0x060014, chan->vblank.value);
  66                 }
  67
  68                 list_del(&chan->vblank.head);
  69                 if (disp->vblank.put)
  70                         disp->vblank.put(disp->vblank.data, crtc);
  71         }
  72         spin_unlock_irqrestore(&disp->vblank.lock, flags);
  73
  74         if (disp->vblank.notify)
  75                 disp->vblank.notify(disp->vblank.data, crtc);
  76 }
  77
  78 static void
  79 nv50_disp_intr(struct nouveau_subdev *subdev)
  80 {
  81         struct nv50_disp_priv *priv = (void *)subdev;
  82         u32 stat1 = nv_rd32(priv, 0x610024);
  83
  84         if (stat1 & 0x00000004) {
  85                 nv50_disp_intr_vblank(priv, 0);
  86                 nv_wr32(priv, 0x610024, 0x00000004);
  87                 stat1 &= ~0x00000004;
  88         }
  89
  90         if (stat1 & 0x00000008) {
  91                 nv50_disp_intr_vblank(priv, 1);
  92                 nv_wr32(priv, 0x610024, 0x00000008);
  93                 stat1 &= ~0x00000008;
  94         }
  95
  96 }
  97
  98 static int
  99 nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 100                   struct nouveau_oclass *oclass, void *data, u32 size,
 101                   struct nouveau_object **pobject)
 102 {
 103         struct nv50_disp_priv *priv;
 104         int ret;
 105
 106         ret = nouveau_disp_create(parent, engine, oclass, "PDISP",
 107                                   "display", &priv);
 108         *pobject = nv_object(priv);
 109         if (ret)
 110                 return ret;
 111
 112         nv_engine(priv)->sclass = nv50_disp_sclass;
 113         nv_subdev(priv)->intr = nv50_disp_intr;
 114
 115         INIT_LIST_HEAD(&priv->base.vblank.list);
 116         spin_lock_init(&priv->base.vblank.lock);
 117         return 0;
 118 }
 119
 120 struct nouveau_oclass
 121 nv50_disp_oclass = {
 122         .handle = NV_ENGINE(DISP, 0x50),
 123         .ofuncs = &(struct nouveau_ofuncs) {
 124                 .ctor = nv50_disp_ctor,
 125                 .dtor = _nouveau_disp_dtor,
 126                 .init = _nouveau_disp_init,
 127                 .fini = _nouveau_disp_fini,
 128         },
 129 };