drivers/gpu/drm/msm/msm_gpu.c

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "msm_gpu.h"
  19 #include "msm_gem.h"
  20 #include "msm_mmu.h"
  21 #include "msm_fence.h"
  22 #include "msm_gpu_trace.h"
  23 #include "adreno/adreno_gpu.h"
  24
  25 #include <generated/utsrelease.h>
  26 #include <linux/string_helpers.h>
  27 #include <linux/pm_opp.h>
  28 #include <linux/devfreq.h>
  29 #include <linux/devcoredump.h>
  30
  31 /*
  32  * Power Management:
  33  */
  34
  35 static int msm_devfreq_target(struct device *dev, unsigned long *freq,
  36                 u32 flags)
  37 {
  38         struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
  39         struct dev_pm_opp *opp;
  40
  41         opp = devfreq_recommended_opp(dev, freq, flags);
  42
  43         if (IS_ERR(opp))
  44                 return PTR_ERR(opp);
  45
  46         if (gpu->funcs->gpu_set_freq)
  47                 gpu->funcs->gpu_set_freq(gpu, (u64)*freq);
  48         else
  49                 clk_set_rate(gpu->core_clk, *freq);
  50
  51         dev_pm_opp_put(opp);
  52
  53         return 0;
  54 }
  55
  56 static int msm_devfreq_get_dev_status(struct device *dev,
  57                 struct devfreq_dev_status *status)
  58 {
  59         struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
  60         ktime_t time;
  61
  62         if (gpu->funcs->gpu_get_freq)
  63                 status->current_frequency = gpu->funcs->gpu_get_freq(gpu);
  64         else
  65                 status->current_frequency = clk_get_rate(gpu->core_clk);
  66
  67         status->busy_time = gpu->funcs->gpu_busy(gpu);
  68
  69         time = ktime_get();
  70         status->total_time = ktime_us_delta(time, gpu->devfreq.time);
  71         gpu->devfreq.time = time;
  72
  73         return 0;
  74 }
  75
  76 static int msm_devfreq_get_cur_freq(struct device *dev, unsigned long *freq)
  77 {
  78         struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
  79
  80         if (gpu->funcs->gpu_get_freq)
  81                 *freq = gpu->funcs->gpu_get_freq(gpu);
  82         else
  83                 *freq = clk_get_rate(gpu->core_clk);
  84
  85         return 0;
  86 }
  87
  88 static struct devfreq_dev_profile msm_devfreq_profile = {
  89         .polling_ms = 10,
  90         .target = msm_devfreq_target,
  91         .get_dev_status = msm_devfreq_get_dev_status,
  92         .get_cur_freq = msm_devfreq_get_cur_freq,
  93 };
  94
  95 static void msm_devfreq_init(struct msm_gpu *gpu)
  96 {
  97         /* We need target support to do devfreq */
  98         if (!gpu->funcs->gpu_busy)
  99                 return;
 100
 101         msm_devfreq_profile.initial_freq = gpu->fast_rate;
 102
 103         /*
 104          * Don't set the freq_table or max_state and let devfreq build the table
 105          * from OPP
 106          */
 107
 108         gpu->devfreq.devfreq = devm_devfreq_add_device(&gpu->pdev->dev,
 109                         &msm_devfreq_profile, "simple_ondemand", NULL);
 110
 111         if (IS_ERR(gpu->devfreq.devfreq)) {
 112                 DRM_DEV_ERROR(&gpu->pdev->dev, "Couldn't initialize GPU devfreq\n");
 113                 gpu->devfreq.devfreq = NULL;
 114         }
 115
 116         devfreq_suspend_device(gpu->devfreq.devfreq);
 117 }
 118
 119 static int enable_pwrrail(struct msm_gpu *gpu)
 120 {
 121         struct drm_device *dev = gpu->dev;
 122         int ret = 0;
 123
 124         if (gpu->gpu_reg) {
 125                 ret = regulator_enable(gpu->gpu_reg);
 126                 if (ret) {
 127                         DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_reg': %d\n", ret);
 128                         return ret;
 129                 }
 130         }
 131
 132         if (gpu->gpu_cx) {
 133                 ret = regulator_enable(gpu->gpu_cx);
 134                 if (ret) {
 135                         DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_cx': %d\n", ret);
 136                         return ret;
 137                 }
 138         }
 139
 140         return 0;
 141 }
 142
 143 static int disable_pwrrail(struct msm_gpu *gpu)
 144 {
 145         if (gpu->gpu_cx)
 146                 regulator_disable(gpu->gpu_cx);
 147         if (gpu->gpu_reg)
 148                 regulator_disable(gpu->gpu_reg);
 149         return 0;
 150 }
 151
 152 static int enable_clk(struct msm_gpu *gpu)
 153 {
 154         if (gpu->core_clk && gpu->fast_rate)
 155                 clk_set_rate(gpu->core_clk, gpu->fast_rate);
 156
 157         /* Set the RBBM timer rate to 19.2Mhz */
 158         if (gpu->rbbmtimer_clk)
 159                 clk_set_rate(gpu->rbbmtimer_clk, 19200000);
 160
 161         return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks);
 162 }
 163
 164 static int disable_clk(struct msm_gpu *gpu)
 165 {
 166         clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
 167
 168         /*
 169          * Set the clock to a deliberately low rate. On older targets the clock
 170          * speed had to be non zero to avoid problems. On newer targets this
 171          * will be rounded down to zero anyway so it all works out.
 172          */
 173         if (gpu->core_clk)
 174                 clk_set_rate(gpu->core_clk, 27000000);
 175
 176         if (gpu->rbbmtimer_clk)
 177                 clk_set_rate(gpu->rbbmtimer_clk, 0);
 178
 179         return 0;
 180 }
 181
 182 static int enable_axi(struct msm_gpu *gpu)
 183 {
 184         if (gpu->ebi1_clk)
 185                 clk_prepare_enable(gpu->ebi1_clk);
 186         return 0;
 187 }
 188
 189 static int disable_axi(struct msm_gpu *gpu)
 190 {
 191         if (gpu->ebi1_clk)
 192                 clk_disable_unprepare(gpu->ebi1_clk);
 193         return 0;
 194 }
 195
 196 void msm_gpu_resume_devfreq(struct msm_gpu *gpu)
 197 {
 198         gpu->devfreq.busy_cycles = 0;
 199         gpu->devfreq.time = ktime_get();
 200
 201         devfreq_resume_device(gpu->devfreq.devfreq);
 202 }
 203
 204 int msm_gpu_pm_resume(struct msm_gpu *gpu)
 205 {
 206         int ret;
 207
 208         DBG("%s", gpu->name);
 209
 210         ret = enable_pwrrail(gpu);
 211         if (ret)
 212                 return ret;
 213
 214         ret = enable_clk(gpu);
 215         if (ret)
 216                 return ret;
 217
 218         ret = enable_axi(gpu);
 219         if (ret)
 220                 return ret;
 221
 222         msm_gpu_resume_devfreq(gpu);
 223
 224         gpu->needs_hw_init = true;
 225
 226         return 0;
 227 }
 228
 229 int msm_gpu_pm_suspend(struct msm_gpu *gpu)
 230 {
 231         int ret;
 232
 233         DBG("%s", gpu->name);
 234
 235         devfreq_suspend_device(gpu->devfreq.devfreq);
 236
 237         ret = disable_axi(gpu);
 238         if (ret)
 239                 return ret;
 240
 241         ret = disable_clk(gpu);
 242         if (ret)
 243                 return ret;
 244
 245         ret = disable_pwrrail(gpu);
 246         if (ret)
 247                 return ret;
 248
 249         return 0;
 250 }
 251
 252 int msm_gpu_hw_init(struct msm_gpu *gpu)
 253 {
 254         int ret;
 255
 256         WARN_ON(!mutex_is_locked(&gpu->dev->struct_mutex));
 257
 258         if (!gpu->needs_hw_init)
 259                 return 0;
 260
 261         disable_irq(gpu->irq);
 262         ret = gpu->funcs->hw_init(gpu);
 263         if (!ret)
 264                 gpu->needs_hw_init = false;
 265         enable_irq(gpu->irq);
 266
 267         return ret;
 268 }
 269
 270 #ifdef CONFIG_DEV_COREDUMP
 271 static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset,
 272                 size_t count, void *data, size_t datalen)
 273 {
 274         struct msm_gpu *gpu = data;
 275         struct drm_print_iterator iter;
 276         struct drm_printer p;
 277         struct msm_gpu_state *state;
 278
 279         state = msm_gpu_crashstate_get(gpu);
 280         if (!state)
 281                 return 0;
 282
 283         iter.data = buffer;
 284         iter.offset = 0;
 285         iter.start = offset;
 286         iter.remain = count;
 287
 288         p = drm_coredump_printer(&iter);
 289
 290         drm_printf(&p, "---\n");
 291         drm_printf(&p, "kernel: " UTS_RELEASE "\n");
 292         drm_printf(&p, "module: " KBUILD_MODNAME "\n");
 293         drm_printf(&p, "time: %lld.%09ld\n",
 294                 state->time.tv_sec, state->time.tv_nsec);
 295         if (state->comm)
 296                 drm_printf(&p, "comm: %s\n", state->comm);
 297         if (state->cmd)
 298                 drm_printf(&p, "cmdline: %s\n", state->cmd);
 299
 300         gpu->funcs->show(gpu, state, &p);
 301
 302         msm_gpu_crashstate_put(gpu);
 303
 304         return count - iter.remain;
 305 }
 306
 307 static void msm_gpu_devcoredump_free(void *data)
 308 {
 309         struct msm_gpu *gpu = data;
 310
 311         msm_gpu_crashstate_put(gpu);
 312 }
 313
 314 static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state,
 315                 struct msm_gem_object *obj, u64 iova, u32 flags)
 316 {
 317         struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos];
 318
 319         /* Don't record write only objects */
 320         state_bo->size = obj->base.size;
 321         state_bo->iova = iova;
 322
 323         /* Only store data for non imported buffer objects marked for read */
 324         if ((flags & MSM_SUBMIT_BO_READ) && !obj->base.import_attach) {
 325                 void *ptr;
 326
 327                 state_bo->data = kvmalloc(obj->base.size, GFP_KERNEL);
 328                 if (!state_bo->data)
 329                         goto out;
 330
 331                 ptr = msm_gem_get_vaddr_active(&obj->base);
 332                 if (IS_ERR(ptr)) {
 333                         kvfree(state_bo->data);
 334                         state_bo->data = NULL;
 335                         goto out;
 336                 }
 337
 338                 memcpy(state_bo->data, ptr, obj->base.size);
 339                 msm_gem_put_vaddr(&obj->base);
 340         }
 341 out:
 342         state->nr_bos++;
 343 }
 344
 345 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
 346                 struct msm_gem_submit *submit, char *comm, char *cmd)
 347 {
 348         struct msm_gpu_state *state;
 349
 350         /* Only save one crash state at a time */
 351         if (gpu->crashstate)
 352                 return;
 353
 354         state = gpu->funcs->gpu_state_get(gpu);
 355         if (IS_ERR_OR_NULL(state))
 356                 return;
 357
 358         /* Fill in the additional crash state information */
 359         state->comm = kstrdup(comm, GFP_KERNEL);
 360         state->cmd = kstrdup(cmd, GFP_KERNEL);
 361
 362         if (submit) {
 363                 int i;
 364
 365                 state->bos = kcalloc(submit->nr_cmds,
 366                         sizeof(struct msm_gpu_state_bo), GFP_KERNEL);
 367
 368                 for (i = 0; state->bos && i < submit->nr_cmds; i++) {
 369                         int idx = submit->cmd[i].idx;
 370
 371                         msm_gpu_crashstate_get_bo(state, submit->bos[idx].obj,
 372                                 submit->bos[idx].iova, submit->bos[idx].flags);
 373                 }
 374         }
 375
 376         /* Set the active crash state to be dumped on failure */
 377         gpu->crashstate = state;
 378
 379         /* FIXME: Release the crashstate if this errors out? */
 380         dev_coredumpm(gpu->dev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL,
 381                 msm_gpu_devcoredump_read, msm_gpu_devcoredump_free);
 382 }
 383 #else
 384 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
 385                 struct msm_gem_submit *submit, char *comm, char *cmd)
 386 {
 387 }
 388 #endif
 389
 390 /*
 391  * Hangcheck detection for locked gpu:
 392  */
 393
 394 static void update_fences(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
 395                 uint32_t fence)
 396 {
 397         struct msm_gem_submit *submit;
 398
 399         list_for_each_entry(submit, &ring->submits, node) {
 400                 if (submit->seqno > fence)
 401                         break;
 402
 403                 msm_update_fence(submit->ring->fctx,
 404                         submit->fence->seqno);
 405         }
 406 }
 407
 408 static struct msm_gem_submit *
 409 find_submit(struct msm_ringbuffer *ring, uint32_t fence)
 410 {
 411         struct msm_gem_submit *submit;
 412
 413         WARN_ON(!mutex_is_locked(&ring->gpu->dev->struct_mutex));
 414
 415         list_for_each_entry(submit, &ring->submits, node)
 416                 if (submit->seqno == fence)
 417                         return submit;
 418
 419         return NULL;
 420 }
 421
 422 static void retire_submits(struct msm_gpu *gpu);
 423
 424 static void recover_worker(struct work_struct *work)
 425 {
 426         struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
 427         struct drm_device *dev = gpu->dev;
 428         struct msm_drm_private *priv = dev->dev_private;
 429         struct msm_gem_submit *submit;
 430         struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
 431         char *comm = NULL, *cmd = NULL;
 432         int i;
 433
 434         mutex_lock(&dev->struct_mutex);
 435
 436         DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name);
 437
 438         submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
 439         if (submit) {
 440                 struct task_struct *task;
 441
 442                 rcu_read_lock();
 443                 task = pid_task(submit->pid, PIDTYPE_PID);
 444                 if (task) {
 445                         comm = kstrdup(task->comm, GFP_ATOMIC);
 446
 447                         /*
 448                          * So slightly annoying, in other paths like
 449                          * mmap'ing gem buffers, mmap_sem is acquired
 450                          * before struct_mutex, which means we can't
 451                          * hold struct_mutex across the call to
 452                          * get_cmdline().  But submits are retired
 453                          * from the same in-order workqueue, so we can
 454                          * safely drop the lock here without worrying
 455                          * about the submit going away.
 456                          */
 457                         mutex_unlock(&dev->struct_mutex);
 458                         cmd = kstrdup_quotable_cmdline(task, GFP_ATOMIC);
 459                         mutex_lock(&dev->struct_mutex);
 460                 }
 461                 rcu_read_unlock();
 462
 463                 if (comm && cmd) {
 464                         DRM_DEV_ERROR(dev->dev, "%s: offending task: %s (%s)\n",
 465                                 gpu->name, comm, cmd);
 466
 467                         msm_rd_dump_submit(priv->hangrd, submit,
 468                                 "offending task: %s (%s)", comm, cmd);
 469                 } else
 470                         msm_rd_dump_submit(priv->hangrd, submit, NULL);
 471         }
 472
 473         /* Record the crash state */
 474         pm_runtime_get_sync(&gpu->pdev->dev);
 475         msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
 476         pm_runtime_put_sync(&gpu->pdev->dev);
 477
 478         kfree(cmd);
 479         kfree(comm);
 480
 481         /*
 482          * Update all the rings with the latest and greatest fence.. this
 483          * needs to happen after msm_rd_dump_submit() to ensure that the
 484          * bo's referenced by the offending submit are still around.
 485          */
 486         for (i = 0; i < gpu->nr_rings; i++) {
 487                 struct msm_ringbuffer *ring = gpu->rb[i];
 488
 489                 uint32_t fence = ring->memptrs->fence;
 490
 491                 /*
 492                  * For the current (faulting?) ring/submit advance the fence by
 493                  * one more to clear the faulting submit
 494                  */
 495                 if (ring == cur_ring)
 496                         fence++;
 497
 498                 update_fences(gpu, ring, fence);
 499         }
 500
 501         if (msm_gpu_active(gpu)) {
 502                 /* retire completed submits, plus the one that hung: */
 503                 retire_submits(gpu);
 504
 505                 pm_runtime_get_sync(&gpu->pdev->dev);
 506                 gpu->funcs->recover(gpu);
 507                 pm_runtime_put_sync(&gpu->pdev->dev);
 508
 509                 /*
 510                  * Replay all remaining submits starting with highest priority
 511                  * ring
 512                  */
 513                 for (i = 0; i < gpu->nr_rings; i++) {
 514                         struct msm_ringbuffer *ring = gpu->rb[i];
 515
 516                         list_for_each_entry(submit, &ring->submits, node)
 517                                 gpu->funcs->submit(gpu, submit, NULL);
 518                 }
 519         }
 520
 521         mutex_unlock(&dev->struct_mutex);
 522
 523         msm_gpu_retire(gpu);
 524 }
 525
 526 static void hangcheck_timer_reset(struct msm_gpu *gpu)
 527 {
 528         DBG("%s", gpu->name);
 529         mod_timer(&gpu->hangcheck_timer,
 530                         round_jiffies_up(jiffies + DRM_MSM_HANGCHECK_JIFFIES));
 531 }
 532
 533 static void hangcheck_handler(struct timer_list *t)
 534 {
 535         struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer);
 536         struct drm_device *dev = gpu->dev;
 537         struct msm_drm_private *priv = dev->dev_private;
 538         struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
 539         uint32_t fence = ring->memptrs->fence;
 540
 541         if (fence != ring->hangcheck_fence) {
 542                 /* some progress has been made.. ya! */
 543                 ring->hangcheck_fence = fence;
 544         } else if (fence < ring->seqno) {
 545                 /* no progress and not done.. hung! */
 546                 ring->hangcheck_fence = fence;
 547                 DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n",
 548                                 gpu->name, ring->id);
 549                 DRM_DEV_ERROR(dev->dev, "%s:     completed fence: %u\n",
 550                                 gpu->name, fence);
 551                 DRM_DEV_ERROR(dev->dev, "%s:     submitted fence: %u\n",
 552                                 gpu->name, ring->seqno);
 553
 554                 queue_work(priv->wq, &gpu->recover_work);
 555         }
 556
 557         /* if still more pending work, reset the hangcheck timer: */
 558         if (ring->seqno > ring->hangcheck_fence)
 559                 hangcheck_timer_reset(gpu);
 560
 561         /* workaround for missing irq: */
 562         queue_work(priv->wq, &gpu->retire_work);
 563 }
 564
 565 /*
 566  * Performance Counters:
 567  */
 568
 569 /* called under perf_lock */
 570 static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs)
 571 {
 572         uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)];
 573         int i, n = min(ncntrs, gpu->num_perfcntrs);
 574
 575         /* read current values: */
 576         for (i = 0; i < gpu->num_perfcntrs; i++)
 577                 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg);
 578
 579         /* update cntrs: */
 580         for (i = 0; i < n; i++)
 581                 cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i];
 582
 583         /* save current values: */
 584         for (i = 0; i < gpu->num_perfcntrs; i++)
 585                 gpu->last_cntrs[i] = current_cntrs[i];
 586
 587         return n;
 588 }
 589
 590 static void update_sw_cntrs(struct msm_gpu *gpu)
 591 {
 592         ktime_t time;
 593         uint32_t elapsed;
 594         unsigned long flags;
 595
 596         spin_lock_irqsave(&gpu->perf_lock, flags);
 597         if (!gpu->perfcntr_active)
 598                 goto out;
 599
 600         time = ktime_get();
 601         elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time));
 602
 603         gpu->totaltime += elapsed;
 604         if (gpu->last_sample.active)
 605                 gpu->activetime += elapsed;
 606
 607         gpu->last_sample.active = msm_gpu_active(gpu);
 608         gpu->last_sample.time = time;
 609
 610 out:
 611         spin_unlock_irqrestore(&gpu->perf_lock, flags);
 612 }
 613
 614 void msm_gpu_perfcntr_start(struct msm_gpu *gpu)
 615 {
 616         unsigned long flags;
 617
 618         pm_runtime_get_sync(&gpu->pdev->dev);
 619
 620         spin_lock_irqsave(&gpu->perf_lock, flags);
 621         /* we could dynamically enable/disable perfcntr registers too.. */
 622         gpu->last_sample.active = msm_gpu_active(gpu);
 623         gpu->last_sample.time = ktime_get();
 624         gpu->activetime = gpu->totaltime = 0;
 625         gpu->perfcntr_active = true;
 626         update_hw_cntrs(gpu, 0, NULL);
 627         spin_unlock_irqrestore(&gpu->perf_lock, flags);
 628 }
 629
 630 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu)
 631 {
 632         gpu->perfcntr_active = false;
 633         pm_runtime_put_sync(&gpu->pdev->dev);
 634 }
 635
 636 /* returns -errno or # of cntrs sampled */
 637 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
 638                 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs)
 639 {
 640         unsigned long flags;
 641         int ret;
 642
 643         spin_lock_irqsave(&gpu->perf_lock, flags);
 644
 645         if (!gpu->perfcntr_active) {
 646                 ret = -EINVAL;
 647                 goto out;
 648         }
 649
 650         *activetime = gpu->activetime;
 651         *totaltime = gpu->totaltime;
 652
 653         gpu->activetime = gpu->totaltime = 0;
 654
 655         ret = update_hw_cntrs(gpu, ncntrs, cntrs);
 656
 657 out:
 658         spin_unlock_irqrestore(&gpu->perf_lock, flags);
 659
 660         return ret;
 661 }
 662
 663 /*
 664  * Cmdstream submission/retirement:
 665  */
 666
 667 static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
 668                 struct msm_gem_submit *submit)
 669 {
 670         int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
 671         volatile struct msm_gpu_submit_stats *stats;
 672         u64 elapsed, clock = 0;
 673         int i;
 674
 675         stats = &ring->memptrs->stats[index];
 676         /* Convert 19.2Mhz alwayson ticks to nanoseconds for elapsed time */
 677         elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000;
 678         do_div(elapsed, 192);
 679
 680         /* Calculate the clock frequency from the number of CP cycles */
 681         if (elapsed) {
 682                 clock = (stats->cpcycles_end - stats->cpcycles_start) * 1000;
 683                 do_div(clock, elapsed);
 684         }
 685
 686         trace_msm_gpu_submit_retired(submit, elapsed, clock,
 687                 stats->alwayson_start, stats->alwayson_end);
 688
 689         for (i = 0; i < submit->nr_bos; i++) {
 690                 struct msm_gem_object *msm_obj = submit->bos[i].obj;
 691                 /* move to inactive: */
 692                 msm_gem_move_to_inactive(&msm_obj->base);
 693                 msm_gem_unpin_iova(&msm_obj->base, gpu->aspace);
 694                 drm_gem_object_put(&msm_obj->base);
 695         }
 696
 697         pm_runtime_mark_last_busy(&gpu->pdev->dev);
 698         pm_runtime_put_autosuspend(&gpu->pdev->dev);
 699         msm_gem_submit_free(submit);
 700 }
 701
 702 static void retire_submits(struct msm_gpu *gpu)
 703 {
 704         struct drm_device *dev = gpu->dev;
 705         struct msm_gem_submit *submit, *tmp;
 706         int i;
 707
 708         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 709
 710         /* Retire the commits starting with highest priority */
 711         for (i = 0; i < gpu->nr_rings; i++) {
 712                 struct msm_ringbuffer *ring = gpu->rb[i];
 713
 714                 list_for_each_entry_safe(submit, tmp, &ring->submits, node) {
 715                         if (dma_fence_is_signaled(submit->fence))
 716                                 retire_submit(gpu, ring, submit);
 717                 }
 718         }
 719 }
 720
 721 static void retire_worker(struct work_struct *work)
 722 {
 723         struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
 724         struct drm_device *dev = gpu->dev;
 725         int i;
 726
 727         for (i = 0; i < gpu->nr_rings; i++)
 728                 update_fences(gpu, gpu->rb[i], gpu->rb[i]->memptrs->fence);
 729
 730         mutex_lock(&dev->struct_mutex);
 731         retire_submits(gpu);
 732         mutex_unlock(&dev->struct_mutex);
 733 }
 734
 735 /* call from irq handler to schedule work to retire bo's */
 736 void msm_gpu_retire(struct msm_gpu *gpu)
 737 {
 738         struct msm_drm_private *priv = gpu->dev->dev_private;
 739         queue_work(priv->wq, &gpu->retire_work);
 740         update_sw_cntrs(gpu);
 741 }
 742
 743 /* add bo's to gpu's ring, and kick gpu: */
 744 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
 745                 struct msm_file_private *ctx)
 746 {
 747         struct drm_device *dev = gpu->dev;
 748         struct msm_drm_private *priv = dev->dev_private;
 749         struct msm_ringbuffer *ring = submit->ring;
 750         int i;
 751
 752         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 753
 754         pm_runtime_get_sync(&gpu->pdev->dev);
 755
 756         msm_gpu_hw_init(gpu);
 757
 758         submit->seqno = ++ring->seqno;
 759
 760         list_add_tail(&submit->node, &ring->submits);
 761
 762         msm_rd_dump_submit(priv->rd, submit, NULL);
 763
 764         update_sw_cntrs(gpu);
 765
 766         for (i = 0; i < submit->nr_bos; i++) {
 767                 struct msm_gem_object *msm_obj = submit->bos[i].obj;
 768                 uint64_t iova;
 769
 770                 /* can't happen yet.. but when we add 2d support we'll have
 771                  * to deal w/ cross-ring synchronization:
 772                  */
 773                 WARN_ON(is_active(msm_obj) && (msm_obj->gpu != gpu));
 774
 775                 /* submit takes a reference to the bo and iova until retired: */
 776                 drm_gem_object_get(&msm_obj->base);
 777                 msm_gem_get_and_pin_iova(&msm_obj->base,
 778                                 submit->gpu->aspace, &iova);
 779
 780                 if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE)
 781                         msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence);
 782                 else if (submit->bos[i].flags & MSM_SUBMIT_BO_READ)
 783                         msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence);
 784         }
 785
 786         gpu->funcs->submit(gpu, submit, ctx);
 787         priv->lastctx = ctx;
 788
 789         hangcheck_timer_reset(gpu);
 790 }
 791
 792 /*
 793  * Init/Cleanup:
 794  */
 795
 796 static irqreturn_t irq_handler(int irq, void *data)
 797 {
 798         struct msm_gpu *gpu = data;
 799         return gpu->funcs->irq(gpu);
 800 }
 801
 802 static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
 803 {
 804         int ret = msm_clk_bulk_get(&pdev->dev, &gpu->grp_clks);
 805
 806         if (ret < 1) {
 807                 gpu->nr_clocks = 0;
 808                 return ret;
 809         }
 810
 811         gpu->nr_clocks = ret;
 812
 813         gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
 814                 gpu->nr_clocks, "core");
 815
 816         gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
 817                 gpu->nr_clocks, "rbbmtimer");
 818
 819         return 0;
 820 }
 821
 822 static struct msm_gem_address_space *
 823 msm_gpu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev,
 824                 uint64_t va_start, uint64_t va_end)
 825 {
 826         struct msm_gem_address_space *aspace;
 827         int ret;
 828
 829         /*
 830          * Setup IOMMU.. eventually we will (I think) do this once per context
 831          * and have separate page tables per context.  For now, to keep things
 832          * simple and to get something working, just use a single address space:
 833          */
 834         if (!adreno_is_a2xx(to_adreno_gpu(gpu))) {
 835                 struct iommu_domain *iommu = iommu_domain_alloc(&platform_bus_type);
 836                 if (!iommu)
 837                         return NULL;
 838
 839                 iommu->geometry.aperture_start = va_start;
 840                 iommu->geometry.aperture_end = va_end;
 841
 842                 DRM_DEV_INFO(gpu->dev->dev, "%s: using IOMMU\n", gpu->name);
 843
 844                 aspace = msm_gem_address_space_create(&pdev->dev, iommu, "gpu");
 845                 if (IS_ERR(aspace))
 846                         iommu_domain_free(iommu);
 847         } else {
 848                 aspace = msm_gem_address_space_create_a2xx(&pdev->dev, gpu, "gpu",
 849                         va_start, va_end);
 850         }
 851
 852         if (IS_ERR(aspace)) {
 853                 DRM_DEV_ERROR(gpu->dev->dev, "failed to init mmu: %ld\n",
 854                         PTR_ERR(aspace));
 855                 return ERR_CAST(aspace);
 856         }
 857
 858         ret = aspace->mmu->funcs->attach(aspace->mmu, NULL, 0);
 859         if (ret) {
 860                 msm_gem_address_space_put(aspace);
 861                 return ERR_PTR(ret);
 862         }
 863
 864         return aspace;
 865 }
 866
 867 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 868                 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
 869                 const char *name, struct msm_gpu_config *config)
 870 {
 871         int i, ret, nr_rings = config->nr_rings;
 872         void *memptrs;
 873         uint64_t memptrs_iova;
 874
 875         if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs)))
 876                 gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs);
 877
 878         gpu->dev = drm;
 879         gpu->funcs = funcs;
 880         gpu->name = name;
 881
 882         INIT_LIST_HEAD(&gpu->active_list);
 883         INIT_WORK(&gpu->retire_work, retire_worker);
 884         INIT_WORK(&gpu->recover_work, recover_worker);
 885
 886
 887         timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0);
 888
 889         spin_lock_init(&gpu->perf_lock);
 890
 891
 892         /* Map registers: */
 893         gpu->mmio = msm_ioremap(pdev, config->ioname, name);
 894         if (IS_ERR(gpu->mmio)) {
 895                 ret = PTR_ERR(gpu->mmio);
 896                 goto fail;
 897         }
 898
 899         /* Get Interrupt: */
 900         gpu->irq = platform_get_irq(pdev, 0);
 901         if (gpu->irq < 0) {
 902                 ret = gpu->irq;
 903                 DRM_DEV_ERROR(drm->dev, "failed to get irq: %d\n", ret);
 904                 goto fail;
 905         }
 906
 907         ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
 908                         IRQF_TRIGGER_HIGH, gpu->name, gpu);
 909         if (ret) {
 910                 DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
 911                 goto fail;
 912         }
 913
 914         ret = get_clocks(pdev, gpu);
 915         if (ret)
 916                 goto fail;
 917
 918         gpu->ebi1_clk = msm_clk_get(pdev, "bus");
 919         DBG("ebi1_clk: %p", gpu->ebi1_clk);
 920         if (IS_ERR(gpu->ebi1_clk))
 921                 gpu->ebi1_clk = NULL;
 922
 923         /* Acquire regulators: */
 924         gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
 925         DBG("gpu_reg: %p", gpu->gpu_reg);
 926         if (IS_ERR(gpu->gpu_reg))
 927                 gpu->gpu_reg = NULL;
 928
 929         gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
 930         DBG("gpu_cx: %p", gpu->gpu_cx);
 931         if (IS_ERR(gpu->gpu_cx))
 932                 gpu->gpu_cx = NULL;
 933
 934         gpu->pdev = pdev;
 935         platform_set_drvdata(pdev, gpu);
 936
 937         msm_devfreq_init(gpu);
 938
 939         gpu->aspace = msm_gpu_create_address_space(gpu, pdev,
 940                 config->va_start, config->va_end);
 941
 942         if (gpu->aspace == NULL)
 943                 DRM_DEV_INFO(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name);
 944         else if (IS_ERR(gpu->aspace)) {
 945                 ret = PTR_ERR(gpu->aspace);
 946                 goto fail;
 947         }
 948
 949         memptrs = msm_gem_kernel_new(drm,
 950                 sizeof(struct msm_rbmemptrs) * nr_rings,
 951                 MSM_BO_UNCACHED, gpu->aspace, &gpu->memptrs_bo,
 952                 &memptrs_iova);
 953
 954         if (IS_ERR(memptrs)) {
 955                 ret = PTR_ERR(memptrs);
 956                 DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret);
 957                 goto fail;
 958         }
 959
 960         msm_gem_object_set_name(gpu->memptrs_bo, "memptrs");
 961
 962         if (nr_rings > ARRAY_SIZE(gpu->rb)) {
 963                 DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n",
 964                         ARRAY_SIZE(gpu->rb));
 965                 nr_rings = ARRAY_SIZE(gpu->rb);
 966         }
 967
 968         /* Create ringbuffer(s): */
 969         for (i = 0; i < nr_rings; i++) {
 970                 gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova);
 971
 972                 if (IS_ERR(gpu->rb[i])) {
 973                         ret = PTR_ERR(gpu->rb[i]);
 974                         DRM_DEV_ERROR(drm->dev,
 975                                 "could not create ringbuffer %d: %d\n", i, ret);
 976                         goto fail;
 977                 }
 978
 979                 memptrs += sizeof(struct msm_rbmemptrs);
 980                 memptrs_iova += sizeof(struct msm_rbmemptrs);
 981         }
 982
 983         gpu->nr_rings = nr_rings;
 984
 985         return 0;
 986
 987 fail:
 988         for (i = 0; i < ARRAY_SIZE(gpu->rb); i++)  {
 989                 msm_ringbuffer_destroy(gpu->rb[i]);
 990                 gpu->rb[i] = NULL;
 991         }
 992
 993         msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace, false);
 994
 995         platform_set_drvdata(pdev, NULL);
 996         return ret;
 997 }
 998
 999 void msm_gpu_cleanup(struct msm_gpu *gpu)
1000 {
1001         int i;
1002
1003         DBG("%s", gpu->name);
1004
1005         WARN_ON(!list_empty(&gpu->active_list));
1006
1007         for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
1008                 msm_ringbuffer_destroy(gpu->rb[i]);
1009                 gpu->rb[i] = NULL;
1010         }
1011
1012         msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace, false);
1013
1014         if (!IS_ERR_OR_NULL(gpu->aspace)) {
1015                 gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu,
1016                         NULL, 0);
1017                 msm_gem_address_space_put(gpu->aspace);
1018         }
1019 }