drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c

   1 /*
   2  * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/sort.h>
  20 #include <drm/drm_mode.h>
  21 #include <drm/drm_crtc.h>
  22 #include <drm/drm_crtc_helper.h>
  23 #include <drm/drm_flip_work.h>
  24
  25 #include "mdp5_kms.h"
  26
  27 #define CURSOR_WIDTH    64
  28 #define CURSOR_HEIGHT   64
  29
  30 struct mdp5_crtc {
  31         struct drm_crtc base;
  32         int id;
  33         bool enabled;
  34
  35         spinlock_t lm_lock;     /* protect REG_MDP5_LM_* registers */
  36
  37         /* if there is a pending flip, these will be non-null: */
  38         struct drm_pending_vblank_event *event;
  39
  40         /* Bits have been flushed at the last commit,
  41          * used to decide if a vsync has happened since last commit.
  42          */
  43         u32 flushed_mask;
  44
  45 #define PENDING_CURSOR 0x1
  46 #define PENDING_FLIP   0x2
  47         atomic_t pending;
  48
  49         /* for unref'ing cursor bo's after scanout completes: */
  50         struct drm_flip_work unref_cursor_work;
  51
  52         struct mdp_irq vblank;
  53         struct mdp_irq err;
  54         struct mdp_irq pp_done;
  55
  56         struct completion pp_completion;
  57
  58         struct {
  59                 /* protect REG_MDP5_LM_CURSOR* registers and cursor scanout_bo*/
  60                 spinlock_t lock;
  61
  62                 /* current cursor being scanned out: */
  63                 struct drm_gem_object *scanout_bo;
  64                 uint32_t width, height;
  65                 uint32_t x, y;
  66         } cursor;
  67 };
  68 #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base)
  69
  70 static struct mdp5_kms *get_kms(struct drm_crtc *crtc)
  71 {
  72         struct msm_drm_private *priv = crtc->dev->dev_private;
  73         return to_mdp5_kms(to_mdp_kms(priv->kms));
  74 }
  75
  76 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
  77 {
  78         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
  79
  80         atomic_or(pending, &mdp5_crtc->pending);
  81         mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank);
  82 }
  83
  84 static void request_pp_done_pending(struct drm_crtc *crtc)
  85 {
  86         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
  87         reinit_completion(&mdp5_crtc->pp_completion);
  88 }
  89
  90 static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask)
  91 {
  92         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
  93         struct mdp5_ctl *ctl = mdp5_cstate->ctl;
  94         struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
  95
  96         DBG("%s: flush=%08x", crtc->name, flush_mask);
  97         return mdp5_ctl_commit(ctl, pipeline, flush_mask);
  98 }
  99
 100 /*
 101  * flush updates, to make sure hw is updated to new scanout fb,
 102  * so that we can safely queue unref to current fb (ie. next
 103  * vblank we know hw is done w/ previous scanout_fb).
 104  */
 105 static u32 crtc_flush_all(struct drm_crtc *crtc)
 106 {
 107         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 108         struct mdp5_hw_mixer *mixer, *r_mixer;
 109         struct drm_plane *plane;
 110         uint32_t flush_mask = 0;
 111
 112         /* this should not happen: */
 113         if (WARN_ON(!mdp5_cstate->ctl))
 114                 return 0;
 115
 116         drm_atomic_crtc_for_each_plane(plane, crtc) {
 117                 flush_mask |= mdp5_plane_get_flush(plane);
 118         }
 119
 120         mixer = mdp5_cstate->pipeline.mixer;
 121         flush_mask |= mdp_ctl_flush_mask_lm(mixer->lm);
 122
 123         r_mixer = mdp5_cstate->pipeline.r_mixer;
 124         if (r_mixer)
 125                 flush_mask |= mdp_ctl_flush_mask_lm(r_mixer->lm);
 126
 127         return crtc_flush(crtc, flush_mask);
 128 }
 129
 130 /* if file!=NULL, this is preclose potential cancel-flip path */
 131 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
 132 {
 133         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 134         struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
 135         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 136         struct mdp5_ctl *ctl = mdp5_cstate->ctl;
 137         struct drm_device *dev = crtc->dev;
 138         struct drm_pending_vblank_event *event;
 139         unsigned long flags;
 140
 141         spin_lock_irqsave(&dev->event_lock, flags);
 142         event = mdp5_crtc->event;
 143         if (event) {
 144                 mdp5_crtc->event = NULL;
 145                 DBG("%s: send event: %p", crtc->name, event);
 146                 drm_crtc_send_vblank_event(crtc, event);
 147         }
 148         spin_unlock_irqrestore(&dev->event_lock, flags);
 149
 150         if (ctl && !crtc->state->enable) {
 151                 /* set STAGE_UNUSED for all layers */
 152                 mdp5_ctl_blend(ctl, pipeline, NULL, NULL, 0, 0);
 153                 /* XXX: What to do here? */
 154                 /* mdp5_crtc->ctl = NULL; */
 155         }
 156 }
 157
 158 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
 159 {
 160         struct mdp5_crtc *mdp5_crtc =
 161                 container_of(work, struct mdp5_crtc, unref_cursor_work);
 162         struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base);
 163         struct msm_kms *kms = &mdp5_kms->base.base;
 164
 165         msm_gem_put_iova(val, kms->aspace);
 166         drm_gem_object_unreference_unlocked(val);
 167 }
 168
 169 static void mdp5_crtc_destroy(struct drm_crtc *crtc)
 170 {
 171         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 172
 173         drm_crtc_cleanup(crtc);
 174         drm_flip_work_cleanup(&mdp5_crtc->unref_cursor_work);
 175
 176         kfree(mdp5_crtc);
 177 }
 178
 179 static inline u32 mdp5_lm_use_fg_alpha_mask(enum mdp_mixer_stage_id stage)
 180 {
 181         switch (stage) {
 182         case STAGE0: return MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA;
 183         case STAGE1: return MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA;
 184         case STAGE2: return MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA;
 185         case STAGE3: return MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA;
 186         case STAGE4: return MDP5_LM_BLEND_COLOR_OUT_STAGE4_FG_ALPHA;
 187         case STAGE5: return MDP5_LM_BLEND_COLOR_OUT_STAGE5_FG_ALPHA;
 188         case STAGE6: return MDP5_LM_BLEND_COLOR_OUT_STAGE6_FG_ALPHA;
 189         default:
 190                 return 0;
 191         }
 192 }
 193
 194 /*
 195  * left/right pipe offsets for the stage array used in blend_setup()
 196  */
 197 #define PIPE_LEFT       0
 198 #define PIPE_RIGHT      1
 199
 200 /*
 201  * blend_setup() - blend all the planes of a CRTC
 202  *
 203  * If no base layer is available, border will be enabled as the base layer.
 204  * Otherwise all layers will be blended based on their stage calculated
 205  * in mdp5_crtc_atomic_check.
 206  */
 207 static void blend_setup(struct drm_crtc *crtc)
 208 {
 209         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 210         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 211         struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
 212         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 213         struct drm_plane *plane;
 214         const struct mdp5_cfg_hw *hw_cfg;
 215         struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL};
 216         const struct mdp_format *format;
 217         struct mdp5_hw_mixer *mixer = pipeline->mixer;
 218         uint32_t lm = mixer->lm;
 219         struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer;
 220         uint32_t r_lm = r_mixer ? r_mixer->lm : 0;
 221         struct mdp5_ctl *ctl = mdp5_cstate->ctl;
 222         uint32_t blend_op, fg_alpha, bg_alpha, ctl_blend_flags = 0;
 223         unsigned long flags;
 224         enum mdp5_pipe stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } };
 225         enum mdp5_pipe r_stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } };
 226         int i, plane_cnt = 0;
 227         bool bg_alpha_enabled = false;
 228         u32 mixer_op_mode = 0;
 229         u32 val;
 230 #define blender(stage)  ((stage) - STAGE0)
 231
 232         hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
 233
 234         spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
 235
 236         /* ctl could be released already when we are shutting down: */
 237         /* XXX: Can this happen now? */
 238         if (!ctl)
 239                 goto out;
 240
 241         /* Collect all plane information */
 242         drm_atomic_crtc_for_each_plane(plane, crtc) {
 243                 enum mdp5_pipe right_pipe;
 244
 245                 pstate = to_mdp5_plane_state(plane->state);
 246                 pstates[pstate->stage] = pstate;
 247                 stage[pstate->stage][PIPE_LEFT] = mdp5_plane_pipe(plane);
 248                 /*
 249                  * if we have a right mixer, stage the same pipe as we
 250                  * have on the left mixer
 251                  */
 252                 if (r_mixer)
 253                         r_stage[pstate->stage][PIPE_LEFT] =
 254                                                 mdp5_plane_pipe(plane);
 255                 /*
 256                  * if we have a right pipe (i.e, the plane comprises of 2
 257                  * hwpipes, then stage the right pipe on the right side of both
 258                  * the layer mixers
 259                  */
 260                 right_pipe = mdp5_plane_right_pipe(plane);
 261                 if (right_pipe) {
 262                         stage[pstate->stage][PIPE_RIGHT] = right_pipe;
 263                         r_stage[pstate->stage][PIPE_RIGHT] = right_pipe;
 264                 }
 265
 266                 plane_cnt++;
 267         }
 268
 269         if (!pstates[STAGE_BASE]) {
 270                 ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT;
 271                 DBG("Border Color is enabled");
 272         } else if (plane_cnt) {
 273                 format = to_mdp_format(msm_framebuffer_format(pstates[STAGE_BASE]->base.fb));
 274
 275                 if (format->alpha_enable)
 276                         bg_alpha_enabled = true;
 277         }
 278
 279         /* The reset for blending */
 280         for (i = STAGE0; i <= STAGE_MAX; i++) {
 281                 if (!pstates[i])
 282                         continue;
 283
 284                 format = to_mdp_format(
 285                         msm_framebuffer_format(pstates[i]->base.fb));
 286                 plane = pstates[i]->base.plane;
 287                 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
 288                         MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST);
 289                 fg_alpha = pstates[i]->alpha;
 290                 bg_alpha = 0xFF - pstates[i]->alpha;
 291
 292                 if (!format->alpha_enable && bg_alpha_enabled)
 293                         mixer_op_mode = 0;
 294                 else
 295                         mixer_op_mode |= mdp5_lm_use_fg_alpha_mask(i);
 296
 297                 DBG("Stage %d fg_alpha %x bg_alpha %x", i, fg_alpha, bg_alpha);
 298
 299                 if (format->alpha_enable && pstates[i]->premultiplied) {
 300                         blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
 301                                 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
 302                         if (fg_alpha != 0xff) {
 303                                 bg_alpha = fg_alpha;
 304                                 blend_op |=
 305                                         MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
 306                                         MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
 307                         } else {
 308                                 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
 309                         }
 310                 } else if (format->alpha_enable) {
 311                         blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) |
 312                                 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
 313                         if (fg_alpha != 0xff) {
 314                                 bg_alpha = fg_alpha;
 315                                 blend_op |=
 316                                        MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA |
 317                                        MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA |
 318                                        MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
 319                                        MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
 320                         } else {
 321                                 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
 322                         }
 323                 }
 324
 325                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm,
 326                                 blender(i)), blend_op);
 327                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm,
 328                                 blender(i)), fg_alpha);
 329                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm,
 330                                 blender(i)), bg_alpha);
 331                 if (r_mixer) {
 332                         mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(r_lm,
 333                                         blender(i)), blend_op);
 334                         mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(r_lm,
 335                                         blender(i)), fg_alpha);
 336                         mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(r_lm,
 337                                         blender(i)), bg_alpha);
 338                 }
 339         }
 340
 341         val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm));
 342         mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm),
 343                    val | mixer_op_mode);
 344         if (r_mixer) {
 345                 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm));
 346                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm),
 347                            val | mixer_op_mode);
 348         }
 349
 350         mdp5_ctl_blend(ctl, pipeline, stage, r_stage, plane_cnt,
 351                        ctl_blend_flags);
 352 out:
 353         spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
 354 }
 355
 356 static void mdp5_crtc_mode_set_nofb(struct drm_crtc *crtc)
 357 {
 358         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 359         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 360         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 361         struct mdp5_hw_mixer *mixer = mdp5_cstate->pipeline.mixer;
 362         struct mdp5_hw_mixer *r_mixer = mdp5_cstate->pipeline.r_mixer;
 363         uint32_t lm = mixer->lm;
 364         u32 mixer_width, val;
 365         unsigned long flags;
 366         struct drm_display_mode *mode;
 367
 368         if (WARN_ON(!crtc->state))
 369                 return;
 370
 371         mode = &crtc->state->adjusted_mode;
 372
 373         DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
 374                         crtc->name, mode->base.id, mode->name,
 375                         mode->vrefresh, mode->clock,
 376                         mode->hdisplay, mode->hsync_start,
 377                         mode->hsync_end, mode->htotal,
 378                         mode->vdisplay, mode->vsync_start,
 379                         mode->vsync_end, mode->vtotal,
 380                         mode->type, mode->flags);
 381
 382         mixer_width = mode->hdisplay;
 383         if (r_mixer)
 384                 mixer_width /= 2;
 385
 386         spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
 387         mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(lm),
 388                         MDP5_LM_OUT_SIZE_WIDTH(mixer_width) |
 389                         MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));
 390
 391         /* Assign mixer to LEFT side in source split mode */
 392         val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm));
 393         val &= ~MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT;
 394         mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), val);
 395
 396         if (r_mixer) {
 397                 u32 r_lm = r_mixer->lm;
 398
 399                 mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(r_lm),
 400                            MDP5_LM_OUT_SIZE_WIDTH(mixer_width) |
 401                            MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));
 402
 403                 /* Assign mixer to RIGHT side in source split mode */
 404                 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm));
 405                 val |= MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT;
 406                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), val);
 407         }
 408
 409         spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
 410 }
 411
 412 static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc,
 413                                      struct drm_crtc_state *old_state)
 414 {
 415         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 416         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 417         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 418         struct device *dev = &mdp5_kms->pdev->dev;
 419
 420         DBG("%s", crtc->name);
 421
 422         if (WARN_ON(!mdp5_crtc->enabled))
 423                 return;
 424
 425         if (mdp5_cstate->cmd_mode)
 426                 mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done);
 427
 428         mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err);
 429         pm_runtime_put_autosuspend(dev);
 430
 431         mdp5_crtc->enabled = false;
 432 }
 433
 434 static void mdp5_crtc_atomic_enable(struct drm_crtc *crtc,
 435                                     struct drm_crtc_state *old_state)
 436 {
 437         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 438         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 439         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 440         struct device *dev = &mdp5_kms->pdev->dev;
 441
 442         DBG("%s", crtc->name);
 443
 444         if (WARN_ON(mdp5_crtc->enabled))
 445                 return;
 446
 447         pm_runtime_get_sync(dev);
 448
 449         mdp5_crtc_mode_set_nofb(crtc);
 450
 451         mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err);
 452
 453         if (mdp5_cstate->cmd_mode)
 454                 mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done);
 455
 456         mdp5_crtc->enabled = true;
 457 }
 458
 459 int mdp5_crtc_setup_pipeline(struct drm_crtc *crtc,
 460                              struct drm_crtc_state *new_crtc_state,
 461                              bool need_right_mixer)
 462 {
 463         struct mdp5_crtc_state *mdp5_cstate =
 464                         to_mdp5_crtc_state(new_crtc_state);
 465         struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
 466         struct mdp5_interface *intf;
 467         bool new_mixer = false;
 468
 469         new_mixer = !pipeline->mixer;
 470
 471         if ((need_right_mixer && !pipeline->r_mixer) ||
 472             (!need_right_mixer && pipeline->r_mixer))
 473                 new_mixer = true;
 474
 475         if (new_mixer) {
 476                 struct mdp5_hw_mixer *old_mixer = pipeline->mixer;
 477                 struct mdp5_hw_mixer *old_r_mixer = pipeline->r_mixer;
 478                 u32 caps;
 479                 int ret;
 480
 481                 caps = MDP_LM_CAP_DISPLAY;
 482                 if (need_right_mixer)
 483                         caps |= MDP_LM_CAP_PAIR;
 484
 485                 ret = mdp5_mixer_assign(new_crtc_state->state, crtc, caps,
 486                                         &pipeline->mixer, need_right_mixer ?
 487                                         &pipeline->r_mixer : NULL);
 488                 if (ret)
 489                         return ret;
 490
 491                 mdp5_mixer_release(new_crtc_state->state, old_mixer);
 492                 if (old_r_mixer) {
 493                         mdp5_mixer_release(new_crtc_state->state, old_r_mixer);
 494                         if (!need_right_mixer)
 495                                 pipeline->r_mixer = NULL;
 496                 }
 497         }
 498
 499         /*
 500          * these should have been already set up in the encoder's atomic
 501          * check (called by drm_atomic_helper_check_modeset)
 502          */
 503         intf = pipeline->intf;
 504
 505         mdp5_cstate->err_irqmask = intf2err(intf->num);
 506         mdp5_cstate->vblank_irqmask = intf2vblank(pipeline->mixer, intf);
 507
 508         if ((intf->type == INTF_DSI) &&
 509             (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) {
 510                 mdp5_cstate->pp_done_irqmask = lm2ppdone(pipeline->mixer);
 511                 mdp5_cstate->cmd_mode = true;
 512         } else {
 513                 mdp5_cstate->pp_done_irqmask = 0;
 514                 mdp5_cstate->cmd_mode = false;
 515         }
 516
 517         return 0;
 518 }
 519
 520 struct plane_state {
 521         struct drm_plane *plane;
 522         struct mdp5_plane_state *state;
 523 };
 524
 525 static int pstate_cmp(const void *a, const void *b)
 526 {
 527         struct plane_state *pa = (struct plane_state *)a;
 528         struct plane_state *pb = (struct plane_state *)b;
 529         return pa->state->zpos - pb->state->zpos;
 530 }
 531
 532 /* is there a helper for this? */
 533 static bool is_fullscreen(struct drm_crtc_state *cstate,
 534                 struct drm_plane_state *pstate)
 535 {
 536         return (pstate->crtc_x <= 0) && (pstate->crtc_y <= 0) &&
 537                 ((pstate->crtc_x + pstate->crtc_w) >= cstate->mode.hdisplay) &&
 538                 ((pstate->crtc_y + pstate->crtc_h) >= cstate->mode.vdisplay);
 539 }
 540
 541 static enum mdp_mixer_stage_id get_start_stage(struct drm_crtc *crtc,
 542                                         struct drm_crtc_state *new_crtc_state,
 543                                         struct drm_plane_state *bpstate)
 544 {
 545         struct mdp5_crtc_state *mdp5_cstate =
 546                         to_mdp5_crtc_state(new_crtc_state);
 547
 548         /*
 549          * if we're in source split mode, it's mandatory to have
 550          * border out on the base stage
 551          */
 552         if (mdp5_cstate->pipeline.r_mixer)
 553                 return STAGE0;
 554
 555         /* if the bottom-most layer is not fullscreen, we need to use
 556          * it for solid-color:
 557          */
 558         if (!is_fullscreen(new_crtc_state, bpstate))
 559                 return STAGE0;
 560
 561         return STAGE_BASE;
 562 }
 563
 564 static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
 565                 struct drm_crtc_state *state)
 566 {
 567         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 568         struct drm_plane *plane;
 569         struct drm_device *dev = crtc->dev;
 570         struct plane_state pstates[STAGE_MAX + 1];
 571         const struct mdp5_cfg_hw *hw_cfg;
 572         const struct drm_plane_state *pstate;
 573         const struct drm_display_mode *mode = &state->adjusted_mode;
 574         bool cursor_plane = false;
 575         bool need_right_mixer = false;
 576         int cnt = 0, i;
 577         int ret;
 578         enum mdp_mixer_stage_id start;
 579
 580         DBG("%s: check", crtc->name);
 581
 582         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
 583                 pstates[cnt].plane = plane;
 584                 pstates[cnt].state = to_mdp5_plane_state(pstate);
 585
 586                 /*
 587                  * if any plane on this crtc uses 2 hwpipes, then we need
 588                  * the crtc to have a right hwmixer.
 589                  */
 590                 if (pstates[cnt].state->r_hwpipe)
 591                         need_right_mixer = true;
 592                 cnt++;
 593
 594                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
 595                         cursor_plane = true;
 596         }
 597
 598         /* bail out early if there aren't any planes */
 599         if (!cnt)
 600                 return 0;
 601
 602         hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
 603
 604         /*
 605          * we need a right hwmixer if the mode's width is greater than a single
 606          * LM's max width
 607          */
 608         if (mode->hdisplay > hw_cfg->lm.max_width)
 609                 need_right_mixer = true;
 610
 611         ret = mdp5_crtc_setup_pipeline(crtc, state, need_right_mixer);
 612         if (ret) {
 613                 dev_err(dev->dev, "couldn't assign mixers %d\n", ret);
 614                 return ret;
 615         }
 616
 617         /* assign a stage based on sorted zpos property */
 618         sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
 619
 620         /* trigger a warning if cursor isn't the highest zorder */
 621         WARN_ON(cursor_plane &&
 622                 (pstates[cnt - 1].plane->type != DRM_PLANE_TYPE_CURSOR));
 623
 624         start = get_start_stage(crtc, state, &pstates[0].state->base);
 625
 626         /* verify that there are not too many planes attached to crtc
 627          * and that we don't have conflicting mixer stages:
 628          */
 629         if ((cnt + start - 1) >= hw_cfg->lm.nb_stages) {
 630                 dev_err(dev->dev, "too many planes! cnt=%d, start stage=%d\n",
 631                         cnt, start);
 632                 return -EINVAL;
 633         }
 634
 635         for (i = 0; i < cnt; i++) {
 636                 if (cursor_plane && (i == (cnt - 1)))
 637                         pstates[i].state->stage = hw_cfg->lm.nb_stages;
 638                 else
 639                         pstates[i].state->stage = start + i;
 640                 DBG("%s: assign pipe %s on stage=%d", crtc->name,
 641                                 pstates[i].plane->name,
 642                                 pstates[i].state->stage);
 643         }
 644
 645         return 0;
 646 }
 647
 648 static void mdp5_crtc_atomic_begin(struct drm_crtc *crtc,
 649                                    struct drm_crtc_state *old_crtc_state)
 650 {
 651         DBG("%s: begin", crtc->name);
 652 }
 653
 654 static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc,
 655                                    struct drm_crtc_state *old_crtc_state)
 656 {
 657         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 658         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 659         struct drm_device *dev = crtc->dev;
 660         unsigned long flags;
 661
 662         DBG("%s: event: %p", crtc->name, crtc->state->event);
 663
 664         WARN_ON(mdp5_crtc->event);
 665
 666         spin_lock_irqsave(&dev->event_lock, flags);
 667         mdp5_crtc->event = crtc->state->event;
 668         spin_unlock_irqrestore(&dev->event_lock, flags);
 669
 670         /*
 671          * If no CTL has been allocated in mdp5_crtc_atomic_check(),
 672          * it means we are trying to flush a CRTC whose state is disabled:
 673          * nothing else needs to be done.
 674          */
 675         /* XXX: Can this happen now ? */
 676         if (unlikely(!mdp5_cstate->ctl))
 677                 return;
 678
 679         blend_setup(crtc);
 680
 681         /* PP_DONE irq is only used by command mode for now.
 682          * It is better to request pending before FLUSH and START trigger
 683          * to make sure no pp_done irq missed.
 684          * This is safe because no pp_done will happen before SW trigger
 685          * in command mode.
 686          */
 687         if (mdp5_cstate->cmd_mode)
 688                 request_pp_done_pending(crtc);
 689
 690         mdp5_crtc->flushed_mask = crtc_flush_all(crtc);
 691
 692         /* XXX are we leaking out state here? */
 693         mdp5_crtc->vblank.irqmask = mdp5_cstate->vblank_irqmask;
 694         mdp5_crtc->err.irqmask = mdp5_cstate->err_irqmask;
 695         mdp5_crtc->pp_done.irqmask = mdp5_cstate->pp_done_irqmask;
 696
 697         request_pending(crtc, PENDING_FLIP);
 698 }
 699
 700 static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h)
 701 {
 702         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 703         uint32_t xres = crtc->mode.hdisplay;
 704         uint32_t yres = crtc->mode.vdisplay;
 705
 706         /*
 707          * Cursor Region Of Interest (ROI) is a plane read from cursor
 708          * buffer to render. The ROI region is determined by the visibility of
 709          * the cursor point. In the default Cursor image the cursor point will
 710          * be at the top left of the cursor image, unless it is specified
 711          * otherwise using hotspot feature.
 712          *
 713          * If the cursor point reaches the right (xres - x < cursor.width) or
 714          * bottom (yres - y < cursor.height) boundary of the screen, then ROI
 715          * width and ROI height need to be evaluated to crop the cursor image
 716          * accordingly.
 717          * (xres-x) will be new cursor width when x > (xres - cursor.width)
 718          * (yres-y) will be new cursor height when y > (yres - cursor.height)
 719          */
 720         *roi_w = min(mdp5_crtc->cursor.width, xres -
 721                         mdp5_crtc->cursor.x);
 722         *roi_h = min(mdp5_crtc->cursor.height, yres -
 723                         mdp5_crtc->cursor.y);
 724 }
 725
 726 static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
 727                 struct drm_file *file, uint32_t handle,
 728                 uint32_t width, uint32_t height)
 729 {
 730         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 731         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 732         struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
 733         struct drm_device *dev = crtc->dev;
 734         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 735         struct platform_device *pdev = mdp5_kms->pdev;
 736         struct msm_kms *kms = &mdp5_kms->base.base;
 737         struct drm_gem_object *cursor_bo, *old_bo = NULL;
 738         uint32_t blendcfg, stride;
 739         uint64_t cursor_addr;
 740         struct mdp5_ctl *ctl;
 741         int ret, lm;
 742         enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL;
 743         uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
 744         uint32_t roi_w, roi_h;
 745         bool cursor_enable = true;
 746         unsigned long flags;
 747
 748         if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
 749                 dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
 750                 return -EINVAL;
 751         }
 752
 753         ctl = mdp5_cstate->ctl;
 754         if (!ctl)
 755                 return -EINVAL;
 756
 757         /* don't support LM cursors when we we have source split enabled */
 758         if (mdp5_cstate->pipeline.r_mixer)
 759                 return -EINVAL;
 760
 761         if (!handle) {
 762                 DBG("Cursor off");
 763                 cursor_enable = false;
 764                 pm_runtime_get_sync(&pdev->dev);
 765                 goto set_cursor;
 766         }
 767
 768         cursor_bo = drm_gem_object_lookup(file, handle);
 769         if (!cursor_bo)
 770                 return -ENOENT;
 771
 772         ret = msm_gem_get_iova(cursor_bo, kms->aspace, &cursor_addr);
 773         if (ret)
 774                 return -EINVAL;
 775
 776         lm = mdp5_cstate->pipeline.mixer->lm;
 777         stride = width * drm_format_plane_cpp(DRM_FORMAT_ARGB8888, 0);
 778
 779         pm_runtime_get_sync(&pdev->dev);
 780
 781         spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
 782         old_bo = mdp5_crtc->cursor.scanout_bo;
 783
 784         mdp5_crtc->cursor.scanout_bo = cursor_bo;
 785         mdp5_crtc->cursor.width = width;
 786         mdp5_crtc->cursor.height = height;
 787
 788         get_roi(crtc, &roi_w, &roi_h);
 789
 790         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride);
 791         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm),
 792                         MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB8888));
 793         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm),
 794                         MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) |
 795                         MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width));
 796         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm),
 797                         MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
 798                         MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
 799         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm), cursor_addr);
 800
 801         blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN;
 802         blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha);
 803         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg);
 804
 805         spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
 806
 807         pm_runtime_put_autosuspend(&pdev->dev);
 808
 809 set_cursor:
 810         ret = mdp5_ctl_set_cursor(ctl, pipeline, 0, cursor_enable);
 811         if (ret) {
 812                 dev_err(dev->dev, "failed to %sable cursor: %d\n",
 813                                 cursor_enable ? "en" : "dis", ret);
 814                 goto end;
 815         }
 816
 817         crtc_flush(crtc, flush_mask);
 818
 819 end:
 820         pm_runtime_put_autosuspend(&pdev->dev);
 821         if (old_bo) {
 822                 drm_flip_work_queue(&mdp5_crtc->unref_cursor_work, old_bo);
 823                 /* enable vblank to complete cursor work: */
 824                 request_pending(crtc, PENDING_CURSOR);
 825         }
 826         return ret;
 827 }
 828
 829 static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 830 {
 831         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 832         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 833         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 834         uint32_t lm = mdp5_cstate->pipeline.mixer->lm;
 835         uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
 836         uint32_t roi_w;
 837         uint32_t roi_h;
 838         unsigned long flags;
 839
 840         /* don't support LM cursors when we we have source split enabled */
 841         if (mdp5_cstate->pipeline.r_mixer)
 842                 return -EINVAL;
 843
 844         /* In case the CRTC is disabled, just drop the cursor update */
 845         if (unlikely(!crtc->state->enable))
 846                 return 0;
 847
 848         mdp5_crtc->cursor.x = x = max(x, 0);
 849         mdp5_crtc->cursor.y = y = max(y, 0);
 850
 851         get_roi(crtc, &roi_w, &roi_h);
 852
 853         pm_runtime_get_sync(&mdp5_kms->pdev->dev);
 854
 855         spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
 856         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm),
 857                         MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
 858                         MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
 859         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(lm),
 860                         MDP5_LM_CURSOR_START_XY_Y_START(y) |
 861                         MDP5_LM_CURSOR_START_XY_X_START(x));
 862         spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
 863
 864         crtc_flush(crtc, flush_mask);
 865
 866         pm_runtime_put_autosuspend(&mdp5_kms->pdev->dev);
 867
 868         return 0;
 869 }
 870
 871 static void
 872 mdp5_crtc_atomic_print_state(struct drm_printer *p,
 873                              const struct drm_crtc_state *state)
 874 {
 875         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state);
 876         struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
 877         struct mdp5_kms *mdp5_kms = get_kms(state->crtc);
 878
 879         if (WARN_ON(!pipeline))
 880                 return;
 881
 882         drm_printf(p, "\thwmixer=%s\n", pipeline->mixer ?
 883                         pipeline->mixer->name : "(null)");
 884
 885         if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT)
 886                 drm_printf(p, "\tright hwmixer=%s\n", pipeline->r_mixer ?
 887                            pipeline->r_mixer->name : "(null)");
 888 }
 889
 890 static void mdp5_crtc_reset(struct drm_crtc *crtc)
 891 {
 892         struct mdp5_crtc_state *mdp5_cstate;
 893
 894         if (crtc->state) {
 895                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
 896                 kfree(to_mdp5_crtc_state(crtc->state));
 897         }
 898
 899         mdp5_cstate = kzalloc(sizeof(*mdp5_cstate), GFP_KERNEL);
 900
 901         if (mdp5_cstate) {
 902                 mdp5_cstate->base.crtc = crtc;
 903                 crtc->state = &mdp5_cstate->base;
 904         }
 905 }
 906
 907 static struct drm_crtc_state *
 908 mdp5_crtc_duplicate_state(struct drm_crtc *crtc)
 909 {
 910         struct mdp5_crtc_state *mdp5_cstate;
 911
 912         if (WARN_ON(!crtc->state))
 913                 return NULL;
 914
 915         mdp5_cstate = kmemdup(to_mdp5_crtc_state(crtc->state),
 916                               sizeof(*mdp5_cstate), GFP_KERNEL);
 917         if (!mdp5_cstate)
 918                 return NULL;
 919
 920         __drm_atomic_helper_crtc_duplicate_state(crtc, &mdp5_cstate->base);
 921
 922         return &mdp5_cstate->base;
 923 }
 924
 925 static void mdp5_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state)
 926 {
 927         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state);
 928
 929         __drm_atomic_helper_crtc_destroy_state(state);
 930
 931         kfree(mdp5_cstate);
 932 }
 933
 934 static const struct drm_crtc_funcs mdp5_crtc_funcs = {
 935         .set_config = drm_atomic_helper_set_config,
 936         .destroy = mdp5_crtc_destroy,
 937         .page_flip = drm_atomic_helper_page_flip,
 938         .reset = mdp5_crtc_reset,
 939         .atomic_duplicate_state = mdp5_crtc_duplicate_state,
 940         .atomic_destroy_state = mdp5_crtc_destroy_state,
 941         .cursor_set = mdp5_crtc_cursor_set,
 942         .cursor_move = mdp5_crtc_cursor_move,
 943         .atomic_print_state = mdp5_crtc_atomic_print_state,
 944 };
 945
 946 static const struct drm_crtc_funcs mdp5_crtc_no_lm_cursor_funcs = {
 947         .set_config = drm_atomic_helper_set_config,
 948         .destroy = mdp5_crtc_destroy,
 949         .page_flip = drm_atomic_helper_page_flip,
 950         .reset = mdp5_crtc_reset,
 951         .atomic_duplicate_state = mdp5_crtc_duplicate_state,
 952         .atomic_destroy_state = mdp5_crtc_destroy_state,
 953         .atomic_print_state = mdp5_crtc_atomic_print_state,
 954 };
 955
 956 static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = {
 957         .mode_set_nofb = mdp5_crtc_mode_set_nofb,
 958         .atomic_check = mdp5_crtc_atomic_check,
 959         .atomic_begin = mdp5_crtc_atomic_begin,
 960         .atomic_flush = mdp5_crtc_atomic_flush,
 961         .atomic_enable = mdp5_crtc_atomic_enable,
 962         .atomic_disable = mdp5_crtc_atomic_disable,
 963 };
 964
 965 static void mdp5_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
 966 {
 967         struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, vblank);
 968         struct drm_crtc *crtc = &mdp5_crtc->base;
 969         struct msm_drm_private *priv = crtc->dev->dev_private;
 970         unsigned pending;
 971
 972         mdp_irq_unregister(&get_kms(crtc)->base, &mdp5_crtc->vblank);
 973
 974         pending = atomic_xchg(&mdp5_crtc->pending, 0);
 975
 976         if (pending & PENDING_FLIP) {
 977                 complete_flip(crtc, NULL);
 978         }
 979
 980         if (pending & PENDING_CURSOR)
 981                 drm_flip_work_commit(&mdp5_crtc->unref_cursor_work, priv->wq);
 982 }
 983
 984 static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
 985 {
 986         struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, err);
 987
 988         DBG("%s: error: %08x", mdp5_crtc->base.name, irqstatus);
 989 }
 990
 991 static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, uint32_t irqstatus)
 992 {
 993         struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc,
 994                                                                 pp_done);
 995
 996         complete(&mdp5_crtc->pp_completion);
 997 }
 998
 999 static void mdp5_crtc_wait_for_pp_done(struct drm_crtc *crtc)
1000 {
1001         struct drm_device *dev = crtc->dev;
1002         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
1003         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1004         int ret;
1005
1006         ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion,
1007                                                 msecs_to_jiffies(50));
1008         if (ret == 0)
1009                 dev_warn(dev->dev, "pp done time out, lm=%d\n",
1010                          mdp5_cstate->pipeline.mixer->lm);
1011 }
1012
1013 static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc)
1014 {
1015         struct drm_device *dev = crtc->dev;
1016         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
1017         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1018         struct mdp5_ctl *ctl = mdp5_cstate->ctl;
1019         int ret;
1020
1021         /* Should not call this function if crtc is disabled. */
1022         if (!ctl)
1023                 return;
1024
1025         ret = drm_crtc_vblank_get(crtc);
1026         if (ret)
1027                 return;
1028
1029         ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue,
1030                 ((mdp5_ctl_get_commit_status(ctl) &
1031                 mdp5_crtc->flushed_mask) == 0),
1032                 msecs_to_jiffies(50));
1033         if (ret <= 0)
1034                 dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp5_crtc->id);
1035
1036         mdp5_crtc->flushed_mask = 0;
1037
1038         drm_crtc_vblank_put(crtc);
1039 }
1040
1041 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc)
1042 {
1043         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
1044         return mdp5_crtc->vblank.irqmask;
1045 }
1046
1047 void mdp5_crtc_set_pipeline(struct drm_crtc *crtc)
1048 {
1049         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1050         struct mdp5_kms *mdp5_kms = get_kms(crtc);
1051
1052         /* should this be done elsewhere ? */
1053         mdp_irq_update(&mdp5_kms->base);
1054
1055         mdp5_ctl_set_pipeline(mdp5_cstate->ctl, &mdp5_cstate->pipeline);
1056 }
1057
1058 struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc)
1059 {
1060         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1061
1062         return mdp5_cstate->ctl;
1063 }
1064
1065 struct mdp5_hw_mixer *mdp5_crtc_get_mixer(struct drm_crtc *crtc)
1066 {
1067         struct mdp5_crtc_state *mdp5_cstate;
1068
1069         if (WARN_ON(!crtc))
1070                 return ERR_PTR(-EINVAL);
1071
1072         mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1073
1074         return WARN_ON(!mdp5_cstate->pipeline.mixer) ?
1075                 ERR_PTR(-EINVAL) : mdp5_cstate->pipeline.mixer;
1076 }
1077
1078 struct mdp5_pipeline *mdp5_crtc_get_pipeline(struct drm_crtc *crtc)
1079 {
1080         struct mdp5_crtc_state *mdp5_cstate;
1081
1082         if (WARN_ON(!crtc))
1083                 return ERR_PTR(-EINVAL);
1084
1085         mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1086
1087         return &mdp5_cstate->pipeline;
1088 }
1089
1090 void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc)
1091 {
1092         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1093
1094         if (mdp5_cstate->cmd_mode)
1095                 mdp5_crtc_wait_for_pp_done(crtc);
1096         else
1097                 mdp5_crtc_wait_for_flush_done(crtc);
1098 }
1099
1100 /* initialize crtc */
1101 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
1102                                 struct drm_plane *plane,
1103                                 struct drm_plane *cursor_plane, int id)
1104 {
1105         struct drm_crtc *crtc = NULL;
1106         struct mdp5_crtc *mdp5_crtc;
1107
1108         mdp5_crtc = kzalloc(sizeof(*mdp5_crtc), GFP_KERNEL);
1109         if (!mdp5_crtc)
1110                 return ERR_PTR(-ENOMEM);
1111
1112         crtc = &mdp5_crtc->base;
1113
1114         mdp5_crtc->id = id;
1115
1116         spin_lock_init(&mdp5_crtc->lm_lock);
1117         spin_lock_init(&mdp5_crtc->cursor.lock);
1118         init_completion(&mdp5_crtc->pp_completion);
1119
1120         mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq;
1121         mdp5_crtc->err.irq = mdp5_crtc_err_irq;
1122         mdp5_crtc->pp_done.irq = mdp5_crtc_pp_done_irq;
1123
1124         if (cursor_plane)
1125                 drm_crtc_init_with_planes(dev, crtc, plane, cursor_plane,
1126                                           &mdp5_crtc_no_lm_cursor_funcs, NULL);
1127         else
1128                 drm_crtc_init_with_planes(dev, crtc, plane, NULL,
1129                                           &mdp5_crtc_funcs, NULL);
1130
1131         drm_flip_work_init(&mdp5_crtc->unref_cursor_work,
1132                         "unref cursor", unref_cursor_worker);
1133
1134         drm_crtc_helper_add(crtc, &mdp5_crtc_helper_funcs);
1135         plane->crtc = crtc;
1136
1137         return crtc;
1138 }