drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

   1 /*
   2  * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved.
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt)     "[drm:%s:%d] " fmt, __func__, __LINE__
  20
  21 #include <linux/debugfs.h>
  22 #include <linux/dma-buf.h>
  23
  24 #include <drm/drm_atomic_uapi.h>
  25
  26 #include "msm_drv.h"
  27 #include "dpu_kms.h"
  28 #include "dpu_formats.h"
  29 #include "dpu_hw_sspp.h"
  30 #include "dpu_hw_catalog_format.h"
  31 #include "dpu_trace.h"
  32 #include "dpu_crtc.h"
  33 #include "dpu_vbif.h"
  34 #include "dpu_plane.h"
  35
  36 #define DPU_DEBUG_PLANE(pl, fmt, ...) DPU_DEBUG("plane%d " fmt,\
  37                 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  38
  39 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\
  40                 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  41
  42 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
  43 #define PHASE_STEP_SHIFT        21
  44 #define PHASE_STEP_UNIT_SCALE   ((int) (1 << PHASE_STEP_SHIFT))
  45 #define PHASE_RESIDUAL          15
  46
  47 #define SHARP_STRENGTH_DEFAULT  32
  48 #define SHARP_EDGE_THR_DEFAULT  112
  49 #define SHARP_SMOOTH_THR_DEFAULT        8
  50 #define SHARP_NOISE_THR_DEFAULT 2
  51
  52 #define DPU_NAME_SIZE  12
  53
  54 #define DPU_PLANE_COLOR_FILL_FLAG       BIT(31)
  55 #define DPU_ZPOS_MAX 255
  56
  57 /* multirect rect index */
  58 enum {
  59         R0,
  60         R1,
  61         R_MAX
  62 };
  63
  64 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4
  65 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3
  66
  67 #define DEFAULT_REFRESH_RATE    60
  68
  69 /**
  70  * enum dpu_plane_qos - Different qos configurations for each pipe
  71  *
  72  * @DPU_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
  73  * @DPU_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
  74  *      this configuration is mutually exclusive from VBLANK_CTRL.
  75  * @DPU_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
  76  */
  77 enum dpu_plane_qos {
  78         DPU_PLANE_QOS_VBLANK_CTRL = BIT(0),
  79         DPU_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
  80         DPU_PLANE_QOS_PANIC_CTRL = BIT(2),
  81 };
  82
  83 /*
  84  * struct dpu_plane - local dpu plane structure
  85  * @aspace: address space pointer
  86  * @csc_ptr: Points to dpu_csc_cfg structure to use for current
  87  * @mplane_list: List of multirect planes of the same pipe
  88  * @catalog: Points to dpu catalog structure
  89  * @revalidate: force revalidation of all the plane properties
  90  */
  91 struct dpu_plane {
  92         struct drm_plane base;
  93
  94         struct mutex lock;
  95
  96         enum dpu_sspp pipe;
  97         uint32_t features;      /* capabilities from catalog */
  98         uint32_t nformats;
  99         uint32_t formats[64];
 100
 101         struct dpu_hw_pipe *pipe_hw;
 102         struct dpu_hw_pipe_cfg pipe_cfg;
 103         struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
 104         uint32_t color_fill;
 105         bool is_error;
 106         bool is_rt_pipe;
 107         bool is_virtual;
 108         struct list_head mplane_list;
 109         struct dpu_mdss_cfg *catalog;
 110
 111         struct dpu_csc_cfg *csc_ptr;
 112
 113         const struct dpu_sspp_sub_blks *pipe_sblk;
 114         char pipe_name[DPU_NAME_SIZE];
 115
 116         /* debugfs related stuff */
 117         struct dentry *debugfs_root;
 118         struct dpu_debugfs_regset32 debugfs_src;
 119         struct dpu_debugfs_regset32 debugfs_scaler;
 120         struct dpu_debugfs_regset32 debugfs_csc;
 121         bool debugfs_default_scale;
 122 };
 123
 124 #define to_dpu_plane(x) container_of(x, struct dpu_plane, base)
 125
 126 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane)
 127 {
 128         struct msm_drm_private *priv = plane->dev->dev_private;
 129
 130         return to_dpu_kms(priv->kms);
 131 }
 132
 133 /**
 134  * _dpu_plane_calc_fill_level - calculate fill level of the given source format
 135  * @plane:              Pointer to drm plane
 136  * @fmt:                Pointer to source buffer format
 137  * @src_wdith:          width of source buffer
 138  * Return: fill level corresponding to the source buffer/format or 0 if error
 139  */
 140 static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
 141                 const struct dpu_format *fmt, u32 src_width)
 142 {
 143         struct dpu_plane *pdpu, *tmp;
 144         struct dpu_plane_state *pstate;
 145         u32 fixed_buff_size;
 146         u32 total_fl;
 147
 148         if (!fmt || !plane->state || !src_width || !fmt->bpp) {
 149                 DPU_ERROR("invalid arguments\n");
 150                 return 0;
 151         }
 152
 153         pdpu = to_dpu_plane(plane);
 154         pstate = to_dpu_plane_state(plane->state);
 155         fixed_buff_size = pdpu->pipe_sblk->common->pixel_ram_size;
 156
 157         list_for_each_entry(tmp, &pdpu->mplane_list, mplane_list) {
 158                 if (!tmp->base.state->visible)
 159                         continue;
 160                 DPU_DEBUG("plane%d/%d src_width:%d/%d\n",
 161                                 pdpu->base.base.id, tmp->base.base.id,
 162                                 src_width,
 163                                 drm_rect_width(&tmp->pipe_cfg.src_rect));
 164                 src_width = max_t(u32, src_width,
 165                                   drm_rect_width(&tmp->pipe_cfg.src_rect));
 166         }
 167
 168         if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) {
 169                 if (fmt->chroma_sample == DPU_CHROMA_420) {
 170                         /* NV12 */
 171                         total_fl = (fixed_buff_size / 2) /
 172                                 ((src_width + 32) * fmt->bpp);
 173                 } else {
 174                         /* non NV12 */
 175                         total_fl = (fixed_buff_size / 2) * 2 /
 176                                 ((src_width + 32) * fmt->bpp);
 177                 }
 178         } else {
 179                 if (pstate->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) {
 180                         total_fl = (fixed_buff_size / 2) * 2 /
 181                                 ((src_width + 32) * fmt->bpp);
 182                 } else {
 183                         total_fl = (fixed_buff_size) * 2 /
 184                                 ((src_width + 32) * fmt->bpp);
 185                 }
 186         }
 187
 188         DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s w:%u fl:%u\n",
 189                         plane->base.id, pdpu->pipe - SSPP_VIG0,
 190                         (char *)&fmt->base.pixel_format,
 191                         src_width, total_fl);
 192
 193         return total_fl;
 194 }
 195
 196 /**
 197  * _dpu_plane_get_qos_lut - get LUT mapping based on fill level
 198  * @tbl:                Pointer to LUT table
 199  * @total_fl:           fill level
 200  * Return: LUT setting corresponding to the fill level
 201  */
 202 static u64 _dpu_plane_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
 203                 u32 total_fl)
 204 {
 205         int i;
 206
 207         if (!tbl || !tbl->nentry || !tbl->entries)
 208                 return 0;
 209
 210         for (i = 0; i < tbl->nentry; i++)
 211                 if (total_fl <= tbl->entries[i].fl)
 212                         return tbl->entries[i].lut;
 213
 214         /* if last fl is zero, use as default */
 215         if (!tbl->entries[i-1].fl)
 216                 return tbl->entries[i-1].lut;
 217
 218         return 0;
 219 }
 220
 221 /**
 222  * _dpu_plane_set_qos_lut - set QoS LUT of the given plane
 223  * @plane:              Pointer to drm plane
 224  * @fb:                 Pointer to framebuffer associated with the given plane
 225  */
 226 static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
 227                 struct drm_framebuffer *fb)
 228 {
 229         struct dpu_plane *pdpu = to_dpu_plane(plane);
 230         const struct dpu_format *fmt = NULL;
 231         u64 qos_lut;
 232         u32 total_fl = 0, lut_usage;
 233
 234         if (!pdpu->is_rt_pipe) {
 235                 lut_usage = DPU_QOS_LUT_USAGE_NRT;
 236         } else {
 237                 fmt = dpu_get_dpu_format_ext(
 238                                 fb->format->format,
 239                                 fb->modifier);
 240                 total_fl = _dpu_plane_calc_fill_level(plane, fmt,
 241                                 drm_rect_width(&pdpu->pipe_cfg.src_rect));
 242
 243                 if (fmt && DPU_FORMAT_IS_LINEAR(fmt))
 244                         lut_usage = DPU_QOS_LUT_USAGE_LINEAR;
 245                 else
 246                         lut_usage = DPU_QOS_LUT_USAGE_MACROTILE;
 247         }
 248
 249         qos_lut = _dpu_plane_get_qos_lut(
 250                         &pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl);
 251
 252         pdpu->pipe_qos_cfg.creq_lut = qos_lut;
 253
 254         trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0,
 255                         (fmt) ? fmt->base.pixel_format : 0,
 256                         pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage);
 257
 258         DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n",
 259                         plane->base.id,
 260                         pdpu->pipe - SSPP_VIG0,
 261                         fmt ? (char *)&fmt->base.pixel_format : NULL,
 262                         pdpu->is_rt_pipe, total_fl, qos_lut);
 263
 264         pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, &pdpu->pipe_qos_cfg);
 265 }
 266
 267 /**
 268  * _dpu_plane_set_panic_lut - set danger/safe LUT of the given plane
 269  * @plane:              Pointer to drm plane
 270  * @fb:                 Pointer to framebuffer associated with the given plane
 271  */
 272 static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
 273                 struct drm_framebuffer *fb)
 274 {
 275         struct dpu_plane *pdpu = to_dpu_plane(plane);
 276         const struct dpu_format *fmt = NULL;
 277         u32 danger_lut, safe_lut;
 278
 279         if (!pdpu->is_rt_pipe) {
 280                 danger_lut = pdpu->catalog->perf.danger_lut_tbl
 281                                 [DPU_QOS_LUT_USAGE_NRT];
 282                 safe_lut = pdpu->catalog->perf.safe_lut_tbl
 283                                 [DPU_QOS_LUT_USAGE_NRT];
 284         } else {
 285                 fmt = dpu_get_dpu_format_ext(
 286                                 fb->format->format,
 287                                 fb->modifier);
 288
 289                 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) {
 290                         danger_lut = pdpu->catalog->perf.danger_lut_tbl
 291                                         [DPU_QOS_LUT_USAGE_LINEAR];
 292                         safe_lut = pdpu->catalog->perf.safe_lut_tbl
 293                                         [DPU_QOS_LUT_USAGE_LINEAR];
 294                 } else {
 295                         danger_lut = pdpu->catalog->perf.danger_lut_tbl
 296                                         [DPU_QOS_LUT_USAGE_MACROTILE];
 297                         safe_lut = pdpu->catalog->perf.safe_lut_tbl
 298                                         [DPU_QOS_LUT_USAGE_MACROTILE];
 299                 }
 300         }
 301
 302         pdpu->pipe_qos_cfg.danger_lut = danger_lut;
 303         pdpu->pipe_qos_cfg.safe_lut = safe_lut;
 304
 305         trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
 306                         (fmt) ? fmt->base.pixel_format : 0,
 307                         (fmt) ? fmt->fetch_mode : 0,
 308                         pdpu->pipe_qos_cfg.danger_lut,
 309                         pdpu->pipe_qos_cfg.safe_lut);
 310
 311         DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n",
 312                 plane->base.id,
 313                 pdpu->pipe - SSPP_VIG0,
 314                 fmt ? (char *)&fmt->base.pixel_format : NULL,
 315                 fmt ? fmt->fetch_mode : -1,
 316                 pdpu->pipe_qos_cfg.danger_lut,
 317                 pdpu->pipe_qos_cfg.safe_lut);
 318
 319         pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw,
 320                         &pdpu->pipe_qos_cfg);
 321 }
 322
 323 /**
 324  * _dpu_plane_set_qos_ctrl - set QoS control of the given plane
 325  * @plane:              Pointer to drm plane
 326  * @enable:             true to enable QoS control
 327  * @flags:              QoS control mode (enum dpu_plane_qos)
 328  */
 329 static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
 330         bool enable, u32 flags)
 331 {
 332         struct dpu_plane *pdpu = to_dpu_plane(plane);
 333
 334         if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
 335                 pdpu->pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank;
 336                 pdpu->pipe_qos_cfg.danger_vblank =
 337                                 pdpu->pipe_sblk->danger_vblank;
 338                 pdpu->pipe_qos_cfg.vblank_en = enable;
 339         }
 340
 341         if (flags & DPU_PLANE_QOS_VBLANK_AMORTIZE) {
 342                 /* this feature overrules previous VBLANK_CTRL */
 343                 pdpu->pipe_qos_cfg.vblank_en = false;
 344                 pdpu->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
 345         }
 346
 347         if (flags & DPU_PLANE_QOS_PANIC_CTRL)
 348                 pdpu->pipe_qos_cfg.danger_safe_en = enable;
 349
 350         if (!pdpu->is_rt_pipe) {
 351                 pdpu->pipe_qos_cfg.vblank_en = false;
 352                 pdpu->pipe_qos_cfg.danger_safe_en = false;
 353         }
 354
 355         DPU_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
 356                 plane->base.id,
 357                 pdpu->pipe - SSPP_VIG0,
 358                 pdpu->pipe_qos_cfg.danger_safe_en,
 359                 pdpu->pipe_qos_cfg.vblank_en,
 360                 pdpu->pipe_qos_cfg.creq_vblank,
 361                 pdpu->pipe_qos_cfg.danger_vblank,
 362                 pdpu->is_rt_pipe);
 363
 364         pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw,
 365                         &pdpu->pipe_qos_cfg);
 366 }
 367
 368 /**
 369  * _dpu_plane_set_ot_limit - set OT limit for the given plane
 370  * @plane:              Pointer to drm plane
 371  * @crtc:               Pointer to drm crtc
 372  */
 373 static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
 374                 struct drm_crtc *crtc)
 375 {
 376         struct dpu_plane *pdpu = to_dpu_plane(plane);
 377         struct dpu_vbif_set_ot_params ot_params;
 378         struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
 379
 380         memset(&ot_params, 0, sizeof(ot_params));
 381         ot_params.xin_id = pdpu->pipe_hw->cap->xin_id;
 382         ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE;
 383         ot_params.width = drm_rect_width(&pdpu->pipe_cfg.src_rect);
 384         ot_params.height = drm_rect_height(&pdpu->pipe_cfg.src_rect);
 385         ot_params.is_wfd = !pdpu->is_rt_pipe;
 386         ot_params.frame_rate = crtc->mode.vrefresh;
 387         ot_params.vbif_idx = VBIF_RT;
 388         ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
 389         ot_params.rd = true;
 390
 391         dpu_vbif_set_ot_limit(dpu_kms, &ot_params);
 392 }
 393
 394 /**
 395  * _dpu_plane_set_vbif_qos - set vbif QoS for the given plane
 396  * @plane:              Pointer to drm plane
 397  */
 398 static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
 399 {
 400         struct dpu_plane *pdpu = to_dpu_plane(plane);
 401         struct dpu_vbif_set_qos_params qos_params;
 402         struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
 403
 404         memset(&qos_params, 0, sizeof(qos_params));
 405         qos_params.vbif_idx = VBIF_RT;
 406         qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
 407         qos_params.xin_id = pdpu->pipe_hw->cap->xin_id;
 408         qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0;
 409         qos_params.is_rt = pdpu->is_rt_pipe;
 410
 411         DPU_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
 412                         plane->base.id, qos_params.num,
 413                         qos_params.vbif_idx,
 414                         qos_params.xin_id, qos_params.is_rt,
 415                         qos_params.clk_ctrl);
 416
 417         dpu_vbif_set_qos_remap(dpu_kms, &qos_params);
 418 }
 419
 420 static void _dpu_plane_set_scanout(struct drm_plane *plane,
 421                 struct dpu_plane_state *pstate,
 422                 struct dpu_hw_pipe_cfg *pipe_cfg,
 423                 struct drm_framebuffer *fb)
 424 {
 425         struct dpu_plane *pdpu = to_dpu_plane(plane);
 426         struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
 427         struct msm_gem_address_space *aspace = kms->base.aspace;
 428         int ret;
 429
 430         ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
 431         if (ret == -EAGAIN)
 432                 DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n");
 433         else if (ret)
 434                 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
 435         else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
 436                 trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx,
 437                                             &pipe_cfg->layout,
 438                                             pstate->multirect_index);
 439                 pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg,
 440                                                 pstate->multirect_index);
 441         }
 442 }
 443
 444 static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
 445                 struct dpu_plane_state *pstate,
 446                 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
 447                 struct dpu_hw_scaler3_cfg *scale_cfg,
 448                 const struct dpu_format *fmt,
 449                 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
 450 {
 451         uint32_t i;
 452
 453         memset(scale_cfg, 0, sizeof(*scale_cfg));
 454         memset(&pstate->pixel_ext, 0, sizeof(struct dpu_hw_pixel_ext));
 455
 456         scale_cfg->phase_step_x[DPU_SSPP_COMP_0] =
 457                 mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w);
 458         scale_cfg->phase_step_y[DPU_SSPP_COMP_0] =
 459                 mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h);
 460
 461
 462         scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] =
 463                 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v;
 464         scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] =
 465                 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h;
 466
 467         scale_cfg->phase_step_x[DPU_SSPP_COMP_2] =
 468                 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2];
 469         scale_cfg->phase_step_y[DPU_SSPP_COMP_2] =
 470                 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2];
 471
 472         scale_cfg->phase_step_x[DPU_SSPP_COMP_3] =
 473                 scale_cfg->phase_step_x[DPU_SSPP_COMP_0];
 474         scale_cfg->phase_step_y[DPU_SSPP_COMP_3] =
 475                 scale_cfg->phase_step_y[DPU_SSPP_COMP_0];
 476
 477         for (i = 0; i < DPU_MAX_PLANES; i++) {
 478                 scale_cfg->src_width[i] = src_w;
 479                 scale_cfg->src_height[i] = src_h;
 480                 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) {
 481                         scale_cfg->src_width[i] /= chroma_subsmpl_h;
 482                         scale_cfg->src_height[i] /= chroma_subsmpl_v;
 483                 }
 484                 scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H;
 485                 scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V;
 486                 pstate->pixel_ext.num_ext_pxls_top[i] =
 487                         scale_cfg->src_height[i];
 488                 pstate->pixel_ext.num_ext_pxls_left[i] =
 489                         scale_cfg->src_width[i];
 490         }
 491         if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
 492                 && (src_w == dst_w))
 493                 return;
 494
 495         scale_cfg->dst_width = dst_w;
 496         scale_cfg->dst_height = dst_h;
 497         scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL;
 498         scale_cfg->uv_filter_cfg = DPU_SCALE_BIL;
 499         scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL;
 500         scale_cfg->lut_flag = 0;
 501         scale_cfg->blend_cfg = 1;
 502         scale_cfg->enable = 1;
 503 }
 504
 505 static void _dpu_plane_setup_csc(struct dpu_plane *pdpu)
 506 {
 507         static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = {
 508                 {
 509                         /* S15.16 format */
 510                         0x00012A00, 0x00000000, 0x00019880,
 511                         0x00012A00, 0xFFFF9B80, 0xFFFF3000,
 512                         0x00012A00, 0x00020480, 0x00000000,
 513                 },
 514                 /* signed bias */
 515                 { 0xfff0, 0xff80, 0xff80,},
 516                 { 0x0, 0x0, 0x0,},
 517                 /* unsigned clamp */
 518                 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
 519                 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
 520         };
 521         static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = {
 522                 {
 523                         /* S15.16 format */
 524                         0x00012A00, 0x00000000, 0x00019880,
 525                         0x00012A00, 0xFFFF9B80, 0xFFFF3000,
 526                         0x00012A00, 0x00020480, 0x00000000,
 527                         },
 528                 /* signed bias */
 529                 { 0xffc0, 0xfe00, 0xfe00,},
 530                 { 0x0, 0x0, 0x0,},
 531                 /* unsigned clamp */
 532                 { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
 533                 { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
 534         };
 535
 536         if (!pdpu) {
 537                 DPU_ERROR("invalid plane\n");
 538                 return;
 539         }
 540
 541         if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->features)
 542                 pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc10_YUV2RGB_601L;
 543         else
 544                 pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc_YUV2RGB_601L;
 545
 546         DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n",
 547                         pdpu->csc_ptr->csc_mv[0],
 548                         pdpu->csc_ptr->csc_mv[1],
 549                         pdpu->csc_ptr->csc_mv[2]);
 550 }
 551
 552 static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
 553                 struct dpu_plane_state *pstate,
 554                 const struct dpu_format *fmt, bool color_fill)
 555 {
 556         uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
 557
 558         /* don't chroma subsample if decimating */
 559         chroma_subsmpl_h =
 560                 drm_format_horz_chroma_subsampling(fmt->base.pixel_format);
 561         chroma_subsmpl_v =
 562                 drm_format_vert_chroma_subsampling(fmt->base.pixel_format);
 563
 564         /* update scaler. calculate default config for QSEED3 */
 565         _dpu_plane_setup_scaler3(pdpu, pstate,
 566                         drm_rect_width(&pdpu->pipe_cfg.src_rect),
 567                         drm_rect_height(&pdpu->pipe_cfg.src_rect),
 568                         drm_rect_width(&pdpu->pipe_cfg.dst_rect),
 569                         drm_rect_height(&pdpu->pipe_cfg.dst_rect),
 570                         &pstate->scaler3_cfg, fmt,
 571                         chroma_subsmpl_h, chroma_subsmpl_v);
 572 }
 573
 574 /**
 575  * _dpu_plane_color_fill - enables color fill on plane
 576  * @pdpu:   Pointer to DPU plane object
 577  * @color:  RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
 578  * @alpha:  8-bit fill alpha value, 255 selects 100% alpha
 579  * Returns: 0 on success
 580  */
 581 static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
 582                 uint32_t color, uint32_t alpha)
 583 {
 584         const struct dpu_format *fmt;
 585         const struct drm_plane *plane = &pdpu->base;
 586         struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
 587
 588         DPU_DEBUG_PLANE(pdpu, "\n");
 589
 590         /*
 591          * select fill format to match user property expectation,
 592          * h/w only supports RGB variants
 593          */
 594         fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888);
 595
 596         /* update sspp */
 597         if (fmt && pdpu->pipe_hw->ops.setup_solidfill) {
 598                 pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw,
 599                                 (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
 600                                 pstate->multirect_index);
 601
 602                 /* override scaler/decimation if solid fill */
 603                 pdpu->pipe_cfg.src_rect.x1 = 0;
 604                 pdpu->pipe_cfg.src_rect.y1 = 0;
 605                 pdpu->pipe_cfg.src_rect.x2 =
 606                         drm_rect_width(&pdpu->pipe_cfg.dst_rect);
 607                 pdpu->pipe_cfg.src_rect.y2 =
 608                         drm_rect_height(&pdpu->pipe_cfg.dst_rect);
 609                 _dpu_plane_setup_scaler(pdpu, pstate, fmt, true);
 610
 611                 if (pdpu->pipe_hw->ops.setup_format)
 612                         pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw,
 613                                         fmt, DPU_SSPP_SOLID_FILL,
 614                                         pstate->multirect_index);
 615
 616                 if (pdpu->pipe_hw->ops.setup_rects)
 617                         pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
 618                                         &pdpu->pipe_cfg,
 619                                         pstate->multirect_index);
 620
 621                 if (pdpu->pipe_hw->ops.setup_pe)
 622                         pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
 623                                         &pstate->pixel_ext);
 624
 625                 if (pdpu->pipe_hw->ops.setup_scaler &&
 626                                 pstate->multirect_index != DPU_SSPP_RECT_1)
 627                         pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
 628                                         &pdpu->pipe_cfg, &pstate->pixel_ext,
 629                                         &pstate->scaler3_cfg);
 630         }
 631
 632         return 0;
 633 }
 634
 635 void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state)
 636 {
 637         struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state);
 638
 639         pstate->multirect_index = DPU_SSPP_RECT_SOLO;
 640         pstate->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
 641 }
 642
 643 int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
 644 {
 645         struct dpu_plane_state *pstate[R_MAX];
 646         const struct drm_plane_state *drm_state[R_MAX];
 647         struct drm_rect src[R_MAX], dst[R_MAX];
 648         struct dpu_plane *dpu_plane[R_MAX];
 649         const struct dpu_format *fmt[R_MAX];
 650         int i, buffer_lines;
 651         unsigned int max_tile_height = 1;
 652         bool parallel_fetch_qualified = true;
 653         bool has_tiled_rect = false;
 654
 655         for (i = 0; i < R_MAX; i++) {
 656                 const struct msm_format *msm_fmt;
 657
 658                 drm_state[i] = i ? plane->r1 : plane->r0;
 659                 msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
 660                 fmt[i] = to_dpu_format(msm_fmt);
 661
 662                 if (DPU_FORMAT_IS_UBWC(fmt[i])) {
 663                         has_tiled_rect = true;
 664                         if (fmt[i]->tile_height > max_tile_height)
 665                                 max_tile_height = fmt[i]->tile_height;
 666                 }
 667         }
 668
 669         for (i = 0; i < R_MAX; i++) {
 670                 int width_threshold;
 671
 672                 pstate[i] = to_dpu_plane_state(drm_state[i]);
 673                 dpu_plane[i] = to_dpu_plane(drm_state[i]->plane);
 674
 675                 if (pstate[i] == NULL) {
 676                         DPU_ERROR("DPU plane state of plane id %d is NULL\n",
 677                                 drm_state[i]->plane->base.id);
 678                         return -EINVAL;
 679                 }
 680
 681                 src[i].x1 = drm_state[i]->src_x >> 16;
 682                 src[i].y1 = drm_state[i]->src_y >> 16;
 683                 src[i].x2 = src[i].x1 + (drm_state[i]->src_w >> 16);
 684                 src[i].y2 = src[i].y1 + (drm_state[i]->src_h >> 16);
 685
 686                 dst[i] = drm_plane_state_dest(drm_state[i]);
 687
 688                 if (drm_rect_calc_hscale(&src[i], &dst[i], 1, 1) != 1 ||
 689                     drm_rect_calc_vscale(&src[i], &dst[i], 1, 1) != 1) {
 690                         DPU_ERROR_PLANE(dpu_plane[i],
 691                                 "scaling is not supported in multirect mode\n");
 692                         return -EINVAL;
 693                 }
 694
 695                 if (DPU_FORMAT_IS_YUV(fmt[i])) {
 696                         DPU_ERROR_PLANE(dpu_plane[i],
 697                                 "Unsupported format for multirect mode\n");
 698                         return -EINVAL;
 699                 }
 700
 701                 /**
 702                  * SSPP PD_MEM is split half - one for each RECT.
 703                  * Tiled formats need 5 lines of buffering while fetching
 704                  * whereas linear formats need only 2 lines.
 705                  * So we cannot support more than half of the supported SSPP
 706                  * width for tiled formats.
 707                  */
 708                 width_threshold = dpu_plane[i]->pipe_sblk->common->maxlinewidth;
 709                 if (has_tiled_rect)
 710                         width_threshold /= 2;
 711
 712                 if (parallel_fetch_qualified &&
 713                     drm_rect_width(&src[i]) > width_threshold)
 714                         parallel_fetch_qualified = false;
 715
 716         }
 717
 718         /* Validate RECT's and set the mode */
 719
 720         /* Prefer PARALLEL FETCH Mode over TIME_MX Mode */
 721         if (parallel_fetch_qualified) {
 722                 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
 723                 pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
 724
 725                 goto done;
 726         }
 727
 728         /* TIME_MX Mode */
 729         buffer_lines = 2 * max_tile_height;
 730
 731         if (dst[R1].y1 >= dst[R0].y2 + buffer_lines ||
 732             dst[R0].y1 >= dst[R1].y2 + buffer_lines) {
 733                 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
 734                 pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
 735         } else {
 736                 DPU_ERROR(
 737                         "No multirect mode possible for the planes (%d - %d)\n",
 738                         drm_state[R0]->plane->base.id,
 739                         drm_state[R1]->plane->base.id);
 740                 return -EINVAL;
 741         }
 742
 743 done:
 744         if (dpu_plane[R0]->is_virtual) {
 745                 pstate[R0]->multirect_index = DPU_SSPP_RECT_1;
 746                 pstate[R1]->multirect_index = DPU_SSPP_RECT_0;
 747         } else {
 748                 pstate[R0]->multirect_index = DPU_SSPP_RECT_0;
 749                 pstate[R1]->multirect_index = DPU_SSPP_RECT_1;
 750         };
 751
 752         DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n",
 753                 pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
 754         DPU_DEBUG_PLANE(dpu_plane[R1], "R1: %d - %d\n",
 755                 pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
 756         return 0;
 757 }
 758
 759 /**
 760  * dpu_plane_get_ctl_flush - get control flush for the given plane
 761  * @plane: Pointer to drm plane structure
 762  * @ctl: Pointer to hardware control driver
 763  * @flush_sspp: Pointer to sspp flush control word
 764  */
 765 void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl,
 766                 u32 *flush_sspp)
 767 {
 768         *flush_sspp = ctl->ops.get_bitmask_sspp(ctl, dpu_plane_pipe(plane));
 769 }
 770
 771 static int dpu_plane_prepare_fb(struct drm_plane *plane,
 772                 struct drm_plane_state *new_state)
 773 {
 774         struct drm_framebuffer *fb = new_state->fb;
 775         struct dpu_plane *pdpu = to_dpu_plane(plane);
 776         struct dpu_plane_state *pstate = to_dpu_plane_state(new_state);
 777         struct dpu_hw_fmt_layout layout;
 778         struct drm_gem_object *obj;
 779         struct msm_gem_object *msm_obj;
 780         struct dma_fence *fence;
 781         struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
 782         int ret;
 783
 784         if (!new_state->fb)
 785                 return 0;
 786
 787         DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id);
 788
 789         /* cache aspace */
 790         pstate->aspace = kms->base.aspace;
 791
 792         /*
 793          * TODO: Need to sort out the msm_framebuffer_prepare() call below so
 794          *       we can use msm_atomic_prepare_fb() instead of doing the
 795          *       implicit fence and fb prepare by hand here.
 796          */
 797         obj = msm_framebuffer_bo(new_state->fb, 0);
 798         msm_obj = to_msm_bo(obj);
 799         fence = reservation_object_get_excl_rcu(msm_obj->resv);
 800         if (fence)
 801                 drm_atomic_set_fence_for_plane(new_state, fence);
 802
 803         if (pstate->aspace) {
 804                 ret = msm_framebuffer_prepare(new_state->fb,
 805                                 pstate->aspace);
 806                 if (ret) {
 807                         DPU_ERROR("failed to prepare framebuffer\n");
 808                         return ret;
 809                 }
 810         }
 811
 812         /* validate framebuffer layout before commit */
 813         ret = dpu_format_populate_layout(pstate->aspace,
 814                         new_state->fb, &layout);
 815         if (ret) {
 816                 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
 817                 return ret;
 818         }
 819
 820         return 0;
 821 }
 822
 823 static void dpu_plane_cleanup_fb(struct drm_plane *plane,
 824                 struct drm_plane_state *old_state)
 825 {
 826         struct dpu_plane *pdpu = to_dpu_plane(plane);
 827         struct dpu_plane_state *old_pstate;
 828
 829         if (!old_state || !old_state->fb)
 830                 return;
 831
 832         old_pstate = to_dpu_plane_state(old_state);
 833
 834         DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id);
 835
 836         msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
 837 }
 838
 839 static bool dpu_plane_validate_src(struct drm_rect *src,
 840                                    struct drm_rect *fb_rect,
 841                                    uint32_t min_src_size)
 842 {
 843         /* Ensure fb size is supported */
 844         if (drm_rect_width(fb_rect) > MAX_IMG_WIDTH ||
 845             drm_rect_height(fb_rect) > MAX_IMG_HEIGHT)
 846                 return false;
 847
 848         /* Ensure src rect is above the minimum size */
 849         if (drm_rect_width(src) < min_src_size ||
 850             drm_rect_height(src) < min_src_size)
 851                 return false;
 852
 853         /* Ensure src is fully encapsulated in fb */
 854         return drm_rect_intersect(fb_rect, src) &&
 855                 drm_rect_equals(fb_rect, src);
 856 }
 857
 858 static int dpu_plane_atomic_check(struct drm_plane *plane,
 859                                   struct drm_plane_state *state)
 860 {
 861         int ret = 0, min_scale;
 862         struct dpu_plane *pdpu = to_dpu_plane(plane);
 863         const struct drm_crtc_state *crtc_state = NULL;
 864         const struct dpu_format *fmt;
 865         struct drm_rect src, dst, fb_rect = { 0 };
 866         uint32_t min_src_size, max_linewidth;
 867
 868         if (state->crtc)
 869                 crtc_state = drm_atomic_get_new_crtc_state(state->state,
 870                                                            state->crtc);
 871
 872         min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxdwnscale);
 873         ret = drm_atomic_helper_check_plane_state(state, crtc_state, min_scale,
 874                                           pdpu->pipe_sblk->maxupscale << 16,
 875                                           true, true);
 876         if (ret) {
 877                 DPU_ERROR_PLANE(pdpu, "Check plane state failed (%d)\n", ret);
 878                 return ret;
 879         }
 880         if (!state->visible)
 881                 return 0;
 882
 883         src.x1 = state->src_x >> 16;
 884         src.y1 = state->src_y >> 16;
 885         src.x2 = src.x1 + (state->src_w >> 16);
 886         src.y2 = src.y1 + (state->src_h >> 16);
 887
 888         dst = drm_plane_state_dest(state);
 889
 890         fb_rect.x2 = state->fb->width;
 891         fb_rect.y2 = state->fb->height;
 892
 893         max_linewidth = pdpu->pipe_sblk->common->maxlinewidth;
 894
 895         fmt = to_dpu_format(msm_framebuffer_format(state->fb));
 896
 897         min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
 898
 899         if (DPU_FORMAT_IS_YUV(fmt) &&
 900                 (!(pdpu->features & DPU_SSPP_SCALER) ||
 901                  !(pdpu->features & (BIT(DPU_SSPP_CSC)
 902                  | BIT(DPU_SSPP_CSC_10BIT))))) {
 903                 DPU_ERROR_PLANE(pdpu,
 904                                 "plane doesn't have scaler/csc for yuv\n");
 905                 return -EINVAL;
 906
 907         /* check src bounds */
 908         } else if (!dpu_plane_validate_src(&src, &fb_rect, min_src_size)) {
 909                 DPU_ERROR_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n",
 910                                 DRM_RECT_ARG(&src));
 911                 return -E2BIG;
 912
 913         /* valid yuv image */
 914         } else if (DPU_FORMAT_IS_YUV(fmt) &&
 915                    (src.x1 & 0x1 || src.y1 & 0x1 ||
 916                     drm_rect_width(&src) & 0x1 ||
 917                     drm_rect_height(&src) & 0x1)) {
 918                 DPU_ERROR_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n",
 919                                 DRM_RECT_ARG(&src));
 920                 return -EINVAL;
 921
 922         /* min dst support */
 923         } else if (drm_rect_width(&dst) < 0x1 || drm_rect_height(&dst) < 0x1) {
 924                 DPU_ERROR_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n",
 925                                 DRM_RECT_ARG(&dst));
 926                 return -EINVAL;
 927
 928         /* check decimated source width */
 929         } else if (drm_rect_width(&src) > max_linewidth) {
 930                 DPU_ERROR_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
 931                                 DRM_RECT_ARG(&src), max_linewidth);
 932                 return -E2BIG;
 933         }
 934
 935         return 0;
 936 }
 937
 938 void dpu_plane_flush(struct drm_plane *plane)
 939 {
 940         struct dpu_plane *pdpu;
 941         struct dpu_plane_state *pstate;
 942
 943         if (!plane || !plane->state) {
 944                 DPU_ERROR("invalid plane\n");
 945                 return;
 946         }
 947
 948         pdpu = to_dpu_plane(plane);
 949         pstate = to_dpu_plane_state(plane->state);
 950
 951         /*
 952          * These updates have to be done immediately before the plane flush
 953          * timing, and may not be moved to the atomic_update/mode_set functions.
 954          */
 955         if (pdpu->is_error)
 956                 /* force white frame with 100% alpha pipe output on error */
 957                 _dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF);
 958         else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
 959                 /* force 100% alpha */
 960                 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
 961         else if (pdpu->pipe_hw && pdpu->csc_ptr && pdpu->pipe_hw->ops.setup_csc)
 962                 pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, pdpu->csc_ptr);
 963
 964         /* flag h/w flush complete */
 965         if (plane->state)
 966                 pstate->pending = false;
 967 }
 968
 969 /**
 970  * dpu_plane_set_error: enable/disable error condition
 971  * @plane: pointer to drm_plane structure
 972  */
 973 void dpu_plane_set_error(struct drm_plane *plane, bool error)
 974 {
 975         struct dpu_plane *pdpu;
 976
 977         if (!plane)
 978                 return;
 979
 980         pdpu = to_dpu_plane(plane);
 981         pdpu->is_error = error;
 982 }
 983
 984 static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
 985 {
 986         uint32_t src_flags;
 987         struct dpu_plane *pdpu = to_dpu_plane(plane);
 988         struct drm_plane_state *state = plane->state;
 989         struct dpu_plane_state *pstate = to_dpu_plane_state(state);
 990         struct drm_crtc *crtc = state->crtc;
 991         struct drm_framebuffer *fb = state->fb;
 992         const struct dpu_format *fmt =
 993                 to_dpu_format(msm_framebuffer_format(fb));
 994
 995         memset(&(pdpu->pipe_cfg), 0, sizeof(struct dpu_hw_pipe_cfg));
 996
 997         _dpu_plane_set_scanout(plane, pstate, &pdpu->pipe_cfg, fb);
 998
 999         pstate->pending = true;
1000
1001         pdpu->is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
1002         _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
1003
1004         DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
1005                         ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
1006                         crtc->base.id, DRM_RECT_ARG(&state->dst),
1007                         (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt));
1008
1009         pdpu->pipe_cfg.src_rect = state->src;
1010
1011         /* state->src is 16.16, src_rect is not */
1012         pdpu->pipe_cfg.src_rect.x1 >>= 16;
1013         pdpu->pipe_cfg.src_rect.x2 >>= 16;
1014         pdpu->pipe_cfg.src_rect.y1 >>= 16;
1015         pdpu->pipe_cfg.src_rect.y2 >>= 16;
1016
1017         pdpu->pipe_cfg.dst_rect = state->dst;
1018
1019         _dpu_plane_setup_scaler(pdpu, pstate, fmt, false);
1020
1021         /* override for color fill */
1022         if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
1023                 /* skip remaining processing on color fill */
1024                 return;
1025         }
1026
1027         if (pdpu->pipe_hw->ops.setup_rects) {
1028                 pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
1029                                 &pdpu->pipe_cfg,
1030                                 pstate->multirect_index);
1031         }
1032
1033         if (pdpu->pipe_hw->ops.setup_pe &&
1034                         (pstate->multirect_index != DPU_SSPP_RECT_1))
1035                 pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
1036                                 &pstate->pixel_ext);
1037
1038         /**
1039          * when programmed in multirect mode, scalar block will be
1040          * bypassed. Still we need to update alpha and bitwidth
1041          * ONLY for RECT0
1042          */
1043         if (pdpu->pipe_hw->ops.setup_scaler &&
1044                         pstate->multirect_index != DPU_SSPP_RECT_1)
1045                 pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
1046                                 &pdpu->pipe_cfg, &pstate->pixel_ext,
1047                                 &pstate->scaler3_cfg);
1048
1049         if (pdpu->pipe_hw->ops.setup_multirect)
1050                 pdpu->pipe_hw->ops.setup_multirect(
1051                                 pdpu->pipe_hw,
1052                                 pstate->multirect_index,
1053                                 pstate->multirect_mode);
1054
1055         if (pdpu->pipe_hw->ops.setup_format) {
1056                 src_flags = 0x0;
1057
1058                 /* update format */
1059                 pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags,
1060                                 pstate->multirect_index);
1061
1062                 if (pdpu->pipe_hw->ops.setup_cdp) {
1063                         struct dpu_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
1064
1065                         memset(cdp_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg));
1066
1067                         cdp_cfg->enable = pdpu->catalog->perf.cdp_cfg
1068                                         [DPU_PERF_CDP_USAGE_RT].rd_enable;
1069                         cdp_cfg->ubwc_meta_enable =
1070                                         DPU_FORMAT_IS_UBWC(fmt);
1071                         cdp_cfg->tile_amortize_enable =
1072                                         DPU_FORMAT_IS_UBWC(fmt) ||
1073                                         DPU_FORMAT_IS_TILE(fmt);
1074                         cdp_cfg->preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
1075
1076                         pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, cdp_cfg);
1077                 }
1078
1079                 /* update csc */
1080                 if (DPU_FORMAT_IS_YUV(fmt))
1081                         _dpu_plane_setup_csc(pdpu);
1082                 else
1083                         pdpu->csc_ptr = 0;
1084         }
1085
1086         _dpu_plane_set_qos_lut(plane, fb);
1087         _dpu_plane_set_danger_lut(plane, fb);
1088
1089         if (plane->type != DRM_PLANE_TYPE_CURSOR) {
1090                 _dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL);
1091                 _dpu_plane_set_ot_limit(plane, crtc);
1092         }
1093
1094         _dpu_plane_set_qos_remap(plane);
1095 }
1096
1097 static void _dpu_plane_atomic_disable(struct drm_plane *plane)
1098 {
1099         struct dpu_plane *pdpu = to_dpu_plane(plane);
1100         struct drm_plane_state *state = plane->state;
1101         struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1102
1103         trace_dpu_plane_disable(DRMID(plane), is_dpu_plane_virtual(plane),
1104                                 pstate->multirect_mode);
1105
1106         pstate->pending = true;
1107
1108         if (is_dpu_plane_virtual(plane) &&
1109                         pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_multirect)
1110                 pdpu->pipe_hw->ops.setup_multirect(pdpu->pipe_hw,
1111                                 DPU_SSPP_RECT_SOLO, DPU_SSPP_MULTIRECT_NONE);
1112 }
1113
1114 static void dpu_plane_atomic_update(struct drm_plane *plane,
1115                                 struct drm_plane_state *old_state)
1116 {
1117         struct dpu_plane *pdpu = to_dpu_plane(plane);
1118         struct drm_plane_state *state = plane->state;
1119
1120         pdpu->is_error = false;
1121
1122         DPU_DEBUG_PLANE(pdpu, "\n");
1123
1124         if (!state->visible) {
1125                 _dpu_plane_atomic_disable(plane);
1126         } else {
1127                 dpu_plane_sspp_atomic_update(plane);
1128         }
1129 }
1130
1131 void dpu_plane_restore(struct drm_plane *plane)
1132 {
1133         struct dpu_plane *pdpu;
1134
1135         if (!plane || !plane->state) {
1136                 DPU_ERROR("invalid plane\n");
1137                 return;
1138         }
1139
1140         pdpu = to_dpu_plane(plane);
1141
1142         DPU_DEBUG_PLANE(pdpu, "\n");
1143
1144         /* last plane state is same as current state */
1145         dpu_plane_atomic_update(plane, plane->state);
1146 }
1147
1148 static void dpu_plane_destroy(struct drm_plane *plane)
1149 {
1150         struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL;
1151
1152         DPU_DEBUG_PLANE(pdpu, "\n");
1153
1154         if (pdpu) {
1155                 _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
1156
1157                 mutex_destroy(&pdpu->lock);
1158
1159                 /* this will destroy the states as well */
1160                 drm_plane_cleanup(plane);
1161
1162                 dpu_hw_sspp_destroy(pdpu->pipe_hw);
1163
1164                 kfree(pdpu);
1165         }
1166 }
1167
1168 static void dpu_plane_destroy_state(struct drm_plane *plane,
1169                 struct drm_plane_state *state)
1170 {
1171         __drm_atomic_helper_plane_destroy_state(state);
1172         kfree(to_dpu_plane_state(state));
1173 }
1174
1175 static struct drm_plane_state *
1176 dpu_plane_duplicate_state(struct drm_plane *plane)
1177 {
1178         struct dpu_plane *pdpu;
1179         struct dpu_plane_state *pstate;
1180         struct dpu_plane_state *old_state;
1181
1182         if (!plane) {
1183                 DPU_ERROR("invalid plane\n");
1184                 return NULL;
1185         } else if (!plane->state) {
1186                 DPU_ERROR("invalid plane state\n");
1187                 return NULL;
1188         }
1189
1190         old_state = to_dpu_plane_state(plane->state);
1191         pdpu = to_dpu_plane(plane);
1192         pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
1193         if (!pstate) {
1194                 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n");
1195                 return NULL;
1196         }
1197
1198         DPU_DEBUG_PLANE(pdpu, "\n");
1199
1200         pstate->pending = false;
1201
1202         __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
1203
1204         return &pstate->base;
1205 }
1206
1207 static void dpu_plane_reset(struct drm_plane *plane)
1208 {
1209         struct dpu_plane *pdpu;
1210         struct dpu_plane_state *pstate;
1211
1212         if (!plane) {
1213                 DPU_ERROR("invalid plane\n");
1214                 return;
1215         }
1216
1217         pdpu = to_dpu_plane(plane);
1218         DPU_DEBUG_PLANE(pdpu, "\n");
1219
1220         /* remove previous state, if present */
1221         if (plane->state) {
1222                 dpu_plane_destroy_state(plane, plane->state);
1223                 plane->state = 0;
1224         }
1225
1226         pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
1227         if (!pstate) {
1228                 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n");
1229                 return;
1230         }
1231
1232         pstate->base.plane = plane;
1233
1234         plane->state = &pstate->base;
1235 }
1236
1237 #ifdef CONFIG_DEBUG_FS
1238 static void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
1239 {
1240         struct dpu_plane *pdpu = to_dpu_plane(plane);
1241         struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
1242
1243         if (!pdpu->is_rt_pipe)
1244                 return;
1245
1246         pm_runtime_get_sync(&dpu_kms->pdev->dev);
1247         _dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL);
1248         pm_runtime_put_sync(&dpu_kms->pdev->dev);
1249 }
1250
1251 static ssize_t _dpu_plane_danger_read(struct file *file,
1252                         char __user *buff, size_t count, loff_t *ppos)
1253 {
1254         struct dpu_kms *kms = file->private_data;
1255         int len;
1256         char buf[40];
1257
1258         len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
1259
1260         return simple_read_from_buffer(buff, count, ppos, buf, len);
1261 }
1262
1263 static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable)
1264 {
1265         struct drm_plane *plane;
1266
1267         drm_for_each_plane(plane, kms->dev) {
1268                 if (plane->fb && plane->state) {
1269                         dpu_plane_danger_signal_ctrl(plane, enable);
1270                         DPU_DEBUG("plane:%d img:%dx%d ",
1271                                 plane->base.id, plane->fb->width,
1272                                 plane->fb->height);
1273                         DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
1274                                 plane->state->src_x >> 16,
1275                                 plane->state->src_y >> 16,
1276                                 plane->state->src_w >> 16,
1277                                 plane->state->src_h >> 16,
1278                                 plane->state->crtc_x, plane->state->crtc_y,
1279                                 plane->state->crtc_w, plane->state->crtc_h);
1280                 } else {
1281                         DPU_DEBUG("Inactive plane:%d\n", plane->base.id);
1282                 }
1283         }
1284 }
1285
1286 static ssize_t _dpu_plane_danger_write(struct file *file,
1287                     const char __user *user_buf, size_t count, loff_t *ppos)
1288 {
1289         struct dpu_kms *kms = file->private_data;
1290         int disable_panic;
1291         int ret;
1292
1293         ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic);
1294         if (ret)
1295                 return ret;
1296
1297         if (disable_panic) {
1298                 /* Disable panic signal for all active pipes */
1299                 DPU_DEBUG("Disabling danger:\n");
1300                 _dpu_plane_set_danger_state(kms, false);
1301                 kms->has_danger_ctrl = false;
1302         } else {
1303                 /* Enable panic signal for all active pipes */
1304                 DPU_DEBUG("Enabling danger:\n");
1305                 kms->has_danger_ctrl = true;
1306                 _dpu_plane_set_danger_state(kms, true);
1307         }
1308
1309         return count;
1310 }
1311
1312 static const struct file_operations dpu_plane_danger_enable = {
1313         .open = simple_open,
1314         .read = _dpu_plane_danger_read,
1315         .write = _dpu_plane_danger_write,
1316 };
1317
1318 static int _dpu_plane_init_debugfs(struct drm_plane *plane)
1319 {
1320         struct dpu_plane *pdpu = to_dpu_plane(plane);
1321         struct dpu_kms *kms = _dpu_plane_get_kms(plane);
1322         const struct dpu_sspp_cfg *cfg = pdpu->pipe_hw->cap;
1323         const struct dpu_sspp_sub_blks *sblk = cfg->sblk;
1324
1325         /* create overall sub-directory for the pipe */
1326         pdpu->debugfs_root =
1327                 debugfs_create_dir(pdpu->pipe_name,
1328                                 plane->dev->primary->debugfs_root);
1329
1330         if (!pdpu->debugfs_root)
1331                 return -ENOMEM;
1332
1333         /* don't error check these */
1334         debugfs_create_x32("features", 0600,
1335                         pdpu->debugfs_root, &pdpu->features);
1336
1337         /* add register dump support */
1338         dpu_debugfs_setup_regset32(&pdpu->debugfs_src,
1339                         sblk->src_blk.base + cfg->base,
1340                         sblk->src_blk.len,
1341                         kms);
1342         dpu_debugfs_create_regset32("src_blk", 0400,
1343                         pdpu->debugfs_root, &pdpu->debugfs_src);
1344
1345         if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) ||
1346                         cfg->features & BIT(DPU_SSPP_SCALER_QSEED2)) {
1347                 dpu_debugfs_setup_regset32(&pdpu->debugfs_scaler,
1348                                 sblk->scaler_blk.base + cfg->base,
1349                                 sblk->scaler_blk.len,
1350                                 kms);
1351                 dpu_debugfs_create_regset32("scaler_blk", 0400,
1352                                 pdpu->debugfs_root,
1353                                 &pdpu->debugfs_scaler);
1354                 debugfs_create_bool("default_scaling",
1355                                 0600,
1356                                 pdpu->debugfs_root,
1357                                 &pdpu->debugfs_default_scale);
1358         }
1359
1360         if (cfg->features & BIT(DPU_SSPP_CSC) ||
1361                         cfg->features & BIT(DPU_SSPP_CSC_10BIT)) {
1362                 dpu_debugfs_setup_regset32(&pdpu->debugfs_csc,
1363                                 sblk->csc_blk.base + cfg->base,
1364                                 sblk->csc_blk.len,
1365                                 kms);
1366                 dpu_debugfs_create_regset32("csc_blk", 0400,
1367                                 pdpu->debugfs_root, &pdpu->debugfs_csc);
1368         }
1369
1370         debugfs_create_u32("xin_id",
1371                         0400,
1372                         pdpu->debugfs_root,
1373                         (u32 *) &cfg->xin_id);
1374         debugfs_create_u32("clk_ctrl",
1375                         0400,
1376                         pdpu->debugfs_root,
1377                         (u32 *) &cfg->clk_ctrl);
1378         debugfs_create_x32("creq_vblank",
1379                         0600,
1380                         pdpu->debugfs_root,
1381                         (u32 *) &sblk->creq_vblank);
1382         debugfs_create_x32("danger_vblank",
1383                         0600,
1384                         pdpu->debugfs_root,
1385                         (u32 *) &sblk->danger_vblank);
1386
1387         debugfs_create_file("disable_danger",
1388                         0600,
1389                         pdpu->debugfs_root,
1390                         kms, &dpu_plane_danger_enable);
1391
1392         return 0;
1393 }
1394 #else
1395 static int _dpu_plane_init_debugfs(struct drm_plane *plane)
1396 {
1397         return 0;
1398 }
1399 #endif
1400
1401 static int dpu_plane_late_register(struct drm_plane *plane)
1402 {
1403         return _dpu_plane_init_debugfs(plane);
1404 }
1405
1406 static void dpu_plane_early_unregister(struct drm_plane *plane)
1407 {
1408         struct dpu_plane *pdpu = to_dpu_plane(plane);
1409
1410         debugfs_remove_recursive(pdpu->debugfs_root);
1411 }
1412
1413 static const struct drm_plane_funcs dpu_plane_funcs = {
1414                 .update_plane = drm_atomic_helper_update_plane,
1415                 .disable_plane = drm_atomic_helper_disable_plane,
1416                 .destroy = dpu_plane_destroy,
1417                 .reset = dpu_plane_reset,
1418                 .atomic_duplicate_state = dpu_plane_duplicate_state,
1419                 .atomic_destroy_state = dpu_plane_destroy_state,
1420                 .late_register = dpu_plane_late_register,
1421                 .early_unregister = dpu_plane_early_unregister,
1422 };
1423
1424 static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = {
1425                 .prepare_fb = dpu_plane_prepare_fb,
1426                 .cleanup_fb = dpu_plane_cleanup_fb,
1427                 .atomic_check = dpu_plane_atomic_check,
1428                 .atomic_update = dpu_plane_atomic_update,
1429 };
1430
1431 enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane)
1432 {
1433         return plane ? to_dpu_plane(plane)->pipe : SSPP_NONE;
1434 }
1435
1436 bool is_dpu_plane_virtual(struct drm_plane *plane)
1437 {
1438         return plane ? to_dpu_plane(plane)->is_virtual : false;
1439 }
1440
1441 /* initialize plane */
1442 struct drm_plane *dpu_plane_init(struct drm_device *dev,
1443                 uint32_t pipe, enum drm_plane_type type,
1444                 unsigned long possible_crtcs, u32 master_plane_id)
1445 {
1446         struct drm_plane *plane = NULL, *master_plane = NULL;
1447         const struct dpu_format_extended *format_list;
1448         struct dpu_plane *pdpu;
1449         struct msm_drm_private *priv = dev->dev_private;
1450         struct dpu_kms *kms = to_dpu_kms(priv->kms);
1451         int zpos_max = DPU_ZPOS_MAX;
1452         int ret = -EINVAL;
1453
1454         /* create and zero local structure */
1455         pdpu = kzalloc(sizeof(*pdpu), GFP_KERNEL);
1456         if (!pdpu) {
1457                 DPU_ERROR("[%u]failed to allocate local plane struct\n", pipe);
1458                 ret = -ENOMEM;
1459                 return ERR_PTR(ret);
1460         }
1461
1462         /* cache local stuff for later */
1463         plane = &pdpu->base;
1464         pdpu->pipe = pipe;
1465         pdpu->is_virtual = (master_plane_id != 0);
1466         INIT_LIST_HEAD(&pdpu->mplane_list);
1467         master_plane = drm_plane_find(dev, NULL, master_plane_id);
1468         if (master_plane) {
1469                 struct dpu_plane *mpdpu = to_dpu_plane(master_plane);
1470
1471                 list_add_tail(&pdpu->mplane_list, &mpdpu->mplane_list);
1472         }
1473
1474         /* initialize underlying h/w driver */
1475         pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog,
1476                                                         master_plane_id != 0);
1477         if (IS_ERR(pdpu->pipe_hw)) {
1478                 DPU_ERROR("[%u]SSPP init failed\n", pipe);
1479                 ret = PTR_ERR(pdpu->pipe_hw);
1480                 goto clean_plane;
1481         } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
1482                 DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
1483                 goto clean_sspp;
1484         }
1485
1486         /* cache features mask for later */
1487         pdpu->features = pdpu->pipe_hw->cap->features;
1488         pdpu->pipe_sblk = pdpu->pipe_hw->cap->sblk;
1489         if (!pdpu->pipe_sblk) {
1490                 DPU_ERROR("[%u]invalid sblk\n", pipe);
1491                 goto clean_sspp;
1492         }
1493
1494         if (!master_plane_id)
1495                 format_list = pdpu->pipe_sblk->format_list;
1496         else
1497                 format_list = pdpu->pipe_sblk->virt_format_list;
1498
1499         pdpu->nformats = dpu_populate_formats(format_list,
1500                                 pdpu->formats,
1501                                 0,
1502                                 ARRAY_SIZE(pdpu->formats));
1503
1504         if (!pdpu->nformats) {
1505                 DPU_ERROR("[%u]no valid formats for plane\n", pipe);
1506                 goto clean_sspp;
1507         }
1508
1509         ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs,
1510                                 pdpu->formats, pdpu->nformats,
1511                                 NULL, type, NULL);
1512         if (ret)
1513                 goto clean_sspp;
1514
1515         pdpu->catalog = kms->catalog;
1516
1517         if (kms->catalog->mixer_count &&
1518                 kms->catalog->mixer[0].sblk->maxblendstages) {
1519                 zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1;
1520                 if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1)
1521                         zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1;
1522         }
1523
1524         ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max);
1525         if (ret)
1526                 DPU_ERROR("failed to install zpos property, rc = %d\n", ret);
1527
1528         /* success! finalize initialization */
1529         drm_plane_helper_add(plane, &dpu_plane_helper_funcs);
1530
1531         /* save user friendly pipe name for later */
1532         snprintf(pdpu->pipe_name, DPU_NAME_SIZE, "plane%u", plane->base.id);
1533
1534         mutex_init(&pdpu->lock);
1535
1536         DPU_DEBUG("%s created for pipe:%u id:%u virtual:%u\n", pdpu->pipe_name,
1537                                         pipe, plane->base.id, master_plane_id);
1538         return plane;
1539
1540 clean_sspp:
1541         if (pdpu && pdpu->pipe_hw)
1542                 dpu_hw_sspp_destroy(pdpu->pipe_hw);
1543 clean_plane:
1544         kfree(pdpu);
1545         return ERR_PTR(ret);
1546 }