drivers/gpu/drm/meson/meson_crtc.c

   1 /*
   2  * Copyright (C) 2016 BayLibre, SAS
   3  * Author: Neil Armstrong <narmstrong@baylibre.com>
   4  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
   5  * Copyright (C) 2014 Endless Mobile
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of the
  10  * License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  * Written by:
  21  *     Jasper St. Pierre <jstpierre@mecheye.net>
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/mutex.h>
  27 #include <linux/platform_device.h>
  28 #include <drm/drmP.h>
  29 #include <drm/drm_atomic.h>
  30 #include <drm/drm_atomic_helper.h>
  31 #include <drm/drm_flip_work.h>
  32 #include <drm/drm_crtc_helper.h>
  33
  34 #include "meson_crtc.h"
  35 #include "meson_plane.h"
  36 #include "meson_venc.h"
  37 #include "meson_vpp.h"
  38 #include "meson_viu.h"
  39 #include "meson_registers.h"
  40
  41 /* CRTC definition */
  42
  43 struct meson_crtc {
  44         struct drm_crtc base;
  45         struct drm_pending_vblank_event *event;
  46         struct meson_drm *priv;
  47 };
  48 #define to_meson_crtc(x) container_of(x, struct meson_crtc, base)
  49
  50 /* CRTC */
  51
  52 static int meson_crtc_enable_vblank(struct drm_crtc *crtc)
  53 {
  54         struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
  55         struct meson_drm *priv = meson_crtc->priv;
  56
  57         meson_venc_enable_vsync(priv);
  58
  59         return 0;
  60 }
  61
  62 static void meson_crtc_disable_vblank(struct drm_crtc *crtc)
  63 {
  64         struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
  65         struct meson_drm *priv = meson_crtc->priv;
  66
  67         meson_venc_disable_vsync(priv);
  68 }
  69
  70 static const struct drm_crtc_funcs meson_crtc_funcs = {
  71         .atomic_destroy_state   = drm_atomic_helper_crtc_destroy_state,
  72         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
  73         .destroy                = drm_crtc_cleanup,
  74         .page_flip              = drm_atomic_helper_page_flip,
  75         .reset                  = drm_atomic_helper_crtc_reset,
  76         .set_config             = drm_atomic_helper_set_config,
  77         .enable_vblank          = meson_crtc_enable_vblank,
  78         .disable_vblank         = meson_crtc_disable_vblank,
  79
  80 };
  81
  82 static void meson_crtc_atomic_enable(struct drm_crtc *crtc,
  83                                      struct drm_crtc_state *old_state)
  84 {
  85         struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
  86         struct drm_crtc_state *crtc_state = crtc->state;
  87         struct meson_drm *priv = meson_crtc->priv;
  88
  89         DRM_DEBUG_DRIVER("\n");
  90
  91         if (!crtc_state) {
  92                 DRM_ERROR("Invalid crtc_state\n");
  93                 return;
  94         }
  95
  96         /* Enable VPP Postblend */
  97         writel(crtc_state->mode.hdisplay,
  98                priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
  99
 100         writel_bits_relaxed(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE,
 101                             priv->io_base + _REG(VPP_MISC));
 102
 103         priv->viu.osd1_enabled = true;
 104 }
 105
 106 static void meson_crtc_atomic_disable(struct drm_crtc *crtc,
 107                                       struct drm_crtc_state *old_state)
 108 {
 109         struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
 110         struct meson_drm *priv = meson_crtc->priv;
 111
 112         priv->viu.osd1_enabled = false;
 113         priv->viu.osd1_commit = false;
 114
 115         /* Disable VPP Postblend */
 116         writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0,
 117                             priv->io_base + _REG(VPP_MISC));
 118
 119         if (crtc->state->event && !crtc->state->active) {
 120                 spin_lock_irq(&crtc->dev->event_lock);
 121                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 122                 spin_unlock_irq(&crtc->dev->event_lock);
 123
 124                 crtc->state->event = NULL;
 125         }
 126 }
 127
 128 static void meson_crtc_atomic_begin(struct drm_crtc *crtc,
 129                                     struct drm_crtc_state *state)
 130 {
 131         struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
 132         unsigned long flags;
 133
 134         if (crtc->state->event) {
 135                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 136
 137                 spin_lock_irqsave(&crtc->dev->event_lock, flags);
 138                 meson_crtc->event = crtc->state->event;
 139                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 140                 crtc->state->event = NULL;
 141         }
 142 }
 143
 144 static void meson_crtc_atomic_flush(struct drm_crtc *crtc,
 145                                     struct drm_crtc_state *old_crtc_state)
 146 {
 147         struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
 148         struct meson_drm *priv = meson_crtc->priv;
 149
 150         priv->viu.osd1_commit = true;
 151 }
 152
 153 static const struct drm_crtc_helper_funcs meson_crtc_helper_funcs = {
 154         .atomic_begin   = meson_crtc_atomic_begin,
 155         .atomic_flush   = meson_crtc_atomic_flush,
 156         .atomic_enable  = meson_crtc_atomic_enable,
 157         .atomic_disable = meson_crtc_atomic_disable,
 158 };
 159
 160 void meson_crtc_irq(struct meson_drm *priv)
 161 {
 162         struct meson_crtc *meson_crtc = to_meson_crtc(priv->crtc);
 163         unsigned long flags;
 164
 165         /* Update the OSD registers */
 166         if (priv->viu.osd1_enabled && priv->viu.osd1_commit) {
 167                 writel_relaxed(priv->viu.osd1_ctrl_stat,
 168                                 priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
 169                 writel_relaxed(priv->viu.osd1_blk0_cfg[0],
 170                                 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0));
 171                 writel_relaxed(priv->viu.osd1_blk0_cfg[1],
 172                                 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W1));
 173                 writel_relaxed(priv->viu.osd1_blk0_cfg[2],
 174                                 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W2));
 175                 writel_relaxed(priv->viu.osd1_blk0_cfg[3],
 176                                 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W3));
 177                 writel_relaxed(priv->viu.osd1_blk0_cfg[4],
 178                                 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W4));
 179
 180                 /* If output is interlace, make use of the Scaler */
 181                 if (priv->viu.osd1_interlace) {
 182                         struct drm_plane *plane = priv->primary_plane;
 183                         struct drm_plane_state *state = plane->state;
 184                         struct drm_rect dest = {
 185                                 .x1 = state->crtc_x,
 186                                 .y1 = state->crtc_y,
 187                                 .x2 = state->crtc_x + state->crtc_w,
 188                                 .y2 = state->crtc_y + state->crtc_h,
 189                         };
 190
 191                         meson_vpp_setup_interlace_vscaler_osd1(priv, &dest);
 192                 } else
 193                         meson_vpp_disable_interlace_vscaler_osd1(priv);
 194
 195                 /* Enable OSD1 */
 196                 writel_bits_relaxed(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND,
 197                                     priv->io_base + _REG(VPP_MISC));
 198
 199                 priv->viu.osd1_commit = false;
 200         }
 201
 202         drm_crtc_handle_vblank(priv->crtc);
 203
 204         spin_lock_irqsave(&priv->drm->event_lock, flags);
 205         if (meson_crtc->event) {
 206                 drm_crtc_send_vblank_event(priv->crtc, meson_crtc->event);
 207                 drm_crtc_vblank_put(priv->crtc);
 208                 meson_crtc->event = NULL;
 209         }
 210         spin_unlock_irqrestore(&priv->drm->event_lock, flags);
 211 }
 212
 213 int meson_crtc_create(struct meson_drm *priv)
 214 {
 215         struct meson_crtc *meson_crtc;
 216         struct drm_crtc *crtc;
 217         int ret;
 218
 219         meson_crtc = devm_kzalloc(priv->drm->dev, sizeof(*meson_crtc),
 220                                   GFP_KERNEL);
 221         if (!meson_crtc)
 222                 return -ENOMEM;
 223
 224         meson_crtc->priv = priv;
 225         crtc = &meson_crtc->base;
 226         ret = drm_crtc_init_with_planes(priv->drm, crtc,
 227                                         priv->primary_plane, NULL,
 228                                         &meson_crtc_funcs, "meson_crtc");
 229         if (ret) {
 230                 dev_err(priv->drm->dev, "Failed to init CRTC\n");
 231                 return ret;
 232         }
 233
 234         drm_crtc_helper_add(crtc, &meson_crtc_helper_funcs);
 235
 236         priv->crtc = crtc;
 237
 238         return 0;
 239 }