drivers/gpu/drm/mediatek/mtk_hdmi_phy.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018 MediaTek Inc.
   4  * Author: Jie Qiu <jie.qiu@mediatek.com>
   5  */
   6
   7 #include "mtk_hdmi_phy.h"
   8
   9 static int mtk_hdmi_phy_power_on(struct phy *phy);
  10 static int mtk_hdmi_phy_power_off(struct phy *phy);
  11
  12 static const struct phy_ops mtk_hdmi_phy_dev_ops = {
  13         .power_on = mtk_hdmi_phy_power_on,
  14         .power_off = mtk_hdmi_phy_power_off,
  15         .owner = THIS_MODULE,
  16 };
  17
  18 long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
  19                              unsigned long *parent_rate)
  20 {
  21         struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
  22
  23         hdmi_phy->pll_rate = rate;
  24         if (rate <= 74250000)
  25                 *parent_rate = rate;
  26         else
  27                 *parent_rate = rate / 2;
  28
  29         return rate;
  30 }
  31
  32 unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
  33                                        unsigned long parent_rate)
  34 {
  35         struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
  36
  37         return hdmi_phy->pll_rate;
  38 }
  39
  40 void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
  41                              u32 bits)
  42 {
  43         void __iomem *reg = hdmi_phy->regs + offset;
  44         u32 tmp;
  45
  46         tmp = readl(reg);
  47         tmp &= ~bits;
  48         writel(tmp, reg);
  49 }
  50
  51 void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
  52                            u32 bits)
  53 {
  54         void __iomem *reg = hdmi_phy->regs + offset;
  55         u32 tmp;
  56
  57         tmp = readl(reg);
  58         tmp |= bits;
  59         writel(tmp, reg);
  60 }
  61
  62 void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
  63                        u32 val, u32 mask)
  64 {
  65         void __iomem *reg = hdmi_phy->regs + offset;
  66         u32 tmp;
  67
  68         tmp = readl(reg);
  69         tmp = (tmp & ~mask) | (val & mask);
  70         writel(tmp, reg);
  71 }
  72
  73 inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw)
  74 {
  75         return container_of(hw, struct mtk_hdmi_phy, pll_hw);
  76 }
  77
  78 static int mtk_hdmi_phy_power_on(struct phy *phy)
  79 {
  80         struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
  81         int ret;
  82
  83         ret = clk_prepare_enable(hdmi_phy->pll);
  84         if (ret < 0)
  85                 return ret;
  86
  87         hdmi_phy->conf->hdmi_phy_enable_tmds(hdmi_phy);
  88         return 0;
  89 }
  90
  91 static int mtk_hdmi_phy_power_off(struct phy *phy)
  92 {
  93         struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
  94
  95         hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);
  96         clk_disable_unprepare(hdmi_phy->pll);
  97
  98         return 0;
  99 }
 100
 101 static const struct phy_ops *
 102 mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)
 103 {
 104         if (hdmi_phy && hdmi_phy->conf &&
 105             hdmi_phy->conf->hdmi_phy_enable_tmds &&
 106             hdmi_phy->conf->hdmi_phy_disable_tmds)
 107                 return &mtk_hdmi_phy_dev_ops;
 108
 109         dev_err(hdmi_phy->dev, "Failed to get dev ops of phy\n");
 110                 return NULL;
 111 }
 112
 113 static void mtk_hdmi_phy_clk_get_ops(struct mtk_hdmi_phy *hdmi_phy,
 114                                      const struct clk_ops **ops)
 115 {
 116         if (hdmi_phy && hdmi_phy->conf && hdmi_phy->conf->hdmi_phy_clk_ops)
 117                 *ops = hdmi_phy->conf->hdmi_phy_clk_ops;
 118         else
 119                 dev_err(hdmi_phy->dev, "Failed to get clk ops of phy\n");
 120 }
 121
 122 static int mtk_hdmi_phy_probe(struct platform_device *pdev)
 123 {
 124         struct device *dev = &pdev->dev;
 125         struct mtk_hdmi_phy *hdmi_phy;
 126         struct resource *mem;
 127         struct clk *ref_clk;
 128         const char *ref_clk_name;
 129         struct clk_init_data clk_init = {
 130                 .num_parents = 1,
 131                 .parent_names = (const char * const *)&ref_clk_name,
 132                 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
 133         };
 134
 135         struct phy *phy;
 136         struct phy_provider *phy_provider;
 137         int ret;
 138
 139         hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
 140         if (!hdmi_phy)
 141                 return -ENOMEM;
 142
 143         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 144         hdmi_phy->regs = devm_ioremap_resource(dev, mem);
 145         if (IS_ERR(hdmi_phy->regs)) {
 146                 ret = PTR_ERR(hdmi_phy->regs);
 147                 dev_err(dev, "Failed to get memory resource: %d\n", ret);
 148                 return ret;
 149         }
 150
 151         ref_clk = devm_clk_get(dev, "pll_ref");
 152         if (IS_ERR(ref_clk)) {
 153                 ret = PTR_ERR(ref_clk);
 154                 dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
 155                         ret);
 156                 return ret;
 157         }
 158         ref_clk_name = __clk_get_name(ref_clk);
 159
 160         ret = of_property_read_string(dev->of_node, "clock-output-names",
 161                                       &clk_init.name);
 162         if (ret < 0) {
 163                 dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
 164                 return ret;
 165         }
 166
 167         hdmi_phy->dev = dev;
 168         hdmi_phy->conf =
 169                 (struct mtk_hdmi_phy_conf *)of_device_get_match_data(dev);
 170         mtk_hdmi_phy_clk_get_ops(hdmi_phy, &clk_init.ops);
 171         hdmi_phy->pll_hw.init = &clk_init;
 172         hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
 173         if (IS_ERR(hdmi_phy->pll)) {
 174                 ret = PTR_ERR(hdmi_phy->pll);
 175                 dev_err(dev, "Failed to register PLL: %d\n", ret);
 176                 return ret;
 177         }
 178
 179         ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
 180                                    &hdmi_phy->ibias);
 181         if (ret < 0) {
 182                 dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
 183                 return ret;
 184         }
 185
 186         ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
 187                                    &hdmi_phy->ibias_up);
 188         if (ret < 0) {
 189                 dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
 190                 return ret;
 191         }
 192
 193         dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
 194         hdmi_phy->drv_imp_clk = 0x30;
 195         hdmi_phy->drv_imp_d2 = 0x30;
 196         hdmi_phy->drv_imp_d1 = 0x30;
 197         hdmi_phy->drv_imp_d0 = 0x30;
 198
 199         phy = devm_phy_create(dev, NULL, mtk_hdmi_phy_dev_get_ops(hdmi_phy));
 200         if (IS_ERR(phy)) {
 201                 dev_err(dev, "Failed to create HDMI PHY\n");
 202                 return PTR_ERR(phy);
 203         }
 204         phy_set_drvdata(phy, hdmi_phy);
 205
 206         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 207         if (IS_ERR(phy_provider)) {
 208                 dev_err(dev, "Failed to register HDMI PHY\n");
 209                 return PTR_ERR(phy_provider);
 210         }
 211
 212         return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
 213                                    hdmi_phy->pll);
 214 }
 215
 216 static const struct of_device_id mtk_hdmi_phy_match[] = {
 217         { .compatible = "mediatek,mt2701-hdmi-phy",
 218           .data = &mtk_hdmi_phy_2701_conf,
 219         },
 220         { .compatible = "mediatek,mt8173-hdmi-phy",
 221           .data = &mtk_hdmi_phy_8173_conf,
 222         },
 223         {},
 224 };
 225
 226 struct platform_driver mtk_hdmi_phy_driver = {
 227         .probe = mtk_hdmi_phy_probe,
 228         .driver = {
 229                 .name = "mediatek-hdmi-phy",
 230                 .of_match_table = mtk_hdmi_phy_match,
 231         },
 232 };
 233
 234 MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
 235 MODULE_LICENSE("GPL v2");