drivers/gpu/drm/mediatek/mtk_hdmi_phy.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018 MediaTek Inc.
   4  * Author: Jie Qiu <jie.qiu@mediatek.com>
   5  */
   6
   7 #include "mtk_hdmi_phy.h"
   8
   9 static int mtk_hdmi_phy_power_on(struct phy *phy);
  10 static int mtk_hdmi_phy_power_off(struct phy *phy);
  11
  12 static const struct phy_ops mtk_hdmi_phy_dev_ops = {
  13         .power_on = mtk_hdmi_phy_power_on,
  14         .power_off = mtk_hdmi_phy_power_off,
  15         .owner = THIS_MODULE,
  16 };
  17
  18 long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
  19                              unsigned long *parent_rate)
  20 {
  21         struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
  22
  23         hdmi_phy->pll_rate = rate;
  24         if (rate <= 74250000)
  25                 *parent_rate = rate;
  26         else
  27                 *parent_rate = rate / 2;
  28
  29         return rate;
  30 }
  31
  32 void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
  33                              u32 bits)
  34 {
  35         void __iomem *reg = hdmi_phy->regs + offset;
  36         u32 tmp;
  37
  38         tmp = readl(reg);
  39         tmp &= ~bits;
  40         writel(tmp, reg);
  41 }
  42
  43 void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
  44                            u32 bits)
  45 {
  46         void __iomem *reg = hdmi_phy->regs + offset;
  47         u32 tmp;
  48
  49         tmp = readl(reg);
  50         tmp |= bits;
  51         writel(tmp, reg);
  52 }
  53
  54 void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
  55                        u32 val, u32 mask)
  56 {
  57         void __iomem *reg = hdmi_phy->regs + offset;
  58         u32 tmp;
  59
  60         tmp = readl(reg);
  61         tmp = (tmp & ~mask) | (val & mask);
  62         writel(tmp, reg);
  63 }
  64
  65 inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw)
  66 {
  67         return container_of(hw, struct mtk_hdmi_phy, pll_hw);
  68 }
  69
  70 static int mtk_hdmi_phy_power_on(struct phy *phy)
  71 {
  72         struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
  73         int ret;
  74
  75         ret = clk_prepare_enable(hdmi_phy->pll);
  76         if (ret < 0)
  77                 return ret;
  78
  79         hdmi_phy->conf->hdmi_phy_enable_tmds(hdmi_phy);
  80         return 0;
  81 }
  82
  83 static int mtk_hdmi_phy_power_off(struct phy *phy)
  84 {
  85         struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
  86
  87         hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);
  88         clk_disable_unprepare(hdmi_phy->pll);
  89
  90         return 0;
  91 }
  92
  93 static const struct phy_ops *
  94 mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)
  95 {
  96         if (hdmi_phy && hdmi_phy->conf &&
  97             hdmi_phy->conf->hdmi_phy_enable_tmds &&
  98             hdmi_phy->conf->hdmi_phy_disable_tmds)
  99                 return &mtk_hdmi_phy_dev_ops;
 100
 101         dev_err(hdmi_phy->dev, "Failed to get dev ops of phy\n");
 102                 return NULL;
 103 }
 104
 105 static void mtk_hdmi_phy_clk_get_data(struct mtk_hdmi_phy *hdmi_phy,
 106                                       struct clk_init_data *clk_init)
 107 {
 108         clk_init->flags = hdmi_phy->conf->flags;
 109         clk_init->ops = hdmi_phy->conf->hdmi_phy_clk_ops;
 110 }
 111
 112 static int mtk_hdmi_phy_probe(struct platform_device *pdev)
 113 {
 114         struct device *dev = &pdev->dev;
 115         struct mtk_hdmi_phy *hdmi_phy;
 116         struct resource *mem;
 117         struct clk *ref_clk;
 118         const char *ref_clk_name;
 119         struct clk_init_data clk_init = {
 120                 .num_parents = 1,
 121                 .parent_names = (const char * const *)&ref_clk_name,
 122         };
 123
 124         struct phy *phy;
 125         struct phy_provider *phy_provider;
 126         int ret;
 127
 128         hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
 129         if (!hdmi_phy)
 130                 return -ENOMEM;
 131
 132         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 133         hdmi_phy->regs = devm_ioremap_resource(dev, mem);
 134         if (IS_ERR(hdmi_phy->regs)) {
 135                 ret = PTR_ERR(hdmi_phy->regs);
 136                 dev_err(dev, "Failed to get memory resource: %d\n", ret);
 137                 return ret;
 138         }
 139
 140         ref_clk = devm_clk_get(dev, "pll_ref");
 141         if (IS_ERR(ref_clk)) {
 142                 ret = PTR_ERR(ref_clk);
 143                 dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
 144                         ret);
 145                 return ret;
 146         }
 147         ref_clk_name = __clk_get_name(ref_clk);
 148
 149         ret = of_property_read_string(dev->of_node, "clock-output-names",
 150                                       &clk_init.name);
 151         if (ret < 0) {
 152                 dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
 153                 return ret;
 154         }
 155
 156         hdmi_phy->dev = dev;
 157         hdmi_phy->conf =
 158                 (struct mtk_hdmi_phy_conf *)of_device_get_match_data(dev);
 159         mtk_hdmi_phy_clk_get_data(hdmi_phy, &clk_init);
 160         hdmi_phy->pll_hw.init = &clk_init;
 161         hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
 162         if (IS_ERR(hdmi_phy->pll)) {
 163                 ret = PTR_ERR(hdmi_phy->pll);
 164                 dev_err(dev, "Failed to register PLL: %d\n", ret);
 165                 return ret;
 166         }
 167
 168         ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
 169                                    &hdmi_phy->ibias);
 170         if (ret < 0) {
 171                 dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
 172                 return ret;
 173         }
 174
 175         ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
 176                                    &hdmi_phy->ibias_up);
 177         if (ret < 0) {
 178                 dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
 179                 return ret;
 180         }
 181
 182         dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
 183         hdmi_phy->drv_imp_clk = 0x30;
 184         hdmi_phy->drv_imp_d2 = 0x30;
 185         hdmi_phy->drv_imp_d1 = 0x30;
 186         hdmi_phy->drv_imp_d0 = 0x30;
 187
 188         phy = devm_phy_create(dev, NULL, mtk_hdmi_phy_dev_get_ops(hdmi_phy));
 189         if (IS_ERR(phy)) {
 190                 dev_err(dev, "Failed to create HDMI PHY\n");
 191                 return PTR_ERR(phy);
 192         }
 193         phy_set_drvdata(phy, hdmi_phy);
 194
 195         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 196         if (IS_ERR(phy_provider)) {
 197                 dev_err(dev, "Failed to register HDMI PHY\n");
 198                 return PTR_ERR(phy_provider);
 199         }
 200
 201         return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
 202                                    hdmi_phy->pll);
 203 }
 204
 205 static const struct of_device_id mtk_hdmi_phy_match[] = {
 206         { .compatible = "mediatek,mt2701-hdmi-phy",
 207           .data = &mtk_hdmi_phy_2701_conf,
 208         },
 209         { .compatible = "mediatek,mt8173-hdmi-phy",
 210           .data = &mtk_hdmi_phy_8173_conf,
 211         },
 212         {},
 213 };
 214
 215 struct platform_driver mtk_hdmi_phy_driver = {
 216         .probe = mtk_hdmi_phy_probe,
 217         .driver = {
 218                 .name = "mediatek-hdmi-phy",
 219                 .of_match_table = mtk_hdmi_phy_match,
 220         },
 221 };
 222
 223 MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
 224 MODULE_LICENSE("GPL v2");