drivers/gpu/drm/i915/selftests/i915_gem_coherency.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/prime_numbers.h>
  26
  27 #include "../i915_selftest.h"
  28 #include "i915_random.h"
  29
  30 static int cpu_set(struct drm_i915_gem_object *obj,
  31                    unsigned long offset,
  32                    u32 v)
  33 {
  34         unsigned int needs_clflush;
  35         struct page *page;
  36         void *map;
  37         u32 *cpu;
  38         int err;
  39
  40         err = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush);
  41         if (err)
  42                 return err;
  43
  44         page = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
  45         map = kmap_atomic(page);
  46         cpu = map + offset_in_page(offset);
  47
  48         if (needs_clflush & CLFLUSH_BEFORE)
  49                 drm_clflush_virt_range(cpu, sizeof(*cpu));
  50
  51         *cpu = v;
  52
  53         if (needs_clflush & CLFLUSH_AFTER)
  54                 drm_clflush_virt_range(cpu, sizeof(*cpu));
  55
  56         kunmap_atomic(map);
  57         i915_gem_obj_finish_shmem_access(obj);
  58
  59         return 0;
  60 }
  61
  62 static int cpu_get(struct drm_i915_gem_object *obj,
  63                    unsigned long offset,
  64                    u32 *v)
  65 {
  66         unsigned int needs_clflush;
  67         struct page *page;
  68         void *map;
  69         u32 *cpu;
  70         int err;
  71
  72         err = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
  73         if (err)
  74                 return err;
  75
  76         page = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
  77         map = kmap_atomic(page);
  78         cpu = map + offset_in_page(offset);
  79
  80         if (needs_clflush & CLFLUSH_BEFORE)
  81                 drm_clflush_virt_range(cpu, sizeof(*cpu));
  82
  83         *v = *cpu;
  84
  85         kunmap_atomic(map);
  86         i915_gem_obj_finish_shmem_access(obj);
  87
  88         return 0;
  89 }
  90
  91 static int gtt_set(struct drm_i915_gem_object *obj,
  92                    unsigned long offset,
  93                    u32 v)
  94 {
  95         struct i915_vma *vma;
  96         u32 __iomem *map;
  97         int err;
  98
  99         err = i915_gem_object_set_to_gtt_domain(obj, true);
 100         if (err)
 101                 return err;
 102
 103         vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
 104         if (IS_ERR(vma))
 105                 return PTR_ERR(vma);
 106
 107         map = i915_vma_pin_iomap(vma);
 108         i915_vma_unpin(vma);
 109         if (IS_ERR(map))
 110                 return PTR_ERR(map);
 111
 112         iowrite32(v, &map[offset / sizeof(*map)]);
 113         i915_vma_unpin_iomap(vma);
 114
 115         return 0;
 116 }
 117
 118 static int gtt_get(struct drm_i915_gem_object *obj,
 119                    unsigned long offset,
 120                    u32 *v)
 121 {
 122         struct i915_vma *vma;
 123         u32 __iomem *map;
 124         int err;
 125
 126         err = i915_gem_object_set_to_gtt_domain(obj, false);
 127         if (err)
 128                 return err;
 129
 130         vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
 131         if (IS_ERR(vma))
 132                 return PTR_ERR(vma);
 133
 134         map = i915_vma_pin_iomap(vma);
 135         i915_vma_unpin(vma);
 136         if (IS_ERR(map))
 137                 return PTR_ERR(map);
 138
 139         *v = ioread32(&map[offset / sizeof(*map)]);
 140         i915_vma_unpin_iomap(vma);
 141
 142         return 0;
 143 }
 144
 145 static int wc_set(struct drm_i915_gem_object *obj,
 146                   unsigned long offset,
 147                   u32 v)
 148 {
 149         u32 *map;
 150         int err;
 151
 152         err = i915_gem_object_set_to_wc_domain(obj, true);
 153         if (err)
 154                 return err;
 155
 156         map = i915_gem_object_pin_map(obj, I915_MAP_WC);
 157         if (IS_ERR(map))
 158                 return PTR_ERR(map);
 159
 160         map[offset / sizeof(*map)] = v;
 161         i915_gem_object_unpin_map(obj);
 162
 163         return 0;
 164 }
 165
 166 static int wc_get(struct drm_i915_gem_object *obj,
 167                   unsigned long offset,
 168                   u32 *v)
 169 {
 170         u32 *map;
 171         int err;
 172
 173         err = i915_gem_object_set_to_wc_domain(obj, false);
 174         if (err)
 175                 return err;
 176
 177         map = i915_gem_object_pin_map(obj, I915_MAP_WC);
 178         if (IS_ERR(map))
 179                 return PTR_ERR(map);
 180
 181         *v = map[offset / sizeof(*map)];
 182         i915_gem_object_unpin_map(obj);
 183
 184         return 0;
 185 }
 186
 187 static int gpu_set(struct drm_i915_gem_object *obj,
 188                    unsigned long offset,
 189                    u32 v)
 190 {
 191         struct drm_i915_private *i915 = to_i915(obj->base.dev);
 192         struct i915_request *rq;
 193         struct i915_vma *vma;
 194         u32 *cs;
 195         int err;
 196
 197         err = i915_gem_object_set_to_gtt_domain(obj, true);
 198         if (err)
 199                 return err;
 200
 201         vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
 202         if (IS_ERR(vma))
 203                 return PTR_ERR(vma);
 204
 205         rq = i915_request_alloc(i915->engine[RCS0], i915->kernel_context);
 206         if (IS_ERR(rq)) {
 207                 i915_vma_unpin(vma);
 208                 return PTR_ERR(rq);
 209         }
 210
 211         cs = intel_ring_begin(rq, 4);
 212         if (IS_ERR(cs)) {
 213                 i915_request_add(rq);
 214                 i915_vma_unpin(vma);
 215                 return PTR_ERR(cs);
 216         }
 217
 218         if (INTEL_GEN(i915) >= 8) {
 219                 *cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
 220                 *cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset);
 221                 *cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset);
 222                 *cs++ = v;
 223         } else if (INTEL_GEN(i915) >= 4) {
 224                 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
 225                 *cs++ = 0;
 226                 *cs++ = i915_ggtt_offset(vma) + offset;
 227                 *cs++ = v;
 228         } else {
 229                 *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
 230                 *cs++ = i915_ggtt_offset(vma) + offset;
 231                 *cs++ = v;
 232                 *cs++ = MI_NOOP;
 233         }
 234         intel_ring_advance(rq, cs);
 235
 236         err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
 237         i915_vma_unpin(vma);
 238
 239         i915_request_add(rq);
 240
 241         return err;
 242 }
 243
 244 static bool always_valid(struct drm_i915_private *i915)
 245 {
 246         return true;
 247 }
 248
 249 static bool needs_fence_registers(struct drm_i915_private *i915)
 250 {
 251         return !i915_terminally_wedged(i915);
 252 }
 253
 254 static bool needs_mi_store_dword(struct drm_i915_private *i915)
 255 {
 256         if (i915_terminally_wedged(i915))
 257                 return false;
 258
 259         return intel_engine_can_store_dword(i915->engine[RCS0]);
 260 }
 261
 262 static const struct igt_coherency_mode {
 263         const char *name;
 264         int (*set)(struct drm_i915_gem_object *, unsigned long offset, u32 v);
 265         int (*get)(struct drm_i915_gem_object *, unsigned long offset, u32 *v);
 266         bool (*valid)(struct drm_i915_private *i915);
 267 } igt_coherency_mode[] = {
 268         { "cpu", cpu_set, cpu_get, always_valid },
 269         { "gtt", gtt_set, gtt_get, needs_fence_registers },
 270         { "wc", wc_set, wc_get, always_valid },
 271         { "gpu", gpu_set, NULL, needs_mi_store_dword },
 272         { },
 273 };
 274
 275 static int igt_gem_coherency(void *arg)
 276 {
 277         const unsigned int ncachelines = PAGE_SIZE/64;
 278         I915_RND_STATE(prng);
 279         struct drm_i915_private *i915 = arg;
 280         const struct igt_coherency_mode *read, *write, *over;
 281         struct drm_i915_gem_object *obj;
 282         intel_wakeref_t wakeref;
 283         unsigned long count, n;
 284         u32 *offsets, *values;
 285         int err = 0;
 286
 287         /* We repeatedly write, overwrite and read from a sequence of
 288          * cachelines in order to try and detect incoherency (unflushed writes
 289          * from either the CPU or GPU). Each setter/getter uses our cache
 290          * domain API which should prevent incoherency.
 291          */
 292
 293         offsets = kmalloc_array(ncachelines, 2*sizeof(u32), GFP_KERNEL);
 294         if (!offsets)
 295                 return -ENOMEM;
 296         for (count = 0; count < ncachelines; count++)
 297                 offsets[count] = count * 64 + 4 * (count % 16);
 298
 299         values = offsets + ncachelines;
 300
 301         mutex_lock(&i915->drm.struct_mutex);
 302         wakeref = intel_runtime_pm_get(i915);
 303         for (over = igt_coherency_mode; over->name; over++) {
 304                 if (!over->set)
 305                         continue;
 306
 307                 if (!over->valid(i915))
 308                         continue;
 309
 310                 for (write = igt_coherency_mode; write->name; write++) {
 311                         if (!write->set)
 312                                 continue;
 313
 314                         if (!write->valid(i915))
 315                                 continue;
 316
 317                         for (read = igt_coherency_mode; read->name; read++) {
 318                                 if (!read->get)
 319                                         continue;
 320
 321                                 if (!read->valid(i915))
 322                                         continue;
 323
 324                                 for_each_prime_number_from(count, 1, ncachelines) {
 325                                         obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
 326                                         if (IS_ERR(obj)) {
 327                                                 err = PTR_ERR(obj);
 328                                                 goto unlock;
 329                                         }
 330
 331                                         i915_random_reorder(offsets, ncachelines, &prng);
 332                                         for (n = 0; n < count; n++)
 333                                                 values[n] = prandom_u32_state(&prng);
 334
 335                                         for (n = 0; n < count; n++) {
 336                                                 err = over->set(obj, offsets[n], ~values[n]);
 337                                                 if (err) {
 338                                                         pr_err("Failed to set stale value[%ld/%ld] in object using %s, err=%d\n",
 339                                                                n, count, over->name, err);
 340                                                         goto put_object;
 341                                                 }
 342                                         }
 343
 344                                         for (n = 0; n < count; n++) {
 345                                                 err = write->set(obj, offsets[n], values[n]);
 346                                                 if (err) {
 347                                                         pr_err("Failed to set value[%ld/%ld] in object using %s, err=%d\n",
 348                                                                n, count, write->name, err);
 349                                                         goto put_object;
 350                                                 }
 351                                         }
 352
 353                                         for (n = 0; n < count; n++) {
 354                                                 u32 found;
 355
 356                                                 err = read->get(obj, offsets[n], &found);
 357                                                 if (err) {
 358                                                         pr_err("Failed to get value[%ld/%ld] in object using %s, err=%d\n",
 359                                                                n, count, read->name, err);
 360                                                         goto put_object;
 361                                                 }
 362
 363                                                 if (found != values[n]) {
 364                                                         pr_err("Value[%ld/%ld] mismatch, (overwrite with %s) wrote [%s] %x read [%s] %x (inverse %x), at offset %x\n",
 365                                                                n, count, over->name,
 366                                                                write->name, values[n],
 367                                                                read->name, found,
 368                                                                ~values[n], offsets[n]);
 369                                                         err = -EINVAL;
 370                                                         goto put_object;
 371                                                 }
 372                                         }
 373
 374                                         __i915_gem_object_release_unless_active(obj);
 375                                 }
 376                         }
 377                 }
 378         }
 379 unlock:
 380         intel_runtime_pm_put(i915, wakeref);
 381         mutex_unlock(&i915->drm.struct_mutex);
 382         kfree(offsets);
 383         return err;
 384
 385 put_object:
 386         __i915_gem_object_release_unless_active(obj);
 387         goto unlock;
 388 }
 389
 390 int i915_gem_coherency_live_selftests(struct drm_i915_private *i915)
 391 {
 392         static const struct i915_subtest tests[] = {
 393                 SUBTEST(igt_gem_coherency),
 394         };
 395
 396         return i915_subtests(tests, i915);
 397 }