drivers/gpu/drm/i915/intel_vdsc.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2018 Intel Corporation
   4  *
   5  * Author: Gaurav K Singh <gaurav.k.singh@intel.com>
   6  *         Manasi Navare <manasi.d.navare@intel.com>
   7  */
   8
   9 #include <drm/i915_drm.h>
  10 #include "i915_drv.h"
  11 #include "intel_drv.h"
  12
  13 enum ROW_INDEX_BPP {
  14         ROW_INDEX_6BPP = 0,
  15         ROW_INDEX_8BPP,
  16         ROW_INDEX_10BPP,
  17         ROW_INDEX_12BPP,
  18         ROW_INDEX_15BPP,
  19         MAX_ROW_INDEX
  20 };
  21
  22 enum COLUMN_INDEX_BPC {
  23         COLUMN_INDEX_8BPC = 0,
  24         COLUMN_INDEX_10BPC,
  25         COLUMN_INDEX_12BPC,
  26         COLUMN_INDEX_14BPC,
  27         COLUMN_INDEX_16BPC,
  28         MAX_COLUMN_INDEX
  29 };
  30
  31 #define DSC_SUPPORTED_VERSION_MIN               1
  32
  33 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
  34 static u16 rc_buf_thresh[] = {
  35         896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
  36         7744, 7872, 8000, 8064
  37 };
  38
  39 struct rc_parameters {
  40         u16 initial_xmit_delay;
  41         u8 first_line_bpg_offset;
  42         u16 initial_offset;
  43         u8 flatness_min_qp;
  44         u8 flatness_max_qp;
  45         u8 rc_quant_incr_limit0;
  46         u8 rc_quant_incr_limit1;
  47         struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
  48 };
  49
  50 /*
  51  * Selected Rate Control Related Parameter Recommended Values
  52  * from DSC_v1.11 spec & C Model release: DSC_model_20161212
  53  */
  54 static struct rc_parameters rc_params[][MAX_COLUMN_INDEX] = {
  55 {
  56         /* 6BPP/8BPC */
  57         { 768, 15, 6144, 3, 13, 11, 11, {
  58                 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
  59                 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
  60                 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
  61                 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
  62                 }
  63         },
  64         /* 6BPP/10BPC */
  65         { 768, 15, 6144, 7, 17, 15, 15, {
  66                 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
  67                 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
  68                 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
  69                 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
  70                 { 17, 18, -12 }
  71                 }
  72         },
  73         /* 6BPP/12BPC */
  74         { 768, 15, 6144, 11, 21, 19, 19, {
  75                 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
  76                 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
  77                 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
  78                 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
  79                 { 21, 22, -12 }
  80                 }
  81         },
  82         /* 6BPP/14BPC */
  83         { 768, 15, 6144, 15, 25, 23, 27, {
  84                 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
  85                 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
  86                 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
  87                 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
  88                 { 25, 26, -12 }
  89                 }
  90         },
  91         /* 6BPP/16BPC */
  92         { 768, 15, 6144, 19, 29, 27, 27, {
  93                 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
  94                 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
  95                 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
  96                 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
  97                 { 29, 30, -12 }
  98                 }
  99         },
 100 },
 101 {
 102         /* 8BPP/8BPC */
 103         { 512, 12, 6144, 3, 12, 11, 11, {
 104                 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
 105                 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
 106                 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
 107                 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
 108                 }
 109         },
 110         /* 8BPP/10BPC */
 111         { 512, 12, 6144, 7, 16, 15, 15, {
 112                 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
 113                 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
 114                 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
 115                 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
 116                 }
 117         },
 118         /* 8BPP/12BPC */
 119         { 512, 12, 6144, 11, 20, 19, 19, {
 120                 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
 121                 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
 122                 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
 123                 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
 124                 { 21, 23, -12 }
 125                 }
 126         },
 127         /* 8BPP/14BPC */
 128         { 512, 12, 6144, 15, 24, 23, 23, {
 129                 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
 130                 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
 131                 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
 132                 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
 133                 { 24, 25, -12 }
 134                 }
 135         },
 136         /* 8BPP/16BPC */
 137         { 512, 12, 6144, 19, 28, 27, 27, {
 138                 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
 139                 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
 140                 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
 141                 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
 142                 { 28, 29, -12 }
 143                 }
 144         },
 145 },
 146 {
 147         /* 10BPP/8BPC */
 148         { 410, 15, 5632, 3, 12, 11, 11, {
 149                 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
 150                 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
 151                 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
 152                 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
 153                 }
 154         },
 155         /* 10BPP/10BPC */
 156         { 410, 15, 5632, 7, 16, 15, 15, {
 157                 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
 158                 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
 159                 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
 160                 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
 161                 }
 162         },
 163         /* 10BPP/12BPC */
 164         { 410, 15, 5632, 11, 20, 19, 19, {
 165                 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
 166                 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
 167                 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
 168                 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
 169                 { 19, 20, -12 }
 170                 }
 171         },
 172         /* 10BPP/14BPC */
 173         { 410, 15, 5632, 15, 24, 23, 23, {
 174                 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
 175                 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
 176                 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
 177                 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
 178                 { 23, 24, -12 }
 179                 }
 180         },
 181         /* 10BPP/16BPC */
 182         { 410, 15, 5632, 19, 28, 27, 27, {
 183                 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
 184                 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
 185                 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
 186                 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
 187                 { 27, 28, -12 }
 188                 }
 189         },
 190 },
 191 {
 192         /* 12BPP/8BPC */
 193         { 341, 15, 2048, 3, 12, 11, 11, {
 194                 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
 195                 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
 196                 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
 197                 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
 198                 }
 199         },
 200         /* 12BPP/10BPC */
 201         { 341, 15, 2048, 7, 16, 15, 15, {
 202                 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
 203                 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
 204                 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
 205                 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
 206                 }
 207         },
 208         /* 12BPP/12BPC */
 209         { 341, 15, 2048, 11, 20, 19, 19, {
 210                 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
 211                 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
 212                 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
 213                 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
 214                 { 21, 23, -12 }
 215                 }
 216         },
 217         /* 12BPP/14BPC */
 218         { 341, 15, 2048, 15, 24, 23, 23, {
 219                 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
 220                 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
 221                 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
 222                 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
 223                 { 22, 23, -12 }
 224                 }
 225         },
 226         /* 12BPP/16BPC */
 227         { 341, 15, 2048, 19, 28, 27, 27, {
 228                 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
 229                 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
 230                 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
 231                 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
 232                 { 26, 27, -12 }
 233                 }
 234         },
 235 },
 236 {
 237         /* 15BPP/8BPC */
 238         { 273, 15, 2048, 3, 12, 11, 11, {
 239                 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
 240                 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
 241                 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
 242                 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
 243                 }
 244         },
 245         /* 15BPP/10BPC */
 246         { 273, 15, 2048, 7, 16, 15, 15, {
 247                 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
 248                 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
 249                 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
 250                 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
 251                 }
 252         },
 253         /* 15BPP/12BPC */
 254         { 273, 15, 2048, 11, 20, 19, 19, {
 255                 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
 256                 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
 257                 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
 258                 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
 259                 { 16, 17, -12 }
 260                 }
 261         },
 262         /* 15BPP/14BPC */
 263         { 273, 15, 2048, 15, 24, 23, 23, {
 264                 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
 265                 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
 266                 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
 267                 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
 268                 { 20, 21, -12 }
 269                 }
 270         },
 271         /* 15BPP/16BPC */
 272         { 273, 15, 2048, 19, 28, 27, 27, {
 273                 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
 274                 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
 275                 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
 276                 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
 277                 { 24, 25, -12 }
 278                 }
 279         }
 280 }
 281
 282 };
 283
 284 static int get_row_index_for_rc_params(u16 compressed_bpp)
 285 {
 286         switch (compressed_bpp) {
 287         case 6:
 288                 return ROW_INDEX_6BPP;
 289         case 8:
 290                 return ROW_INDEX_8BPP;
 291         case 10:
 292                 return ROW_INDEX_10BPP;
 293         case 12:
 294                 return ROW_INDEX_12BPP;
 295         case 15:
 296                 return ROW_INDEX_15BPP;
 297         default:
 298                 return -EINVAL;
 299         }
 300 }
 301
 302 static int get_column_index_for_rc_params(u8 bits_per_component)
 303 {
 304         switch (bits_per_component) {
 305         case 8:
 306                 return COLUMN_INDEX_8BPC;
 307         case 10:
 308                 return COLUMN_INDEX_10BPC;
 309         case 12:
 310                 return COLUMN_INDEX_12BPC;
 311         case 14:
 312                 return COLUMN_INDEX_14BPC;
 313         case 16:
 314                 return COLUMN_INDEX_16BPC;
 315         default:
 316                 return -EINVAL;
 317         }
 318 }
 319
 320 static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
 321 {
 322         unsigned long groups_per_line = 0;
 323         unsigned long groups_total = 0;
 324         unsigned long num_extra_mux_bits = 0;
 325         unsigned long slice_bits = 0;
 326         unsigned long hrd_delay = 0;
 327         unsigned long final_scale = 0;
 328         unsigned long rbs_min = 0;
 329
 330         /* Number of groups used to code each line of a slice */
 331         groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
 332                                        DSC_RC_PIXELS_PER_GROUP);
 333
 334         /* chunksize in Bytes */
 335         vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
 336                                                   vdsc_cfg->bits_per_pixel,
 337                                                   (8 * 16));
 338
 339         if (vdsc_cfg->convert_rgb)
 340                 num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
 341                                           (4 * vdsc_cfg->bits_per_component + 4)
 342                                           - 2);
 343         else
 344                 num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
 345                         (4 * vdsc_cfg->bits_per_component + 4) +
 346                         2 * (4 * vdsc_cfg->bits_per_component) - 2;
 347         /* Number of bits in one Slice */
 348         slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
 349
 350         while ((num_extra_mux_bits > 0) &&
 351                ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
 352                 num_extra_mux_bits--;
 353
 354         if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
 355                 vdsc_cfg->initial_scale_value = groups_per_line + 8;
 356
 357         /* scale_decrement_interval calculation according to DSC spec 1.11 */
 358         if (vdsc_cfg->initial_scale_value > 8)
 359                 vdsc_cfg->scale_decrement_interval = groups_per_line /
 360                         (vdsc_cfg->initial_scale_value - 8);
 361         else
 362                 vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
 363
 364         vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
 365                 (vdsc_cfg->initial_xmit_delay *
 366                  vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
 367
 368         if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
 369                 DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
 370                 return -ERANGE;
 371         }
 372
 373         final_scale = (vdsc_cfg->rc_model_size * 8) /
 374                 (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
 375         if (vdsc_cfg->slice_height > 1)
 376                 /*
 377                  * NflBpgOffset is 16 bit value with 11 fractional bits
 378                  * hence we multiply by 2^11 for preserving the
 379                  * fractional part
 380                  */
 381                 vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
 382                                                         (vdsc_cfg->slice_height - 1));
 383         else
 384                 vdsc_cfg->nfl_bpg_offset = 0;
 385
 386         /* 2^16 - 1 */
 387         if (vdsc_cfg->nfl_bpg_offset > 65535) {
 388                 DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n");
 389                 return -ERANGE;
 390         }
 391
 392         /* Number of groups used to code the entire slice */
 393         groups_total = groups_per_line * vdsc_cfg->slice_height;
 394
 395         /* slice_bpg_offset is 16 bit value with 11 fractional bits */
 396         vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
 397                                                     vdsc_cfg->initial_offset +
 398                                                     num_extra_mux_bits) << 11),
 399                                                   groups_total);
 400
 401         if (final_scale > 9) {
 402                 /*
 403                  * ScaleIncrementInterval =
 404                  * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
 405                  * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
 406                  * we need divide by 2^11 from pstDscCfg values
 407                  */
 408                 vdsc_cfg->scale_increment_interval =
 409                                 (vdsc_cfg->final_offset * (1 << 11)) /
 410                                 ((vdsc_cfg->nfl_bpg_offset +
 411                                 vdsc_cfg->slice_bpg_offset) *
 412                                 (final_scale - 9));
 413         } else {
 414                 /*
 415                  * If finalScaleValue is less than or equal to 9, a value of 0 should
 416                  * be used to disable the scale increment at the end of the slice
 417                  */
 418                 vdsc_cfg->scale_increment_interval = 0;
 419         }
 420
 421         if (vdsc_cfg->scale_increment_interval > 65535) {
 422                 DRM_DEBUG_KMS("ScaleIncrementInterval is large for slice height\n");
 423                 return -ERANGE;
 424         }
 425
 426         /*
 427          * DSC spec mentions that bits_per_pixel specifies the target
 428          * bits/pixel (bpp) rate that is used by the encoder,
 429          * in steps of 1/16 of a bit per pixel
 430          */
 431         rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
 432                 DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
 433                              vdsc_cfg->bits_per_pixel, 16) +
 434                 groups_per_line * vdsc_cfg->first_line_bpg_offset;
 435
 436         hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
 437         vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
 438         vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
 439
 440         return 0;
 441 }
 442
 443 int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
 444                                 struct intel_crtc_state *pipe_config)
 445 {
 446         struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg;
 447         u16 compressed_bpp = pipe_config->dsc_params.compressed_bpp;
 448         u8 i = 0;
 449         int row_index = 0;
 450         int column_index = 0;
 451         u8 line_buf_depth = 0;
 452
 453         vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay;
 454         vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay;
 455         vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
 456                                              pipe_config->dsc_params.slice_count);
 457         /*
 458          * Slice Height of 8 works for all currently available panels. So start
 459          * with that if pic_height is an integral multiple of 8.
 460          * Eventually add logic to try multiple slice heights.
 461          */
 462         if (vdsc_cfg->pic_height % 8 == 0)
 463                 vdsc_cfg->slice_height = 8;
 464         else if (vdsc_cfg->pic_height % 4 == 0)
 465                 vdsc_cfg->slice_height = 4;
 466         else
 467                 vdsc_cfg->slice_height = 2;
 468
 469         /* Values filled from DSC Sink DPCD */
 470         vdsc_cfg->dsc_version_major =
 471                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
 472                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
 473         vdsc_cfg->dsc_version_minor =
 474                 min(DSC_SUPPORTED_VERSION_MIN,
 475                     (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
 476                      DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
 477
 478         vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
 479                 DP_DSC_RGB;
 480
 481         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
 482         if (!line_buf_depth) {
 483                 DRM_DEBUG_KMS("DSC Sink Line Buffer Depth invalid\n");
 484                 return -EINVAL;
 485         }
 486         if (vdsc_cfg->dsc_version_minor == 2)
 487                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
 488                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
 489         else
 490                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
 491                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
 492
 493         /* Gen 11 does not support YCbCr */
 494         vdsc_cfg->enable422 = false;
 495         /* Gen 11 does not support VBR */
 496         vdsc_cfg->vbr_enable = false;
 497         vdsc_cfg->block_pred_enable =
 498                         intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
 499                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
 500
 501         /* Gen 11 only supports integral values of bpp */
 502         vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
 503         vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
 504
 505         for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
 506                 /*
 507                  * six 0s are appended to the lsb of each threshold value
 508                  * internally in h/w.
 509                  * Only 8 bits are allowed for programming RcBufThreshold
 510                  */
 511                 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
 512         }
 513
 514         /*
 515          * For 6bpp, RC Buffer threshold 12 and 13 need a different value
 516          * as per C Model
 517          */
 518         if (compressed_bpp == 6) {
 519                 vdsc_cfg->rc_buf_thresh[12] = 0x7C;
 520                 vdsc_cfg->rc_buf_thresh[13] = 0x7D;
 521         }
 522
 523         row_index = get_row_index_for_rc_params(compressed_bpp);
 524         column_index =
 525                 get_column_index_for_rc_params(vdsc_cfg->bits_per_component);
 526
 527         if (row_index < 0 || column_index < 0)
 528                 return -EINVAL;
 529
 530         vdsc_cfg->first_line_bpg_offset =
 531                 rc_params[row_index][column_index].first_line_bpg_offset;
 532         vdsc_cfg->initial_xmit_delay =
 533                 rc_params[row_index][column_index].initial_xmit_delay;
 534         vdsc_cfg->initial_offset =
 535                 rc_params[row_index][column_index].initial_offset;
 536         vdsc_cfg->flatness_min_qp =
 537                 rc_params[row_index][column_index].flatness_min_qp;
 538         vdsc_cfg->flatness_max_qp =
 539                 rc_params[row_index][column_index].flatness_max_qp;
 540         vdsc_cfg->rc_quant_incr_limit0 =
 541                 rc_params[row_index][column_index].rc_quant_incr_limit0;
 542         vdsc_cfg->rc_quant_incr_limit1 =
 543                 rc_params[row_index][column_index].rc_quant_incr_limit1;
 544
 545         for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
 546                 vdsc_cfg->rc_range_params[i].range_min_qp =
 547                         rc_params[row_index][column_index].rc_range_params[i].range_min_qp;
 548                 vdsc_cfg->rc_range_params[i].range_max_qp =
 549                         rc_params[row_index][column_index].rc_range_params[i].range_max_qp;
 550                 /*
 551                  * Range BPG Offset uses 2's complement and is only a 6 bits. So
 552                  * mask it to get only 6 bits.
 553                  */
 554                 vdsc_cfg->rc_range_params[i].range_bpg_offset =
 555                         rc_params[row_index][column_index].rc_range_params[i].range_bpg_offset &
 556                         DSC_RANGE_BPG_OFFSET_MASK;
 557         }
 558
 559         /*
 560          * BitsPerComponent value determines mux_word_size:
 561          * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits
 562          * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to
 563          * 48 bits
 564          */
 565         if (vdsc_cfg->bits_per_component == 8 ||
 566             vdsc_cfg->bits_per_component == 10)
 567                 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
 568         else if (vdsc_cfg->bits_per_component == 12)
 569                 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
 570
 571         /* RC_MODEL_SIZE is a constant across all configurations */
 572         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
 573         /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
 574         vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
 575                 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
 576
 577         return intel_compute_rc_parameters(vdsc_cfg);
 578 }
 579
 580 enum intel_display_power_domain
 581 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
 582 {
 583         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 584
 585         /*
 586          * On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
 587          * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
 588          * For any other transcoder, VDSC/joining uses the power well associated
 589          * with the pipe/transcoder in use. Hence another reference on the
 590          * transcoder power domain will suffice.
 591          */
 592         if (cpu_transcoder == TRANSCODER_EDP)
 593                 return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
 594         else
 595                 return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 596 }
 597
 598 static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
 599                                                 const struct intel_crtc_state *crtc_state)
 600 {
 601         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 602         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 603         const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
 604         enum pipe pipe = crtc->pipe;
 605         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 606         u32 pps_val = 0;
 607         u32 rc_buf_thresh_dword[4];
 608         u32 rc_range_params_dword[8];
 609         u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1;
 610         int i = 0;
 611
 612         /* Populate PICTURE_PARAMETER_SET_0 registers */
 613         pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
 614                 DSC_VER_MIN_SHIFT |
 615                 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
 616                 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
 617         if (vdsc_cfg->block_pred_enable)
 618                 pps_val |= DSC_BLOCK_PREDICTION;
 619         if (vdsc_cfg->convert_rgb)
 620                 pps_val |= DSC_COLOR_SPACE_CONVERSION;
 621         if (vdsc_cfg->enable422)
 622                 pps_val |= DSC_422_ENABLE;
 623         if (vdsc_cfg->vbr_enable)
 624                 pps_val |= DSC_VBR_ENABLE;
 625         DRM_INFO("PPS0 = 0x%08x\n", pps_val);
 626         if (cpu_transcoder == TRANSCODER_EDP) {
 627                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val);
 628                 /*
 629                  * If 2 VDSC instances are needed, configure PPS for second
 630                  * VDSC
 631                  */
 632                 if (crtc_state->dsc_params.dsc_split)
 633                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val);
 634         } else {
 635                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val);
 636                 if (crtc_state->dsc_params.dsc_split)
 637                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
 638                                    pps_val);
 639         }
 640
 641         /* Populate PICTURE_PARAMETER_SET_1 registers */
 642         pps_val = 0;
 643         pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
 644         DRM_INFO("PPS1 = 0x%08x\n", pps_val);
 645         if (cpu_transcoder == TRANSCODER_EDP) {
 646                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val);
 647                 /*
 648                  * If 2 VDSC instances are needed, configure PPS for second
 649                  * VDSC
 650                  */
 651                 if (crtc_state->dsc_params.dsc_split)
 652                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val);
 653         } else {
 654                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val);
 655                 if (crtc_state->dsc_params.dsc_split)
 656                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
 657                                    pps_val);
 658         }
 659
 660         /* Populate PICTURE_PARAMETER_SET_2 registers */
 661         pps_val = 0;
 662         pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
 663                 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
 664         DRM_INFO("PPS2 = 0x%08x\n", pps_val);
 665         if (encoder->type == INTEL_OUTPUT_EDP) {
 666                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val);
 667                 /*
 668                  * If 2 VDSC instances are needed, configure PPS for second
 669                  * VDSC
 670                  */
 671                 if (crtc_state->dsc_params.dsc_split)
 672                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val);
 673         } else {
 674                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val);
 675                 if (crtc_state->dsc_params.dsc_split)
 676                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
 677                                    pps_val);
 678         }
 679
 680         /* Populate PICTURE_PARAMETER_SET_3 registers */
 681         pps_val = 0;
 682         pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
 683                 DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
 684         DRM_INFO("PPS3 = 0x%08x\n", pps_val);
 685         if (cpu_transcoder == TRANSCODER_EDP) {
 686                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val);
 687                 /*
 688                  * If 2 VDSC instances are needed, configure PPS for second
 689                  * VDSC
 690                  */
 691                 if (crtc_state->dsc_params.dsc_split)
 692                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, pps_val);
 693         } else {
 694                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val);
 695                 if (crtc_state->dsc_params.dsc_split)
 696                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
 697                                    pps_val);
 698         }
 699
 700         /* Populate PICTURE_PARAMETER_SET_4 registers */
 701         pps_val = 0;
 702         pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
 703                 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
 704         DRM_INFO("PPS4 = 0x%08x\n", pps_val);
 705         if (cpu_transcoder == TRANSCODER_EDP) {
 706                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val);
 707                 /*
 708                  * If 2 VDSC instances are needed, configure PPS for second
 709                  * VDSC
 710                  */
 711                 if (crtc_state->dsc_params.dsc_split)
 712                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, pps_val);
 713         } else {
 714                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val);
 715                 if (crtc_state->dsc_params.dsc_split)
 716                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
 717                                    pps_val);
 718         }
 719
 720         /* Populate PICTURE_PARAMETER_SET_5 registers */
 721         pps_val = 0;
 722         pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
 723                 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
 724         DRM_INFO("PPS5 = 0x%08x\n", pps_val);
 725         if (cpu_transcoder == TRANSCODER_EDP) {
 726                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val);
 727                 /*
 728                  * If 2 VDSC instances are needed, configure PPS for second
 729                  * VDSC
 730                  */
 731                 if (crtc_state->dsc_params.dsc_split)
 732                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, pps_val);
 733         } else {
 734                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val);
 735                 if (crtc_state->dsc_params.dsc_split)
 736                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
 737                                    pps_val);
 738         }
 739
 740         /* Populate PICTURE_PARAMETER_SET_6 registers */
 741         pps_val = 0;
 742         pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
 743                 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
 744                 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
 745                 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
 746         DRM_INFO("PPS6 = 0x%08x\n", pps_val);
 747         if (cpu_transcoder == TRANSCODER_EDP) {
 748                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val);
 749                 /*
 750                  * If 2 VDSC instances are needed, configure PPS for second
 751                  * VDSC
 752                  */
 753                 if (crtc_state->dsc_params.dsc_split)
 754                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, pps_val);
 755         } else {
 756                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val);
 757                 if (crtc_state->dsc_params.dsc_split)
 758                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
 759                                    pps_val);
 760         }
 761
 762         /* Populate PICTURE_PARAMETER_SET_7 registers */
 763         pps_val = 0;
 764         pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
 765                 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
 766         DRM_INFO("PPS7 = 0x%08x\n", pps_val);
 767         if (cpu_transcoder == TRANSCODER_EDP) {
 768                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val);
 769                 /*
 770                  * If 2 VDSC instances are needed, configure PPS for second
 771                  * VDSC
 772                  */
 773                 if (crtc_state->dsc_params.dsc_split)
 774                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, pps_val);
 775         } else {
 776                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val);
 777                 if (crtc_state->dsc_params.dsc_split)
 778                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
 779                                    pps_val);
 780         }
 781
 782         /* Populate PICTURE_PARAMETER_SET_8 registers */
 783         pps_val = 0;
 784         pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
 785                 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
 786         DRM_INFO("PPS8 = 0x%08x\n", pps_val);
 787         if (cpu_transcoder == TRANSCODER_EDP) {
 788                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val);
 789                 /*
 790                  * If 2 VDSC instances are needed, configure PPS for second
 791                  * VDSC
 792                  */
 793                 if (crtc_state->dsc_params.dsc_split)
 794                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, pps_val);
 795         } else {
 796                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val);
 797                 if (crtc_state->dsc_params.dsc_split)
 798                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
 799                                    pps_val);
 800         }
 801
 802         /* Populate PICTURE_PARAMETER_SET_9 registers */
 803         pps_val = 0;
 804         pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) |
 805                 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
 806         DRM_INFO("PPS9 = 0x%08x\n", pps_val);
 807         if (cpu_transcoder == TRANSCODER_EDP) {
 808                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val);
 809                 /*
 810                  * If 2 VDSC instances are needed, configure PPS for second
 811                  * VDSC
 812                  */
 813                 if (crtc_state->dsc_params.dsc_split)
 814                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, pps_val);
 815         } else {
 816                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val);
 817                 if (crtc_state->dsc_params.dsc_split)
 818                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
 819                                    pps_val);
 820         }
 821
 822         /* Populate PICTURE_PARAMETER_SET_10 registers */
 823         pps_val = 0;
 824         pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
 825                 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
 826                 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
 827                 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
 828         DRM_INFO("PPS10 = 0x%08x\n", pps_val);
 829         if (cpu_transcoder == TRANSCODER_EDP) {
 830                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val);
 831                 /*
 832                  * If 2 VDSC instances are needed, configure PPS for second
 833                  * VDSC
 834                  */
 835                 if (crtc_state->dsc_params.dsc_split)
 836                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, pps_val);
 837         } else {
 838                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val);
 839                 if (crtc_state->dsc_params.dsc_split)
 840                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
 841                                    pps_val);
 842         }
 843
 844         /* Populate Picture parameter set 16 */
 845         pps_val = 0;
 846         pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
 847                 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
 848                                    vdsc_cfg->slice_width) |
 849                 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
 850                                         vdsc_cfg->slice_height);
 851         DRM_INFO("PPS16 = 0x%08x\n", pps_val);
 852         if (cpu_transcoder == TRANSCODER_EDP) {
 853                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val);
 854                 /*
 855                  * If 2 VDSC instances are needed, configure PPS for second
 856                  * VDSC
 857                  */
 858                 if (crtc_state->dsc_params.dsc_split)
 859                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, pps_val);
 860         } else {
 861                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val);
 862                 if (crtc_state->dsc_params.dsc_split)
 863                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
 864                                    pps_val);
 865         }
 866
 867         /* Populate the RC_BUF_THRESH registers */
 868         memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
 869         for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
 870                 rc_buf_thresh_dword[i / 4] |=
 871                         (u32)(vdsc_cfg->rc_buf_thresh[i] <<
 872                               BITS_PER_BYTE * (i % 4));
 873                 DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i,
 874                          rc_buf_thresh_dword[i / 4]);
 875         }
 876         if (cpu_transcoder == TRANSCODER_EDP) {
 877                 I915_WRITE(DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]);
 878                 I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]);
 879                 I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]);
 880                 I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]);
 881                 if (crtc_state->dsc_params.dsc_split) {
 882                         I915_WRITE(DSCC_RC_BUF_THRESH_0,
 883                                    rc_buf_thresh_dword[0]);
 884                         I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW,
 885                                    rc_buf_thresh_dword[1]);
 886                         I915_WRITE(DSCC_RC_BUF_THRESH_1,
 887                                    rc_buf_thresh_dword[2]);
 888                         I915_WRITE(DSCC_RC_BUF_THRESH_1_UDW,
 889                                    rc_buf_thresh_dword[3]);
 890                 }
 891         } else {
 892                 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0(pipe),
 893                            rc_buf_thresh_dword[0]);
 894                 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
 895                            rc_buf_thresh_dword[1]);
 896                 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1(pipe),
 897                            rc_buf_thresh_dword[2]);
 898                 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
 899                            rc_buf_thresh_dword[3]);
 900                 if (crtc_state->dsc_params.dsc_split) {
 901                         I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe),
 902                                    rc_buf_thresh_dword[0]);
 903                         I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
 904                                    rc_buf_thresh_dword[1]);
 905                         I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1(pipe),
 906                                    rc_buf_thresh_dword[2]);
 907                         I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
 908                                    rc_buf_thresh_dword[3]);
 909                 }
 910         }
 911
 912         /* Populate the RC_RANGE_PARAMETERS registers */
 913         memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));
 914         for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
 915                 rc_range_params_dword[i / 2] |=
 916                         (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
 917                                 RC_BPG_OFFSET_SHIFT) |
 918                                (vdsc_cfg->rc_range_params[i].range_max_qp <<
 919                                 RC_MAX_QP_SHIFT) |
 920                                (vdsc_cfg->rc_range_params[i].range_min_qp <<
 921                                 RC_MIN_QP_SHIFT)) << 16 * (i % 2));
 922                 DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i,
 923                          rc_range_params_dword[i / 2]);
 924         }
 925         if (cpu_transcoder == TRANSCODER_EDP) {
 926                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0,
 927                            rc_range_params_dword[0]);
 928                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW,
 929                            rc_range_params_dword[1]);
 930                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1,
 931                            rc_range_params_dword[2]);
 932                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1_UDW,
 933                            rc_range_params_dword[3]);
 934                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2,
 935                            rc_range_params_dword[4]);
 936                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2_UDW,
 937                            rc_range_params_dword[5]);
 938                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3,
 939                            rc_range_params_dword[6]);
 940                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW,
 941                            rc_range_params_dword[7]);
 942                 if (crtc_state->dsc_params.dsc_split) {
 943                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0,
 944                                    rc_range_params_dword[0]);
 945                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW,
 946                                    rc_range_params_dword[1]);
 947                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1,
 948                                    rc_range_params_dword[2]);
 949                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1_UDW,
 950                                    rc_range_params_dword[3]);
 951                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2,
 952                                    rc_range_params_dword[4]);
 953                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2_UDW,
 954                                    rc_range_params_dword[5]);
 955                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3,
 956                                    rc_range_params_dword[6]);
 957                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3_UDW,
 958                                    rc_range_params_dword[7]);
 959                 }
 960         } else {
 961                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
 962                            rc_range_params_dword[0]);
 963                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
 964                            rc_range_params_dword[1]);
 965                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
 966                            rc_range_params_dword[2]);
 967                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
 968                            rc_range_params_dword[3]);
 969                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
 970                            rc_range_params_dword[4]);
 971                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
 972                            rc_range_params_dword[5]);
 973                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
 974                            rc_range_params_dword[6]);
 975                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
 976                            rc_range_params_dword[7]);
 977                 if (crtc_state->dsc_params.dsc_split) {
 978                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
 979                                    rc_range_params_dword[0]);
 980                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
 981                                    rc_range_params_dword[1]);
 982                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
 983                                    rc_range_params_dword[2]);
 984                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
 985                                    rc_range_params_dword[3]);
 986                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
 987                                    rc_range_params_dword[4]);
 988                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
 989                                    rc_range_params_dword[5]);
 990                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
 991                                    rc_range_params_dword[6]);
 992                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
 993                                    rc_range_params_dword[7]);
 994                 }
 995         }
 996 }
 997
 998 static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
 999                                        const struct intel_crtc_state *crtc_state)
1000 {
1001         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1002         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1003         const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
1004         struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
1005
1006         /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
1007         drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp);
1008
1009         /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
1010         drm_dsc_pps_infoframe_pack(&dp_dsc_pps_sdp, vdsc_cfg);
1011
1012         intel_dig_port->write_infoframe(encoder, crtc_state,
1013                                         DP_SDP_PPS, &dp_dsc_pps_sdp,
1014                                         sizeof(dp_dsc_pps_sdp));
1015 }
1016
1017 void intel_dsc_enable(struct intel_encoder *encoder,
1018                       const struct intel_crtc_state *crtc_state)
1019 {
1020         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1021         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1022         enum pipe pipe = crtc->pipe;
1023         i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
1024         u32 dss_ctl1_val = 0;
1025         u32 dss_ctl2_val = 0;
1026
1027         if (!crtc_state->dsc_params.compression_enable)
1028                 return;
1029
1030         /* Enable Power wells for VDSC/joining */
1031         intel_display_power_get(dev_priv,
1032                                 intel_dsc_power_domain(crtc_state));
1033
1034         intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
1035
1036         intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
1037
1038         if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
1039                 dss_ctl1_reg = DSS_CTL1;
1040                 dss_ctl2_reg = DSS_CTL2;
1041         } else {
1042                 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
1043                 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
1044         }
1045         dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
1046         if (crtc_state->dsc_params.dsc_split) {
1047                 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
1048                 dss_ctl1_val |= JOINER_ENABLE;
1049         }
1050         I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
1051         I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
1052 }
1053
1054 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
1055 {
1056         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1057         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1058         enum pipe pipe = crtc->pipe;
1059         i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
1060         u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
1061
1062         if (!old_crtc_state->dsc_params.compression_enable)
1063                 return;
1064
1065         if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) {
1066                 dss_ctl1_reg = DSS_CTL1;
1067                 dss_ctl2_reg = DSS_CTL2;
1068         } else {
1069                 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
1070                 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
1071         }
1072         dss_ctl1_val = I915_READ(dss_ctl1_reg);
1073         if (dss_ctl1_val & JOINER_ENABLE)
1074                 dss_ctl1_val &= ~JOINER_ENABLE;
1075         I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
1076
1077         dss_ctl2_val = I915_READ(dss_ctl2_reg);
1078         if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
1079             dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
1080                 dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
1081                                   RIGHT_BRANCH_VDSC_ENABLE);
1082         I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
1083
1084         /* Disable Power wells for VDSC/joining */
1085         intel_display_power_put(dev_priv,
1086                                 intel_dsc_power_domain(old_crtc_state));
1087 }