drivers/gpu/drm/i915/intel_uncore.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #ifndef __INTEL_UNCORE_H__
  26 #define __INTEL_UNCORE_H__
  27
  28 #include <linux/spinlock.h>
  29 #include <linux/notifier.h>
  30 #include <linux/hrtimer.h>
  31
  32 #include "i915_reg.h"
  33
  34 struct drm_i915_private;
  35 struct intel_uncore;
  36
  37 enum forcewake_domain_id {
  38         FW_DOMAIN_ID_RENDER = 0,
  39         FW_DOMAIN_ID_BLITTER,
  40         FW_DOMAIN_ID_MEDIA,
  41         FW_DOMAIN_ID_MEDIA_VDBOX0,
  42         FW_DOMAIN_ID_MEDIA_VDBOX1,
  43         FW_DOMAIN_ID_MEDIA_VDBOX2,
  44         FW_DOMAIN_ID_MEDIA_VDBOX3,
  45         FW_DOMAIN_ID_MEDIA_VEBOX0,
  46         FW_DOMAIN_ID_MEDIA_VEBOX1,
  47
  48         FW_DOMAIN_ID_COUNT
  49 };
  50
  51 enum forcewake_domains {
  52         FORCEWAKE_RENDER        = BIT(FW_DOMAIN_ID_RENDER),
  53         FORCEWAKE_BLITTER       = BIT(FW_DOMAIN_ID_BLITTER),
  54         FORCEWAKE_MEDIA         = BIT(FW_DOMAIN_ID_MEDIA),
  55         FORCEWAKE_MEDIA_VDBOX0  = BIT(FW_DOMAIN_ID_MEDIA_VDBOX0),
  56         FORCEWAKE_MEDIA_VDBOX1  = BIT(FW_DOMAIN_ID_MEDIA_VDBOX1),
  57         FORCEWAKE_MEDIA_VDBOX2  = BIT(FW_DOMAIN_ID_MEDIA_VDBOX2),
  58         FORCEWAKE_MEDIA_VDBOX3  = BIT(FW_DOMAIN_ID_MEDIA_VDBOX3),
  59         FORCEWAKE_MEDIA_VEBOX0  = BIT(FW_DOMAIN_ID_MEDIA_VEBOX0),
  60         FORCEWAKE_MEDIA_VEBOX1  = BIT(FW_DOMAIN_ID_MEDIA_VEBOX1),
  61
  62         FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1
  63 };
  64
  65 struct intel_uncore_funcs {
  66         void (*force_wake_get)(struct intel_uncore *uncore,
  67                                enum forcewake_domains domains);
  68         void (*force_wake_put)(struct intel_uncore *uncore,
  69                                enum forcewake_domains domains);
  70
  71         u8 (*mmio_readb)(struct drm_i915_private *dev_priv,
  72                          i915_reg_t r, bool trace);
  73         u16 (*mmio_readw)(struct drm_i915_private *dev_priv,
  74                           i915_reg_t r, bool trace);
  75         u32 (*mmio_readl)(struct drm_i915_private *dev_priv,
  76                           i915_reg_t r, bool trace);
  77         u64 (*mmio_readq)(struct drm_i915_private *dev_priv,
  78                           i915_reg_t r, bool trace);
  79
  80         void (*mmio_writeb)(struct drm_i915_private *dev_priv,
  81                             i915_reg_t r, u8 val, bool trace);
  82         void (*mmio_writew)(struct drm_i915_private *dev_priv,
  83                             i915_reg_t r, u16 val, bool trace);
  84         void (*mmio_writel)(struct drm_i915_private *dev_priv,
  85                             i915_reg_t r, u32 val, bool trace);
  86 };
  87
  88 struct intel_forcewake_range {
  89         u32 start;
  90         u32 end;
  91
  92         enum forcewake_domains domains;
  93 };
  94
  95 struct intel_uncore {
  96         spinlock_t lock; /** lock is also taken in irq contexts. */
  97
  98         const struct intel_forcewake_range *fw_domains_table;
  99         unsigned int fw_domains_table_entries;
 100
 101         struct notifier_block pmic_bus_access_nb;
 102         struct intel_uncore_funcs funcs;
 103
 104         unsigned int fifo_count;
 105
 106         enum forcewake_domains fw_domains;
 107         enum forcewake_domains fw_domains_active;
 108         enum forcewake_domains fw_domains_saved; /* user domains saved for S3 */
 109
 110         struct intel_uncore_forcewake_domain {
 111                 enum forcewake_domain_id id;
 112                 enum forcewake_domains mask;
 113                 unsigned int wake_count;
 114                 bool active;
 115                 struct hrtimer timer;
 116                 u32 __iomem *reg_set;
 117                 u32 __iomem *reg_ack;
 118         } fw_domain[FW_DOMAIN_ID_COUNT];
 119
 120         struct {
 121                 unsigned int count;
 122
 123                 int saved_mmio_check;
 124                 int saved_mmio_debug;
 125         } user_forcewake;
 126
 127         int unclaimed_mmio_check;
 128 };
 129
 130 /* Iterate over initialised fw domains */
 131 #define for_each_fw_domain_masked(domain__, mask__, uncore__, tmp__) \
 132         for (tmp__ = (mask__); \
 133              tmp__ ? (domain__ = &(uncore__)->fw_domain[__mask_next_bit(tmp__)]), 1 : 0;)
 134
 135 #define for_each_fw_domain(domain__, uncore__, tmp__) \
 136         for_each_fw_domain_masked(domain__, (uncore__)->fw_domains, uncore__, tmp__)
 137
 138 static inline struct intel_uncore *
 139 forcewake_domain_to_uncore(const struct intel_uncore_forcewake_domain *d)
 140 {
 141         return container_of(d, struct intel_uncore, fw_domain[d->id]);
 142 }
 143
 144 void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
 145 void intel_uncore_init(struct drm_i915_private *dev_priv);
 146 void intel_uncore_prune(struct drm_i915_private *dev_priv);
 147 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
 148 bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
 149 void intel_uncore_fini(struct drm_i915_private *dev_priv);
 150 void intel_uncore_suspend(struct drm_i915_private *dev_priv);
 151 void intel_uncore_resume_early(struct drm_i915_private *dev_priv);
 152 void intel_uncore_runtime_resume(struct drm_i915_private *dev_priv);
 153
 154 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
 155 void assert_forcewakes_inactive(struct intel_uncore *uncore);
 156 void assert_forcewakes_active(struct intel_uncore *uncore,
 157                               enum forcewake_domains fw_domains);
 158 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
 159
 160 enum forcewake_domains
 161 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
 162                                i915_reg_t reg, unsigned int op);
 163 #define FW_REG_READ  (1)
 164 #define FW_REG_WRITE (2)
 165
 166 void intel_uncore_forcewake_get(struct intel_uncore *uncore,
 167                                 enum forcewake_domains domains);
 168 void intel_uncore_forcewake_put(struct intel_uncore *uncore,
 169                                 enum forcewake_domains domains);
 170 /* Like above but the caller must manage the uncore.lock itself.
 171  * Must be used with I915_READ_FW and friends.
 172  */
 173 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
 174                                         enum forcewake_domains domains);
 175 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
 176                                         enum forcewake_domains domains);
 177
 178 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore);
 179 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore);
 180
 181 int __intel_wait_for_register(struct drm_i915_private *dev_priv,
 182                               i915_reg_t reg,
 183                               u32 mask,
 184                               u32 value,
 185                               unsigned int fast_timeout_us,
 186                               unsigned int slow_timeout_ms,
 187                               u32 *out_value);
 188 static inline
 189 int intel_wait_for_register(struct drm_i915_private *dev_priv,
 190                             i915_reg_t reg,
 191                             u32 mask,
 192                             u32 value,
 193                             unsigned int timeout_ms)
 194 {
 195         return __intel_wait_for_register(dev_priv, reg, mask, value, 2,
 196                                          timeout_ms, NULL);
 197 }
 198 int __intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
 199                                  i915_reg_t reg,
 200                                  u32 mask,
 201                                  u32 value,
 202                                  unsigned int fast_timeout_us,
 203                                  unsigned int slow_timeout_ms,
 204                                  u32 *out_value);
 205 static inline
 206 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
 207                                i915_reg_t reg,
 208                                u32 mask,
 209                                u32 value,
 210                                unsigned int timeout_ms)
 211 {
 212         return __intel_wait_for_register_fw(dev_priv, reg, mask, value,
 213                                             2, timeout_ms, NULL);
 214 }
 215
 216 #define raw_reg_read(base, reg) \
 217         readl(base + i915_mmio_reg_offset(reg))
 218 #define raw_reg_write(base, reg, value) \
 219         writel(value, base + i915_mmio_reg_offset(reg))
 220
 221 #endif /* !__INTEL_UNCORE_H__ */