drivers/gpu/drm/i915/intel_uncore.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #ifndef __INTEL_UNCORE_H__
  26 #define __INTEL_UNCORE_H__
  27
  28 #include <linux/spinlock.h>
  29 #include <linux/notifier.h>
  30 #include <linux/hrtimer.h>
  31
  32 #include "i915_reg.h"
  33
  34 struct drm_i915_private;
  35
  36 enum forcewake_domain_id {
  37         FW_DOMAIN_ID_RENDER = 0,
  38         FW_DOMAIN_ID_BLITTER,
  39         FW_DOMAIN_ID_MEDIA,
  40         FW_DOMAIN_ID_MEDIA_VDBOX0,
  41         FW_DOMAIN_ID_MEDIA_VDBOX1,
  42         FW_DOMAIN_ID_MEDIA_VDBOX2,
  43         FW_DOMAIN_ID_MEDIA_VDBOX3,
  44         FW_DOMAIN_ID_MEDIA_VEBOX0,
  45         FW_DOMAIN_ID_MEDIA_VEBOX1,
  46
  47         FW_DOMAIN_ID_COUNT
  48 };
  49
  50 enum forcewake_domains {
  51         FORCEWAKE_RENDER        = BIT(FW_DOMAIN_ID_RENDER),
  52         FORCEWAKE_BLITTER       = BIT(FW_DOMAIN_ID_BLITTER),
  53         FORCEWAKE_MEDIA         = BIT(FW_DOMAIN_ID_MEDIA),
  54         FORCEWAKE_MEDIA_VDBOX0  = BIT(FW_DOMAIN_ID_MEDIA_VDBOX0),
  55         FORCEWAKE_MEDIA_VDBOX1  = BIT(FW_DOMAIN_ID_MEDIA_VDBOX1),
  56         FORCEWAKE_MEDIA_VDBOX2  = BIT(FW_DOMAIN_ID_MEDIA_VDBOX2),
  57         FORCEWAKE_MEDIA_VDBOX3  = BIT(FW_DOMAIN_ID_MEDIA_VDBOX3),
  58         FORCEWAKE_MEDIA_VEBOX0  = BIT(FW_DOMAIN_ID_MEDIA_VEBOX0),
  59         FORCEWAKE_MEDIA_VEBOX1  = BIT(FW_DOMAIN_ID_MEDIA_VEBOX1),
  60
  61         FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1
  62 };
  63
  64 struct intel_uncore_funcs {
  65         void (*force_wake_get)(struct drm_i915_private *dev_priv,
  66                                enum forcewake_domains domains);
  67         void (*force_wake_put)(struct drm_i915_private *dev_priv,
  68                                enum forcewake_domains domains);
  69
  70         u8 (*mmio_readb)(struct drm_i915_private *dev_priv,
  71                          i915_reg_t r, bool trace);
  72         u16 (*mmio_readw)(struct drm_i915_private *dev_priv,
  73                           i915_reg_t r, bool trace);
  74         u32 (*mmio_readl)(struct drm_i915_private *dev_priv,
  75                           i915_reg_t r, bool trace);
  76         u64 (*mmio_readq)(struct drm_i915_private *dev_priv,
  77                           i915_reg_t r, bool trace);
  78
  79         void (*mmio_writeb)(struct drm_i915_private *dev_priv,
  80                             i915_reg_t r, u8 val, bool trace);
  81         void (*mmio_writew)(struct drm_i915_private *dev_priv,
  82                             i915_reg_t r, u16 val, bool trace);
  83         void (*mmio_writel)(struct drm_i915_private *dev_priv,
  84                             i915_reg_t r, u32 val, bool trace);
  85 };
  86
  87 struct intel_forcewake_range {
  88         u32 start;
  89         u32 end;
  90
  91         enum forcewake_domains domains;
  92 };
  93
  94 struct intel_uncore {
  95         spinlock_t lock; /** lock is also taken in irq contexts. */
  96
  97         const struct intel_forcewake_range *fw_domains_table;
  98         unsigned int fw_domains_table_entries;
  99
 100         struct notifier_block pmic_bus_access_nb;
 101         struct intel_uncore_funcs funcs;
 102
 103         unsigned int fifo_count;
 104
 105         enum forcewake_domains fw_domains;
 106         enum forcewake_domains fw_domains_active;
 107         enum forcewake_domains fw_domains_saved; /* user domains saved for S3 */
 108
 109         struct intel_uncore_forcewake_domain {
 110                 enum forcewake_domain_id id;
 111                 enum forcewake_domains mask;
 112                 unsigned int wake_count;
 113                 bool active;
 114                 struct hrtimer timer;
 115                 u32 __iomem *reg_set;
 116                 u32 __iomem *reg_ack;
 117         } fw_domain[FW_DOMAIN_ID_COUNT];
 118
 119         struct {
 120                 unsigned int count;
 121
 122                 int saved_mmio_check;
 123                 int saved_mmio_debug;
 124         } user_forcewake;
 125
 126         int unclaimed_mmio_check;
 127 };
 128
 129 /* Iterate over initialised fw domains */
 130 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__, tmp__) \
 131         for (tmp__ = (mask__); \
 132              tmp__ ? (domain__ = &(dev_priv__)->uncore.fw_domain[__mask_next_bit(tmp__)]), 1 : 0;)
 133
 134 #define for_each_fw_domain(domain__, dev_priv__, tmp__) \
 135         for_each_fw_domain_masked(domain__, (dev_priv__)->uncore.fw_domains, dev_priv__, tmp__)
 136
 137 static inline struct intel_uncore *
 138 forcewake_domain_to_uncore(const struct intel_uncore_forcewake_domain *d)
 139 {
 140         return container_of(d, struct intel_uncore, fw_domain[d->id]);
 141 }
 142
 143 void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
 144 void intel_uncore_init(struct drm_i915_private *dev_priv);
 145 void intel_uncore_prune(struct drm_i915_private *dev_priv);
 146 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
 147 bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
 148 void intel_uncore_fini(struct drm_i915_private *dev_priv);
 149 void intel_uncore_suspend(struct drm_i915_private *dev_priv);
 150 void intel_uncore_resume_early(struct drm_i915_private *dev_priv);
 151 void intel_uncore_runtime_resume(struct drm_i915_private *dev_priv);
 152
 153 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
 154 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
 155 void assert_forcewakes_active(struct drm_i915_private *dev_priv,
 156                               enum forcewake_domains fw_domains);
 157 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
 158
 159 enum forcewake_domains
 160 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
 161                                i915_reg_t reg, unsigned int op);
 162 #define FW_REG_READ  (1)
 163 #define FW_REG_WRITE (2)
 164
 165 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 166                                 enum forcewake_domains domains);
 167 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 168                                 enum forcewake_domains domains);
 169 /* Like above but the caller must manage the uncore.lock itself.
 170  * Must be used with I915_READ_FW and friends.
 171  */
 172 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
 173                                         enum forcewake_domains domains);
 174 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
 175                                         enum forcewake_domains domains);
 176
 177 void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv);
 178 void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv);
 179
 180 int __intel_wait_for_register(struct drm_i915_private *dev_priv,
 181                               i915_reg_t reg,
 182                               u32 mask,
 183                               u32 value,
 184                               unsigned int fast_timeout_us,
 185                               unsigned int slow_timeout_ms,
 186                               u32 *out_value);
 187 static inline
 188 int intel_wait_for_register(struct drm_i915_private *dev_priv,
 189                             i915_reg_t reg,
 190                             u32 mask,
 191                             u32 value,
 192                             unsigned int timeout_ms)
 193 {
 194         return __intel_wait_for_register(dev_priv, reg, mask, value, 2,
 195                                          timeout_ms, NULL);
 196 }
 197 int __intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
 198                                  i915_reg_t reg,
 199                                  u32 mask,
 200                                  u32 value,
 201                                  unsigned int fast_timeout_us,
 202                                  unsigned int slow_timeout_ms,
 203                                  u32 *out_value);
 204 static inline
 205 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
 206                                i915_reg_t reg,
 207                                u32 mask,
 208                                u32 value,
 209                                unsigned int timeout_ms)
 210 {
 211         return __intel_wait_for_register_fw(dev_priv, reg, mask, value,
 212                                             2, timeout_ms, NULL);
 213 }
 214
 215 #define raw_reg_read(base, reg) \
 216         readl(base + i915_mmio_reg_offset(reg))
 217 #define raw_reg_write(base, reg, value) \
 218         writel(value, base + i915_mmio_reg_offset(reg))
 219
 220 #endif /* !__INTEL_UNCORE_H__ */