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27 #include "intel_guc_fwif.h"
28 #include "i915_guc_reg.h"
29 #include "intel_ringbuffer.h"
33 struct drm_i915_gem_request;
36 * This structure primarily describes the GEM object shared with the GuC.
37 * The specs sometimes refer to this object as a "GuC context", but we use
38 * the term "client" to avoid confusion with hardware contexts. This
39 * GEM object is held for the entire lifetime of our interaction with
40 * the GuC, being allocated before the GuC is loaded with its firmware.
41 * Because there's no way to update the address used by the GuC after
42 * initialisation, the shared object must stay pinned into the GGTT as
43 * long as the GuC is in use. We also keep the first page (only) mapped
44 * into kernel address space, as it includes shared data that must be
45 * updated on every request submission.
47 * The single GEM object described here is actually made up of several
48 * separate areas, as far as the GuC is concerned. The first page (kept
49 * kmap'd) includes the "process descriptor" which holds sequence data for
50 * the doorbell, and one cacheline which actually *is* the doorbell; a
51 * write to this will "ring the doorbell" (i.e. send an interrupt to the
52 * GuC). The subsequent pages of the client object constitute the work
53 * queue (a circular array of work items), again described in the process
54 * descriptor. Work queue pages are mapped momentarily as required.
56 * We also keep a few statistics on failures. Ideally, these should all
58 * no_wq_space: times that the submission pre-check found no space was
59 * available in the work queue (note, the queue is shared,
60 * not per-engine). It is OK for this to be nonzero, but
61 * it should not be huge!
62 * b_fail: failed to ring the doorbell. This should never happen, unless
63 * somehow the hardware misbehaves, or maybe if the GuC firmware
64 * crashes? We probably need to reset the GPU to recover.
65 * retcode: errno from last guc_submit()
67 struct i915_guc_client {
70 struct i915_gem_context *owner;
71 struct intel_guc *guc;
73 uint32_t engines; /* bitmap of (host) engine ids */
76 uint32_t proc_desc_offset;
79 unsigned long doorbell_offset;
91 /* Per-engine counts of GuC submissions */
92 uint64_t submissions[I915_NUM_ENGINES];
95 enum intel_uc_fw_status {
96 INTEL_UC_FIRMWARE_FAIL = -1,
97 INTEL_UC_FIRMWARE_NONE = 0,
98 INTEL_UC_FIRMWARE_PENDING,
99 INTEL_UC_FIRMWARE_SUCCESS
102 /* User-friendly representation of an enum */
104 const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
107 case INTEL_UC_FIRMWARE_FAIL:
109 case INTEL_UC_FIRMWARE_NONE:
111 case INTEL_UC_FIRMWARE_PENDING:
113 case INTEL_UC_FIRMWARE_SUCCESS:
119 enum intel_uc_fw_type {
120 INTEL_UC_FW_TYPE_GUC,
124 /* User-friendly representation of an enum */
125 static inline const char *intel_uc_fw_type_repr(enum intel_uc_fw_type type)
128 case INTEL_UC_FW_TYPE_GUC:
130 case INTEL_UC_FW_TYPE_HUC:
137 * This structure encapsulates all the data needed during the process
138 * of fetching, caching, and loading the firmware image into the GuC.
143 struct drm_i915_gem_object *obj;
144 enum intel_uc_fw_status fetch_status;
145 enum intel_uc_fw_status load_status;
147 uint16_t major_ver_wanted;
148 uint16_t minor_ver_wanted;
149 uint16_t major_ver_found;
150 uint16_t minor_ver_found;
152 enum intel_uc_fw_type type;
153 uint32_t header_size;
154 uint32_t header_offset;
158 uint32_t ucode_offset;
161 struct intel_guc_log {
163 struct i915_vma *vma;
164 /* The runtime stuff gets created only when GuC logging gets enabled */
167 struct workqueue_struct *flush_wq;
168 struct work_struct flush_work;
169 struct rchan *relay_chan;
171 /* logging related stats */
172 u32 capture_miss_count;
173 u32 flush_interrupt_count;
174 u32 prev_overflow_count[GUC_MAX_LOG_BUFFER];
175 u32 total_overflow_count[GUC_MAX_LOG_BUFFER];
176 u32 flush_count[GUC_MAX_LOG_BUFFER];
180 struct intel_uc_fw fw;
181 struct intel_guc_log log;
183 /* intel_guc_recv interrupt related state */
184 bool interrupts_enabled;
186 struct i915_vma *ads_vma;
187 struct i915_vma *stage_desc_pool;
188 void *stage_desc_pool_vaddr;
189 struct ida stage_ids;
191 struct i915_guc_client *execbuf_client;
193 DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
194 uint32_t db_cacheline; /* Cyclic counter mod pagesize */
196 /* Action status & statistics */
197 uint64_t action_count; /* Total commands issued */
198 uint32_t action_cmd; /* Last command word */
199 uint32_t action_status; /* Last return status */
200 uint32_t action_fail; /* Total number of failures */
201 int32_t action_err; /* Last error code */
203 uint64_t submissions[I915_NUM_ENGINES];
204 uint32_t last_seqno[I915_NUM_ENGINES];
206 /* To serialize the intel_guc_send actions */
207 struct mutex send_mutex;
209 /* GuC's FW specific send function */
210 int (*send)(struct intel_guc *guc, const u32 *data, u32 len);
214 /* Generic uC firmware management */
215 struct intel_uc_fw fw;
217 /* HuC-specific additions */
221 void intel_uc_sanitize_options(struct drm_i915_private *dev_priv);
222 void intel_uc_init_early(struct drm_i915_private *dev_priv);
223 void intel_uc_init_fw(struct drm_i915_private *dev_priv);
224 void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
225 int intel_uc_init_hw(struct drm_i915_private *dev_priv);
226 void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
227 int intel_guc_sample_forcewake(struct intel_guc *guc);
228 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
229 static inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
231 return guc->send(guc, action, len);
234 /* intel_guc_loader.c */
235 int intel_guc_select_fw(struct intel_guc *guc);
236 int intel_guc_init_hw(struct intel_guc *guc);
237 int intel_guc_suspend(struct drm_i915_private *dev_priv);
238 int intel_guc_resume(struct drm_i915_private *dev_priv);
239 u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
241 /* i915_guc_submission.c */
242 int i915_guc_submission_init(struct drm_i915_private *dev_priv);
243 int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
244 int i915_guc_wq_reserve(struct drm_i915_gem_request *rq);
245 void i915_guc_wq_unreserve(struct drm_i915_gem_request *request);
246 void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
247 void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
248 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
250 /* intel_guc_log.c */
251 int intel_guc_log_create(struct intel_guc *guc);
252 void intel_guc_log_destroy(struct intel_guc *guc);
253 int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
254 void i915_guc_log_register(struct drm_i915_private *dev_priv);
255 void i915_guc_log_unregister(struct drm_i915_private *dev_priv);
257 static inline u32 guc_ggtt_offset(struct i915_vma *vma)
259 u32 offset = i915_ggtt_offset(vma);
260 GEM_BUG_ON(offset < GUC_WOPCM_TOP);
261 GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
266 void intel_huc_select_fw(struct intel_huc *huc);
267 int intel_huc_init_hw(struct intel_huc *huc);
268 void intel_guc_auth_huc(struct drm_i915_private *dev_priv);