drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_fourcc.h>
  36 #include <drm/drm_rect.h>
  37 #include <drm/drm_atomic.h>
  38 #include <drm/drm_plane_helper.h>
  39 #include "intel_drv.h"
  40 #include "intel_frontbuffer.h"
  41 #include <drm/i915_drm.h>
  42 #include "i915_drv.h"
  43
  44 static bool
  45 format_is_yuv(uint32_t format)
  46 {
  47         switch (format) {
  48         case DRM_FORMAT_YUYV:
  49         case DRM_FORMAT_UYVY:
  50         case DRM_FORMAT_VYUY:
  51         case DRM_FORMAT_YVYU:
  52                 return true;
  53         default:
  54                 return false;
  55         }
  56 }
  57
  58 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  59                              int usecs)
  60 {
  61         /* paranoia */
  62         if (!adjusted_mode->crtc_htotal)
  63                 return 1;
  64
  65         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  66                             1000 * adjusted_mode->crtc_htotal);
  67 }
  68
  69 /* FIXME: We should instead only take spinlocks once for the entire update
  70  * instead of once per mmio. */
  71 #if IS_ENABLED(CONFIG_PROVE_LOCKING)
  72 #define VBLANK_EVASION_TIME_US 250
  73 #else
  74 #define VBLANK_EVASION_TIME_US 100
  75 #endif
  76
  77 /**
  78  * intel_pipe_update_start() - start update of a set of display registers
  79  * @new_crtc_state: the new crtc state
  80  *
  81  * Mark the start of an update to pipe registers that should be updated
  82  * atomically regarding vblank. If the next vblank will happens within
  83  * the next 100 us, this function waits until the vblank passes.
  84  *
  85  * After a successful call to this function, interrupts will be disabled
  86  * until a subsequent call to intel_pipe_update_end(). That is done to
  87  * avoid random delays.
  88  */
  89 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
  90 {
  91         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
  92         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  93         const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
  94         long timeout = msecs_to_jiffies_timeout(1);
  95         int scanline, min, max, vblank_start;
  96         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  97         bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
  98                 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
  99         DEFINE_WAIT(wait);
 100
 101         vblank_start = adjusted_mode->crtc_vblank_start;
 102         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
 103                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
 104
 105         /* FIXME needs to be calibrated sensibly */
 106         min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
 107                                                       VBLANK_EVASION_TIME_US);
 108         max = vblank_start - 1;
 109
 110         local_irq_disable();
 111
 112         if (min <= 0 || max <= 0)
 113                 return;
 114
 115         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 116                 return;
 117
 118         crtc->debug.min_vbl = min;
 119         crtc->debug.max_vbl = max;
 120         trace_i915_pipe_update_start(crtc);
 121
 122         for (;;) {
 123                 /*
 124                  * prepare_to_wait() has a memory barrier, which guarantees
 125                  * other CPUs can see the task state update by the time we
 126                  * read the scanline.
 127                  */
 128                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 129
 130                 scanline = intel_get_crtc_scanline(crtc);
 131                 if (scanline < min || scanline > max)
 132                         break;
 133
 134                 if (timeout <= 0) {
 135                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 136                                   pipe_name(crtc->pipe));
 137                         break;
 138                 }
 139
 140                 local_irq_enable();
 141
 142                 timeout = schedule_timeout(timeout);
 143
 144                 local_irq_disable();
 145         }
 146
 147         finish_wait(wq, &wait);
 148
 149         drm_crtc_vblank_put(&crtc->base);
 150
 151         /*
 152          * On VLV/CHV DSI the scanline counter would appear to
 153          * increment approx. 1/3 of a scanline before start of vblank.
 154          * The registers still get latched at start of vblank however.
 155          * This means we must not write any registers on the first
 156          * line of vblank (since not the whole line is actually in
 157          * vblank). And unfortunately we can't use the interrupt to
 158          * wait here since it will fire too soon. We could use the
 159          * frame start interrupt instead since it will fire after the
 160          * critical scanline, but that would require more changes
 161          * in the interrupt code. So for now we'll just do the nasty
 162          * thing and poll for the bad scanline to pass us by.
 163          *
 164          * FIXME figure out if BXT+ DSI suffers from this as well
 165          */
 166         while (need_vlv_dsi_wa && scanline == vblank_start)
 167                 scanline = intel_get_crtc_scanline(crtc);
 168
 169         crtc->debug.scanline_start = scanline;
 170         crtc->debug.start_vbl_time = ktime_get();
 171         crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
 172
 173         trace_i915_pipe_update_vblank_evaded(crtc);
 174 }
 175
 176 /**
 177  * intel_pipe_update_end() - end update of a set of display registers
 178  * @new_crtc_state: the new crtc state
 179  *
 180  * Mark the end of an update started with intel_pipe_update_start(). This
 181  * re-enables interrupts and verifies the update was actually completed
 182  * before a vblank.
 183  */
 184 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 185 {
 186         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
 187         enum pipe pipe = crtc->pipe;
 188         int scanline_end = intel_get_crtc_scanline(crtc);
 189         u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
 190         ktime_t end_vbl_time = ktime_get();
 191         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 192
 193         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
 194
 195         /* We're still in the vblank-evade critical section, this can't race.
 196          * Would be slightly nice to just grab the vblank count and arm the
 197          * event outside of the critical section - the spinlock might spin for a
 198          * while ... */
 199         if (new_crtc_state->base.event) {
 200                 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
 201
 202                 spin_lock(&crtc->base.dev->event_lock);
 203                 drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
 204                 spin_unlock(&crtc->base.dev->event_lock);
 205
 206                 new_crtc_state->base.event = NULL;
 207         }
 208
 209         local_irq_enable();
 210
 211         if (intel_vgpu_active(dev_priv))
 212                 return;
 213
 214         if (crtc->debug.start_vbl_count &&
 215             crtc->debug.start_vbl_count != end_vbl_count) {
 216                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
 217                           pipe_name(pipe), crtc->debug.start_vbl_count,
 218                           end_vbl_count,
 219                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 220                           crtc->debug.min_vbl, crtc->debug.max_vbl,
 221                           crtc->debug.scanline_start, scanline_end);
 222         }
 223 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
 224         else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
 225                  VBLANK_EVASION_TIME_US)
 226                 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
 227                          pipe_name(pipe),
 228                          ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 229                          VBLANK_EVASION_TIME_US);
 230 #endif
 231 }
 232
 233 void
 234 skl_update_plane(struct intel_plane *plane,
 235                  const struct intel_crtc_state *crtc_state,
 236                  const struct intel_plane_state *plane_state)
 237 {
 238         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 239         const struct drm_framebuffer *fb = plane_state->base.fb;
 240         enum plane_id plane_id = plane->id;
 241         enum pipe pipe = plane->pipe;
 242         u32 plane_ctl = plane_state->ctl;
 243         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 244         u32 surf_addr = plane_state->main.offset;
 245         unsigned int rotation = plane_state->base.rotation;
 246         u32 stride = skl_plane_stride(fb, 0, rotation);
 247         u32 aux_stride = skl_plane_stride(fb, 1, rotation);
 248         int crtc_x = plane_state->base.dst.x1;
 249         int crtc_y = plane_state->base.dst.y1;
 250         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 251         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 252         uint32_t x = plane_state->main.x;
 253         uint32_t y = plane_state->main.y;
 254         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 255         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 256         unsigned long irqflags;
 257
 258         /* Sizes are 0 based */
 259         src_w--;
 260         src_h--;
 261         crtc_w--;
 262         crtc_h--;
 263
 264         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 265
 266         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 267                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
 268                               plane_state->color_ctl);
 269         if (key->flags) {
 270                 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
 271                 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
 272                 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
 273         }
 274
 275         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
 276         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
 277         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
 278         I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
 279                       (plane_state->aux.offset - surf_addr) | aux_stride);
 280         I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
 281                       (plane_state->aux.y << 16) | plane_state->aux.x);
 282
 283         /* program plane scaler */
 284         if (plane_state->scaler_id >= 0) {
 285                 int scaler_id = plane_state->scaler_id;
 286                 const struct intel_scaler *scaler;
 287
 288                 scaler = &crtc_state->scaler_state.scalers[scaler_id];
 289
 290                 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
 291                               PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
 292                 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 293                 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 294                 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
 295                               ((crtc_w + 1) << 16)|(crtc_h + 1));
 296
 297                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
 298         } else {
 299                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 300         }
 301
 302         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
 303         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
 304                       intel_plane_ggtt_offset(plane_state) + surf_addr);
 305         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 306
 307         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 308 }
 309
 310 void
 311 skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 312 {
 313         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 314         enum plane_id plane_id = plane->id;
 315         enum pipe pipe = plane->pipe;
 316         unsigned long irqflags;
 317
 318         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 319
 320         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
 321
 322         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
 323         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 324
 325         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 326 }
 327
 328 static void
 329 chv_update_csc(struct intel_plane *plane, uint32_t format)
 330 {
 331         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 332         enum plane_id plane_id = plane->id;
 333
 334         /* Seems RGB data bypasses the CSC always */
 335         if (!format_is_yuv(format))
 336                 return;
 337
 338         /*
 339          * BT.601 limited range YCbCr -> full range RGB
 340          *
 341          * |r|   | 6537 4769     0|   |cr  |
 342          * |g| = |-3330 4769 -1605| x |y-64|
 343          * |b|   |    0 4769  8263|   |cb  |
 344          *
 345          * Cb and Cr apparently come in as signed already, so no
 346          * need for any offset. For Y we need to remove the offset.
 347          */
 348         I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
 349         I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 350         I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 351
 352         I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(4769) | SPCSC_C0(6537));
 353         I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(-3330) | SPCSC_C0(0));
 354         I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(-1605) | SPCSC_C0(4769));
 355         I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(4769) | SPCSC_C0(0));
 356         I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(8263));
 357
 358         I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(940) | SPCSC_IMIN(64));
 359         I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 360         I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 361
 362         I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 363         I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 364         I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 365 }
 366
 367 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
 368                           const struct intel_plane_state *plane_state)
 369 {
 370         const struct drm_framebuffer *fb = plane_state->base.fb;
 371         unsigned int rotation = plane_state->base.rotation;
 372         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 373         u32 sprctl;
 374
 375         sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
 376
 377         switch (fb->format->format) {
 378         case DRM_FORMAT_YUYV:
 379                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 380                 break;
 381         case DRM_FORMAT_YVYU:
 382                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 383                 break;
 384         case DRM_FORMAT_UYVY:
 385                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 386                 break;
 387         case DRM_FORMAT_VYUY:
 388                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 389                 break;
 390         case DRM_FORMAT_RGB565:
 391                 sprctl |= SP_FORMAT_BGR565;
 392                 break;
 393         case DRM_FORMAT_XRGB8888:
 394                 sprctl |= SP_FORMAT_BGRX8888;
 395                 break;
 396         case DRM_FORMAT_ARGB8888:
 397                 sprctl |= SP_FORMAT_BGRA8888;
 398                 break;
 399         case DRM_FORMAT_XBGR2101010:
 400                 sprctl |= SP_FORMAT_RGBX1010102;
 401                 break;
 402         case DRM_FORMAT_ABGR2101010:
 403                 sprctl |= SP_FORMAT_RGBA1010102;
 404                 break;
 405         case DRM_FORMAT_XBGR8888:
 406                 sprctl |= SP_FORMAT_RGBX8888;
 407                 break;
 408         case DRM_FORMAT_ABGR8888:
 409                 sprctl |= SP_FORMAT_RGBA8888;
 410                 break;
 411         default:
 412                 MISSING_CASE(fb->format->format);
 413                 return 0;
 414         }
 415
 416         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 417                 sprctl |= SP_TILED;
 418
 419         if (rotation & DRM_MODE_ROTATE_180)
 420                 sprctl |= SP_ROTATE_180;
 421
 422         if (rotation & DRM_MODE_REFLECT_X)
 423                 sprctl |= SP_MIRROR;
 424
 425         if (key->flags & I915_SET_COLORKEY_SOURCE)
 426                 sprctl |= SP_SOURCE_KEY;
 427
 428         return sprctl;
 429 }
 430
 431 static void
 432 vlv_update_plane(struct intel_plane *plane,
 433                  const struct intel_crtc_state *crtc_state,
 434                  const struct intel_plane_state *plane_state)
 435 {
 436         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 437         const struct drm_framebuffer *fb = plane_state->base.fb;
 438         enum pipe pipe = plane->pipe;
 439         enum plane_id plane_id = plane->id;
 440         u32 sprctl = plane_state->ctl;
 441         u32 sprsurf_offset = plane_state->main.offset;
 442         u32 linear_offset;
 443         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 444         int crtc_x = plane_state->base.dst.x1;
 445         int crtc_y = plane_state->base.dst.y1;
 446         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 447         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 448         uint32_t x = plane_state->main.x;
 449         uint32_t y = plane_state->main.y;
 450         unsigned long irqflags;
 451
 452         /* Sizes are 0 based */
 453         crtc_w--;
 454         crtc_h--;
 455
 456         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 457
 458         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 459
 460         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
 461                 chv_update_csc(plane, fb->format->format);
 462
 463         if (key->flags) {
 464                 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
 465                 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
 466                 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
 467         }
 468         I915_WRITE_FW(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
 469         I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 470
 471         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 472                 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
 473         else
 474                 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
 475
 476         I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
 477
 478         I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
 479         I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
 480         I915_WRITE_FW(SPSURF(pipe, plane_id),
 481                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 482         POSTING_READ_FW(SPSURF(pipe, plane_id));
 483
 484         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 485 }
 486
 487 static void
 488 vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 489 {
 490         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 491         enum pipe pipe = plane->pipe;
 492         enum plane_id plane_id = plane->id;
 493         unsigned long irqflags;
 494
 495         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 496
 497         I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
 498
 499         I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
 500         POSTING_READ_FW(SPSURF(pipe, plane_id));
 501
 502         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 503 }
 504
 505 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
 506                           const struct intel_plane_state *plane_state)
 507 {
 508         struct drm_i915_private *dev_priv =
 509                 to_i915(plane_state->base.plane->dev);
 510         const struct drm_framebuffer *fb = plane_state->base.fb;
 511         unsigned int rotation = plane_state->base.rotation;
 512         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 513         u32 sprctl;
 514
 515         sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
 516
 517         if (IS_IVYBRIDGE(dev_priv))
 518                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 519
 520         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 521                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 522
 523         switch (fb->format->format) {
 524         case DRM_FORMAT_XBGR8888:
 525                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 526                 break;
 527         case DRM_FORMAT_XRGB8888:
 528                 sprctl |= SPRITE_FORMAT_RGBX888;
 529                 break;
 530         case DRM_FORMAT_YUYV:
 531                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 532                 break;
 533         case DRM_FORMAT_YVYU:
 534                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 535                 break;
 536         case DRM_FORMAT_UYVY:
 537                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 538                 break;
 539         case DRM_FORMAT_VYUY:
 540                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 541                 break;
 542         default:
 543                 MISSING_CASE(fb->format->format);
 544                 return 0;
 545         }
 546
 547         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 548                 sprctl |= SPRITE_TILED;
 549
 550         if (rotation & DRM_MODE_ROTATE_180)
 551                 sprctl |= SPRITE_ROTATE_180;
 552
 553         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 554                 sprctl |= SPRITE_DEST_KEY;
 555         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 556                 sprctl |= SPRITE_SOURCE_KEY;
 557
 558         return sprctl;
 559 }
 560
 561 static void
 562 ivb_update_plane(struct intel_plane *plane,
 563                  const struct intel_crtc_state *crtc_state,
 564                  const struct intel_plane_state *plane_state)
 565 {
 566         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 567         const struct drm_framebuffer *fb = plane_state->base.fb;
 568         enum pipe pipe = plane->pipe;
 569         u32 sprctl = plane_state->ctl, sprscale = 0;
 570         u32 sprsurf_offset = plane_state->main.offset;
 571         u32 linear_offset;
 572         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 573         int crtc_x = plane_state->base.dst.x1;
 574         int crtc_y = plane_state->base.dst.y1;
 575         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 576         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 577         uint32_t x = plane_state->main.x;
 578         uint32_t y = plane_state->main.y;
 579         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 580         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 581         unsigned long irqflags;
 582
 583         /* Sizes are 0 based */
 584         src_w--;
 585         src_h--;
 586         crtc_w--;
 587         crtc_h--;
 588
 589         if (crtc_w != src_w || crtc_h != src_h)
 590                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 591
 592         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 593
 594         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 595
 596         if (key->flags) {
 597                 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
 598                 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
 599                 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
 600         }
 601
 602         I915_WRITE_FW(SPRSTRIDE(pipe), fb->pitches[0]);
 603         I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 604
 605         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 606          * register */
 607         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 608                 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
 609         else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 610                 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
 611         else
 612                 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
 613
 614         I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 615         if (plane->can_scale)
 616                 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
 617         I915_WRITE_FW(SPRCTL(pipe), sprctl);
 618         I915_WRITE_FW(SPRSURF(pipe),
 619                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 620         POSTING_READ_FW(SPRSURF(pipe));
 621
 622         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 623 }
 624
 625 static void
 626 ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 627 {
 628         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 629         enum pipe pipe = plane->pipe;
 630         unsigned long irqflags;
 631
 632         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 633
 634         I915_WRITE_FW(SPRCTL(pipe), 0);
 635         /* Can't leave the scaler enabled... */
 636         if (plane->can_scale)
 637                 I915_WRITE_FW(SPRSCALE(pipe), 0);
 638
 639         I915_WRITE_FW(SPRSURF(pipe), 0);
 640         POSTING_READ_FW(SPRSURF(pipe));
 641
 642         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 643 }
 644
 645 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
 646                           const struct intel_plane_state *plane_state)
 647 {
 648         struct drm_i915_private *dev_priv =
 649                 to_i915(plane_state->base.plane->dev);
 650         const struct drm_framebuffer *fb = plane_state->base.fb;
 651         unsigned int rotation = plane_state->base.rotation;
 652         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 653         u32 dvscntr;
 654
 655         dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
 656
 657         if (IS_GEN6(dev_priv))
 658                 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
 659
 660         switch (fb->format->format) {
 661         case DRM_FORMAT_XBGR8888:
 662                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 663                 break;
 664         case DRM_FORMAT_XRGB8888:
 665                 dvscntr |= DVS_FORMAT_RGBX888;
 666                 break;
 667         case DRM_FORMAT_YUYV:
 668                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 669                 break;
 670         case DRM_FORMAT_YVYU:
 671                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 672                 break;
 673         case DRM_FORMAT_UYVY:
 674                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 675                 break;
 676         case DRM_FORMAT_VYUY:
 677                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 678                 break;
 679         default:
 680                 MISSING_CASE(fb->format->format);
 681                 return 0;
 682         }
 683
 684         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 685                 dvscntr |= DVS_TILED;
 686
 687         if (rotation & DRM_MODE_ROTATE_180)
 688                 dvscntr |= DVS_ROTATE_180;
 689
 690         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 691                 dvscntr |= DVS_DEST_KEY;
 692         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 693                 dvscntr |= DVS_SOURCE_KEY;
 694
 695         return dvscntr;
 696 }
 697
 698 static void
 699 g4x_update_plane(struct intel_plane *plane,
 700                  const struct intel_crtc_state *crtc_state,
 701                  const struct intel_plane_state *plane_state)
 702 {
 703         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 704         const struct drm_framebuffer *fb = plane_state->base.fb;
 705         enum pipe pipe = plane->pipe;
 706         u32 dvscntr = plane_state->ctl, dvsscale = 0;
 707         u32 dvssurf_offset = plane_state->main.offset;
 708         u32 linear_offset;
 709         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 710         int crtc_x = plane_state->base.dst.x1;
 711         int crtc_y = plane_state->base.dst.y1;
 712         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 713         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 714         uint32_t x = plane_state->main.x;
 715         uint32_t y = plane_state->main.y;
 716         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 717         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 718         unsigned long irqflags;
 719
 720         /* Sizes are 0 based */
 721         src_w--;
 722         src_h--;
 723         crtc_w--;
 724         crtc_h--;
 725
 726         if (crtc_w != src_w || crtc_h != src_h)
 727                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 728
 729         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 730
 731         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 732
 733         if (key->flags) {
 734                 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
 735                 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
 736                 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
 737         }
 738
 739         I915_WRITE_FW(DVSSTRIDE(pipe), fb->pitches[0]);
 740         I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 741
 742         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 743                 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
 744         else
 745                 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
 746
 747         I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 748         I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
 749         I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
 750         I915_WRITE_FW(DVSSURF(pipe),
 751                       intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
 752         POSTING_READ_FW(DVSSURF(pipe));
 753
 754         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 755 }
 756
 757 static void
 758 g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 759 {
 760         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 761         enum pipe pipe = plane->pipe;
 762         unsigned long irqflags;
 763
 764         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 765
 766         I915_WRITE_FW(DVSCNTR(pipe), 0);
 767         /* Disable the scaler */
 768         I915_WRITE_FW(DVSSCALE(pipe), 0);
 769
 770         I915_WRITE_FW(DVSSURF(pipe), 0);
 771         POSTING_READ_FW(DVSSURF(pipe));
 772
 773         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 774 }
 775
 776 static int
 777 intel_check_sprite_plane(struct intel_plane *plane,
 778                          struct intel_crtc_state *crtc_state,
 779                          struct intel_plane_state *state)
 780 {
 781         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 782         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 783         struct drm_framebuffer *fb = state->base.fb;
 784         int crtc_x, crtc_y;
 785         unsigned int crtc_w, crtc_h;
 786         uint32_t src_x, src_y, src_w, src_h;
 787         struct drm_rect *src = &state->base.src;
 788         struct drm_rect *dst = &state->base.dst;
 789         const struct drm_rect *clip = &state->clip;
 790         int hscale, vscale;
 791         int max_scale, min_scale;
 792         bool can_scale;
 793         int ret;
 794
 795         *src = drm_plane_state_src(&state->base);
 796         *dst = drm_plane_state_dest(&state->base);
 797
 798         if (!fb) {
 799                 state->base.visible = false;
 800                 return 0;
 801         }
 802
 803         /* Don't modify another pipe's plane */
 804         if (plane->pipe != crtc->pipe) {
 805                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
 806                 return -EINVAL;
 807         }
 808
 809         /* FIXME check all gen limits */
 810         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
 811                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
 812                 return -EINVAL;
 813         }
 814
 815         /* setup can_scale, min_scale, max_scale */
 816         if (INTEL_GEN(dev_priv) >= 9) {
 817                 /* use scaler when colorkey is not required */
 818                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
 819                         can_scale = 1;
 820                         min_scale = 1;
 821                         max_scale = skl_max_scale(crtc, crtc_state);
 822                 } else {
 823                         can_scale = 0;
 824                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
 825                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
 826                 }
 827         } else {
 828                 can_scale = plane->can_scale;
 829                 max_scale = plane->max_downscale << 16;
 830                 min_scale = plane->can_scale ? 1 : (1 << 16);
 831         }
 832
 833         /*
 834          * FIXME the following code does a bunch of fuzzy adjustments to the
 835          * coordinates and sizes. We probably need some way to decide whether
 836          * more strict checking should be done instead.
 837          */
 838         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
 839                         state->base.rotation);
 840
 841         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
 842         BUG_ON(hscale < 0);
 843
 844         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
 845         BUG_ON(vscale < 0);
 846
 847         state->base.visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
 848
 849         crtc_x = dst->x1;
 850         crtc_y = dst->y1;
 851         crtc_w = drm_rect_width(dst);
 852         crtc_h = drm_rect_height(dst);
 853
 854         if (state->base.visible) {
 855                 /* check again in case clipping clamped the results */
 856                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
 857                 if (hscale < 0) {
 858                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
 859                         drm_rect_debug_print("src: ", src, true);
 860                         drm_rect_debug_print("dst: ", dst, false);
 861
 862                         return hscale;
 863                 }
 864
 865                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
 866                 if (vscale < 0) {
 867                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
 868                         drm_rect_debug_print("src: ", src, true);
 869                         drm_rect_debug_print("dst: ", dst, false);
 870
 871                         return vscale;
 872                 }
 873
 874                 /* Make the source viewport size an exact multiple of the scaling factors. */
 875                 drm_rect_adjust_size(src,
 876                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
 877                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
 878
 879                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
 880                                     state->base.rotation);
 881
 882                 /* sanity check to make sure the src viewport wasn't enlarged */
 883                 WARN_ON(src->x1 < (int) state->base.src_x ||
 884                         src->y1 < (int) state->base.src_y ||
 885                         src->x2 > (int) state->base.src_x + state->base.src_w ||
 886                         src->y2 > (int) state->base.src_y + state->base.src_h);
 887
 888                 /*
 889                  * Hardware doesn't handle subpixel coordinates.
 890                  * Adjust to (macro)pixel boundary, but be careful not to
 891                  * increase the source viewport size, because that could
 892                  * push the downscaling factor out of bounds.
 893                  */
 894                 src_x = src->x1 >> 16;
 895                 src_w = drm_rect_width(src) >> 16;
 896                 src_y = src->y1 >> 16;
 897                 src_h = drm_rect_height(src) >> 16;
 898
 899                 if (format_is_yuv(fb->format->format)) {
 900                         src_x &= ~1;
 901                         src_w &= ~1;
 902
 903                         /*
 904                          * Must keep src and dst the
 905                          * same if we can't scale.
 906                          */
 907                         if (!can_scale)
 908                                 crtc_w &= ~1;
 909
 910                         if (crtc_w == 0)
 911                                 state->base.visible = false;
 912                 }
 913         }
 914
 915         /* Check size restrictions when scaling */
 916         if (state->base.visible && (src_w != crtc_w || src_h != crtc_h)) {
 917                 unsigned int width_bytes;
 918                 int cpp = fb->format->cpp[0];
 919
 920                 WARN_ON(!can_scale);
 921
 922                 /* FIXME interlacing min height is 6 */
 923
 924                 if (crtc_w < 3 || crtc_h < 3)
 925                         state->base.visible = false;
 926
 927                 if (src_w < 3 || src_h < 3)
 928                         state->base.visible = false;
 929
 930                 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
 931
 932                 if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
 933                     width_bytes > 4096 || fb->pitches[0] > 4096)) {
 934                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
 935                         return -EINVAL;
 936                 }
 937         }
 938
 939         if (state->base.visible) {
 940                 src->x1 = src_x << 16;
 941                 src->x2 = (src_x + src_w) << 16;
 942                 src->y1 = src_y << 16;
 943                 src->y2 = (src_y + src_h) << 16;
 944         }
 945
 946         dst->x1 = crtc_x;
 947         dst->x2 = crtc_x + crtc_w;
 948         dst->y1 = crtc_y;
 949         dst->y2 = crtc_y + crtc_h;
 950
 951         if (INTEL_GEN(dev_priv) >= 9) {
 952                 ret = skl_check_plane_surface(state);
 953                 if (ret)
 954                         return ret;
 955
 956                 state->ctl = skl_plane_ctl(crtc_state, state);
 957         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 958                 ret = i9xx_check_plane_surface(state);
 959                 if (ret)
 960                         return ret;
 961
 962                 state->ctl = vlv_sprite_ctl(crtc_state, state);
 963         } else if (INTEL_GEN(dev_priv) >= 7) {
 964                 ret = i9xx_check_plane_surface(state);
 965                 if (ret)
 966                         return ret;
 967
 968                 state->ctl = ivb_sprite_ctl(crtc_state, state);
 969         } else {
 970                 ret = i9xx_check_plane_surface(state);
 971                 if (ret)
 972                         return ret;
 973
 974                 state->ctl = g4x_sprite_ctl(crtc_state, state);
 975         }
 976
 977         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 978                 state->color_ctl = glk_plane_color_ctl(crtc_state, state);
 979
 980         return 0;
 981 }
 982
 983 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 984                               struct drm_file *file_priv)
 985 {
 986         struct drm_i915_private *dev_priv = to_i915(dev);
 987         struct drm_intel_sprite_colorkey *set = data;
 988         struct drm_plane *plane;
 989         struct drm_plane_state *plane_state;
 990         struct drm_atomic_state *state;
 991         struct drm_modeset_acquire_ctx ctx;
 992         int ret = 0;
 993
 994         /* Make sure we don't try to enable both src & dest simultaneously */
 995         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 996                 return -EINVAL;
 997
 998         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 999             set->flags & I915_SET_COLORKEY_DESTINATION)
1000                 return -EINVAL;
1001
1002         plane = drm_plane_find(dev, file_priv, set->plane_id);
1003         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
1004                 return -ENOENT;
1005
1006         drm_modeset_acquire_init(&ctx, 0);
1007
1008         state = drm_atomic_state_alloc(plane->dev);
1009         if (!state) {
1010                 ret = -ENOMEM;
1011                 goto out;
1012         }
1013         state->acquire_ctx = &ctx;
1014
1015         while (1) {
1016                 plane_state = drm_atomic_get_plane_state(state, plane);
1017                 ret = PTR_ERR_OR_ZERO(plane_state);
1018                 if (!ret) {
1019                         to_intel_plane_state(plane_state)->ckey = *set;
1020                         ret = drm_atomic_commit(state);
1021                 }
1022
1023                 if (ret != -EDEADLK)
1024                         break;
1025
1026                 drm_atomic_state_clear(state);
1027                 drm_modeset_backoff(&ctx);
1028         }
1029
1030         drm_atomic_state_put(state);
1031 out:
1032         drm_modeset_drop_locks(&ctx);
1033         drm_modeset_acquire_fini(&ctx);
1034         return ret;
1035 }
1036
1037 static const uint32_t g4x_plane_formats[] = {
1038         DRM_FORMAT_XRGB8888,
1039         DRM_FORMAT_YUYV,
1040         DRM_FORMAT_YVYU,
1041         DRM_FORMAT_UYVY,
1042         DRM_FORMAT_VYUY,
1043 };
1044
1045 static const uint64_t i9xx_plane_format_modifiers[] = {
1046         I915_FORMAT_MOD_X_TILED,
1047         DRM_FORMAT_MOD_LINEAR,
1048         DRM_FORMAT_MOD_INVALID
1049 };
1050
1051 static const uint32_t snb_plane_formats[] = {
1052         DRM_FORMAT_XBGR8888,
1053         DRM_FORMAT_XRGB8888,
1054         DRM_FORMAT_YUYV,
1055         DRM_FORMAT_YVYU,
1056         DRM_FORMAT_UYVY,
1057         DRM_FORMAT_VYUY,
1058 };
1059
1060 static const uint32_t vlv_plane_formats[] = {
1061         DRM_FORMAT_RGB565,
1062         DRM_FORMAT_ABGR8888,
1063         DRM_FORMAT_ARGB8888,
1064         DRM_FORMAT_XBGR8888,
1065         DRM_FORMAT_XRGB8888,
1066         DRM_FORMAT_XBGR2101010,
1067         DRM_FORMAT_ABGR2101010,
1068         DRM_FORMAT_YUYV,
1069         DRM_FORMAT_YVYU,
1070         DRM_FORMAT_UYVY,
1071         DRM_FORMAT_VYUY,
1072 };
1073
1074 static uint32_t skl_plane_formats[] = {
1075         DRM_FORMAT_RGB565,
1076         DRM_FORMAT_ABGR8888,
1077         DRM_FORMAT_ARGB8888,
1078         DRM_FORMAT_XBGR8888,
1079         DRM_FORMAT_XRGB8888,
1080         DRM_FORMAT_YUYV,
1081         DRM_FORMAT_YVYU,
1082         DRM_FORMAT_UYVY,
1083         DRM_FORMAT_VYUY,
1084 };
1085
1086 static const uint64_t skl_plane_format_modifiers[] = {
1087         I915_FORMAT_MOD_X_TILED,
1088         DRM_FORMAT_MOD_LINEAR,
1089         DRM_FORMAT_MOD_INVALID
1090 };
1091
1092 static bool g4x_sprite_plane_format_mod_supported(struct drm_plane *plane,
1093                                                   uint32_t format,
1094                                                   uint64_t modifier)
1095 {
1096         switch (format) {
1097         case DRM_FORMAT_XBGR8888:
1098         case DRM_FORMAT_XRGB8888:
1099         case DRM_FORMAT_YUYV:
1100         case DRM_FORMAT_YVYU:
1101         case DRM_FORMAT_UYVY:
1102         case DRM_FORMAT_VYUY:
1103                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1104                     modifier == I915_FORMAT_MOD_X_TILED)
1105                         return true;
1106                 /* fall through */
1107         default:
1108                 return false;
1109         }
1110 }
1111
1112 static bool vlv_sprite_plane_format_mod_supported(struct drm_plane *plane,
1113                                                   uint32_t format,
1114                                                   uint64_t modifier)
1115 {
1116         switch (format) {
1117         case DRM_FORMAT_YUYV:
1118         case DRM_FORMAT_YVYU:
1119         case DRM_FORMAT_UYVY:
1120         case DRM_FORMAT_VYUY:
1121         case DRM_FORMAT_RGB565:
1122         case DRM_FORMAT_XRGB8888:
1123         case DRM_FORMAT_ARGB8888:
1124         case DRM_FORMAT_XBGR2101010:
1125         case DRM_FORMAT_ABGR2101010:
1126         case DRM_FORMAT_XBGR8888:
1127         case DRM_FORMAT_ABGR8888:
1128                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1129                     modifier == I915_FORMAT_MOD_X_TILED)
1130                         return true;
1131                 /* fall through */
1132         default:
1133                 return false;
1134         }
1135 }
1136
1137 static bool skl_sprite_plane_format_mod_supported(struct drm_plane *plane,
1138                                                   uint32_t format,
1139                                                   uint64_t modifier)
1140 {
1141         /* This is the same as primary plane since SKL has universal planes */
1142         switch (format) {
1143         case DRM_FORMAT_XRGB8888:
1144         case DRM_FORMAT_XBGR8888:
1145         case DRM_FORMAT_ARGB8888:
1146         case DRM_FORMAT_ABGR8888:
1147         case DRM_FORMAT_RGB565:
1148         case DRM_FORMAT_XRGB2101010:
1149         case DRM_FORMAT_XBGR2101010:
1150         case DRM_FORMAT_YUYV:
1151         case DRM_FORMAT_YVYU:
1152         case DRM_FORMAT_UYVY:
1153         case DRM_FORMAT_VYUY:
1154                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
1155                         return true;
1156                 /* fall through */
1157         case DRM_FORMAT_C8:
1158                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1159                     modifier == I915_FORMAT_MOD_X_TILED ||
1160                     modifier == I915_FORMAT_MOD_Y_TILED)
1161                         return true;
1162                 /* fall through */
1163         default:
1164                 return false;
1165         }
1166 }
1167
1168 static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane,
1169                                                     uint32_t format,
1170                                                     uint64_t modifier)
1171 {
1172         struct drm_i915_private *dev_priv = to_i915(plane->dev);
1173
1174         if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
1175                 return false;
1176
1177         if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
1178             modifier != DRM_FORMAT_MOD_LINEAR)
1179                 return false;
1180
1181         if (INTEL_GEN(dev_priv) >= 9)
1182                 return skl_sprite_plane_format_mod_supported(plane, format, modifier);
1183         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1184                 return vlv_sprite_plane_format_mod_supported(plane, format, modifier);
1185         else
1186                 return g4x_sprite_plane_format_mod_supported(plane, format, modifier);
1187
1188         unreachable();
1189 }
1190
1191 static const struct drm_plane_funcs intel_sprite_plane_funcs = {
1192         .update_plane = drm_atomic_helper_update_plane,
1193         .disable_plane = drm_atomic_helper_disable_plane,
1194         .destroy = intel_plane_destroy,
1195         .atomic_get_property = intel_plane_atomic_get_property,
1196         .atomic_set_property = intel_plane_atomic_set_property,
1197         .atomic_duplicate_state = intel_plane_duplicate_state,
1198         .atomic_destroy_state = intel_plane_destroy_state,
1199         .format_mod_supported = intel_sprite_plane_format_mod_supported,
1200 };
1201
1202 struct intel_plane *
1203 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1204                           enum pipe pipe, int plane)
1205 {
1206         struct intel_plane *intel_plane = NULL;
1207         struct intel_plane_state *state = NULL;
1208         unsigned long possible_crtcs;
1209         const uint32_t *plane_formats;
1210         const uint64_t *modifiers;
1211         unsigned int supported_rotations;
1212         int num_plane_formats;
1213         int ret;
1214
1215         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1216         if (!intel_plane) {
1217                 ret = -ENOMEM;
1218                 goto fail;
1219         }
1220
1221         state = intel_create_plane_state(&intel_plane->base);
1222         if (!state) {
1223                 ret = -ENOMEM;
1224                 goto fail;
1225         }
1226         intel_plane->base.state = &state->base;
1227
1228         if (INTEL_GEN(dev_priv) >= 10) {
1229                 intel_plane->can_scale = true;
1230                 state->scaler_id = -1;
1231
1232                 intel_plane->update_plane = skl_update_plane;
1233                 intel_plane->disable_plane = skl_disable_plane;
1234
1235                 plane_formats = skl_plane_formats;
1236                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1237                 modifiers = skl_plane_format_modifiers;
1238         } else if (INTEL_GEN(dev_priv) >= 9) {
1239                 intel_plane->can_scale = true;
1240                 state->scaler_id = -1;
1241
1242                 intel_plane->update_plane = skl_update_plane;
1243                 intel_plane->disable_plane = skl_disable_plane;
1244
1245                 plane_formats = skl_plane_formats;
1246                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1247                 modifiers = skl_plane_format_modifiers;
1248         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1249                 intel_plane->can_scale = false;
1250                 intel_plane->max_downscale = 1;
1251
1252                 intel_plane->update_plane = vlv_update_plane;
1253                 intel_plane->disable_plane = vlv_disable_plane;
1254
1255                 plane_formats = vlv_plane_formats;
1256                 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1257                 modifiers = i9xx_plane_format_modifiers;
1258         } else if (INTEL_GEN(dev_priv) >= 7) {
1259                 if (IS_IVYBRIDGE(dev_priv)) {
1260                         intel_plane->can_scale = true;
1261                         intel_plane->max_downscale = 2;
1262                 } else {
1263                         intel_plane->can_scale = false;
1264                         intel_plane->max_downscale = 1;
1265                 }
1266
1267                 intel_plane->update_plane = ivb_update_plane;
1268                 intel_plane->disable_plane = ivb_disable_plane;
1269
1270                 plane_formats = snb_plane_formats;
1271                 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1272                 modifiers = i9xx_plane_format_modifiers;
1273         } else {
1274                 intel_plane->can_scale = true;
1275                 intel_plane->max_downscale = 16;
1276
1277                 intel_plane->update_plane = g4x_update_plane;
1278                 intel_plane->disable_plane = g4x_disable_plane;
1279
1280                 modifiers = i9xx_plane_format_modifiers;
1281                 if (IS_GEN6(dev_priv)) {
1282                         plane_formats = snb_plane_formats;
1283                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1284                 } else {
1285                         plane_formats = g4x_plane_formats;
1286                         num_plane_formats = ARRAY_SIZE(g4x_plane_formats);
1287                 }
1288         }
1289
1290         if (INTEL_GEN(dev_priv) >= 9) {
1291                 supported_rotations =
1292                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
1293                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
1294         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1295                 supported_rotations =
1296                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
1297                         DRM_MODE_REFLECT_X;
1298         } else {
1299                 supported_rotations =
1300                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
1301         }
1302
1303         intel_plane->pipe = pipe;
1304         intel_plane->plane = plane;
1305         intel_plane->id = PLANE_SPRITE0 + plane;
1306         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
1307         intel_plane->check_plane = intel_check_sprite_plane;
1308
1309         possible_crtcs = (1 << pipe);
1310
1311         if (INTEL_GEN(dev_priv) >= 9)
1312                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1313                                                possible_crtcs, &intel_sprite_plane_funcs,
1314                                                plane_formats, num_plane_formats,
1315                                                modifiers,
1316                                                DRM_PLANE_TYPE_OVERLAY,
1317                                                "plane %d%c", plane + 2, pipe_name(pipe));
1318         else
1319                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1320                                                possible_crtcs, &intel_sprite_plane_funcs,
1321                                                plane_formats, num_plane_formats,
1322                                                modifiers,
1323                                                DRM_PLANE_TYPE_OVERLAY,
1324                                                "sprite %c", sprite_name(pipe, plane));
1325         if (ret)
1326                 goto fail;
1327
1328         drm_plane_create_rotation_property(&intel_plane->base,
1329                                            DRM_MODE_ROTATE_0,
1330                                            supported_rotations);
1331
1332         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1333
1334         return intel_plane;
1335
1336 fail:
1337         kfree(state);
1338         kfree(intel_plane);
1339
1340         return ERR_PTR(ret);
1341 }