drm/i915/icl: Fix power well 2 wrt. DC-off toggling order
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / intel_runtime_pm.c
1 /*
2  * Copyright © 2012-2014 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
25  *    Daniel Vetter <daniel.vetter@ffwll.ch>
26  *
27  */
28
29 #include <linux/pm_runtime.h>
30 #include <linux/vgaarb.h>
31
32 #include "i915_drv.h"
33 #include "intel_drv.h"
34
35 /**
36  * DOC: runtime pm
37  *
38  * The i915 driver supports dynamic enabling and disabling of entire hardware
39  * blocks at runtime. This is especially important on the display side where
40  * software is supposed to control many power gates manually on recent hardware,
41  * since on the GT side a lot of the power management is done by the hardware.
42  * But even there some manual control at the device level is required.
43  *
44  * Since i915 supports a diverse set of platforms with a unified codebase and
45  * hardware engineers just love to shuffle functionality around between power
46  * domains there's a sizeable amount of indirection required. This file provides
47  * generic functions to the driver for grabbing and releasing references for
48  * abstract power domains. It then maps those to the actual power wells
49  * present for a given platform.
50  */
51
52 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
53                                          enum i915_power_well_id power_well_id);
54
55 const char *
56 intel_display_power_domain_str(enum intel_display_power_domain domain)
57 {
58         switch (domain) {
59         case POWER_DOMAIN_PIPE_A:
60                 return "PIPE_A";
61         case POWER_DOMAIN_PIPE_B:
62                 return "PIPE_B";
63         case POWER_DOMAIN_PIPE_C:
64                 return "PIPE_C";
65         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
66                 return "PIPE_A_PANEL_FITTER";
67         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
68                 return "PIPE_B_PANEL_FITTER";
69         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
70                 return "PIPE_C_PANEL_FITTER";
71         case POWER_DOMAIN_TRANSCODER_A:
72                 return "TRANSCODER_A";
73         case POWER_DOMAIN_TRANSCODER_B:
74                 return "TRANSCODER_B";
75         case POWER_DOMAIN_TRANSCODER_C:
76                 return "TRANSCODER_C";
77         case POWER_DOMAIN_TRANSCODER_EDP:
78                 return "TRANSCODER_EDP";
79         case POWER_DOMAIN_TRANSCODER_DSI_A:
80                 return "TRANSCODER_DSI_A";
81         case POWER_DOMAIN_TRANSCODER_DSI_C:
82                 return "TRANSCODER_DSI_C";
83         case POWER_DOMAIN_PORT_DDI_A_LANES:
84                 return "PORT_DDI_A_LANES";
85         case POWER_DOMAIN_PORT_DDI_B_LANES:
86                 return "PORT_DDI_B_LANES";
87         case POWER_DOMAIN_PORT_DDI_C_LANES:
88                 return "PORT_DDI_C_LANES";
89         case POWER_DOMAIN_PORT_DDI_D_LANES:
90                 return "PORT_DDI_D_LANES";
91         case POWER_DOMAIN_PORT_DDI_E_LANES:
92                 return "PORT_DDI_E_LANES";
93         case POWER_DOMAIN_PORT_DDI_F_LANES:
94                 return "PORT_DDI_F_LANES";
95         case POWER_DOMAIN_PORT_DDI_A_IO:
96                 return "PORT_DDI_A_IO";
97         case POWER_DOMAIN_PORT_DDI_B_IO:
98                 return "PORT_DDI_B_IO";
99         case POWER_DOMAIN_PORT_DDI_C_IO:
100                 return "PORT_DDI_C_IO";
101         case POWER_DOMAIN_PORT_DDI_D_IO:
102                 return "PORT_DDI_D_IO";
103         case POWER_DOMAIN_PORT_DDI_E_IO:
104                 return "PORT_DDI_E_IO";
105         case POWER_DOMAIN_PORT_DDI_F_IO:
106                 return "PORT_DDI_F_IO";
107         case POWER_DOMAIN_PORT_DSI:
108                 return "PORT_DSI";
109         case POWER_DOMAIN_PORT_CRT:
110                 return "PORT_CRT";
111         case POWER_DOMAIN_PORT_OTHER:
112                 return "PORT_OTHER";
113         case POWER_DOMAIN_VGA:
114                 return "VGA";
115         case POWER_DOMAIN_AUDIO:
116                 return "AUDIO";
117         case POWER_DOMAIN_PLLS:
118                 return "PLLS";
119         case POWER_DOMAIN_AUX_A:
120                 return "AUX_A";
121         case POWER_DOMAIN_AUX_B:
122                 return "AUX_B";
123         case POWER_DOMAIN_AUX_C:
124                 return "AUX_C";
125         case POWER_DOMAIN_AUX_D:
126                 return "AUX_D";
127         case POWER_DOMAIN_AUX_E:
128                 return "AUX_E";
129         case POWER_DOMAIN_AUX_F:
130                 return "AUX_F";
131         case POWER_DOMAIN_AUX_IO_A:
132                 return "AUX_IO_A";
133         case POWER_DOMAIN_AUX_TBT1:
134                 return "AUX_TBT1";
135         case POWER_DOMAIN_AUX_TBT2:
136                 return "AUX_TBT2";
137         case POWER_DOMAIN_AUX_TBT3:
138                 return "AUX_TBT3";
139         case POWER_DOMAIN_AUX_TBT4:
140                 return "AUX_TBT4";
141         case POWER_DOMAIN_GMBUS:
142                 return "GMBUS";
143         case POWER_DOMAIN_INIT:
144                 return "INIT";
145         case POWER_DOMAIN_MODESET:
146                 return "MODESET";
147         case POWER_DOMAIN_GT_IRQ:
148                 return "GT_IRQ";
149         default:
150                 MISSING_CASE(domain);
151                 return "?";
152         }
153 }
154
155 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
156                                     struct i915_power_well *power_well)
157 {
158         DRM_DEBUG_KMS("enabling %s\n", power_well->desc->name);
159         power_well->desc->ops->enable(dev_priv, power_well);
160         power_well->hw_enabled = true;
161 }
162
163 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
164                                      struct i915_power_well *power_well)
165 {
166         DRM_DEBUG_KMS("disabling %s\n", power_well->desc->name);
167         power_well->hw_enabled = false;
168         power_well->desc->ops->disable(dev_priv, power_well);
169 }
170
171 static void intel_power_well_get(struct drm_i915_private *dev_priv,
172                                  struct i915_power_well *power_well)
173 {
174         if (!power_well->count++)
175                 intel_power_well_enable(dev_priv, power_well);
176 }
177
178 static void intel_power_well_put(struct drm_i915_private *dev_priv,
179                                  struct i915_power_well *power_well)
180 {
181         WARN(!power_well->count, "Use count on power well %s is already zero",
182              power_well->desc->name);
183
184         if (!--power_well->count)
185                 intel_power_well_disable(dev_priv, power_well);
186 }
187
188 /**
189  * __intel_display_power_is_enabled - unlocked check for a power domain
190  * @dev_priv: i915 device instance
191  * @domain: power domain to check
192  *
193  * This is the unlocked version of intel_display_power_is_enabled() and should
194  * only be used from error capture and recovery code where deadlocks are
195  * possible.
196  *
197  * Returns:
198  * True when the power domain is enabled, false otherwise.
199  */
200 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
201                                       enum intel_display_power_domain domain)
202 {
203         struct i915_power_well *power_well;
204         bool is_enabled;
205
206         if (dev_priv->runtime_pm.suspended)
207                 return false;
208
209         is_enabled = true;
210
211         for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) {
212                 if (power_well->desc->always_on)
213                         continue;
214
215                 if (!power_well->hw_enabled) {
216                         is_enabled = false;
217                         break;
218                 }
219         }
220
221         return is_enabled;
222 }
223
224 /**
225  * intel_display_power_is_enabled - check for a power domain
226  * @dev_priv: i915 device instance
227  * @domain: power domain to check
228  *
229  * This function can be used to check the hw power domain state. It is mostly
230  * used in hardware state readout functions. Everywhere else code should rely
231  * upon explicit power domain reference counting to ensure that the hardware
232  * block is powered up before accessing it.
233  *
234  * Callers must hold the relevant modesetting locks to ensure that concurrent
235  * threads can't disable the power well while the caller tries to read a few
236  * registers.
237  *
238  * Returns:
239  * True when the power domain is enabled, false otherwise.
240  */
241 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
242                                     enum intel_display_power_domain domain)
243 {
244         struct i915_power_domains *power_domains;
245         bool ret;
246
247         power_domains = &dev_priv->power_domains;
248
249         mutex_lock(&power_domains->lock);
250         ret = __intel_display_power_is_enabled(dev_priv, domain);
251         mutex_unlock(&power_domains->lock);
252
253         return ret;
254 }
255
256 /*
257  * Starting with Haswell, we have a "Power Down Well" that can be turned off
258  * when not needed anymore. We have 4 registers that can request the power well
259  * to be enabled, and it will only be disabled if none of the registers is
260  * requesting it to be enabled.
261  */
262 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
263                                        u8 irq_pipe_mask, bool has_vga)
264 {
265         struct pci_dev *pdev = dev_priv->drm.pdev;
266
267         /*
268          * After we re-enable the power well, if we touch VGA register 0x3d5
269          * we'll get unclaimed register interrupts. This stops after we write
270          * anything to the VGA MSR register. The vgacon module uses this
271          * register all the time, so if we unbind our driver and, as a
272          * consequence, bind vgacon, we'll get stuck in an infinite loop at
273          * console_unlock(). So make here we touch the VGA MSR register, making
274          * sure vgacon can keep working normally without triggering interrupts
275          * and error messages.
276          */
277         if (has_vga) {
278                 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
279                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
280                 vga_put(pdev, VGA_RSRC_LEGACY_IO);
281         }
282
283         if (irq_pipe_mask)
284                 gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
285 }
286
287 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
288                                        u8 irq_pipe_mask)
289 {
290         if (irq_pipe_mask)
291                 gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
292 }
293
294
295 static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
296                                            struct i915_power_well *power_well)
297 {
298         const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
299         int pw_idx = power_well->desc->hsw.idx;
300
301         /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
302         WARN_ON(intel_wait_for_register(dev_priv,
303                                         regs->driver,
304                                         HSW_PWR_WELL_CTL_STATE(pw_idx),
305                                         HSW_PWR_WELL_CTL_STATE(pw_idx),
306                                         1));
307 }
308
309 static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,
310                                      const struct i915_power_well_regs *regs,
311                                      int pw_idx)
312 {
313         u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
314         u32 ret;
315
316         ret = I915_READ(regs->bios) & req_mask ? 1 : 0;
317         ret |= I915_READ(regs->driver) & req_mask ? 2 : 0;
318         if (regs->kvmr.reg)
319                 ret |= I915_READ(regs->kvmr) & req_mask ? 4 : 0;
320         ret |= I915_READ(regs->debug) & req_mask ? 8 : 0;
321
322         return ret;
323 }
324
325 static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
326                                             struct i915_power_well *power_well)
327 {
328         const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
329         int pw_idx = power_well->desc->hsw.idx;
330         bool disabled;
331         u32 reqs;
332
333         /*
334          * Bspec doesn't require waiting for PWs to get disabled, but still do
335          * this for paranoia. The known cases where a PW will be forced on:
336          * - a KVMR request on any power well via the KVMR request register
337          * - a DMC request on PW1 and MISC_IO power wells via the BIOS and
338          *   DEBUG request registers
339          * Skip the wait in case any of the request bits are set and print a
340          * diagnostic message.
341          */
342         wait_for((disabled = !(I915_READ(regs->driver) &
343                                HSW_PWR_WELL_CTL_STATE(pw_idx))) ||
344                  (reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1);
345         if (disabled)
346                 return;
347
348         DRM_DEBUG_KMS("%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n",
349                       power_well->desc->name,
350                       !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
351 }
352
353 static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
354                                            enum skl_power_gate pg)
355 {
356         /* Timeout 5us for PG#0, for other PGs 1us */
357         WARN_ON(intel_wait_for_register(dev_priv, SKL_FUSE_STATUS,
358                                         SKL_FUSE_PG_DIST_STATUS(pg),
359                                         SKL_FUSE_PG_DIST_STATUS(pg), 1));
360 }
361
362 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
363                                   struct i915_power_well *power_well)
364 {
365         const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
366         int pw_idx = power_well->desc->hsw.idx;
367         bool wait_fuses = power_well->desc->hsw.has_fuses;
368         enum skl_power_gate uninitialized_var(pg);
369         u32 val;
370
371         if (wait_fuses) {
372                 pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
373                                                  SKL_PW_CTL_IDX_TO_PG(pw_idx);
374                 /*
375                  * For PW1 we have to wait both for the PW0/PG0 fuse state
376                  * before enabling the power well and PW1/PG1's own fuse
377                  * state after the enabling. For all other power wells with
378                  * fuses we only have to wait for that PW/PG's fuse state
379                  * after the enabling.
380                  */
381                 if (pg == SKL_PG1)
382                         gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0);
383         }
384
385         val = I915_READ(regs->driver);
386         I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
387         hsw_wait_for_power_well_enable(dev_priv, power_well);
388
389         /* Display WA #1178: cnl */
390         if (IS_CANNONLAKE(dev_priv) &&
391             pw_idx >= GLK_PW_CTL_IDX_AUX_B &&
392             pw_idx <= CNL_PW_CTL_IDX_AUX_F) {
393                 val = I915_READ(CNL_AUX_ANAOVRD1(pw_idx));
394                 val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
395                 I915_WRITE(CNL_AUX_ANAOVRD1(pw_idx), val);
396         }
397
398         if (wait_fuses)
399                 gen9_wait_for_power_well_fuses(dev_priv, pg);
400
401         hsw_power_well_post_enable(dev_priv,
402                                    power_well->desc->hsw.irq_pipe_mask,
403                                    power_well->desc->hsw.has_vga);
404 }
405
406 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
407                                    struct i915_power_well *power_well)
408 {
409         const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
410         int pw_idx = power_well->desc->hsw.idx;
411         u32 val;
412
413         hsw_power_well_pre_disable(dev_priv,
414                                    power_well->desc->hsw.irq_pipe_mask);
415
416         val = I915_READ(regs->driver);
417         I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
418         hsw_wait_for_power_well_disable(dev_priv, power_well);
419 }
420
421 #define ICL_AUX_PW_TO_PORT(pw_idx)      ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
422
423 static void
424 icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
425                                     struct i915_power_well *power_well)
426 {
427         const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
428         int pw_idx = power_well->desc->hsw.idx;
429         enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
430         u32 val;
431
432         val = I915_READ(regs->driver);
433         I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
434
435         val = I915_READ(ICL_PORT_CL_DW12(port));
436         I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
437
438         hsw_wait_for_power_well_enable(dev_priv, power_well);
439 }
440
441 static void
442 icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
443                                      struct i915_power_well *power_well)
444 {
445         const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
446         int pw_idx = power_well->desc->hsw.idx;
447         enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
448         u32 val;
449
450         val = I915_READ(ICL_PORT_CL_DW12(port));
451         I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);
452
453         val = I915_READ(regs->driver);
454         I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
455
456         hsw_wait_for_power_well_disable(dev_priv, power_well);
457 }
458
459 /*
460  * We should only use the power well if we explicitly asked the hardware to
461  * enable it, so check if it's enabled and also check if we've requested it to
462  * be enabled.
463  */
464 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
465                                    struct i915_power_well *power_well)
466 {
467         const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
468         int pw_idx = power_well->desc->hsw.idx;
469         u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |
470                    HSW_PWR_WELL_CTL_STATE(pw_idx);
471
472         return (I915_READ(regs->driver) & mask) == mask;
473 }
474
475 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
476 {
477         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
478                   "DC9 already programmed to be enabled.\n");
479         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
480                   "DC5 still not disabled to enable DC9.\n");
481         WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL2) &
482                   HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2),
483                   "Power well 2 on.\n");
484         WARN_ONCE(intel_irqs_enabled(dev_priv),
485                   "Interrupts not disabled yet.\n");
486
487          /*
488           * TODO: check for the following to verify the conditions to enter DC9
489           * state are satisfied:
490           * 1] Check relevant display engine registers to verify if mode set
491           * disable sequence was followed.
492           * 2] Check if display uninitialize sequence is initialized.
493           */
494 }
495
496 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
497 {
498         WARN_ONCE(intel_irqs_enabled(dev_priv),
499                   "Interrupts not disabled yet.\n");
500         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
501                   "DC5 still not disabled.\n");
502
503          /*
504           * TODO: check for the following to verify DC9 state was indeed
505           * entered before programming to disable it:
506           * 1] Check relevant display engine registers to verify if mode
507           *  set disable sequence was followed.
508           * 2] Check if display uninitialize sequence is initialized.
509           */
510 }
511
512 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
513                                 u32 state)
514 {
515         int rewrites = 0;
516         int rereads = 0;
517         u32 v;
518
519         I915_WRITE(DC_STATE_EN, state);
520
521         /* It has been observed that disabling the dc6 state sometimes
522          * doesn't stick and dmc keeps returning old value. Make sure
523          * the write really sticks enough times and also force rewrite until
524          * we are confident that state is exactly what we want.
525          */
526         do  {
527                 v = I915_READ(DC_STATE_EN);
528
529                 if (v != state) {
530                         I915_WRITE(DC_STATE_EN, state);
531                         rewrites++;
532                         rereads = 0;
533                 } else if (rereads++ > 5) {
534                         break;
535                 }
536
537         } while (rewrites < 100);
538
539         if (v != state)
540                 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
541                           state, v);
542
543         /* Most of the times we need one retry, avoid spam */
544         if (rewrites > 1)
545                 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
546                               state, rewrites);
547 }
548
549 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
550 {
551         u32 mask;
552
553         mask = DC_STATE_EN_UPTO_DC5;
554         if (IS_GEN9_LP(dev_priv))
555                 mask |= DC_STATE_EN_DC9;
556         else
557                 mask |= DC_STATE_EN_UPTO_DC6;
558
559         return mask;
560 }
561
562 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
563 {
564         u32 val;
565
566         val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);
567
568         DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n",
569                       dev_priv->csr.dc_state, val);
570         dev_priv->csr.dc_state = val;
571 }
572
573 /**
574  * gen9_set_dc_state - set target display C power state
575  * @dev_priv: i915 device instance
576  * @state: target DC power state
577  * - DC_STATE_DISABLE
578  * - DC_STATE_EN_UPTO_DC5
579  * - DC_STATE_EN_UPTO_DC6
580  * - DC_STATE_EN_DC9
581  *
582  * Signal to DMC firmware/HW the target DC power state passed in @state.
583  * DMC/HW can turn off individual display clocks and power rails when entering
584  * a deeper DC power state (higher in number) and turns these back when exiting
585  * that state to a shallower power state (lower in number). The HW will decide
586  * when to actually enter a given state on an on-demand basis, for instance
587  * depending on the active state of display pipes. The state of display
588  * registers backed by affected power rails are saved/restored as needed.
589  *
590  * Based on the above enabling a deeper DC power state is asynchronous wrt.
591  * enabling it. Disabling a deeper power state is synchronous: for instance
592  * setting %DC_STATE_DISABLE won't complete until all HW resources are turned
593  * back on and register state is restored. This is guaranteed by the MMIO write
594  * to DC_STATE_EN blocking until the state is restored.
595  */
596 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
597 {
598         uint32_t val;
599         uint32_t mask;
600
601         if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
602                 state &= dev_priv->csr.allowed_dc_mask;
603
604         val = I915_READ(DC_STATE_EN);
605         mask = gen9_dc_mask(dev_priv);
606         DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
607                       val & mask, state);
608
609         /* Check if DMC is ignoring our DC state requests */
610         if ((val & mask) != dev_priv->csr.dc_state)
611                 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
612                           dev_priv->csr.dc_state, val & mask);
613
614         val &= ~mask;
615         val |= state;
616
617         gen9_write_dc_state(dev_priv, val);
618
619         dev_priv->csr.dc_state = val & mask;
620 }
621
622 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
623 {
624         assert_can_enable_dc9(dev_priv);
625
626         DRM_DEBUG_KMS("Enabling DC9\n");
627
628         intel_power_sequencer_reset(dev_priv);
629         gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
630 }
631
632 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
633 {
634         assert_can_disable_dc9(dev_priv);
635
636         DRM_DEBUG_KMS("Disabling DC9\n");
637
638         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
639
640         intel_pps_unlock_regs_wa(dev_priv);
641 }
642
643 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
644 {
645         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
646                   "CSR program storage start is NULL\n");
647         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
648         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
649 }
650
651 static struct i915_power_well *
652 lookup_power_well(struct drm_i915_private *dev_priv,
653                   enum i915_power_well_id power_well_id)
654 {
655         struct i915_power_well *power_well;
656
657         for_each_power_well(dev_priv, power_well)
658                 if (power_well->desc->id == power_well_id)
659                         return power_well;
660
661         /*
662          * It's not feasible to add error checking code to the callers since
663          * this condition really shouldn't happen and it doesn't even make sense
664          * to abort things like display initialization sequences. Just return
665          * the first power well and hope the WARN gets reported so we can fix
666          * our driver.
667          */
668         WARN(1, "Power well %d not defined for this platform\n", power_well_id);
669         return &dev_priv->power_domains.power_wells[0];
670 }
671
672 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
673 {
674         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
675                                         SKL_DISP_PW_2);
676
677         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
678
679         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
680                   "DC5 already programmed to be enabled.\n");
681         assert_rpm_wakelock_held(dev_priv);
682
683         assert_csr_loaded(dev_priv);
684 }
685
686 void gen9_enable_dc5(struct drm_i915_private *dev_priv)
687 {
688         assert_can_enable_dc5(dev_priv);
689
690         DRM_DEBUG_KMS("Enabling DC5\n");
691
692         /* Wa Display #1183: skl,kbl,cfl */
693         if (IS_GEN9_BC(dev_priv))
694                 I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
695                            SKL_SELECT_ALTERNATE_DC_EXIT);
696
697         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
698 }
699
700 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
701 {
702         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
703                   "Backlight is not disabled.\n");
704         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
705                   "DC6 already programmed to be enabled.\n");
706
707         assert_csr_loaded(dev_priv);
708 }
709
710 static void skl_enable_dc6(struct drm_i915_private *dev_priv)
711 {
712         assert_can_enable_dc6(dev_priv);
713
714         DRM_DEBUG_KMS("Enabling DC6\n");
715
716         /* Wa Display #1183: skl,kbl,cfl */
717         if (IS_GEN9_BC(dev_priv))
718                 I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
719                            SKL_SELECT_ALTERNATE_DC_EXIT);
720
721         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
722 }
723
724 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
725                                    struct i915_power_well *power_well)
726 {
727         const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
728         int pw_idx = power_well->desc->hsw.idx;
729         u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
730         u32 bios_req = I915_READ(regs->bios);
731
732         /* Take over the request bit if set by BIOS. */
733         if (bios_req & mask) {
734                 u32 drv_req = I915_READ(regs->driver);
735
736                 if (!(drv_req & mask))
737                         I915_WRITE(regs->driver, drv_req | mask);
738                 I915_WRITE(regs->bios, bios_req & ~mask);
739         }
740 }
741
742 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
743                                            struct i915_power_well *power_well)
744 {
745         bxt_ddi_phy_init(dev_priv, power_well->desc->bxt.phy);
746 }
747
748 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
749                                             struct i915_power_well *power_well)
750 {
751         bxt_ddi_phy_uninit(dev_priv, power_well->desc->bxt.phy);
752 }
753
754 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
755                                             struct i915_power_well *power_well)
756 {
757         return bxt_ddi_phy_is_enabled(dev_priv, power_well->desc->bxt.phy);
758 }
759
760 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
761 {
762         struct i915_power_well *power_well;
763
764         power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A);
765         if (power_well->count > 0)
766                 bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
767
768         power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
769         if (power_well->count > 0)
770                 bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
771
772         if (IS_GEMINILAKE(dev_priv)) {
773                 power_well = lookup_power_well(dev_priv,
774                                                GLK_DISP_PW_DPIO_CMN_C);
775                 if (power_well->count > 0)
776                         bxt_ddi_phy_verify_state(dev_priv,
777                                                  power_well->desc->bxt.phy);
778         }
779 }
780
781 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
782                                            struct i915_power_well *power_well)
783 {
784         return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
785 }
786
787 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
788 {
789         u32 tmp = I915_READ(DBUF_CTL);
790
791         WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
792              (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
793              "Unexpected DBuf power power state (0x%08x)\n", tmp);
794 }
795
796 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
797                                           struct i915_power_well *power_well)
798 {
799         struct intel_cdclk_state cdclk_state = {};
800
801         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
802
803         dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
804         /* Can't read out voltage_level so can't use intel_cdclk_changed() */
805         WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
806
807         gen9_assert_dbuf_enabled(dev_priv);
808
809         if (IS_GEN9_LP(dev_priv))
810                 bxt_verify_ddi_phy_power_wells(dev_priv);
811 }
812
813 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
814                                            struct i915_power_well *power_well)
815 {
816         if (!dev_priv->csr.dmc_payload)
817                 return;
818
819         if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
820                 skl_enable_dc6(dev_priv);
821         else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
822                 gen9_enable_dc5(dev_priv);
823 }
824
825 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
826                                          struct i915_power_well *power_well)
827 {
828 }
829
830 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
831                                            struct i915_power_well *power_well)
832 {
833 }
834
835 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
836                                              struct i915_power_well *power_well)
837 {
838         return true;
839 }
840
841 static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv,
842                                          struct i915_power_well *power_well)
843 {
844         if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0)
845                 i830_enable_pipe(dev_priv, PIPE_A);
846         if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0)
847                 i830_enable_pipe(dev_priv, PIPE_B);
848 }
849
850 static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv,
851                                           struct i915_power_well *power_well)
852 {
853         i830_disable_pipe(dev_priv, PIPE_B);
854         i830_disable_pipe(dev_priv, PIPE_A);
855 }
856
857 static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv,
858                                           struct i915_power_well *power_well)
859 {
860         return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE &&
861                 I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
862 }
863
864 static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
865                                           struct i915_power_well *power_well)
866 {
867         if (power_well->count > 0)
868                 i830_pipes_power_well_enable(dev_priv, power_well);
869         else
870                 i830_pipes_power_well_disable(dev_priv, power_well);
871 }
872
873 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
874                                struct i915_power_well *power_well, bool enable)
875 {
876         int pw_idx = power_well->desc->vlv.idx;
877         u32 mask;
878         u32 state;
879         u32 ctrl;
880
881         mask = PUNIT_PWRGT_MASK(pw_idx);
882         state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) :
883                          PUNIT_PWRGT_PWR_GATE(pw_idx);
884
885         mutex_lock(&dev_priv->pcu_lock);
886
887 #define COND \
888         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
889
890         if (COND)
891                 goto out;
892
893         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
894         ctrl &= ~mask;
895         ctrl |= state;
896         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
897
898         if (wait_for(COND, 100))
899                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
900                           state,
901                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
902
903 #undef COND
904
905 out:
906         mutex_unlock(&dev_priv->pcu_lock);
907 }
908
909 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
910                                   struct i915_power_well *power_well)
911 {
912         vlv_set_power_well(dev_priv, power_well, true);
913 }
914
915 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
916                                    struct i915_power_well *power_well)
917 {
918         vlv_set_power_well(dev_priv, power_well, false);
919 }
920
921 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
922                                    struct i915_power_well *power_well)
923 {
924         int pw_idx = power_well->desc->vlv.idx;
925         bool enabled = false;
926         u32 mask;
927         u32 state;
928         u32 ctrl;
929
930         mask = PUNIT_PWRGT_MASK(pw_idx);
931         ctrl = PUNIT_PWRGT_PWR_ON(pw_idx);
932
933         mutex_lock(&dev_priv->pcu_lock);
934
935         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
936         /*
937          * We only ever set the power-on and power-gate states, anything
938          * else is unexpected.
939          */
940         WARN_ON(state != PUNIT_PWRGT_PWR_ON(pw_idx) &&
941                 state != PUNIT_PWRGT_PWR_GATE(pw_idx));
942         if (state == ctrl)
943                 enabled = true;
944
945         /*
946          * A transient state at this point would mean some unexpected party
947          * is poking at the power controls too.
948          */
949         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
950         WARN_ON(ctrl != state);
951
952         mutex_unlock(&dev_priv->pcu_lock);
953
954         return enabled;
955 }
956
957 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
958 {
959         u32 val;
960
961         /*
962          * On driver load, a pipe may be active and driving a DSI display.
963          * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck
964          * (and never recovering) in this case. intel_dsi_post_disable() will
965          * clear it when we turn off the display.
966          */
967         val = I915_READ(DSPCLK_GATE_D);
968         val &= DPOUNIT_CLOCK_GATE_DISABLE;
969         val |= VRHUNIT_CLOCK_GATE_DISABLE;
970         I915_WRITE(DSPCLK_GATE_D, val);
971
972         /*
973          * Disable trickle feed and enable pnd deadline calculation
974          */
975         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
976         I915_WRITE(CBR1_VLV, 0);
977
978         WARN_ON(dev_priv->rawclk_freq == 0);
979
980         I915_WRITE(RAWCLK_FREQ_VLV,
981                    DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000));
982 }
983
984 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
985 {
986         struct intel_encoder *encoder;
987         enum pipe pipe;
988
989         /*
990          * Enable the CRI clock source so we can get at the
991          * display and the reference clock for VGA
992          * hotplug / manual detection. Supposedly DSI also
993          * needs the ref clock up and running.
994          *
995          * CHV DPLL B/C have some issues if VGA mode is enabled.
996          */
997         for_each_pipe(dev_priv, pipe) {
998                 u32 val = I915_READ(DPLL(pipe));
999
1000                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1001                 if (pipe != PIPE_A)
1002                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1003
1004                 I915_WRITE(DPLL(pipe), val);
1005         }
1006
1007         vlv_init_display_clock_gating(dev_priv);
1008
1009         spin_lock_irq(&dev_priv->irq_lock);
1010         valleyview_enable_display_irqs(dev_priv);
1011         spin_unlock_irq(&dev_priv->irq_lock);
1012
1013         /*
1014          * During driver initialization/resume we can avoid restoring the
1015          * part of the HW/SW state that will be inited anyway explicitly.
1016          */
1017         if (dev_priv->power_domains.initializing)
1018                 return;
1019
1020         intel_hpd_init(dev_priv);
1021
1022         /* Re-enable the ADPA, if we have one */
1023         for_each_intel_encoder(&dev_priv->drm, encoder) {
1024                 if (encoder->type == INTEL_OUTPUT_ANALOG)
1025                         intel_crt_reset(&encoder->base);
1026         }
1027
1028         i915_redisable_vga_power_on(dev_priv);
1029
1030         intel_pps_unlock_regs_wa(dev_priv);
1031 }
1032
1033 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
1034 {
1035         spin_lock_irq(&dev_priv->irq_lock);
1036         valleyview_disable_display_irqs(dev_priv);
1037         spin_unlock_irq(&dev_priv->irq_lock);
1038
1039         /* make sure we're done processing display irqs */
1040         synchronize_irq(dev_priv->drm.irq);
1041
1042         intel_power_sequencer_reset(dev_priv);
1043
1044         /* Prevent us from re-enabling polling on accident in late suspend */
1045         if (!dev_priv->drm.dev->power.is_suspended)
1046                 intel_hpd_poll_init(dev_priv);
1047 }
1048
1049 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
1050                                           struct i915_power_well *power_well)
1051 {
1052         vlv_set_power_well(dev_priv, power_well, true);
1053
1054         vlv_display_power_well_init(dev_priv);
1055 }
1056
1057 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
1058                                            struct i915_power_well *power_well)
1059 {
1060         vlv_display_power_well_deinit(dev_priv);
1061
1062         vlv_set_power_well(dev_priv, power_well, false);
1063 }
1064
1065 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1066                                            struct i915_power_well *power_well)
1067 {
1068         /* since ref/cri clock was enabled */
1069         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1070
1071         vlv_set_power_well(dev_priv, power_well, true);
1072
1073         /*
1074          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1075          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1076          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1077          *   b. The other bits such as sfr settings / modesel may all
1078          *      be set to 0.
1079          *
1080          * This should only be done on init and resume from S3 with
1081          * both PLLs disabled, or we risk losing DPIO and PLL
1082          * synchronization.
1083          */
1084         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1085 }
1086
1087 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1088                                             struct i915_power_well *power_well)
1089 {
1090         enum pipe pipe;
1091
1092         for_each_pipe(dev_priv, pipe)
1093                 assert_pll_disabled(dev_priv, pipe);
1094
1095         /* Assert common reset */
1096         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1097
1098         vlv_set_power_well(dev_priv, power_well, false);
1099 }
1100
1101 #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
1102
1103 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1104
1105 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1106 {
1107         struct i915_power_well *cmn_bc =
1108                 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
1109         struct i915_power_well *cmn_d =
1110                 lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
1111         u32 phy_control = dev_priv->chv_phy_control;
1112         u32 phy_status = 0;
1113         u32 phy_status_mask = 0xffffffff;
1114
1115         /*
1116          * The BIOS can leave the PHY is some weird state
1117          * where it doesn't fully power down some parts.
1118          * Disable the asserts until the PHY has been fully
1119          * reset (ie. the power well has been disabled at
1120          * least once).
1121          */
1122         if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1123                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1124                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1125                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1126                                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1127                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1128                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1129
1130         if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1131                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1132                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1133                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1134
1135         if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) {
1136                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1137
1138                 /* this assumes override is only used to enable lanes */
1139                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1140                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1141
1142                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1143                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1144
1145                 /* CL1 is on whenever anything is on in either channel */
1146                 if (BITS_SET(phy_control,
1147                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1148                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1149                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1150
1151                 /*
1152                  * The DPLLB check accounts for the pipe B + port A usage
1153                  * with CL2 powered up but all the lanes in the second channel
1154                  * powered down.
1155                  */
1156                 if (BITS_SET(phy_control,
1157                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1158                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1159                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1160
1161                 if (BITS_SET(phy_control,
1162                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1163                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1164                 if (BITS_SET(phy_control,
1165                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1166                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1167
1168                 if (BITS_SET(phy_control,
1169                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1170                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1171                 if (BITS_SET(phy_control,
1172                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1173                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1174         }
1175
1176         if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) {
1177                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1178
1179                 /* this assumes override is only used to enable lanes */
1180                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1181                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1182
1183                 if (BITS_SET(phy_control,
1184                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1185                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1186
1187                 if (BITS_SET(phy_control,
1188                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1189                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1190                 if (BITS_SET(phy_control,
1191                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1192                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1193         }
1194
1195         phy_status &= phy_status_mask;
1196
1197         /*
1198          * The PHY may be busy with some initial calibration and whatnot,
1199          * so the power state can take a while to actually change.
1200          */
1201         if (intel_wait_for_register(dev_priv,
1202                                     DISPLAY_PHY_STATUS,
1203                                     phy_status_mask,
1204                                     phy_status,
1205                                     10))
1206                 DRM_ERROR("Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1207                           I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask,
1208                            phy_status, dev_priv->chv_phy_control);
1209 }
1210
1211 #undef BITS_SET
1212
1213 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1214                                            struct i915_power_well *power_well)
1215 {
1216         enum dpio_phy phy;
1217         enum pipe pipe;
1218         uint32_t tmp;
1219
1220         WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
1221                      power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
1222
1223         if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
1224                 pipe = PIPE_A;
1225                 phy = DPIO_PHY0;
1226         } else {
1227                 pipe = PIPE_C;
1228                 phy = DPIO_PHY1;
1229         }
1230
1231         /* since ref/cri clock was enabled */
1232         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1233         vlv_set_power_well(dev_priv, power_well, true);
1234
1235         /* Poll for phypwrgood signal */
1236         if (intel_wait_for_register(dev_priv,
1237                                     DISPLAY_PHY_STATUS,
1238                                     PHY_POWERGOOD(phy),
1239                                     PHY_POWERGOOD(phy),
1240                                     1))
1241                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1242
1243         mutex_lock(&dev_priv->sb_lock);
1244
1245         /* Enable dynamic power down */
1246         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1247         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1248                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1249         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1250
1251         if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
1252                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1253                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1254                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1255         } else {
1256                 /*
1257                  * Force the non-existing CL2 off. BXT does this
1258                  * too, so maybe it saves some power even though
1259                  * CL2 doesn't exist?
1260                  */
1261                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1262                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1263                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1264         }
1265
1266         mutex_unlock(&dev_priv->sb_lock);
1267
1268         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1269         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1270
1271         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1272                       phy, dev_priv->chv_phy_control);
1273
1274         assert_chv_phy_status(dev_priv);
1275 }
1276
1277 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1278                                             struct i915_power_well *power_well)
1279 {
1280         enum dpio_phy phy;
1281
1282         WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
1283                      power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
1284
1285         if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
1286                 phy = DPIO_PHY0;
1287                 assert_pll_disabled(dev_priv, PIPE_A);
1288                 assert_pll_disabled(dev_priv, PIPE_B);
1289         } else {
1290                 phy = DPIO_PHY1;
1291                 assert_pll_disabled(dev_priv, PIPE_C);
1292         }
1293
1294         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1295         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1296
1297         vlv_set_power_well(dev_priv, power_well, false);
1298
1299         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1300                       phy, dev_priv->chv_phy_control);
1301
1302         /* PHY is fully reset now, so we can enable the PHY state asserts */
1303         dev_priv->chv_phy_assert[phy] = true;
1304
1305         assert_chv_phy_status(dev_priv);
1306 }
1307
1308 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1309                                      enum dpio_channel ch, bool override, unsigned int mask)
1310 {
1311         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1312         u32 reg, val, expected, actual;
1313
1314         /*
1315          * The BIOS can leave the PHY is some weird state
1316          * where it doesn't fully power down some parts.
1317          * Disable the asserts until the PHY has been fully
1318          * reset (ie. the power well has been disabled at
1319          * least once).
1320          */
1321         if (!dev_priv->chv_phy_assert[phy])
1322                 return;
1323
1324         if (ch == DPIO_CH0)
1325                 reg = _CHV_CMN_DW0_CH0;
1326         else
1327                 reg = _CHV_CMN_DW6_CH1;
1328
1329         mutex_lock(&dev_priv->sb_lock);
1330         val = vlv_dpio_read(dev_priv, pipe, reg);
1331         mutex_unlock(&dev_priv->sb_lock);
1332
1333         /*
1334          * This assumes !override is only used when the port is disabled.
1335          * All lanes should power down even without the override when
1336          * the port is disabled.
1337          */
1338         if (!override || mask == 0xf) {
1339                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1340                 /*
1341                  * If CH1 common lane is not active anymore
1342                  * (eg. for pipe B DPLL) the entire channel will
1343                  * shut down, which causes the common lane registers
1344                  * to read as 0. That means we can't actually check
1345                  * the lane power down status bits, but as the entire
1346                  * register reads as 0 it's a good indication that the
1347                  * channel is indeed entirely powered down.
1348                  */
1349                 if (ch == DPIO_CH1 && val == 0)
1350                         expected = 0;
1351         } else if (mask != 0x0) {
1352                 expected = DPIO_ANYDL_POWERDOWN;
1353         } else {
1354                 expected = 0;
1355         }
1356
1357         if (ch == DPIO_CH0)
1358                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1359         else
1360                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1361         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1362
1363         WARN(actual != expected,
1364              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1365              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1366              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1367              reg, val);
1368 }
1369
1370 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1371                           enum dpio_channel ch, bool override)
1372 {
1373         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1374         bool was_override;
1375
1376         mutex_lock(&power_domains->lock);
1377
1378         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1379
1380         if (override == was_override)
1381                 goto out;
1382
1383         if (override)
1384                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1385         else
1386                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1387
1388         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1389
1390         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1391                       phy, ch, dev_priv->chv_phy_control);
1392
1393         assert_chv_phy_status(dev_priv);
1394
1395 out:
1396         mutex_unlock(&power_domains->lock);
1397
1398         return was_override;
1399 }
1400
1401 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1402                              bool override, unsigned int mask)
1403 {
1404         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1405         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1406         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1407         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1408
1409         mutex_lock(&power_domains->lock);
1410
1411         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1412         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1413
1414         if (override)
1415                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1416         else
1417                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1418
1419         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1420
1421         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1422                       phy, ch, mask, dev_priv->chv_phy_control);
1423
1424         assert_chv_phy_status(dev_priv);
1425
1426         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1427
1428         mutex_unlock(&power_domains->lock);
1429 }
1430
1431 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1432                                         struct i915_power_well *power_well)
1433 {
1434         enum pipe pipe = PIPE_A;
1435         bool enabled;
1436         u32 state, ctrl;
1437
1438         mutex_lock(&dev_priv->pcu_lock);
1439
1440         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1441         /*
1442          * We only ever set the power-on and power-gate states, anything
1443          * else is unexpected.
1444          */
1445         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1446         enabled = state == DP_SSS_PWR_ON(pipe);
1447
1448         /*
1449          * A transient state at this point would mean some unexpected party
1450          * is poking at the power controls too.
1451          */
1452         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1453         WARN_ON(ctrl << 16 != state);
1454
1455         mutex_unlock(&dev_priv->pcu_lock);
1456
1457         return enabled;
1458 }
1459
1460 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1461                                     struct i915_power_well *power_well,
1462                                     bool enable)
1463 {
1464         enum pipe pipe = PIPE_A;
1465         u32 state;
1466         u32 ctrl;
1467
1468         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1469
1470         mutex_lock(&dev_priv->pcu_lock);
1471
1472 #define COND \
1473         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1474
1475         if (COND)
1476                 goto out;
1477
1478         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1479         ctrl &= ~DP_SSC_MASK(pipe);
1480         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1481         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1482
1483         if (wait_for(COND, 100))
1484                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1485                           state,
1486                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1487
1488 #undef COND
1489
1490 out:
1491         mutex_unlock(&dev_priv->pcu_lock);
1492 }
1493
1494 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1495                                        struct i915_power_well *power_well)
1496 {
1497         chv_set_pipe_power_well(dev_priv, power_well, true);
1498
1499         vlv_display_power_well_init(dev_priv);
1500 }
1501
1502 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1503                                         struct i915_power_well *power_well)
1504 {
1505         vlv_display_power_well_deinit(dev_priv);
1506
1507         chv_set_pipe_power_well(dev_priv, power_well, false);
1508 }
1509
1510 static void
1511 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1512                                  enum intel_display_power_domain domain)
1513 {
1514         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1515         struct i915_power_well *power_well;
1516
1517         for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
1518                 intel_power_well_get(dev_priv, power_well);
1519
1520         power_domains->domain_use_count[domain]++;
1521 }
1522
1523 /**
1524  * intel_display_power_get - grab a power domain reference
1525  * @dev_priv: i915 device instance
1526  * @domain: power domain to reference
1527  *
1528  * This function grabs a power domain reference for @domain and ensures that the
1529  * power domain and all its parents are powered up. Therefore users should only
1530  * grab a reference to the innermost power domain they need.
1531  *
1532  * Any power domain reference obtained by this function must have a symmetric
1533  * call to intel_display_power_put() to release the reference again.
1534  */
1535 void intel_display_power_get(struct drm_i915_private *dev_priv,
1536                              enum intel_display_power_domain domain)
1537 {
1538         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1539
1540         intel_runtime_pm_get(dev_priv);
1541
1542         mutex_lock(&power_domains->lock);
1543
1544         __intel_display_power_get_domain(dev_priv, domain);
1545
1546         mutex_unlock(&power_domains->lock);
1547 }
1548
1549 /**
1550  * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1551  * @dev_priv: i915 device instance
1552  * @domain: power domain to reference
1553  *
1554  * This function grabs a power domain reference for @domain and ensures that the
1555  * power domain and all its parents are powered up. Therefore users should only
1556  * grab a reference to the innermost power domain they need.
1557  *
1558  * Any power domain reference obtained by this function must have a symmetric
1559  * call to intel_display_power_put() to release the reference again.
1560  */
1561 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1562                                         enum intel_display_power_domain domain)
1563 {
1564         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1565         bool is_enabled;
1566
1567         if (!intel_runtime_pm_get_if_in_use(dev_priv))
1568                 return false;
1569
1570         mutex_lock(&power_domains->lock);
1571
1572         if (__intel_display_power_is_enabled(dev_priv, domain)) {
1573                 __intel_display_power_get_domain(dev_priv, domain);
1574                 is_enabled = true;
1575         } else {
1576                 is_enabled = false;
1577         }
1578
1579         mutex_unlock(&power_domains->lock);
1580
1581         if (!is_enabled)
1582                 intel_runtime_pm_put(dev_priv);
1583
1584         return is_enabled;
1585 }
1586
1587 /**
1588  * intel_display_power_put - release a power domain reference
1589  * @dev_priv: i915 device instance
1590  * @domain: power domain to reference
1591  *
1592  * This function drops the power domain reference obtained by
1593  * intel_display_power_get() and might power down the corresponding hardware
1594  * block right away if this is the last reference.
1595  */
1596 void intel_display_power_put(struct drm_i915_private *dev_priv,
1597                              enum intel_display_power_domain domain)
1598 {
1599         struct i915_power_domains *power_domains;
1600         struct i915_power_well *power_well;
1601
1602         power_domains = &dev_priv->power_domains;
1603
1604         mutex_lock(&power_domains->lock);
1605
1606         WARN(!power_domains->domain_use_count[domain],
1607              "Use count on domain %s is already zero\n",
1608              intel_display_power_domain_str(domain));
1609         power_domains->domain_use_count[domain]--;
1610
1611         for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain))
1612                 intel_power_well_put(dev_priv, power_well);
1613
1614         mutex_unlock(&power_domains->lock);
1615
1616         intel_runtime_pm_put(dev_priv);
1617 }
1618
1619 #define I830_PIPES_POWER_DOMAINS (              \
1620         BIT_ULL(POWER_DOMAIN_PIPE_A) |          \
1621         BIT_ULL(POWER_DOMAIN_PIPE_B) |          \
1622         BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |     \
1623         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |     \
1624         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |    \
1625         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |    \
1626         BIT_ULL(POWER_DOMAIN_INIT))
1627
1628 #define VLV_DISPLAY_POWER_DOMAINS (             \
1629         BIT_ULL(POWER_DOMAIN_PIPE_A) |          \
1630         BIT_ULL(POWER_DOMAIN_PIPE_B) |          \
1631         BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |     \
1632         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |     \
1633         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |    \
1634         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |    \
1635         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |        \
1636         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |        \
1637         BIT_ULL(POWER_DOMAIN_PORT_DSI) |                \
1638         BIT_ULL(POWER_DOMAIN_PORT_CRT) |                \
1639         BIT_ULL(POWER_DOMAIN_VGA) |                     \
1640         BIT_ULL(POWER_DOMAIN_AUDIO) |           \
1641         BIT_ULL(POWER_DOMAIN_AUX_B) |           \
1642         BIT_ULL(POWER_DOMAIN_AUX_C) |           \
1643         BIT_ULL(POWER_DOMAIN_GMBUS) |           \
1644         BIT_ULL(POWER_DOMAIN_INIT))
1645
1646 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1647         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |        \
1648         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |        \
1649         BIT_ULL(POWER_DOMAIN_PORT_CRT) |                \
1650         BIT_ULL(POWER_DOMAIN_AUX_B) |           \
1651         BIT_ULL(POWER_DOMAIN_AUX_C) |           \
1652         BIT_ULL(POWER_DOMAIN_INIT))
1653
1654 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1655         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |        \
1656         BIT_ULL(POWER_DOMAIN_AUX_B) |           \
1657         BIT_ULL(POWER_DOMAIN_INIT))
1658
1659 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1660         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |        \
1661         BIT_ULL(POWER_DOMAIN_AUX_B) |           \
1662         BIT_ULL(POWER_DOMAIN_INIT))
1663
1664 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1665         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |        \
1666         BIT_ULL(POWER_DOMAIN_AUX_C) |           \
1667         BIT_ULL(POWER_DOMAIN_INIT))
1668
1669 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1670         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |        \
1671         BIT_ULL(POWER_DOMAIN_AUX_C) |           \
1672         BIT_ULL(POWER_DOMAIN_INIT))
1673
1674 #define CHV_DISPLAY_POWER_DOMAINS (             \
1675         BIT_ULL(POWER_DOMAIN_PIPE_A) |          \
1676         BIT_ULL(POWER_DOMAIN_PIPE_B) |          \
1677         BIT_ULL(POWER_DOMAIN_PIPE_C) |          \
1678         BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |     \
1679         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |     \
1680         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |     \
1681         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |    \
1682         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |    \
1683         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |    \
1684         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |        \
1685         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |        \
1686         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |        \
1687         BIT_ULL(POWER_DOMAIN_PORT_DSI) |                \
1688         BIT_ULL(POWER_DOMAIN_VGA) |                     \
1689         BIT_ULL(POWER_DOMAIN_AUDIO) |           \
1690         BIT_ULL(POWER_DOMAIN_AUX_B) |           \
1691         BIT_ULL(POWER_DOMAIN_AUX_C) |           \
1692         BIT_ULL(POWER_DOMAIN_AUX_D) |           \
1693         BIT_ULL(POWER_DOMAIN_GMBUS) |           \
1694         BIT_ULL(POWER_DOMAIN_INIT))
1695
1696 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1697         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |        \
1698         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |        \
1699         BIT_ULL(POWER_DOMAIN_AUX_B) |           \
1700         BIT_ULL(POWER_DOMAIN_AUX_C) |           \
1701         BIT_ULL(POWER_DOMAIN_INIT))
1702
1703 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1704         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |        \
1705         BIT_ULL(POWER_DOMAIN_AUX_D) |           \
1706         BIT_ULL(POWER_DOMAIN_INIT))
1707
1708 #define HSW_DISPLAY_POWER_DOMAINS (                     \
1709         BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
1710         BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
1711         BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |             \
1712         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
1713         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
1714         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
1715         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
1716         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
1717         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
1718         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
1719         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |                \
1720         BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */    \
1721         BIT_ULL(POWER_DOMAIN_VGA) |                             \
1722         BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
1723         BIT_ULL(POWER_DOMAIN_INIT))
1724
1725 #define BDW_DISPLAY_POWER_DOMAINS (                     \
1726         BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
1727         BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
1728         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
1729         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
1730         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
1731         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
1732         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
1733         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
1734         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
1735         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |                \
1736         BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */    \
1737         BIT_ULL(POWER_DOMAIN_VGA) |                             \
1738         BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
1739         BIT_ULL(POWER_DOMAIN_INIT))
1740
1741 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
1742         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
1743         BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
1744         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
1745         BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
1746         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
1747         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
1748         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
1749         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
1750         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
1751         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |                \
1752         BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |                \
1753         BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
1754         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
1755         BIT_ULL(POWER_DOMAIN_AUX_D) |                   \
1756         BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
1757         BIT_ULL(POWER_DOMAIN_VGA) |                             \
1758         BIT_ULL(POWER_DOMAIN_INIT))
1759 #define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS (          \
1760         BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) |           \
1761         BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) |           \
1762         BIT_ULL(POWER_DOMAIN_INIT))
1763 #define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS (            \
1764         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) |           \
1765         BIT_ULL(POWER_DOMAIN_INIT))
1766 #define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS (            \
1767         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) |           \
1768         BIT_ULL(POWER_DOMAIN_INIT))
1769 #define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS (            \
1770         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) |           \
1771         BIT_ULL(POWER_DOMAIN_INIT))
1772 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
1773         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
1774         BIT_ULL(POWER_DOMAIN_GT_IRQ) |                  \
1775         BIT_ULL(POWER_DOMAIN_MODESET) |                 \
1776         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
1777         BIT_ULL(POWER_DOMAIN_INIT))
1778
1779 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
1780         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
1781         BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
1782         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
1783         BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
1784         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
1785         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
1786         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
1787         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
1788         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
1789         BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
1790         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
1791         BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
1792         BIT_ULL(POWER_DOMAIN_VGA) |                             \
1793         BIT_ULL(POWER_DOMAIN_INIT))
1794 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (              \
1795         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
1796         BIT_ULL(POWER_DOMAIN_GT_IRQ) |                  \
1797         BIT_ULL(POWER_DOMAIN_MODESET) |                 \
1798         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
1799         BIT_ULL(POWER_DOMAIN_GMBUS) |                   \
1800         BIT_ULL(POWER_DOMAIN_INIT))
1801 #define BXT_DPIO_CMN_A_POWER_DOMAINS (                  \
1802         BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) |                \
1803         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
1804         BIT_ULL(POWER_DOMAIN_INIT))
1805 #define BXT_DPIO_CMN_BC_POWER_DOMAINS (                 \
1806         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
1807         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
1808         BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
1809         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
1810         BIT_ULL(POWER_DOMAIN_INIT))
1811
1812 #define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
1813         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
1814         BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
1815         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
1816         BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
1817         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
1818         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
1819         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
1820         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
1821         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
1822         BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
1823         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
1824         BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
1825         BIT_ULL(POWER_DOMAIN_VGA) |                             \
1826         BIT_ULL(POWER_DOMAIN_INIT))
1827 #define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS (            \
1828         BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
1829 #define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS (            \
1830         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO))
1831 #define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS (            \
1832         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
1833 #define GLK_DPIO_CMN_A_POWER_DOMAINS (                  \
1834         BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) |                \
1835         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
1836         BIT_ULL(POWER_DOMAIN_INIT))
1837 #define GLK_DPIO_CMN_B_POWER_DOMAINS (                  \
1838         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
1839         BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
1840         BIT_ULL(POWER_DOMAIN_INIT))
1841 #define GLK_DPIO_CMN_C_POWER_DOMAINS (                  \
1842         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
1843         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
1844         BIT_ULL(POWER_DOMAIN_INIT))
1845 #define GLK_DISPLAY_AUX_A_POWER_DOMAINS (               \
1846         BIT_ULL(POWER_DOMAIN_AUX_A) |           \
1847         BIT_ULL(POWER_DOMAIN_AUX_IO_A) |                \
1848         BIT_ULL(POWER_DOMAIN_INIT))
1849 #define GLK_DISPLAY_AUX_B_POWER_DOMAINS (               \
1850         BIT_ULL(POWER_DOMAIN_AUX_B) |           \
1851         BIT_ULL(POWER_DOMAIN_INIT))
1852 #define GLK_DISPLAY_AUX_C_POWER_DOMAINS (               \
1853         BIT_ULL(POWER_DOMAIN_AUX_C) |           \
1854         BIT_ULL(POWER_DOMAIN_INIT))
1855 #define GLK_DISPLAY_DC_OFF_POWER_DOMAINS (              \
1856         GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
1857         BIT_ULL(POWER_DOMAIN_GT_IRQ) |                  \
1858         BIT_ULL(POWER_DOMAIN_MODESET) |                 \
1859         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
1860         BIT_ULL(POWER_DOMAIN_GMBUS) |                   \
1861         BIT_ULL(POWER_DOMAIN_INIT))
1862
1863 #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
1864         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
1865         BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
1866         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
1867         BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
1868         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
1869         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
1870         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
1871         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
1872         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
1873         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |                \
1874         BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) |                \
1875         BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
1876         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
1877         BIT_ULL(POWER_DOMAIN_AUX_D) |                   \
1878         BIT_ULL(POWER_DOMAIN_AUX_F) |                   \
1879         BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
1880         BIT_ULL(POWER_DOMAIN_VGA) |                             \
1881         BIT_ULL(POWER_DOMAIN_INIT))
1882 #define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS (            \
1883         BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) |           \
1884         BIT_ULL(POWER_DOMAIN_INIT))
1885 #define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS (            \
1886         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) |           \
1887         BIT_ULL(POWER_DOMAIN_INIT))
1888 #define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS (            \
1889         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) |           \
1890         BIT_ULL(POWER_DOMAIN_INIT))
1891 #define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS (            \
1892         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) |           \
1893         BIT_ULL(POWER_DOMAIN_INIT))
1894 #define CNL_DISPLAY_AUX_A_POWER_DOMAINS (               \
1895         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
1896         BIT_ULL(POWER_DOMAIN_AUX_IO_A) |                \
1897         BIT_ULL(POWER_DOMAIN_INIT))
1898 #define CNL_DISPLAY_AUX_B_POWER_DOMAINS (               \
1899         BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
1900         BIT_ULL(POWER_DOMAIN_INIT))
1901 #define CNL_DISPLAY_AUX_C_POWER_DOMAINS (               \
1902         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
1903         BIT_ULL(POWER_DOMAIN_INIT))
1904 #define CNL_DISPLAY_AUX_D_POWER_DOMAINS (               \
1905         BIT_ULL(POWER_DOMAIN_AUX_D) |                   \
1906         BIT_ULL(POWER_DOMAIN_INIT))
1907 #define CNL_DISPLAY_AUX_F_POWER_DOMAINS (               \
1908         BIT_ULL(POWER_DOMAIN_AUX_F) |                   \
1909         BIT_ULL(POWER_DOMAIN_INIT))
1910 #define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS (            \
1911         BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) |           \
1912         BIT_ULL(POWER_DOMAIN_INIT))
1913 #define CNL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
1914         CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
1915         BIT_ULL(POWER_DOMAIN_GT_IRQ) |                  \
1916         BIT_ULL(POWER_DOMAIN_MODESET) |                 \
1917         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
1918         BIT_ULL(POWER_DOMAIN_INIT))
1919
1920 /*
1921  * ICL PW_0/PG_0 domains (HW/DMC control):
1922  * - PCI
1923  * - clocks except port PLL
1924  * - central power except FBC
1925  * - shared functions except pipe interrupts, pipe MBUS, DBUF registers
1926  * ICL PW_1/PG_1 domains (HW/DMC control):
1927  * - DBUF function
1928  * - PIPE_A and its planes, except VGA
1929  * - transcoder EDP + PSR
1930  * - transcoder DSI
1931  * - DDI_A
1932  * - FBC
1933  */
1934 #define ICL_PW_4_POWER_DOMAINS (                        \
1935         BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
1936         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |     \
1937         BIT_ULL(POWER_DOMAIN_INIT))
1938         /* VDSC/joining */
1939 #define ICL_PW_3_POWER_DOMAINS (                        \
1940         ICL_PW_4_POWER_DOMAINS |                        \
1941         BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
1942         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
1943         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
1944         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
1945         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |     \
1946         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |        \
1947         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) |           \
1948         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |        \
1949         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) |           \
1950         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |        \
1951         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) |           \
1952         BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |        \
1953         BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) |           \
1954         BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) |        \
1955         BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) |           \
1956         BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
1957         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
1958         BIT_ULL(POWER_DOMAIN_AUX_D) |                   \
1959         BIT_ULL(POWER_DOMAIN_AUX_E) |                   \
1960         BIT_ULL(POWER_DOMAIN_AUX_F) |                   \
1961         BIT_ULL(POWER_DOMAIN_AUX_TBT1) |                \
1962         BIT_ULL(POWER_DOMAIN_AUX_TBT2) |                \
1963         BIT_ULL(POWER_DOMAIN_AUX_TBT3) |                \
1964         BIT_ULL(POWER_DOMAIN_AUX_TBT4) |                \
1965         BIT_ULL(POWER_DOMAIN_VGA) |                     \
1966         BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
1967         BIT_ULL(POWER_DOMAIN_INIT))
1968         /*
1969          * - transcoder WD
1970          * - KVMR (HW control)
1971          */
1972 #define ICL_PW_2_POWER_DOMAINS (                        \
1973         ICL_PW_3_POWER_DOMAINS |                        \
1974         BIT_ULL(POWER_DOMAIN_INIT))
1975         /*
1976          * - eDP/DSI VDSC
1977          * - KVMR (HW control)
1978          */
1979 #define ICL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
1980         ICL_PW_2_POWER_DOMAINS |                        \
1981         BIT_ULL(POWER_DOMAIN_MODESET) |                 \
1982         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
1983         BIT_ULL(POWER_DOMAIN_INIT))
1984
1985 #define ICL_DDI_IO_A_POWER_DOMAINS (                    \
1986         BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
1987 #define ICL_DDI_IO_B_POWER_DOMAINS (                    \
1988         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO))
1989 #define ICL_DDI_IO_C_POWER_DOMAINS (                    \
1990         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
1991 #define ICL_DDI_IO_D_POWER_DOMAINS (                    \
1992         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO))
1993 #define ICL_DDI_IO_E_POWER_DOMAINS (                    \
1994         BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO))
1995 #define ICL_DDI_IO_F_POWER_DOMAINS (                    \
1996         BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO))
1997
1998 #define ICL_AUX_A_IO_POWER_DOMAINS (                    \
1999         BIT_ULL(POWER_DOMAIN_AUX_IO_A) |                \
2000         BIT_ULL(POWER_DOMAIN_AUX_A))
2001 #define ICL_AUX_B_IO_POWER_DOMAINS (                    \
2002         BIT_ULL(POWER_DOMAIN_AUX_B))
2003 #define ICL_AUX_C_IO_POWER_DOMAINS (                    \
2004         BIT_ULL(POWER_DOMAIN_AUX_C))
2005 #define ICL_AUX_D_IO_POWER_DOMAINS (                    \
2006         BIT_ULL(POWER_DOMAIN_AUX_D))
2007 #define ICL_AUX_E_IO_POWER_DOMAINS (                    \
2008         BIT_ULL(POWER_DOMAIN_AUX_E))
2009 #define ICL_AUX_F_IO_POWER_DOMAINS (                    \
2010         BIT_ULL(POWER_DOMAIN_AUX_F))
2011 #define ICL_AUX_TBT1_IO_POWER_DOMAINS (                 \
2012         BIT_ULL(POWER_DOMAIN_AUX_TBT1))
2013 #define ICL_AUX_TBT2_IO_POWER_DOMAINS (                 \
2014         BIT_ULL(POWER_DOMAIN_AUX_TBT2))
2015 #define ICL_AUX_TBT3_IO_POWER_DOMAINS (                 \
2016         BIT_ULL(POWER_DOMAIN_AUX_TBT3))
2017 #define ICL_AUX_TBT4_IO_POWER_DOMAINS (                 \
2018         BIT_ULL(POWER_DOMAIN_AUX_TBT4))
2019
2020 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
2021         .sync_hw = i9xx_power_well_sync_hw_noop,
2022         .enable = i9xx_always_on_power_well_noop,
2023         .disable = i9xx_always_on_power_well_noop,
2024         .is_enabled = i9xx_always_on_power_well_enabled,
2025 };
2026
2027 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
2028         .sync_hw = i9xx_power_well_sync_hw_noop,
2029         .enable = chv_pipe_power_well_enable,
2030         .disable = chv_pipe_power_well_disable,
2031         .is_enabled = chv_pipe_power_well_enabled,
2032 };
2033
2034 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
2035         .sync_hw = i9xx_power_well_sync_hw_noop,
2036         .enable = chv_dpio_cmn_power_well_enable,
2037         .disable = chv_dpio_cmn_power_well_disable,
2038         .is_enabled = vlv_power_well_enabled,
2039 };
2040
2041 static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
2042         {
2043                 .name = "always-on",
2044                 .always_on = 1,
2045                 .domains = POWER_DOMAIN_MASK,
2046                 .ops = &i9xx_always_on_power_well_ops,
2047                 .id = DISP_PW_ID_NONE,
2048         },
2049 };
2050
2051 static const struct i915_power_well_ops i830_pipes_power_well_ops = {
2052         .sync_hw = i830_pipes_power_well_sync_hw,
2053         .enable = i830_pipes_power_well_enable,
2054         .disable = i830_pipes_power_well_disable,
2055         .is_enabled = i830_pipes_power_well_enabled,
2056 };
2057
2058 static const struct i915_power_well_desc i830_power_wells[] = {
2059         {
2060                 .name = "always-on",
2061                 .always_on = 1,
2062                 .domains = POWER_DOMAIN_MASK,
2063                 .ops = &i9xx_always_on_power_well_ops,
2064                 .id = DISP_PW_ID_NONE,
2065         },
2066         {
2067                 .name = "pipes",
2068                 .domains = I830_PIPES_POWER_DOMAINS,
2069                 .ops = &i830_pipes_power_well_ops,
2070                 .id = DISP_PW_ID_NONE,
2071         },
2072 };
2073
2074 static const struct i915_power_well_ops hsw_power_well_ops = {
2075         .sync_hw = hsw_power_well_sync_hw,
2076         .enable = hsw_power_well_enable,
2077         .disable = hsw_power_well_disable,
2078         .is_enabled = hsw_power_well_enabled,
2079 };
2080
2081 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
2082         .sync_hw = i9xx_power_well_sync_hw_noop,
2083         .enable = gen9_dc_off_power_well_enable,
2084         .disable = gen9_dc_off_power_well_disable,
2085         .is_enabled = gen9_dc_off_power_well_enabled,
2086 };
2087
2088 static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
2089         .sync_hw = i9xx_power_well_sync_hw_noop,
2090         .enable = bxt_dpio_cmn_power_well_enable,
2091         .disable = bxt_dpio_cmn_power_well_disable,
2092         .is_enabled = bxt_dpio_cmn_power_well_enabled,
2093 };
2094
2095 static const struct i915_power_well_regs hsw_power_well_regs = {
2096         .bios   = HSW_PWR_WELL_CTL1,
2097         .driver = HSW_PWR_WELL_CTL2,
2098         .kvmr   = HSW_PWR_WELL_CTL3,
2099         .debug  = HSW_PWR_WELL_CTL4,
2100 };
2101
2102 static const struct i915_power_well_desc hsw_power_wells[] = {
2103         {
2104                 .name = "always-on",
2105                 .always_on = 1,
2106                 .domains = POWER_DOMAIN_MASK,
2107                 .ops = &i9xx_always_on_power_well_ops,
2108                 .id = DISP_PW_ID_NONE,
2109         },
2110         {
2111                 .name = "display",
2112                 .domains = HSW_DISPLAY_POWER_DOMAINS,
2113                 .ops = &hsw_power_well_ops,
2114                 .id = HSW_DISP_PW_GLOBAL,
2115                 {
2116                         .hsw.regs = &hsw_power_well_regs,
2117                         .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
2118                         .hsw.has_vga = true,
2119                 },
2120         },
2121 };
2122
2123 static const struct i915_power_well_desc bdw_power_wells[] = {
2124         {
2125                 .name = "always-on",
2126                 .always_on = 1,
2127                 .domains = POWER_DOMAIN_MASK,
2128                 .ops = &i9xx_always_on_power_well_ops,
2129                 .id = DISP_PW_ID_NONE,
2130         },
2131         {
2132                 .name = "display",
2133                 .domains = BDW_DISPLAY_POWER_DOMAINS,
2134                 .ops = &hsw_power_well_ops,
2135                 .id = HSW_DISP_PW_GLOBAL,
2136                 {
2137                         .hsw.regs = &hsw_power_well_regs,
2138                         .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
2139                         .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2140                         .hsw.has_vga = true,
2141                 },
2142         },
2143 };
2144
2145 static const struct i915_power_well_ops vlv_display_power_well_ops = {
2146         .sync_hw = i9xx_power_well_sync_hw_noop,
2147         .enable = vlv_display_power_well_enable,
2148         .disable = vlv_display_power_well_disable,
2149         .is_enabled = vlv_power_well_enabled,
2150 };
2151
2152 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
2153         .sync_hw = i9xx_power_well_sync_hw_noop,
2154         .enable = vlv_dpio_cmn_power_well_enable,
2155         .disable = vlv_dpio_cmn_power_well_disable,
2156         .is_enabled = vlv_power_well_enabled,
2157 };
2158
2159 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
2160         .sync_hw = i9xx_power_well_sync_hw_noop,
2161         .enable = vlv_power_well_enable,
2162         .disable = vlv_power_well_disable,
2163         .is_enabled = vlv_power_well_enabled,
2164 };
2165
2166 static const struct i915_power_well_desc vlv_power_wells[] = {
2167         {
2168                 .name = "always-on",
2169                 .always_on = 1,
2170                 .domains = POWER_DOMAIN_MASK,
2171                 .ops = &i9xx_always_on_power_well_ops,
2172                 .id = DISP_PW_ID_NONE,
2173         },
2174         {
2175                 .name = "display",
2176                 .domains = VLV_DISPLAY_POWER_DOMAINS,
2177                 .ops = &vlv_display_power_well_ops,
2178                 .id = VLV_DISP_PW_DISP2D,
2179                 {
2180                         .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
2181                 },
2182         },
2183         {
2184                 .name = "dpio-tx-b-01",
2185                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2186                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2187                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2188                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2189                 .ops = &vlv_dpio_power_well_ops,
2190                 .id = DISP_PW_ID_NONE,
2191                 {
2192                         .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01,
2193                 },
2194         },
2195         {
2196                 .name = "dpio-tx-b-23",
2197                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2198                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2199                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2200                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2201                 .ops = &vlv_dpio_power_well_ops,
2202                 .id = DISP_PW_ID_NONE,
2203                 {
2204                         .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23,
2205                 },
2206         },
2207         {
2208                 .name = "dpio-tx-c-01",
2209                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2210                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2211                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2212                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2213                 .ops = &vlv_dpio_power_well_ops,
2214                 .id = DISP_PW_ID_NONE,
2215                 {
2216                         .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01,
2217                 },
2218         },
2219         {
2220                 .name = "dpio-tx-c-23",
2221                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2222                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2223                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2224                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2225                 .ops = &vlv_dpio_power_well_ops,
2226                 .id = DISP_PW_ID_NONE,
2227                 {
2228                         .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23,
2229                 },
2230         },
2231         {
2232                 .name = "dpio-common",
2233                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
2234                 .ops = &vlv_dpio_cmn_power_well_ops,
2235                 .id = VLV_DISP_PW_DPIO_CMN_BC,
2236                 {
2237                         .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
2238                 },
2239         },
2240 };
2241
2242 static const struct i915_power_well_desc chv_power_wells[] = {
2243         {
2244                 .name = "always-on",
2245                 .always_on = 1,
2246                 .domains = POWER_DOMAIN_MASK,
2247                 .ops = &i9xx_always_on_power_well_ops,
2248                 .id = DISP_PW_ID_NONE,
2249         },
2250         {
2251                 .name = "display",
2252                 /*
2253                  * Pipe A power well is the new disp2d well. Pipe B and C
2254                  * power wells don't actually exist. Pipe A power well is
2255                  * required for any pipe to work.
2256                  */
2257                 .domains = CHV_DISPLAY_POWER_DOMAINS,
2258                 .ops = &chv_pipe_power_well_ops,
2259                 .id = DISP_PW_ID_NONE,
2260         },
2261         {
2262                 .name = "dpio-common-bc",
2263                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
2264                 .ops = &chv_dpio_cmn_power_well_ops,
2265                 .id = VLV_DISP_PW_DPIO_CMN_BC,
2266                 {
2267                         .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
2268                 },
2269         },
2270         {
2271                 .name = "dpio-common-d",
2272                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
2273                 .ops = &chv_dpio_cmn_power_well_ops,
2274                 .id = CHV_DISP_PW_DPIO_CMN_D,
2275                 {
2276                         .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
2277                 },
2278         },
2279 };
2280
2281 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
2282                                          enum i915_power_well_id power_well_id)
2283 {
2284         struct i915_power_well *power_well;
2285         bool ret;
2286
2287         power_well = lookup_power_well(dev_priv, power_well_id);
2288         ret = power_well->desc->ops->is_enabled(dev_priv, power_well);
2289
2290         return ret;
2291 }
2292
2293 static const struct i915_power_well_desc skl_power_wells[] = {
2294         {
2295                 .name = "always-on",
2296                 .always_on = 1,
2297                 .domains = POWER_DOMAIN_MASK,
2298                 .ops = &i9xx_always_on_power_well_ops,
2299                 .id = DISP_PW_ID_NONE,
2300         },
2301         {
2302                 .name = "power well 1",
2303                 /* Handled by the DMC firmware */
2304                 .domains = 0,
2305                 .ops = &hsw_power_well_ops,
2306                 .id = SKL_DISP_PW_1,
2307                 {
2308                         .hsw.regs = &hsw_power_well_regs,
2309                         .hsw.idx = SKL_PW_CTL_IDX_PW_1,
2310                         .hsw.has_fuses = true,
2311                 },
2312         },
2313         {
2314                 .name = "MISC IO power well",
2315                 /* Handled by the DMC firmware */
2316                 .domains = 0,
2317                 .ops = &hsw_power_well_ops,
2318                 .id = SKL_DISP_PW_MISC_IO,
2319                 {
2320                         .hsw.regs = &hsw_power_well_regs,
2321                         .hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
2322                 },
2323         },
2324         {
2325                 .name = "DC off",
2326                 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
2327                 .ops = &gen9_dc_off_power_well_ops,
2328                 .id = DISP_PW_ID_NONE,
2329         },
2330         {
2331                 .name = "power well 2",
2332                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2333                 .ops = &hsw_power_well_ops,
2334                 .id = SKL_DISP_PW_2,
2335                 {
2336                         .hsw.regs = &hsw_power_well_regs,
2337                         .hsw.idx = SKL_PW_CTL_IDX_PW_2,
2338                         .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2339                         .hsw.has_vga = true,
2340                         .hsw.has_fuses = true,
2341                 },
2342         },
2343         {
2344                 .name = "DDI A/E IO power well",
2345                 .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
2346                 .ops = &hsw_power_well_ops,
2347                 .id = DISP_PW_ID_NONE,
2348                 {
2349                         .hsw.regs = &hsw_power_well_regs,
2350                         .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,
2351                 },
2352         },
2353         {
2354                 .name = "DDI B IO power well",
2355                 .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
2356                 .ops = &hsw_power_well_ops,
2357                 .id = DISP_PW_ID_NONE,
2358                 {
2359                         .hsw.regs = &hsw_power_well_regs,
2360                         .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
2361                 },
2362         },
2363         {
2364                 .name = "DDI C IO power well",
2365                 .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
2366                 .ops = &hsw_power_well_ops,
2367                 .id = DISP_PW_ID_NONE,
2368                 {
2369                         .hsw.regs = &hsw_power_well_regs,
2370                         .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
2371                 },
2372         },
2373         {
2374                 .name = "DDI D IO power well",
2375                 .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
2376                 .ops = &hsw_power_well_ops,
2377                 .id = DISP_PW_ID_NONE,
2378                 {
2379                         .hsw.regs = &hsw_power_well_regs,
2380                         .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
2381                 },
2382         },
2383 };
2384
2385 static const struct i915_power_well_desc bxt_power_wells[] = {
2386         {
2387                 .name = "always-on",
2388                 .always_on = 1,
2389                 .domains = POWER_DOMAIN_MASK,
2390                 .ops = &i9xx_always_on_power_well_ops,
2391                 .id = DISP_PW_ID_NONE,
2392         },
2393         {
2394                 .name = "power well 1",
2395                 .domains = 0,
2396                 .ops = &hsw_power_well_ops,
2397                 .id = SKL_DISP_PW_1,
2398                 {
2399                         .hsw.regs = &hsw_power_well_regs,
2400                         .hsw.idx = SKL_PW_CTL_IDX_PW_1,
2401                         .hsw.has_fuses = true,
2402                 },
2403         },
2404         {
2405                 .name = "DC off",
2406                 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
2407                 .ops = &gen9_dc_off_power_well_ops,
2408                 .id = DISP_PW_ID_NONE,
2409         },
2410         {
2411                 .name = "power well 2",
2412                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2413                 .ops = &hsw_power_well_ops,
2414                 .id = SKL_DISP_PW_2,
2415                 {
2416                         .hsw.regs = &hsw_power_well_regs,
2417                         .hsw.idx = SKL_PW_CTL_IDX_PW_2,
2418                         .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2419                         .hsw.has_vga = true,
2420                         .hsw.has_fuses = true,
2421                 },
2422         },
2423         {
2424                 .name = "dpio-common-a",
2425                 .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
2426                 .ops = &bxt_dpio_cmn_power_well_ops,
2427                 .id = BXT_DISP_PW_DPIO_CMN_A,
2428                 {
2429                         .bxt.phy = DPIO_PHY1,
2430                 },
2431         },
2432         {
2433                 .name = "dpio-common-bc",
2434                 .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
2435                 .ops = &bxt_dpio_cmn_power_well_ops,
2436                 .id = VLV_DISP_PW_DPIO_CMN_BC,
2437                 {
2438                         .bxt.phy = DPIO_PHY0,
2439                 },
2440         },
2441 };
2442
2443 static const struct i915_power_well_desc glk_power_wells[] = {
2444         {
2445                 .name = "always-on",
2446                 .always_on = 1,
2447                 .domains = POWER_DOMAIN_MASK,
2448                 .ops = &i9xx_always_on_power_well_ops,
2449                 .id = DISP_PW_ID_NONE,
2450         },
2451         {
2452                 .name = "power well 1",
2453                 /* Handled by the DMC firmware */
2454                 .domains = 0,
2455                 .ops = &hsw_power_well_ops,
2456                 .id = SKL_DISP_PW_1,
2457                 {
2458                         .hsw.regs = &hsw_power_well_regs,
2459                         .hsw.idx = SKL_PW_CTL_IDX_PW_1,
2460                         .hsw.has_fuses = true,
2461                 },
2462         },
2463         {
2464                 .name = "DC off",
2465                 .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
2466                 .ops = &gen9_dc_off_power_well_ops,
2467                 .id = DISP_PW_ID_NONE,
2468         },
2469         {
2470                 .name = "power well 2",
2471                 .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2472                 .ops = &hsw_power_well_ops,
2473                 .id = SKL_DISP_PW_2,
2474                 {
2475                         .hsw.regs = &hsw_power_well_regs,
2476                         .hsw.idx = SKL_PW_CTL_IDX_PW_2,
2477                         .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2478                         .hsw.has_vga = true,
2479                         .hsw.has_fuses = true,
2480                 },
2481         },
2482         {
2483                 .name = "dpio-common-a",
2484                 .domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
2485                 .ops = &bxt_dpio_cmn_power_well_ops,
2486                 .id = BXT_DISP_PW_DPIO_CMN_A,
2487                 {
2488                         .bxt.phy = DPIO_PHY1,
2489                 },
2490         },
2491         {
2492                 .name = "dpio-common-b",
2493                 .domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
2494                 .ops = &bxt_dpio_cmn_power_well_ops,
2495                 .id = VLV_DISP_PW_DPIO_CMN_BC,
2496                 {
2497                         .bxt.phy = DPIO_PHY0,
2498                 },
2499         },
2500         {
2501                 .name = "dpio-common-c",
2502                 .domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
2503                 .ops = &bxt_dpio_cmn_power_well_ops,
2504                 .id = GLK_DISP_PW_DPIO_CMN_C,
2505                 {
2506                         .bxt.phy = DPIO_PHY2,
2507                 },
2508         },
2509         {
2510                 .name = "AUX A",
2511                 .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
2512                 .ops = &hsw_power_well_ops,
2513                 .id = DISP_PW_ID_NONE,
2514                 {
2515                         .hsw.regs = &hsw_power_well_regs,
2516                         .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
2517                 },
2518         },
2519         {
2520                 .name = "AUX B",
2521                 .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
2522                 .ops = &hsw_power_well_ops,
2523                 .id = DISP_PW_ID_NONE,
2524                 {
2525                         .hsw.regs = &hsw_power_well_regs,
2526                         .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
2527                 },
2528         },
2529         {
2530                 .name = "AUX C",
2531                 .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
2532                 .ops = &hsw_power_well_ops,
2533                 .id = DISP_PW_ID_NONE,
2534                 {
2535                         .hsw.regs = &hsw_power_well_regs,
2536                         .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
2537                 },
2538         },
2539         {
2540                 .name = "DDI A IO power well",
2541                 .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
2542                 .ops = &hsw_power_well_ops,
2543                 .id = DISP_PW_ID_NONE,
2544                 {
2545                         .hsw.regs = &hsw_power_well_regs,
2546                         .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
2547                 },
2548         },
2549         {
2550                 .name = "DDI B IO power well",
2551                 .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
2552                 .ops = &hsw_power_well_ops,
2553                 .id = DISP_PW_ID_NONE,
2554                 {
2555                         .hsw.regs = &hsw_power_well_regs,
2556                         .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
2557                 },
2558         },
2559         {
2560                 .name = "DDI C IO power well",
2561                 .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
2562                 .ops = &hsw_power_well_ops,
2563                 .id = DISP_PW_ID_NONE,
2564                 {
2565                         .hsw.regs = &hsw_power_well_regs,
2566                         .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
2567                 },
2568         },
2569 };
2570
2571 static const struct i915_power_well_desc cnl_power_wells[] = {
2572         {
2573                 .name = "always-on",
2574                 .always_on = 1,
2575                 .domains = POWER_DOMAIN_MASK,
2576                 .ops = &i9xx_always_on_power_well_ops,
2577                 .id = DISP_PW_ID_NONE,
2578         },
2579         {
2580                 .name = "power well 1",
2581                 /* Handled by the DMC firmware */
2582                 .domains = 0,
2583                 .ops = &hsw_power_well_ops,
2584                 .id = SKL_DISP_PW_1,
2585                 {
2586                         .hsw.regs = &hsw_power_well_regs,
2587                         .hsw.idx = SKL_PW_CTL_IDX_PW_1,
2588                         .hsw.has_fuses = true,
2589                 },
2590         },
2591         {
2592                 .name = "AUX A",
2593                 .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
2594                 .ops = &hsw_power_well_ops,
2595                 .id = DISP_PW_ID_NONE,
2596                 {
2597                         .hsw.regs = &hsw_power_well_regs,
2598                         .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
2599                 },
2600         },
2601         {
2602                 .name = "AUX B",
2603                 .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
2604                 .ops = &hsw_power_well_ops,
2605                 .id = DISP_PW_ID_NONE,
2606                 {
2607                         .hsw.regs = &hsw_power_well_regs,
2608                         .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
2609                 },
2610         },
2611         {
2612                 .name = "AUX C",
2613                 .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
2614                 .ops = &hsw_power_well_ops,
2615                 .id = DISP_PW_ID_NONE,
2616                 {
2617                         .hsw.regs = &hsw_power_well_regs,
2618                         .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
2619                 },
2620         },
2621         {
2622                 .name = "AUX D",
2623                 .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
2624                 .ops = &hsw_power_well_ops,
2625                 .id = DISP_PW_ID_NONE,
2626                 {
2627                         .hsw.regs = &hsw_power_well_regs,
2628                         .hsw.idx = CNL_PW_CTL_IDX_AUX_D,
2629                 },
2630         },
2631         {
2632                 .name = "DC off",
2633                 .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
2634                 .ops = &gen9_dc_off_power_well_ops,
2635                 .id = DISP_PW_ID_NONE,
2636         },
2637         {
2638                 .name = "power well 2",
2639                 .domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2640                 .ops = &hsw_power_well_ops,
2641                 .id = SKL_DISP_PW_2,
2642                 {
2643                         .hsw.regs = &hsw_power_well_regs,
2644                         .hsw.idx = SKL_PW_CTL_IDX_PW_2,
2645                         .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2646                         .hsw.has_vga = true,
2647                         .hsw.has_fuses = true,
2648                 },
2649         },
2650         {
2651                 .name = "DDI A IO power well",
2652                 .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
2653                 .ops = &hsw_power_well_ops,
2654                 .id = DISP_PW_ID_NONE,
2655                 {
2656                         .hsw.regs = &hsw_power_well_regs,
2657                         .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
2658                 },
2659         },
2660         {
2661                 .name = "DDI B IO power well",
2662                 .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
2663                 .ops = &hsw_power_well_ops,
2664                 .id = DISP_PW_ID_NONE,
2665                 {
2666                         .hsw.regs = &hsw_power_well_regs,
2667                         .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
2668                 },
2669         },
2670         {
2671                 .name = "DDI C IO power well",
2672                 .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
2673                 .ops = &hsw_power_well_ops,
2674                 .id = DISP_PW_ID_NONE,
2675                 {
2676                         .hsw.regs = &hsw_power_well_regs,
2677                         .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
2678                 },
2679         },
2680         {
2681                 .name = "DDI D IO power well",
2682                 .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
2683                 .ops = &hsw_power_well_ops,
2684                 .id = DISP_PW_ID_NONE,
2685                 {
2686                         .hsw.regs = &hsw_power_well_regs,
2687                         .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
2688                 },
2689         },
2690         {
2691                 .name = "DDI F IO power well",
2692                 .domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
2693                 .ops = &hsw_power_well_ops,
2694                 .id = DISP_PW_ID_NONE,
2695                 {
2696                         .hsw.regs = &hsw_power_well_regs,
2697                         .hsw.idx = CNL_PW_CTL_IDX_DDI_F,
2698                 },
2699         },
2700         {
2701                 .name = "AUX F",
2702                 .domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
2703                 .ops = &hsw_power_well_ops,
2704                 .id = DISP_PW_ID_NONE,
2705                 {
2706                         .hsw.regs = &hsw_power_well_regs,
2707                         .hsw.idx = CNL_PW_CTL_IDX_AUX_F,
2708                 },
2709         },
2710 };
2711
2712 static const struct i915_power_well_ops icl_combo_phy_aux_power_well_ops = {
2713         .sync_hw = hsw_power_well_sync_hw,
2714         .enable = icl_combo_phy_aux_power_well_enable,
2715         .disable = icl_combo_phy_aux_power_well_disable,
2716         .is_enabled = hsw_power_well_enabled,
2717 };
2718
2719 static const struct i915_power_well_regs icl_aux_power_well_regs = {
2720         .bios   = ICL_PWR_WELL_CTL_AUX1,
2721         .driver = ICL_PWR_WELL_CTL_AUX2,
2722         .debug  = ICL_PWR_WELL_CTL_AUX4,
2723 };
2724
2725 static const struct i915_power_well_regs icl_ddi_power_well_regs = {
2726         .bios   = ICL_PWR_WELL_CTL_DDI1,
2727         .driver = ICL_PWR_WELL_CTL_DDI2,
2728         .debug  = ICL_PWR_WELL_CTL_DDI4,
2729 };
2730
2731 static const struct i915_power_well_desc icl_power_wells[] = {
2732         {
2733                 .name = "always-on",
2734                 .always_on = 1,
2735                 .domains = POWER_DOMAIN_MASK,
2736                 .ops = &i9xx_always_on_power_well_ops,
2737                 .id = DISP_PW_ID_NONE,
2738         },
2739         {
2740                 .name = "power well 1",
2741                 /* Handled by the DMC firmware */
2742                 .domains = 0,
2743                 .ops = &hsw_power_well_ops,
2744                 .id = SKL_DISP_PW_1,
2745                 {
2746                         .hsw.regs = &hsw_power_well_regs,
2747                         .hsw.idx = ICL_PW_CTL_IDX_PW_1,
2748                         .hsw.has_fuses = true,
2749                 },
2750         },
2751         {
2752                 .name = "DC off",
2753                 .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
2754                 .ops = &gen9_dc_off_power_well_ops,
2755                 .id = DISP_PW_ID_NONE,
2756         },
2757         {
2758                 .name = "power well 2",
2759                 .domains = ICL_PW_2_POWER_DOMAINS,
2760                 .ops = &hsw_power_well_ops,
2761                 .id = SKL_DISP_PW_2,
2762                 {
2763                         .hsw.regs = &hsw_power_well_regs,
2764                         .hsw.idx = ICL_PW_CTL_IDX_PW_2,
2765                         .hsw.has_fuses = true,
2766                 },
2767         },
2768         {
2769                 .name = "power well 3",
2770                 .domains = ICL_PW_3_POWER_DOMAINS,
2771                 .ops = &hsw_power_well_ops,
2772                 .id = DISP_PW_ID_NONE,
2773                 {
2774                         .hsw.regs = &hsw_power_well_regs,
2775                         .hsw.idx = ICL_PW_CTL_IDX_PW_3,
2776                         .hsw.irq_pipe_mask = BIT(PIPE_B),
2777                         .hsw.has_vga = true,
2778                         .hsw.has_fuses = true,
2779                 },
2780         },
2781         {
2782                 .name = "DDI A IO",
2783                 .domains = ICL_DDI_IO_A_POWER_DOMAINS,
2784                 .ops = &hsw_power_well_ops,
2785                 .id = DISP_PW_ID_NONE,
2786                 {
2787                         .hsw.regs = &icl_ddi_power_well_regs,
2788                         .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
2789                 },
2790         },
2791         {
2792                 .name = "DDI B IO",
2793                 .domains = ICL_DDI_IO_B_POWER_DOMAINS,
2794                 .ops = &hsw_power_well_ops,
2795                 .id = DISP_PW_ID_NONE,
2796                 {
2797                         .hsw.regs = &icl_ddi_power_well_regs,
2798                         .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
2799                 },
2800         },
2801         {
2802                 .name = "DDI C IO",
2803                 .domains = ICL_DDI_IO_C_POWER_DOMAINS,
2804                 .ops = &hsw_power_well_ops,
2805                 .id = DISP_PW_ID_NONE,
2806                 {
2807                         .hsw.regs = &icl_ddi_power_well_regs,
2808                         .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
2809                 },
2810         },
2811         {
2812                 .name = "DDI D IO",
2813                 .domains = ICL_DDI_IO_D_POWER_DOMAINS,
2814                 .ops = &hsw_power_well_ops,
2815                 .id = DISP_PW_ID_NONE,
2816                 {
2817                         .hsw.regs = &icl_ddi_power_well_regs,
2818                         .hsw.idx = ICL_PW_CTL_IDX_DDI_D,
2819                 },
2820         },
2821         {
2822                 .name = "DDI E IO",
2823                 .domains = ICL_DDI_IO_E_POWER_DOMAINS,
2824                 .ops = &hsw_power_well_ops,
2825                 .id = DISP_PW_ID_NONE,
2826                 {
2827                         .hsw.regs = &icl_ddi_power_well_regs,
2828                         .hsw.idx = ICL_PW_CTL_IDX_DDI_E,
2829                 },
2830         },
2831         {
2832                 .name = "DDI F IO",
2833                 .domains = ICL_DDI_IO_F_POWER_DOMAINS,
2834                 .ops = &hsw_power_well_ops,
2835                 .id = DISP_PW_ID_NONE,
2836                 {
2837                         .hsw.regs = &icl_ddi_power_well_regs,
2838                         .hsw.idx = ICL_PW_CTL_IDX_DDI_F,
2839                 },
2840         },
2841         {
2842                 .name = "AUX A",
2843                 .domains = ICL_AUX_A_IO_POWER_DOMAINS,
2844                 .ops = &icl_combo_phy_aux_power_well_ops,
2845                 .id = DISP_PW_ID_NONE,
2846                 {
2847                         .hsw.regs = &icl_aux_power_well_regs,
2848                         .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
2849                 },
2850         },
2851         {
2852                 .name = "AUX B",
2853                 .domains = ICL_AUX_B_IO_POWER_DOMAINS,
2854                 .ops = &icl_combo_phy_aux_power_well_ops,
2855                 .id = DISP_PW_ID_NONE,
2856                 {
2857                         .hsw.regs = &icl_aux_power_well_regs,
2858                         .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
2859                 },
2860         },
2861         {
2862                 .name = "AUX C",
2863                 .domains = ICL_AUX_C_IO_POWER_DOMAINS,
2864                 .ops = &hsw_power_well_ops,
2865                 .id = DISP_PW_ID_NONE,
2866                 {
2867                         .hsw.regs = &icl_aux_power_well_regs,
2868                         .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
2869                 },
2870         },
2871         {
2872                 .name = "AUX D",
2873                 .domains = ICL_AUX_D_IO_POWER_DOMAINS,
2874                 .ops = &hsw_power_well_ops,
2875                 .id = DISP_PW_ID_NONE,
2876                 {
2877                         .hsw.regs = &icl_aux_power_well_regs,
2878                         .hsw.idx = ICL_PW_CTL_IDX_AUX_D,
2879                 },
2880         },
2881         {
2882                 .name = "AUX E",
2883                 .domains = ICL_AUX_E_IO_POWER_DOMAINS,
2884                 .ops = &hsw_power_well_ops,
2885                 .id = DISP_PW_ID_NONE,
2886                 {
2887                         .hsw.regs = &icl_aux_power_well_regs,
2888                         .hsw.idx = ICL_PW_CTL_IDX_AUX_E,
2889                 },
2890         },
2891         {
2892                 .name = "AUX F",
2893                 .domains = ICL_AUX_F_IO_POWER_DOMAINS,
2894                 .ops = &hsw_power_well_ops,
2895                 .id = DISP_PW_ID_NONE,
2896                 {
2897                         .hsw.regs = &icl_aux_power_well_regs,
2898                         .hsw.idx = ICL_PW_CTL_IDX_AUX_F,
2899                 },
2900         },
2901         {
2902                 .name = "AUX TBT1",
2903                 .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
2904                 .ops = &hsw_power_well_ops,
2905                 .id = DISP_PW_ID_NONE,
2906                 {
2907                         .hsw.regs = &icl_aux_power_well_regs,
2908                         .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
2909                 },
2910         },
2911         {
2912                 .name = "AUX TBT2",
2913                 .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
2914                 .ops = &hsw_power_well_ops,
2915                 .id = DISP_PW_ID_NONE,
2916                 {
2917                         .hsw.regs = &icl_aux_power_well_regs,
2918                         .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
2919                 },
2920         },
2921         {
2922                 .name = "AUX TBT3",
2923                 .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
2924                 .ops = &hsw_power_well_ops,
2925                 .id = DISP_PW_ID_NONE,
2926                 {
2927                         .hsw.regs = &icl_aux_power_well_regs,
2928                         .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
2929                 },
2930         },
2931         {
2932                 .name = "AUX TBT4",
2933                 .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
2934                 .ops = &hsw_power_well_ops,
2935                 .id = DISP_PW_ID_NONE,
2936                 {
2937                         .hsw.regs = &icl_aux_power_well_regs,
2938                         .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
2939                 },
2940         },
2941         {
2942                 .name = "power well 4",
2943                 .domains = ICL_PW_4_POWER_DOMAINS,
2944                 .ops = &hsw_power_well_ops,
2945                 .id = DISP_PW_ID_NONE,
2946                 {
2947                         .hsw.regs = &hsw_power_well_regs,
2948                         .hsw.idx = ICL_PW_CTL_IDX_PW_4,
2949                         .hsw.has_fuses = true,
2950                         .hsw.irq_pipe_mask = BIT(PIPE_C),
2951                 },
2952         },
2953 };
2954
2955 static int
2956 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
2957                                    int disable_power_well)
2958 {
2959         if (disable_power_well >= 0)
2960                 return !!disable_power_well;
2961
2962         return 1;
2963 }
2964
2965 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
2966                                     int enable_dc)
2967 {
2968         uint32_t mask;
2969         int requested_dc;
2970         int max_dc;
2971
2972         if (IS_GEN9_BC(dev_priv) || INTEL_INFO(dev_priv)->gen >= 10) {
2973                 max_dc = 2;
2974                 mask = 0;
2975         } else if (IS_GEN9_LP(dev_priv)) {
2976                 max_dc = 1;
2977                 /*
2978                  * DC9 has a separate HW flow from the rest of the DC states,
2979                  * not depending on the DMC firmware. It's needed by system
2980                  * suspend/resume, so allow it unconditionally.
2981                  */
2982                 mask = DC_STATE_EN_DC9;
2983         } else {
2984                 max_dc = 0;
2985                 mask = 0;
2986         }