2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
37 intel_ring_initialized(struct intel_engine_cs *ring)
39 struct drm_device *dev = ring->dev;
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
50 return ring->buffer && ring->buffer->obj;
53 int __intel_ring_space(int head, int tail, int size)
55 int space = head - tail;
58 return space - I915_RING_FREE_SPACE;
61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
78 bool intel_ring_stopped(struct intel_engine_cs *ring)
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
84 void __intel_ring_advance(struct intel_engine_cs *ring)
86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88 if (intel_ring_stopped(ring))
90 ring->write_tail(ring, ringbuf->tail);
94 gen2_render_ring_flush(struct intel_engine_cs *ring,
95 u32 invalidate_domains,
102 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
103 cmd |= MI_NO_WRITE_FLUSH;
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
108 ret = intel_ring_begin(ring, 2);
112 intel_ring_emit(ring, cmd);
113 intel_ring_emit(ring, MI_NOOP);
114 intel_ring_advance(ring);
120 gen4_render_ring_flush(struct intel_engine_cs *ring,
121 u32 invalidate_domains,
124 struct drm_device *dev = ring->dev;
131 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
132 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
133 * also flushed at 2d versus 3d pipeline switches.
137 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
138 * MI_READ_FLUSH is set, and is always flushed on 965.
140 * I915_GEM_DOMAIN_COMMAND may not exist?
142 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
143 * invalidated when MI_EXE_FLUSH is set.
145 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
146 * invalidated with every MI_FLUSH.
150 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
151 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
152 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
153 * are flushed at any MI_FLUSH.
156 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
157 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
158 cmd &= ~MI_NO_WRITE_FLUSH;
159 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
162 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
163 (IS_G4X(dev) || IS_GEN5(dev)))
164 cmd |= MI_INVALIDATE_ISP;
166 ret = intel_ring_begin(ring, 2);
170 intel_ring_emit(ring, cmd);
171 intel_ring_emit(ring, MI_NOOP);
172 intel_ring_advance(ring);
178 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
179 * implementing two workarounds on gen6. From section 1.4.7.1
180 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
182 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
183 * produced by non-pipelined state commands), software needs to first
184 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
187 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
188 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
190 * And the workaround for these two requires this workaround first:
192 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
193 * BEFORE the pipe-control with a post-sync op and no write-cache
196 * And this last workaround is tricky because of the requirements on
197 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
200 * "1 of the following must also be set:
201 * - Render Target Cache Flush Enable ([12] of DW1)
202 * - Depth Cache Flush Enable ([0] of DW1)
203 * - Stall at Pixel Scoreboard ([1] of DW1)
204 * - Depth Stall ([13] of DW1)
205 * - Post-Sync Operation ([13] of DW1)
206 * - Notify Enable ([8] of DW1)"
208 * The cache flushes require the workaround flush that triggered this
209 * one, so we can't use it. Depth stall would trigger the same.
210 * Post-sync nonzero is what triggered this second workaround, so we
211 * can't use that one either. Notify enable is IRQs, which aren't
212 * really our business. That leaves only stall at scoreboard.
215 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
217 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
221 ret = intel_ring_begin(ring, 6);
225 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
226 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
227 PIPE_CONTROL_STALL_AT_SCOREBOARD);
228 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
229 intel_ring_emit(ring, 0); /* low dword */
230 intel_ring_emit(ring, 0); /* high dword */
231 intel_ring_emit(ring, MI_NOOP);
232 intel_ring_advance(ring);
234 ret = intel_ring_begin(ring, 6);
238 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
239 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
240 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
241 intel_ring_emit(ring, 0);
242 intel_ring_emit(ring, 0);
243 intel_ring_emit(ring, MI_NOOP);
244 intel_ring_advance(ring);
250 gen6_render_ring_flush(struct intel_engine_cs *ring,
251 u32 invalidate_domains, u32 flush_domains)
254 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
257 /* Force SNB workarounds for PIPE_CONTROL flushes */
258 ret = intel_emit_post_sync_nonzero_flush(ring);
262 /* Just flush everything. Experiments have shown that reducing the
263 * number of bits based on the write domains has little performance
267 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
268 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
270 * Ensure that any following seqno writes only happen
271 * when the render cache is indeed flushed.
273 flags |= PIPE_CONTROL_CS_STALL;
275 if (invalidate_domains) {
276 flags |= PIPE_CONTROL_TLB_INVALIDATE;
277 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
278 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
279 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
280 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
283 * TLB invalidate requires a post-sync write.
285 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
288 ret = intel_ring_begin(ring, 4);
292 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
293 intel_ring_emit(ring, flags);
294 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
295 intel_ring_emit(ring, 0);
296 intel_ring_advance(ring);
302 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
306 ret = intel_ring_begin(ring, 4);
310 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
311 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
312 PIPE_CONTROL_STALL_AT_SCOREBOARD);
313 intel_ring_emit(ring, 0);
314 intel_ring_emit(ring, 0);
315 intel_ring_advance(ring);
320 static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
324 if (!ring->fbc_dirty)
327 ret = intel_ring_begin(ring, 6);
330 /* WaFbcNukeOn3DBlt:ivb/hsw */
331 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
332 intel_ring_emit(ring, MSG_FBC_REND_STATE);
333 intel_ring_emit(ring, value);
334 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
335 intel_ring_emit(ring, MSG_FBC_REND_STATE);
336 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
337 intel_ring_advance(ring);
339 ring->fbc_dirty = false;
344 gen7_render_ring_flush(struct intel_engine_cs *ring,
345 u32 invalidate_domains, u32 flush_domains)
348 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
352 * Ensure that any following seqno writes only happen when the render
353 * cache is indeed flushed.
355 * Workaround: 4th PIPE_CONTROL command (except the ones with only
356 * read-cache invalidate bits set) must have the CS_STALL bit set. We
357 * don't try to be clever and just set it unconditionally.
359 flags |= PIPE_CONTROL_CS_STALL;
361 /* Just flush everything. Experiments have shown that reducing the
362 * number of bits based on the write domains has little performance
366 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
367 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
369 if (invalidate_domains) {
370 flags |= PIPE_CONTROL_TLB_INVALIDATE;
371 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
372 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
373 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
374 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
375 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
376 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
378 * TLB invalidate requires a post-sync write.
380 flags |= PIPE_CONTROL_QW_WRITE;
381 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
383 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
385 /* Workaround: we must issue a pipe_control with CS-stall bit
386 * set before a pipe_control command that has the state cache
387 * invalidate bit set. */
388 gen7_render_ring_cs_stall_wa(ring);
391 ret = intel_ring_begin(ring, 4);
395 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
396 intel_ring_emit(ring, flags);
397 intel_ring_emit(ring, scratch_addr);
398 intel_ring_emit(ring, 0);
399 intel_ring_advance(ring);
401 if (!invalidate_domains && flush_domains)
402 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
408 gen8_emit_pipe_control(struct intel_engine_cs *ring,
409 u32 flags, u32 scratch_addr)
413 ret = intel_ring_begin(ring, 6);
417 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
418 intel_ring_emit(ring, flags);
419 intel_ring_emit(ring, scratch_addr);
420 intel_ring_emit(ring, 0);
421 intel_ring_emit(ring, 0);
422 intel_ring_emit(ring, 0);
423 intel_ring_advance(ring);
429 gen8_render_ring_flush(struct intel_engine_cs *ring,
430 u32 invalidate_domains, u32 flush_domains)
433 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
436 flags |= PIPE_CONTROL_CS_STALL;
439 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
440 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
442 if (invalidate_domains) {
443 flags |= PIPE_CONTROL_TLB_INVALIDATE;
444 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
445 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
446 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
447 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
448 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
449 flags |= PIPE_CONTROL_QW_WRITE;
450 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
452 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
453 ret = gen8_emit_pipe_control(ring,
454 PIPE_CONTROL_CS_STALL |
455 PIPE_CONTROL_STALL_AT_SCOREBOARD,
461 ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
465 if (!invalidate_domains && flush_domains)
466 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
471 static void ring_write_tail(struct intel_engine_cs *ring,
474 struct drm_i915_private *dev_priv = ring->dev->dev_private;
475 I915_WRITE_TAIL(ring, value);
478 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
480 struct drm_i915_private *dev_priv = ring->dev->dev_private;
483 if (INTEL_INFO(ring->dev)->gen >= 8)
484 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
485 RING_ACTHD_UDW(ring->mmio_base));
486 else if (INTEL_INFO(ring->dev)->gen >= 4)
487 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
489 acthd = I915_READ(ACTHD);
494 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
496 struct drm_i915_private *dev_priv = ring->dev->dev_private;
499 addr = dev_priv->status_page_dmah->busaddr;
500 if (INTEL_INFO(ring->dev)->gen >= 4)
501 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
502 I915_WRITE(HWS_PGA, addr);
505 static bool stop_ring(struct intel_engine_cs *ring)
507 struct drm_i915_private *dev_priv = to_i915(ring->dev);
509 if (!IS_GEN2(ring->dev)) {
510 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
511 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
512 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
513 /* Sometimes we observe that the idle flag is not
514 * set even though the ring is empty. So double
515 * check before giving up.
517 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
522 I915_WRITE_CTL(ring, 0);
523 I915_WRITE_HEAD(ring, 0);
524 ring->write_tail(ring, 0);
526 if (!IS_GEN2(ring->dev)) {
527 (void)I915_READ_CTL(ring);
528 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
531 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
534 static int init_ring_common(struct intel_engine_cs *ring)
536 struct drm_device *dev = ring->dev;
537 struct drm_i915_private *dev_priv = dev->dev_private;
538 struct intel_ringbuffer *ringbuf = ring->buffer;
539 struct drm_i915_gem_object *obj = ringbuf->obj;
542 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
544 if (!stop_ring(ring)) {
545 /* G45 ring initialization often fails to reset head to zero */
546 DRM_DEBUG_KMS("%s head not reset to zero "
547 "ctl %08x head %08x tail %08x start %08x\n",
550 I915_READ_HEAD(ring),
551 I915_READ_TAIL(ring),
552 I915_READ_START(ring));
554 if (!stop_ring(ring)) {
555 DRM_ERROR("failed to set %s head to zero "
556 "ctl %08x head %08x tail %08x start %08x\n",
559 I915_READ_HEAD(ring),
560 I915_READ_TAIL(ring),
561 I915_READ_START(ring));
567 if (I915_NEED_GFX_HWS(dev))
568 intel_ring_setup_status_page(ring);
570 ring_setup_phys_status_page(ring);
572 /* Enforce ordering by reading HEAD register back */
573 I915_READ_HEAD(ring);
575 /* Initialize the ring. This must happen _after_ we've cleared the ring
576 * registers with the above sequence (the readback of the HEAD registers
577 * also enforces ordering), otherwise the hw might lose the new ring
578 * register values. */
579 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
581 /* WaClearRingBufHeadRegAtInit:ctg,elk */
582 if (I915_READ_HEAD(ring))
583 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
584 ring->name, I915_READ_HEAD(ring));
585 I915_WRITE_HEAD(ring, 0);
586 (void)I915_READ_HEAD(ring);
589 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
592 /* If the head is still not zero, the ring is dead */
593 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
594 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
595 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
596 DRM_ERROR("%s initialization failed "
597 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
599 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
600 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
601 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
606 ringbuf->last_retired_head = -1;
607 ringbuf->head = I915_READ_HEAD(ring);
608 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
609 intel_ring_update_space(ringbuf);
611 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
614 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
620 intel_fini_pipe_control(struct intel_engine_cs *ring)
622 struct drm_device *dev = ring->dev;
624 if (ring->scratch.obj == NULL)
627 if (INTEL_INFO(dev)->gen >= 5) {
628 kunmap(sg_page(ring->scratch.obj->pages->sgl));
629 i915_gem_object_ggtt_unpin(ring->scratch.obj);
632 drm_gem_object_unreference(&ring->scratch.obj->base);
633 ring->scratch.obj = NULL;
637 intel_init_pipe_control(struct intel_engine_cs *ring)
641 WARN_ON(ring->scratch.obj);
643 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
644 if (ring->scratch.obj == NULL) {
645 DRM_ERROR("Failed to allocate seqno page\n");
650 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
654 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
658 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
659 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
660 if (ring->scratch.cpu_page == NULL) {
665 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
666 ring->name, ring->scratch.gtt_offset);
670 i915_gem_object_ggtt_unpin(ring->scratch.obj);
672 drm_gem_object_unreference(&ring->scratch.obj->base);
677 static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
678 struct intel_context *ctx)
681 struct drm_device *dev = ring->dev;
682 struct drm_i915_private *dev_priv = dev->dev_private;
683 struct i915_workarounds *w = &dev_priv->workarounds;
685 if (WARN_ON_ONCE(w->count == 0))
688 ring->gpu_caches_dirty = true;
689 ret = intel_ring_flush_all_caches(ring);
693 ret = intel_ring_begin(ring, (w->count * 2 + 2));
697 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
698 for (i = 0; i < w->count; i++) {
699 intel_ring_emit(ring, w->reg[i].addr);
700 intel_ring_emit(ring, w->reg[i].value);
702 intel_ring_emit(ring, MI_NOOP);
704 intel_ring_advance(ring);
706 ring->gpu_caches_dirty = true;
707 ret = intel_ring_flush_all_caches(ring);
711 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
716 static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
717 struct intel_context *ctx)
721 ret = intel_ring_workarounds_emit(ring, ctx);
725 ret = i915_gem_render_state_init(ring);
727 DRM_ERROR("init render state: %d\n", ret);
732 static int wa_add(struct drm_i915_private *dev_priv,
733 const u32 addr, const u32 mask, const u32 val)
735 const u32 idx = dev_priv->workarounds.count;
737 if (WARN_ON(idx >= I915_MAX_WA_REGS))
740 dev_priv->workarounds.reg[idx].addr = addr;
741 dev_priv->workarounds.reg[idx].value = val;
742 dev_priv->workarounds.reg[idx].mask = mask;
744 dev_priv->workarounds.count++;
749 #define WA_REG(addr, mask, val) { \
750 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
755 #define WA_SET_BIT_MASKED(addr, mask) \
756 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
758 #define WA_CLR_BIT_MASKED(addr, mask) \
759 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
761 #define WA_SET_FIELD_MASKED(addr, mask, value) \
762 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
764 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
765 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
767 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
769 static int bdw_init_workarounds(struct intel_engine_cs *ring)
771 struct drm_device *dev = ring->dev;
772 struct drm_i915_private *dev_priv = dev->dev_private;
774 /* WaDisablePartialInstShootdown:bdw */
775 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
776 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
777 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
778 STALL_DOP_GATING_DISABLE);
780 /* WaDisableDopClockGating:bdw */
781 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
782 DOP_CLOCK_GATING_DISABLE);
784 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
785 GEN8_SAMPLER_POWER_BYPASS_DIS);
787 /* Use Force Non-Coherent whenever executing a 3D context. This is a
788 * workaround for for a possible hang in the unlikely event a TLB
789 * invalidation occurs during a PSD flush.
791 /* WaForceEnableNonCoherent:bdw */
792 /* WaHdcDisableFetchWhenMasked:bdw */
793 /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
794 WA_SET_BIT_MASKED(HDC_CHICKEN0,
795 HDC_FORCE_NON_COHERENT |
796 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
797 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
799 /* Wa4x4STCOptimizationDisable:bdw */
800 WA_SET_BIT_MASKED(CACHE_MODE_1,
801 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
804 * BSpec recommends 8x4 when MSAA is used,
805 * however in practice 16x4 seems fastest.
807 * Note that PS/WM thread counts depend on the WIZ hashing
808 * disable bit, which we don't touch here, but it's good
809 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
811 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
812 GEN6_WIZ_HASHING_MASK,
813 GEN6_WIZ_HASHING_16x4);
818 static int chv_init_workarounds(struct intel_engine_cs *ring)
820 struct drm_device *dev = ring->dev;
821 struct drm_i915_private *dev_priv = dev->dev_private;
823 /* WaDisablePartialInstShootdown:chv */
824 /* WaDisableThreadStallDopClockGating:chv */
825 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
826 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
827 STALL_DOP_GATING_DISABLE);
829 /* Use Force Non-Coherent whenever executing a 3D context. This is a
830 * workaround for a possible hang in the unlikely event a TLB
831 * invalidation occurs during a PSD flush.
833 /* WaForceEnableNonCoherent:chv */
834 /* WaHdcDisableFetchWhenMasked:chv */
835 WA_SET_BIT_MASKED(HDC_CHICKEN0,
836 HDC_FORCE_NON_COHERENT |
837 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
839 /* Improve HiZ throughput on CHV. */
840 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
845 int init_workarounds_ring(struct intel_engine_cs *ring)
847 struct drm_device *dev = ring->dev;
848 struct drm_i915_private *dev_priv = dev->dev_private;
850 WARN_ON(ring->id != RCS);
852 dev_priv->workarounds.count = 0;
854 if (IS_BROADWELL(dev))
855 return bdw_init_workarounds(ring);
857 if (IS_CHERRYVIEW(dev))
858 return chv_init_workarounds(ring);
863 static int init_render_ring(struct intel_engine_cs *ring)
865 struct drm_device *dev = ring->dev;
866 struct drm_i915_private *dev_priv = dev->dev_private;
867 int ret = init_ring_common(ring);
871 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
872 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
873 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
875 /* We need to disable the AsyncFlip performance optimisations in order
876 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
877 * programmed to '1' on all products.
879 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
881 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
882 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
884 /* Required for the hardware to program scanline values for waiting */
885 /* WaEnableFlushTlbInvalidationMode:snb */
886 if (INTEL_INFO(dev)->gen == 6)
888 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
890 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
892 I915_WRITE(GFX_MODE_GEN7,
893 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
894 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
897 /* From the Sandybridge PRM, volume 1 part 3, page 24:
898 * "If this bit is set, STCunit will have LRA as replacement
899 * policy. [...] This bit must be reset. LRA replacement
900 * policy is not supported."
902 I915_WRITE(CACHE_MODE_0,
903 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
906 if (INTEL_INFO(dev)->gen >= 6)
907 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
910 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
912 return init_workarounds_ring(ring);
915 static void render_ring_cleanup(struct intel_engine_cs *ring)
917 struct drm_device *dev = ring->dev;
918 struct drm_i915_private *dev_priv = dev->dev_private;
920 if (dev_priv->semaphore_obj) {
921 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
922 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
923 dev_priv->semaphore_obj = NULL;
926 intel_fini_pipe_control(ring);
929 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
930 unsigned int num_dwords)
932 #define MBOX_UPDATE_DWORDS 8
933 struct drm_device *dev = signaller->dev;
934 struct drm_i915_private *dev_priv = dev->dev_private;
935 struct intel_engine_cs *waiter;
936 int i, ret, num_rings;
938 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
939 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
940 #undef MBOX_UPDATE_DWORDS
942 ret = intel_ring_begin(signaller, num_dwords);
946 for_each_ring(waiter, dev_priv, i) {
948 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
949 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
952 seqno = i915_gem_request_get_seqno(
953 signaller->outstanding_lazy_request);
954 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
955 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
956 PIPE_CONTROL_QW_WRITE |
957 PIPE_CONTROL_FLUSH_ENABLE);
958 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
959 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
960 intel_ring_emit(signaller, seqno);
961 intel_ring_emit(signaller, 0);
962 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
963 MI_SEMAPHORE_TARGET(waiter->id));
964 intel_ring_emit(signaller, 0);
970 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
971 unsigned int num_dwords)
973 #define MBOX_UPDATE_DWORDS 6
974 struct drm_device *dev = signaller->dev;
975 struct drm_i915_private *dev_priv = dev->dev_private;
976 struct intel_engine_cs *waiter;
977 int i, ret, num_rings;
979 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
980 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
981 #undef MBOX_UPDATE_DWORDS
983 ret = intel_ring_begin(signaller, num_dwords);
987 for_each_ring(waiter, dev_priv, i) {
989 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
990 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
993 seqno = i915_gem_request_get_seqno(
994 signaller->outstanding_lazy_request);
995 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
996 MI_FLUSH_DW_OP_STOREDW);
997 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
998 MI_FLUSH_DW_USE_GTT);
999 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1000 intel_ring_emit(signaller, seqno);
1001 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1002 MI_SEMAPHORE_TARGET(waiter->id));
1003 intel_ring_emit(signaller, 0);
1009 static int gen6_signal(struct intel_engine_cs *signaller,
1010 unsigned int num_dwords)
1012 struct drm_device *dev = signaller->dev;
1013 struct drm_i915_private *dev_priv = dev->dev_private;
1014 struct intel_engine_cs *useless;
1015 int i, ret, num_rings;
1017 #define MBOX_UPDATE_DWORDS 3
1018 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1019 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1020 #undef MBOX_UPDATE_DWORDS
1022 ret = intel_ring_begin(signaller, num_dwords);
1026 for_each_ring(useless, dev_priv, i) {
1027 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1028 if (mbox_reg != GEN6_NOSYNC) {
1029 u32 seqno = i915_gem_request_get_seqno(
1030 signaller->outstanding_lazy_request);
1031 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1032 intel_ring_emit(signaller, mbox_reg);
1033 intel_ring_emit(signaller, seqno);
1037 /* If num_dwords was rounded, make sure the tail pointer is correct */
1038 if (num_rings % 2 == 0)
1039 intel_ring_emit(signaller, MI_NOOP);
1045 * gen6_add_request - Update the semaphore mailbox registers
1047 * @ring - ring that is adding a request
1048 * @seqno - return seqno stuck into the ring
1050 * Update the mailbox registers in the *other* rings with the current seqno.
1051 * This acts like a signal in the canonical semaphore.
1054 gen6_add_request(struct intel_engine_cs *ring)
1058 if (ring->semaphore.signal)
1059 ret = ring->semaphore.signal(ring, 4);
1061 ret = intel_ring_begin(ring, 4);
1066 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1067 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1068 intel_ring_emit(ring,
1069 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1070 intel_ring_emit(ring, MI_USER_INTERRUPT);
1071 __intel_ring_advance(ring);
1076 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1079 struct drm_i915_private *dev_priv = dev->dev_private;
1080 return dev_priv->last_seqno < seqno;
1084 * intel_ring_sync - sync the waiter to the signaller on seqno
1086 * @waiter - ring that is waiting
1087 * @signaller - ring which has, or will signal
1088 * @seqno - seqno which the waiter will block on
1092 gen8_ring_sync(struct intel_engine_cs *waiter,
1093 struct intel_engine_cs *signaller,
1096 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1099 ret = intel_ring_begin(waiter, 4);
1103 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1104 MI_SEMAPHORE_GLOBAL_GTT |
1106 MI_SEMAPHORE_SAD_GTE_SDD);
1107 intel_ring_emit(waiter, seqno);
1108 intel_ring_emit(waiter,
1109 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1110 intel_ring_emit(waiter,
1111 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1112 intel_ring_advance(waiter);
1117 gen6_ring_sync(struct intel_engine_cs *waiter,
1118 struct intel_engine_cs *signaller,
1121 u32 dw1 = MI_SEMAPHORE_MBOX |
1122 MI_SEMAPHORE_COMPARE |
1123 MI_SEMAPHORE_REGISTER;
1124 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1127 /* Throughout all of the GEM code, seqno passed implies our current
1128 * seqno is >= the last seqno executed. However for hardware the
1129 * comparison is strictly greater than.
1133 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1135 ret = intel_ring_begin(waiter, 4);
1139 /* If seqno wrap happened, omit the wait with no-ops */
1140 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1141 intel_ring_emit(waiter, dw1 | wait_mbox);
1142 intel_ring_emit(waiter, seqno);
1143 intel_ring_emit(waiter, 0);
1144 intel_ring_emit(waiter, MI_NOOP);
1146 intel_ring_emit(waiter, MI_NOOP);
1147 intel_ring_emit(waiter, MI_NOOP);
1148 intel_ring_emit(waiter, MI_NOOP);
1149 intel_ring_emit(waiter, MI_NOOP);
1151 intel_ring_advance(waiter);
1156 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1158 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1159 PIPE_CONTROL_DEPTH_STALL); \
1160 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1161 intel_ring_emit(ring__, 0); \
1162 intel_ring_emit(ring__, 0); \
1166 pc_render_add_request(struct intel_engine_cs *ring)
1168 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1171 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1172 * incoherent with writes to memory, i.e. completely fubar,
1173 * so we need to use PIPE_NOTIFY instead.
1175 * However, we also need to workaround the qword write
1176 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1177 * memory before requesting an interrupt.
1179 ret = intel_ring_begin(ring, 32);
1183 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1184 PIPE_CONTROL_WRITE_FLUSH |
1185 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1186 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1187 intel_ring_emit(ring,
1188 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1189 intel_ring_emit(ring, 0);
1190 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1191 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1192 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1193 scratch_addr += 2 * CACHELINE_BYTES;
1194 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1195 scratch_addr += 2 * CACHELINE_BYTES;
1196 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1197 scratch_addr += 2 * CACHELINE_BYTES;
1198 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1199 scratch_addr += 2 * CACHELINE_BYTES;
1200 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1202 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1203 PIPE_CONTROL_WRITE_FLUSH |
1204 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1205 PIPE_CONTROL_NOTIFY);
1206 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1207 intel_ring_emit(ring,
1208 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1209 intel_ring_emit(ring, 0);
1210 __intel_ring_advance(ring);
1216 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1218 /* Workaround to force correct ordering between irq and seqno writes on
1219 * ivb (and maybe also on snb) by reading from a CS register (like
1220 * ACTHD) before reading the status page. */
1221 if (!lazy_coherency) {
1222 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1223 POSTING_READ(RING_ACTHD(ring->mmio_base));
1226 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1230 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1232 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1236 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1238 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1242 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1244 return ring->scratch.cpu_page[0];
1248 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1250 ring->scratch.cpu_page[0] = seqno;
1254 gen5_ring_get_irq(struct intel_engine_cs *ring)
1256 struct drm_device *dev = ring->dev;
1257 struct drm_i915_private *dev_priv = dev->dev_private;
1258 unsigned long flags;
1260 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1263 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1264 if (ring->irq_refcount++ == 0)
1265 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1266 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1272 gen5_ring_put_irq(struct intel_engine_cs *ring)
1274 struct drm_device *dev = ring->dev;
1275 struct drm_i915_private *dev_priv = dev->dev_private;
1276 unsigned long flags;
1278 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1279 if (--ring->irq_refcount == 0)
1280 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1281 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1285 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1287 struct drm_device *dev = ring->dev;
1288 struct drm_i915_private *dev_priv = dev->dev_private;
1289 unsigned long flags;
1291 if (!intel_irqs_enabled(dev_priv))
1294 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1295 if (ring->irq_refcount++ == 0) {
1296 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1297 I915_WRITE(IMR, dev_priv->irq_mask);
1300 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1306 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1308 struct drm_device *dev = ring->dev;
1309 struct drm_i915_private *dev_priv = dev->dev_private;
1310 unsigned long flags;
1312 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1313 if (--ring->irq_refcount == 0) {
1314 dev_priv->irq_mask |= ring->irq_enable_mask;
1315 I915_WRITE(IMR, dev_priv->irq_mask);
1318 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1322 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1324 struct drm_device *dev = ring->dev;
1325 struct drm_i915_private *dev_priv = dev->dev_private;
1326 unsigned long flags;
1328 if (!intel_irqs_enabled(dev_priv))
1331 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1332 if (ring->irq_refcount++ == 0) {
1333 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1334 I915_WRITE16(IMR, dev_priv->irq_mask);
1335 POSTING_READ16(IMR);
1337 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1343 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1345 struct drm_device *dev = ring->dev;
1346 struct drm_i915_private *dev_priv = dev->dev_private;
1347 unsigned long flags;
1349 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1350 if (--ring->irq_refcount == 0) {
1351 dev_priv->irq_mask |= ring->irq_enable_mask;
1352 I915_WRITE16(IMR, dev_priv->irq_mask);
1353 POSTING_READ16(IMR);
1355 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1358 void intel_ring_setup_status_page(struct intel_engine_cs *ring)
1360 struct drm_device *dev = ring->dev;
1361 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1364 /* The ring status page addresses are no longer next to the rest of
1365 * the ring registers as of gen7.
1370 mmio = RENDER_HWS_PGA_GEN7;
1373 mmio = BLT_HWS_PGA_GEN7;
1376 * VCS2 actually doesn't exist on Gen7. Only shut up
1377 * gcc switch check warning
1381 mmio = BSD_HWS_PGA_GEN7;
1384 mmio = VEBOX_HWS_PGA_GEN7;
1387 } else if (IS_GEN6(ring->dev)) {
1388 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1390 /* XXX: gen8 returns to sanity */
1391 mmio = RING_HWS_PGA(ring->mmio_base);
1394 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1398 * Flush the TLB for this page
1400 * FIXME: These two bits have disappeared on gen8, so a question
1401 * arises: do we still need this and if so how should we go about
1402 * invalidating the TLB?
1404 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
1405 u32 reg = RING_INSTPM(ring->mmio_base);
1407 /* ring should be idle before issuing a sync flush*/
1408 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1411 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1412 INSTPM_SYNC_FLUSH));
1413 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1415 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1421 bsd_ring_flush(struct intel_engine_cs *ring,
1422 u32 invalidate_domains,
1427 ret = intel_ring_begin(ring, 2);
1431 intel_ring_emit(ring, MI_FLUSH);
1432 intel_ring_emit(ring, MI_NOOP);
1433 intel_ring_advance(ring);
1438 i9xx_add_request(struct intel_engine_cs *ring)
1442 ret = intel_ring_begin(ring, 4);
1446 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1447 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1448 intel_ring_emit(ring,
1449 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1450 intel_ring_emit(ring, MI_USER_INTERRUPT);
1451 __intel_ring_advance(ring);
1457 gen6_ring_get_irq(struct intel_engine_cs *ring)
1459 struct drm_device *dev = ring->dev;
1460 struct drm_i915_private *dev_priv = dev->dev_private;
1461 unsigned long flags;
1463 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1466 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1467 if (ring->irq_refcount++ == 0) {
1468 if (HAS_L3_DPF(dev) && ring->id == RCS)
1469 I915_WRITE_IMR(ring,
1470 ~(ring->irq_enable_mask |
1471 GT_PARITY_ERROR(dev)));
1473 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1474 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1476 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1482 gen6_ring_put_irq(struct intel_engine_cs *ring)
1484 struct drm_device *dev = ring->dev;
1485 struct drm_i915_private *dev_priv = dev->dev_private;
1486 unsigned long flags;
1488 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1489 if (--ring->irq_refcount == 0) {
1490 if (HAS_L3_DPF(dev) && ring->id == RCS)
1491 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1493 I915_WRITE_IMR(ring, ~0);
1494 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1496 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1500 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1502 struct drm_device *dev = ring->dev;
1503 struct drm_i915_private *dev_priv = dev->dev_private;
1504 unsigned long flags;
1506 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1509 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1510 if (ring->irq_refcount++ == 0) {
1511 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1512 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1514 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1520 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1522 struct drm_device *dev = ring->dev;
1523 struct drm_i915_private *dev_priv = dev->dev_private;
1524 unsigned long flags;
1526 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1527 if (--ring->irq_refcount == 0) {
1528 I915_WRITE_IMR(ring, ~0);
1529 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1531 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1535 gen8_ring_get_irq(struct intel_engine_cs *ring)
1537 struct drm_device *dev = ring->dev;
1538 struct drm_i915_private *dev_priv = dev->dev_private;
1539 unsigned long flags;
1541 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1544 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1545 if (ring->irq_refcount++ == 0) {
1546 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1547 I915_WRITE_IMR(ring,
1548 ~(ring->irq_enable_mask |
1549 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1551 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1553 POSTING_READ(RING_IMR(ring->mmio_base));
1555 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1561 gen8_ring_put_irq(struct intel_engine_cs *ring)
1563 struct drm_device *dev = ring->dev;
1564 struct drm_i915_private *dev_priv = dev->dev_private;
1565 unsigned long flags;
1567 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1568 if (--ring->irq_refcount == 0) {
1569 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1570 I915_WRITE_IMR(ring,
1571 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1573 I915_WRITE_IMR(ring, ~0);
1575 POSTING_READ(RING_IMR(ring->mmio_base));
1577 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1581 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1582 u64 offset, u32 length,
1587 ret = intel_ring_begin(ring, 2);
1591 intel_ring_emit(ring,
1592 MI_BATCH_BUFFER_START |
1594 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1595 intel_ring_emit(ring, offset);
1596 intel_ring_advance(ring);
1601 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1602 #define I830_BATCH_LIMIT (256*1024)
1603 #define I830_TLB_ENTRIES (2)
1604 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1606 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1607 u64 offset, u32 len,
1610 u32 cs_offset = ring->scratch.gtt_offset;
1613 ret = intel_ring_begin(ring, 6);
1617 /* Evict the invalid PTE TLBs */
1618 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1619 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1620 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1621 intel_ring_emit(ring, cs_offset);
1622 intel_ring_emit(ring, 0xdeadbeef);
1623 intel_ring_emit(ring, MI_NOOP);
1624 intel_ring_advance(ring);
1626 if ((flags & I915_DISPATCH_PINNED) == 0) {
1627 if (len > I830_BATCH_LIMIT)
1630 ret = intel_ring_begin(ring, 6 + 2);
1634 /* Blit the batch (which has now all relocs applied) to the
1635 * stable batch scratch bo area (so that the CS never
1636 * stumbles over its tlb invalidation bug) ...
1638 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1639 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1640 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1641 intel_ring_emit(ring, cs_offset);
1642 intel_ring_emit(ring, 4096);
1643 intel_ring_emit(ring, offset);
1645 intel_ring_emit(ring, MI_FLUSH);
1646 intel_ring_emit(ring, MI_NOOP);
1647 intel_ring_advance(ring);
1649 /* ... and execute it. */
1653 ret = intel_ring_begin(ring, 4);
1657 intel_ring_emit(ring, MI_BATCH_BUFFER);
1658 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1659 intel_ring_emit(ring, offset + len - 8);
1660 intel_ring_emit(ring, MI_NOOP);
1661 intel_ring_advance(ring);
1667 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1668 u64 offset, u32 len,
1673 ret = intel_ring_begin(ring, 2);
1677 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1678 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1679 intel_ring_advance(ring);
1684 static void cleanup_status_page(struct intel_engine_cs *ring)
1686 struct drm_i915_gem_object *obj;
1688 obj = ring->status_page.obj;
1692 kunmap(sg_page(obj->pages->sgl));
1693 i915_gem_object_ggtt_unpin(obj);
1694 drm_gem_object_unreference(&obj->base);
1695 ring->status_page.obj = NULL;
1698 static int init_status_page(struct intel_engine_cs *ring)
1700 struct drm_i915_gem_object *obj;
1702 if ((obj = ring->status_page.obj) == NULL) {
1706 obj = i915_gem_alloc_object(ring->dev, 4096);
1708 DRM_ERROR("Failed to allocate status page\n");
1712 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1717 if (!HAS_LLC(ring->dev))
1718 /* On g33, we cannot place HWS above 256MiB, so
1719 * restrict its pinning to the low mappable arena.
1720 * Though this restriction is not documented for
1721 * gen4, gen5, or byt, they also behave similarly
1722 * and hang if the HWS is placed at the top of the
1723 * GTT. To generalise, it appears that all !llc
1724 * platforms have issues with us placing the HWS
1725 * above the mappable region (even though we never
1728 flags |= PIN_MAPPABLE;
1729 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1732 drm_gem_object_unreference(&obj->base);
1736 ring->status_page.obj = obj;
1739 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1740 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1741 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1743 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1744 ring->name, ring->status_page.gfx_addr);
1749 static int init_phys_status_page(struct intel_engine_cs *ring)
1751 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1753 if (!dev_priv->status_page_dmah) {
1754 dev_priv->status_page_dmah =
1755 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1756 if (!dev_priv->status_page_dmah)
1760 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1761 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1766 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1768 iounmap(ringbuf->virtual_start);
1769 ringbuf->virtual_start = NULL;
1770 i915_gem_object_ggtt_unpin(ringbuf->obj);
1773 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1774 struct intel_ringbuffer *ringbuf)
1776 struct drm_i915_private *dev_priv = to_i915(dev);
1777 struct drm_i915_gem_object *obj = ringbuf->obj;
1780 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1784 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1786 i915_gem_object_ggtt_unpin(obj);
1790 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1791 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1792 if (ringbuf->virtual_start == NULL) {
1793 i915_gem_object_ggtt_unpin(obj);
1800 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1802 drm_gem_object_unreference(&ringbuf->obj->base);
1803 ringbuf->obj = NULL;
1806 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1807 struct intel_ringbuffer *ringbuf)
1809 struct drm_i915_gem_object *obj;
1813 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1815 obj = i915_gem_alloc_object(dev, ringbuf->size);
1819 /* mark ring buffers as read-only from GPU side by default */
1827 static int intel_init_ring_buffer(struct drm_device *dev,
1828 struct intel_engine_cs *ring)
1830 struct intel_ringbuffer *ringbuf;
1833 WARN_ON(ring->buffer);
1835 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1838 ring->buffer = ringbuf;
1841 INIT_LIST_HEAD(&ring->active_list);
1842 INIT_LIST_HEAD(&ring->request_list);
1843 INIT_LIST_HEAD(&ring->execlist_queue);
1844 ringbuf->size = 32 * PAGE_SIZE;
1845 ringbuf->ring = ring;
1846 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
1848 init_waitqueue_head(&ring->irq_queue);
1850 if (I915_NEED_GFX_HWS(dev)) {
1851 ret = init_status_page(ring);
1855 BUG_ON(ring->id != RCS);
1856 ret = init_phys_status_page(ring);
1861 WARN_ON(ringbuf->obj);
1863 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1865 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
1870 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1872 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
1874 intel_destroy_ringbuffer_obj(ringbuf);
1878 /* Workaround an erratum on the i830 which causes a hang if
1879 * the TAIL pointer points to within the last 2 cachelines
1882 ringbuf->effective_size = ringbuf->size;
1883 if (IS_I830(dev) || IS_845G(dev))
1884 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
1886 ret = i915_cmd_parser_init_ring(ring);
1894 ring->buffer = NULL;
1898 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
1900 struct drm_i915_private *dev_priv;
1901 struct intel_ringbuffer *ringbuf;
1903 if (!intel_ring_initialized(ring))
1906 dev_priv = to_i915(ring->dev);
1907 ringbuf = ring->buffer;
1909 intel_stop_ring_buffer(ring);
1910 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
1912 intel_unpin_ringbuffer_obj(ringbuf);
1913 intel_destroy_ringbuffer_obj(ringbuf);
1914 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
1917 ring->cleanup(ring);
1919 cleanup_status_page(ring);
1921 i915_cmd_parser_fini_ring(ring);
1924 ring->buffer = NULL;
1927 static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
1929 struct intel_ringbuffer *ringbuf = ring->buffer;
1930 struct drm_i915_gem_request *request;
1933 if (intel_ring_space(ringbuf) >= n)
1936 list_for_each_entry(request, &ring->request_list, list) {
1937 if (__intel_ring_space(request->tail, ringbuf->tail,
1938 ringbuf->size) >= n) {
1943 if (&request->list == &ring->request_list)
1946 ret = i915_wait_request(request);
1950 i915_gem_retire_requests_ring(ring);
1955 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
1957 struct drm_device *dev = ring->dev;
1958 struct drm_i915_private *dev_priv = dev->dev_private;
1959 struct intel_ringbuffer *ringbuf = ring->buffer;
1963 ret = intel_ring_wait_request(ring, n);
1967 /* force the tail write in case we have been skipping them */
1968 __intel_ring_advance(ring);
1970 /* With GEM the hangcheck timer should kick us out of the loop,
1971 * leaving it early runs the risk of corrupting GEM state (due
1972 * to running on almost untested codepaths). But on resume
1973 * timers don't work yet, so prevent a complete hang in that
1974 * case by choosing an insanely large timeout. */
1975 end = jiffies + 60 * HZ;
1978 trace_i915_ring_wait_begin(ring);
1980 if (intel_ring_space(ringbuf) >= n)
1982 ringbuf->head = I915_READ_HEAD(ring);
1983 if (intel_ring_space(ringbuf) >= n)
1988 if (dev_priv->mm.interruptible && signal_pending(current)) {
1993 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1994 dev_priv->mm.interruptible);
1998 if (time_after(jiffies, end)) {
2003 trace_i915_ring_wait_end(ring);
2007 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
2009 uint32_t __iomem *virt;
2010 struct intel_ringbuffer *ringbuf = ring->buffer;
2011 int rem = ringbuf->size - ringbuf->tail;
2013 if (ringbuf->space < rem) {
2014 int ret = ring_wait_for_space(ring, rem);
2019 virt = ringbuf->virtual_start + ringbuf->tail;
2022 iowrite32(MI_NOOP, virt++);
2025 intel_ring_update_space(ringbuf);
2030 int intel_ring_idle(struct intel_engine_cs *ring)
2032 struct drm_i915_gem_request *req;
2035 /* We need to add any requests required to flush the objects and ring */
2036 if (ring->outstanding_lazy_request) {
2037 ret = i915_add_request(ring);
2042 /* Wait upon the last request to be completed */
2043 if (list_empty(&ring->request_list))
2046 req = list_entry(ring->request_list.prev,
2047 struct drm_i915_gem_request,
2050 return i915_wait_request(req);
2054 intel_ring_alloc_request(struct intel_engine_cs *ring)
2057 struct drm_i915_gem_request *request;
2058 struct drm_i915_private *dev_private = ring->dev->dev_private;
2060 if (ring->outstanding_lazy_request)
2063 request = kzalloc(sizeof(*request), GFP_KERNEL);
2064 if (request == NULL)
2067 kref_init(&request->ref);
2068 request->ring = ring;
2069 request->uniq = dev_private->request_uniq++;
2071 ret = i915_gem_get_seqno(ring->dev, &request->seqno);
2077 ring->outstanding_lazy_request = request;
2081 static int __intel_ring_prepare(struct intel_engine_cs *ring,
2084 struct intel_ringbuffer *ringbuf = ring->buffer;
2087 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2088 ret = intel_wrap_ring_buffer(ring);
2093 if (unlikely(ringbuf->space < bytes)) {
2094 ret = ring_wait_for_space(ring, bytes);
2102 int intel_ring_begin(struct intel_engine_cs *ring,
2105 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2108 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2109 dev_priv->mm.interruptible);
2113 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2117 /* Preallocate the olr before touching the ring */
2118 ret = intel_ring_alloc_request(ring);
2122 ring->buffer->space -= num_dwords * sizeof(uint32_t);
2126 /* Align the ring tail to a cacheline boundary */
2127 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2129 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2132 if (num_dwords == 0)
2135 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2136 ret = intel_ring_begin(ring, num_dwords);
2140 while (num_dwords--)
2141 intel_ring_emit(ring, MI_NOOP);
2143 intel_ring_advance(ring);
2148 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2150 struct drm_device *dev = ring->dev;
2151 struct drm_i915_private *dev_priv = dev->dev_private;
2153 BUG_ON(ring->outstanding_lazy_request);
2155 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2156 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2157 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2159 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2162 ring->set_seqno(ring, seqno);
2163 ring->hangcheck.seqno = seqno;
2166 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2169 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2171 /* Every tail move must follow the sequence below */
2173 /* Disable notification that the ring is IDLE. The GT
2174 * will then assume that it is busy and bring it out of rc6.
2176 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2177 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2179 /* Clear the context id. Here be magic! */
2180 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2182 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2183 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2184 GEN6_BSD_SLEEP_INDICATOR) == 0,
2186 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2188 /* Now that the ring is fully powered up, update the tail */
2189 I915_WRITE_TAIL(ring, value);
2190 POSTING_READ(RING_TAIL(ring->mmio_base));
2192 /* Let the ring send IDLE messages to the GT again,
2193 * and so let it sleep to conserve power when idle.
2195 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2196 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2199 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
2200 u32 invalidate, u32 flush)
2205 ret = intel_ring_begin(ring, 4);
2210 if (INTEL_INFO(ring->dev)->gen >= 8)
2213 * Bspec vol 1c.5 - video engine command streamer:
2214 * "If ENABLED, all TLBs will be invalidated once the flush
2215 * operation is complete. This bit is only valid when the
2216 * Post-Sync Operation field is a value of 1h or 3h."
2218 if (invalidate & I915_GEM_GPU_DOMAINS)
2219 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
2220 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2221 intel_ring_emit(ring, cmd);
2222 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2223 if (INTEL_INFO(ring->dev)->gen >= 8) {
2224 intel_ring_emit(ring, 0); /* upper addr */
2225 intel_ring_emit(ring, 0); /* value */
2227 intel_ring_emit(ring, 0);
2228 intel_ring_emit(ring, MI_NOOP);
2230 intel_ring_advance(ring);
2235 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2236 u64 offset, u32 len,
2239 bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
2242 ret = intel_ring_begin(ring, 4);
2246 /* FIXME(BDW): Address space and security selectors. */
2247 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2248 intel_ring_emit(ring, lower_32_bits(offset));
2249 intel_ring_emit(ring, upper_32_bits(offset));
2250 intel_ring_emit(ring, MI_NOOP);
2251 intel_ring_advance(ring);
2257 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2258 u64 offset, u32 len,
2263 ret = intel_ring_begin(ring, 2);
2267 intel_ring_emit(ring,
2268 MI_BATCH_BUFFER_START |
2269 (flags & I915_DISPATCH_SECURE ?
2270 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2271 /* bit0-7 is the length on GEN6+ */
2272 intel_ring_emit(ring, offset);
2273 intel_ring_advance(ring);
2279 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2280 u64 offset, u32 len,
2285 ret = intel_ring_begin(ring, 2);
2289 intel_ring_emit(ring,
2290 MI_BATCH_BUFFER_START |
2291 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
2292 /* bit0-7 is the length on GEN6+ */
2293 intel_ring_emit(ring, offset);
2294 intel_ring_advance(ring);
2299 /* Blitter support (SandyBridge+) */
2301 static int gen6_ring_flush(struct intel_engine_cs *ring,
2302 u32 invalidate, u32 flush)
2304 struct drm_device *dev = ring->dev;
2305 struct drm_i915_private *dev_priv = dev->dev_private;
2309 ret = intel_ring_begin(ring, 4);
2314 if (INTEL_INFO(ring->dev)->gen >= 8)
2317 * Bspec vol 1c.3 - blitter engine command streamer:
2318 * "If ENABLED, all TLBs will be invalidated once the flush
2319 * operation is complete. This bit is only valid when the
2320 * Post-Sync Operation field is a value of 1h or 3h."
2322 if (invalidate & I915_GEM_DOMAIN_RENDER)
2323 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
2324 MI_FLUSH_DW_OP_STOREDW;
2325 intel_ring_emit(ring, cmd);
2326 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2327 if (INTEL_INFO(ring->dev)->gen >= 8) {
2328 intel_ring_emit(ring, 0); /* upper addr */
2329 intel_ring_emit(ring, 0); /* value */
2331 intel_ring_emit(ring, 0);
2332 intel_ring_emit(ring, MI_NOOP);
2334 intel_ring_advance(ring);
2336 if (!invalidate && flush) {
2338 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2339 else if (IS_BROADWELL(dev))
2340 dev_priv->fbc.need_sw_cache_clean = true;
2346 int intel_init_render_ring_buffer(struct drm_device *dev)
2348 struct drm_i915_private *dev_priv = dev->dev_private;
2349 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2350 struct drm_i915_gem_object *obj;
2353 ring->name = "render ring";
2355 ring->mmio_base = RENDER_RING_BASE;
2357 if (INTEL_INFO(dev)->gen >= 8) {
2358 if (i915_semaphore_is_enabled(dev)) {
2359 obj = i915_gem_alloc_object(dev, 4096);
2361 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2362 i915.semaphores = 0;
2364 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2365 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2367 drm_gem_object_unreference(&obj->base);
2368 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2369 i915.semaphores = 0;
2371 dev_priv->semaphore_obj = obj;
2375 ring->init_context = intel_rcs_ctx_init;
2376 ring->add_request = gen6_add_request;
2377 ring->flush = gen8_render_ring_flush;
2378 ring->irq_get = gen8_ring_get_irq;
2379 ring->irq_put = gen8_ring_put_irq;
2380 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2381 ring->get_seqno = gen6_ring_get_seqno;
2382 ring->set_seqno = ring_set_seqno;
2383 if (i915_semaphore_is_enabled(dev)) {
2384 WARN_ON(!dev_priv->semaphore_obj);
2385 ring->semaphore.sync_to = gen8_ring_sync;
2386 ring->semaphore.signal = gen8_rcs_signal;
2387 GEN8_RING_SEMAPHORE_INIT;
2389 } else if (INTEL_INFO(dev)->gen >= 6) {
2390 ring->add_request = gen6_add_request;
2391 ring->flush = gen7_render_ring_flush;
2392 if (INTEL_INFO(dev)->gen == 6)
2393 ring->flush = gen6_render_ring_flush;
2394 ring->irq_get = gen6_ring_get_irq;
2395 ring->irq_put = gen6_ring_put_irq;
2396 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2397 ring->get_seqno = gen6_ring_get_seqno;
2398 ring->set_seqno = ring_set_seqno;
2399 if (i915_semaphore_is_enabled(dev)) {
2400 ring->semaphore.sync_to = gen6_ring_sync;
2401 ring->semaphore.signal = gen6_signal;
2403 * The current semaphore is only applied on pre-gen8
2404 * platform. And there is no VCS2 ring on the pre-gen8
2405 * platform. So the semaphore between RCS and VCS2 is
2406 * initialized as INVALID. Gen8 will initialize the
2407 * sema between VCS2 and RCS later.
2409 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2410 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2411 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2412 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2413 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2414 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2415 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2416 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2417 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2418 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2420 } else if (IS_GEN5(dev)) {
2421 ring->add_request = pc_render_add_request;
2422 ring->flush = gen4_render_ring_flush;
2423 ring->get_seqno = pc_render_get_seqno;
2424 ring->set_seqno = pc_render_set_seqno;
2425 ring->irq_get = gen5_ring_get_irq;
2426 ring->irq_put = gen5_ring_put_irq;
2427 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2428 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2430 ring->add_request = i9xx_add_request;
2431 if (INTEL_INFO(dev)->gen < 4)
2432 ring->flush = gen2_render_ring_flush;
2434 ring->flush = gen4_render_ring_flush;
2435 ring->get_seqno = ring_get_seqno;
2436 ring->set_seqno = ring_set_seqno;
2438 ring->irq_get = i8xx_ring_get_irq;
2439 ring->irq_put = i8xx_ring_put_irq;
2441 ring->irq_get = i9xx_ring_get_irq;
2442 ring->irq_put = i9xx_ring_put_irq;
2444 ring->irq_enable_mask = I915_USER_INTERRUPT;
2446 ring->write_tail = ring_write_tail;
2448 if (IS_HASWELL(dev))
2449 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2450 else if (IS_GEN8(dev))
2451 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2452 else if (INTEL_INFO(dev)->gen >= 6)
2453 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2454 else if (INTEL_INFO(dev)->gen >= 4)
2455 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2456 else if (IS_I830(dev) || IS_845G(dev))
2457 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2459 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2460 ring->init_hw = init_render_ring;
2461 ring->cleanup = render_ring_cleanup;
2463 /* Workaround batchbuffer to combat CS tlb bug. */
2464 if (HAS_BROKEN_CS_TLB(dev)) {
2465 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2467 DRM_ERROR("Failed to allocate batch bo\n");
2471 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2473 drm_gem_object_unreference(&obj->base);
2474 DRM_ERROR("Failed to ping batch bo\n");
2478 ring->scratch.obj = obj;
2479 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2482 ret = intel_init_ring_buffer(dev, ring);
2486 if (INTEL_INFO(dev)->gen >= 5) {
2487 ret = intel_init_pipe_control(ring);
2495 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2497 struct drm_i915_private *dev_priv = dev->dev_private;
2498 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2500 ring->name = "bsd ring";
2503 ring->write_tail = ring_write_tail;
2504 if (INTEL_INFO(dev)->gen >= 6) {
2505 ring->mmio_base = GEN6_BSD_RING_BASE;
2506 /* gen6 bsd needs a special wa for tail updates */
2508 ring->write_tail = gen6_bsd_ring_write_tail;
2509 ring->flush = gen6_bsd_ring_flush;
2510 ring->add_request = gen6_add_request;
2511 ring->get_seqno = gen6_ring_get_seqno;
2512 ring->set_seqno = ring_set_seqno;
2513 if (INTEL_INFO(dev)->gen >= 8) {
2514 ring->irq_enable_mask =
2515 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2516 ring->irq_get = gen8_ring_get_irq;
2517 ring->irq_put = gen8_ring_put_irq;
2518 ring->dispatch_execbuffer =
2519 gen8_ring_dispatch_execbuffer;
2520 if (i915_semaphore_is_enabled(dev)) {
2521 ring->semaphore.sync_to = gen8_ring_sync;
2522 ring->semaphore.signal = gen8_xcs_signal;
2523 GEN8_RING_SEMAPHORE_INIT;
2526 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2527 ring->irq_get = gen6_ring_get_irq;
2528 ring->irq_put = gen6_ring_put_irq;
2529 ring->dispatch_execbuffer =
2530 gen6_ring_dispatch_execbuffer;
2531 if (i915_semaphore_is_enabled(dev)) {
2532 ring->semaphore.sync_to = gen6_ring_sync;
2533 ring->semaphore.signal = gen6_signal;
2534 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2535 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2536 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2537 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2538 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2539 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2540 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2541 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2542 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2543 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2547 ring->mmio_base = BSD_RING_BASE;
2548 ring->flush = bsd_ring_flush;
2549 ring->add_request = i9xx_add_request;
2550 ring->get_seqno = ring_get_seqno;
2551 ring->set_seqno = ring_set_seqno;
2553 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2554 ring->irq_get = gen5_ring_get_irq;
2555 ring->irq_put = gen5_ring_put_irq;
2557 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2558 ring->irq_get = i9xx_ring_get_irq;
2559 ring->irq_put = i9xx_ring_put_irq;
2561 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2563 ring->init_hw = init_ring_common;
2565 return intel_init_ring_buffer(dev, ring);
2569 * Initialize the second BSD ring for Broadwell GT3.
2570 * It is noted that this only exists on Broadwell GT3.
2572 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2574 struct drm_i915_private *dev_priv = dev->dev_private;
2575 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2577 if ((INTEL_INFO(dev)->gen != 8)) {
2578 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2582 ring->name = "bsd2 ring";
2585 ring->write_tail = ring_write_tail;
2586 ring->mmio_base = GEN8_BSD2_RING_BASE;
2587 ring->flush = gen6_bsd_ring_flush;
2588 ring->add_request = gen6_add_request;
2589 ring->get_seqno = gen6_ring_get_seqno;
2590 ring->set_seqno = ring_set_seqno;
2591 ring->irq_enable_mask =
2592 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2593 ring->irq_get = gen8_ring_get_irq;
2594 ring->irq_put = gen8_ring_put_irq;
2595 ring->dispatch_execbuffer =
2596 gen8_ring_dispatch_execbuffer;
2597 if (i915_semaphore_is_enabled(dev)) {
2598 ring->semaphore.sync_to = gen8_ring_sync;
2599 ring->semaphore.signal = gen8_xcs_signal;
2600 GEN8_RING_SEMAPHORE_INIT;
2602 ring->init_hw = init_ring_common;
2604 return intel_init_ring_buffer(dev, ring);
2607 int intel_init_blt_ring_buffer(struct drm_device *dev)
2609 struct drm_i915_private *dev_priv = dev->dev_private;
2610 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2612 ring->name = "blitter ring";
2615 ring->mmio_base = BLT_RING_BASE;
2616 ring->write_tail = ring_write_tail;
2617 ring->flush = gen6_ring_flush;
2618 ring->add_request = gen6_add_request;
2619 ring->get_seqno = gen6_ring_get_seqno;
2620 ring->set_seqno = ring_set_seqno;
2621 if (INTEL_INFO(dev)->gen >= 8) {
2622 ring->irq_enable_mask =
2623 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2624 ring->irq_get = gen8_ring_get_irq;
2625 ring->irq_put = gen8_ring_put_irq;
2626 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2627 if (i915_semaphore_is_enabled(dev)) {
2628 ring->semaphore.sync_to = gen8_ring_sync;
2629 ring->semaphore.signal = gen8_xcs_signal;
2630 GEN8_RING_SEMAPHORE_INIT;
2633 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2634 ring->irq_get = gen6_ring_get_irq;
2635 ring->irq_put = gen6_ring_put_irq;
2636 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2637 if (i915_semaphore_is_enabled(dev)) {
2638 ring->semaphore.signal = gen6_signal;
2639 ring->semaphore.sync_to = gen6_ring_sync;
2641 * The current semaphore is only applied on pre-gen8
2642 * platform. And there is no VCS2 ring on the pre-gen8
2643 * platform. So the semaphore between BCS and VCS2 is
2644 * initialized as INVALID. Gen8 will initialize the
2645 * sema between BCS and VCS2 later.
2647 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2648 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2649 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2650 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2651 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2652 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2653 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2654 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2655 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2656 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2659 ring->init_hw = init_ring_common;
2661 return intel_init_ring_buffer(dev, ring);
2664 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2666 struct drm_i915_private *dev_priv = dev->dev_private;
2667 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2669 ring->name = "video enhancement ring";
2672 ring->mmio_base = VEBOX_RING_BASE;
2673 ring->write_tail = ring_write_tail;
2674 ring->flush = gen6_ring_flush;
2675 ring->add_request = gen6_add_request;
2676 ring->get_seqno = gen6_ring_get_seqno;
2677 ring->set_seqno = ring_set_seqno;
2679 if (INTEL_INFO(dev)->gen >= 8) {
2680 ring->irq_enable_mask =
2681 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2682 ring->irq_get = gen8_ring_get_irq;
2683 ring->irq_put = gen8_ring_put_irq;
2684 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2685 if (i915_semaphore_is_enabled(dev)) {
2686 ring->semaphore.sync_to = gen8_ring_sync;
2687 ring->semaphore.signal = gen8_xcs_signal;
2688 GEN8_RING_SEMAPHORE_INIT;
2691 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2692 ring->irq_get = hsw_vebox_get_irq;
2693 ring->irq_put = hsw_vebox_put_irq;
2694 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2695 if (i915_semaphore_is_enabled(dev)) {
2696 ring->semaphore.sync_to = gen6_ring_sync;
2697 ring->semaphore.signal = gen6_signal;
2698 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2699 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2700 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2701 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2702 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2703 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2704 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2705 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2706 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2707 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2710 ring->init_hw = init_ring_common;
2712 return intel_init_ring_buffer(dev, ring);
2716 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2720 if (!ring->gpu_caches_dirty)
2723 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2727 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2729 ring->gpu_caches_dirty = false;
2734 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2736 uint32_t flush_domains;
2740 if (ring->gpu_caches_dirty)
2741 flush_domains = I915_GEM_GPU_DOMAINS;
2743 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2747 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2749 ring->gpu_caches_dirty = false;
2754 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2758 if (!intel_ring_initialized(ring))
2761 ret = intel_ring_idle(ring);
2762 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2763 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",