drivers/gpu/drm/i915/intel_psr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Panel Self Refresh (PSR/SRD)
  26  *
  27  * Since Haswell Display controller supports Panel Self-Refresh on display
  28  * panels witch have a remote frame buffer (RFB) implemented according to PSR
  29  * spec in eDP1.3. PSR feature allows the display to go to lower standby states
  30  * when system is idle but display is on as it eliminates display refresh
  31  * request to DDR memory completely as long as the frame buffer for that
  32  * display is unchanged.
  33  *
  34  * Panel Self Refresh must be supported by both Hardware (source) and
  35  * Panel (sink).
  36  *
  37  * PSR saves power by caching the framebuffer in the panel RFB, which allows us
  38  * to power down the link and memory controller. For DSI panels the same idea
  39  * is called "manual mode".
  40  *
  41  * The implementation uses the hardware-based PSR support which automatically
  42  * enters/exits self-refresh mode. The hardware takes care of sending the
  43  * required DP aux message and could even retrain the link (that part isn't
  44  * enabled yet though). The hardware also keeps track of any frontbuffer
  45  * changes to know when to exit self-refresh mode again. Unfortunately that
  46  * part doesn't work too well, hence why the i915 PSR support uses the
  47  * software frontbuffer tracking to make sure it doesn't miss a screen
  48  * update. For this integration intel_psr_invalidate() and intel_psr_flush()
  49  * get called by the frontbuffer tracking code. Note that because of locking
  50  * issues the self-refresh re-enable code is done from a work queue, which
  51  * must be correctly synchronized/cancelled when shutting down the pipe."
  52  */
  53
  54 #include <drm/drmP.h>
  55
  56 #include "intel_drv.h"
  57 #include "i915_drv.h"
  58
  59 static bool psr_global_enabled(u32 debug)
  60 {
  61         switch (debug & I915_PSR_DEBUG_MODE_MASK) {
  62         case I915_PSR_DEBUG_DEFAULT:
  63                 return i915_modparams.enable_psr;
  64         case I915_PSR_DEBUG_DISABLE:
  65                 return false;
  66         default:
  67                 return true;
  68         }
  69 }
  70
  71 static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
  72                                const struct intel_crtc_state *crtc_state)
  73 {
  74         /* Disable PSR2 by default for all platforms */
  75         if (i915_modparams.enable_psr == -1)
  76                 return false;
  77
  78         /* Cannot enable DSC and PSR2 simultaneously */
  79         WARN_ON(crtc_state->dsc_params.compression_enable &&
  80                 crtc_state->has_psr2);
  81
  82         switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
  83         case I915_PSR_DEBUG_FORCE_PSR1:
  84                 return false;
  85         default:
  86                 return crtc_state->has_psr2;
  87         }
  88 }
  89
  90 static int edp_psr_shift(enum transcoder cpu_transcoder)
  91 {
  92         switch (cpu_transcoder) {
  93         case TRANSCODER_A:
  94                 return EDP_PSR_TRANSCODER_A_SHIFT;
  95         case TRANSCODER_B:
  96                 return EDP_PSR_TRANSCODER_B_SHIFT;
  97         case TRANSCODER_C:
  98                 return EDP_PSR_TRANSCODER_C_SHIFT;
  99         default:
 100                 MISSING_CASE(cpu_transcoder);
 101                 /* fallthrough */
 102         case TRANSCODER_EDP:
 103                 return EDP_PSR_TRANSCODER_EDP_SHIFT;
 104         }
 105 }
 106
 107 void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
 108 {
 109         u32 debug_mask, mask;
 110         enum transcoder cpu_transcoder;
 111         u32 transcoders = BIT(TRANSCODER_EDP);
 112
 113         if (INTEL_GEN(dev_priv) >= 8)
 114                 transcoders |= BIT(TRANSCODER_A) |
 115                                BIT(TRANSCODER_B) |
 116                                BIT(TRANSCODER_C);
 117
 118         debug_mask = 0;
 119         mask = 0;
 120         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
 121                 int shift = edp_psr_shift(cpu_transcoder);
 122
 123                 mask |= EDP_PSR_ERROR(shift);
 124                 debug_mask |= EDP_PSR_POST_EXIT(shift) |
 125                               EDP_PSR_PRE_ENTRY(shift);
 126         }
 127
 128         if (debug & I915_PSR_DEBUG_IRQ)
 129                 mask |= debug_mask;
 130
 131         I915_WRITE(EDP_PSR_IMR, ~mask);
 132 }
 133
 134 static void psr_event_print(u32 val, bool psr2_enabled)
 135 {
 136         DRM_DEBUG_KMS("PSR exit events: 0x%x\n", val);
 137         if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE)
 138                 DRM_DEBUG_KMS("\tPSR2 watchdog timer expired\n");
 139         if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled)
 140                 DRM_DEBUG_KMS("\tPSR2 disabled\n");
 141         if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN)
 142                 DRM_DEBUG_KMS("\tSU dirty FIFO underrun\n");
 143         if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN)
 144                 DRM_DEBUG_KMS("\tSU CRC FIFO underrun\n");
 145         if (val & PSR_EVENT_GRAPHICS_RESET)
 146                 DRM_DEBUG_KMS("\tGraphics reset\n");
 147         if (val & PSR_EVENT_PCH_INTERRUPT)
 148                 DRM_DEBUG_KMS("\tPCH interrupt\n");
 149         if (val & PSR_EVENT_MEMORY_UP)
 150                 DRM_DEBUG_KMS("\tMemory up\n");
 151         if (val & PSR_EVENT_FRONT_BUFFER_MODIFY)
 152                 DRM_DEBUG_KMS("\tFront buffer modification\n");
 153         if (val & PSR_EVENT_WD_TIMER_EXPIRE)
 154                 DRM_DEBUG_KMS("\tPSR watchdog timer expired\n");
 155         if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE)
 156                 DRM_DEBUG_KMS("\tPIPE registers updated\n");
 157         if (val & PSR_EVENT_REGISTER_UPDATE)
 158                 DRM_DEBUG_KMS("\tRegister updated\n");
 159         if (val & PSR_EVENT_HDCP_ENABLE)
 160                 DRM_DEBUG_KMS("\tHDCP enabled\n");
 161         if (val & PSR_EVENT_KVMR_SESSION_ENABLE)
 162                 DRM_DEBUG_KMS("\tKVMR session enabled\n");
 163         if (val & PSR_EVENT_VBI_ENABLE)
 164                 DRM_DEBUG_KMS("\tVBI enabled\n");
 165         if (val & PSR_EVENT_LPSP_MODE_EXIT)
 166                 DRM_DEBUG_KMS("\tLPSP mode exited\n");
 167         if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled)
 168                 DRM_DEBUG_KMS("\tPSR disabled\n");
 169 }
 170
 171 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
 172 {
 173         u32 transcoders = BIT(TRANSCODER_EDP);
 174         enum transcoder cpu_transcoder;
 175         ktime_t time_ns =  ktime_get();
 176         u32 mask = 0;
 177
 178         if (INTEL_GEN(dev_priv) >= 8)
 179                 transcoders |= BIT(TRANSCODER_A) |
 180                                BIT(TRANSCODER_B) |
 181                                BIT(TRANSCODER_C);
 182
 183         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
 184                 int shift = edp_psr_shift(cpu_transcoder);
 185
 186                 if (psr_iir & EDP_PSR_ERROR(shift)) {
 187                         DRM_WARN("[transcoder %s] PSR aux error\n",
 188                                  transcoder_name(cpu_transcoder));
 189
 190                         dev_priv->psr.irq_aux_error = true;
 191
 192                         /*
 193                          * If this interruption is not masked it will keep
 194                          * interrupting so fast that it prevents the scheduled
 195                          * work to run.
 196                          * Also after a PSR error, we don't want to arm PSR
 197                          * again so we don't care about unmask the interruption
 198                          * or unset irq_aux_error.
 199                          */
 200                         mask |= EDP_PSR_ERROR(shift);
 201                 }
 202
 203                 if (psr_iir & EDP_PSR_PRE_ENTRY(shift)) {
 204                         dev_priv->psr.last_entry_attempt = time_ns;
 205                         DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
 206                                       transcoder_name(cpu_transcoder));
 207                 }
 208
 209                 if (psr_iir & EDP_PSR_POST_EXIT(shift)) {
 210                         dev_priv->psr.last_exit = time_ns;
 211                         DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
 212                                       transcoder_name(cpu_transcoder));
 213
 214                         if (INTEL_GEN(dev_priv) >= 9) {
 215                                 u32 val = I915_READ(PSR_EVENT(cpu_transcoder));
 216                                 bool psr2_enabled = dev_priv->psr.psr2_enabled;
 217
 218                                 I915_WRITE(PSR_EVENT(cpu_transcoder), val);
 219                                 psr_event_print(val, psr2_enabled);
 220                         }
 221                 }
 222         }
 223
 224         if (mask) {
 225                 mask |= I915_READ(EDP_PSR_IMR);
 226                 I915_WRITE(EDP_PSR_IMR, mask);
 227
 228                 schedule_work(&dev_priv->psr.work);
 229         }
 230 }
 231
 232 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
 233 {
 234         uint8_t dprx = 0;
 235
 236         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
 237                               &dprx) != 1)
 238                 return false;
 239         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
 240 }
 241
 242 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
 243 {
 244         uint8_t alpm_caps = 0;
 245
 246         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
 247                               &alpm_caps) != 1)
 248                 return false;
 249         return alpm_caps & DP_ALPM_CAP;
 250 }
 251
 252 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
 253 {
 254         u8 val = 8; /* assume the worst if we can't read the value */
 255
 256         if (drm_dp_dpcd_readb(&intel_dp->aux,
 257                               DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1)
 258                 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
 259         else
 260                 DRM_DEBUG_KMS("Unable to get sink synchronization latency, assuming 8 frames\n");
 261         return val;
 262 }
 263
 264 void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 265 {
 266         struct drm_i915_private *dev_priv =
 267                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
 268
 269         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
 270                          sizeof(intel_dp->psr_dpcd));
 271
 272         if (!intel_dp->psr_dpcd[0])
 273                 return;
 274         DRM_DEBUG_KMS("eDP panel supports PSR version %x\n",
 275                       intel_dp->psr_dpcd[0]);
 276
 277         if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
 278                 DRM_DEBUG_KMS("PSR support not currently available for this panel\n");
 279                 return;
 280         }
 281
 282         if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
 283                 DRM_DEBUG_KMS("Panel lacks power state control, PSR cannot be enabled\n");
 284                 return;
 285         }
 286
 287         dev_priv->psr.sink_support = true;
 288         dev_priv->psr.sink_sync_latency =
 289                 intel_dp_get_sink_sync_latency(intel_dp);
 290
 291         WARN_ON(dev_priv->psr.dp);
 292         dev_priv->psr.dp = intel_dp;
 293
 294         if (INTEL_GEN(dev_priv) >= 9 &&
 295             (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
 296                 bool y_req = intel_dp->psr_dpcd[1] &
 297                              DP_PSR2_SU_Y_COORDINATE_REQUIRED;
 298                 bool alpm = intel_dp_get_alpm_status(intel_dp);
 299
 300                 /*
 301                  * All panels that supports PSR version 03h (PSR2 +
 302                  * Y-coordinate) can handle Y-coordinates in VSC but we are
 303                  * only sure that it is going to be used when required by the
 304                  * panel. This way panel is capable to do selective update
 305                  * without a aux frame sync.
 306                  *
 307                  * To support PSR version 02h and PSR version 03h without
 308                  * Y-coordinate requirement panels we would need to enable
 309                  * GTC first.
 310                  */
 311                 dev_priv->psr.sink_psr2_support = y_req && alpm;
 312                 DRM_DEBUG_KMS("PSR2 %ssupported\n",
 313                               dev_priv->psr.sink_psr2_support ? "" : "not ");
 314
 315                 if (dev_priv->psr.sink_psr2_support) {
 316                         dev_priv->psr.colorimetry_support =
 317                                 intel_dp_get_colorimetry_status(intel_dp);
 318                 }
 319         }
 320 }
 321
 322 static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
 323                                 const struct intel_crtc_state *crtc_state)
 324 {
 325         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 326         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 327         struct edp_vsc_psr psr_vsc;
 328
 329         if (dev_priv->psr.psr2_enabled) {
 330                 /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
 331                 memset(&psr_vsc, 0, sizeof(psr_vsc));
 332                 psr_vsc.sdp_header.HB0 = 0;
 333                 psr_vsc.sdp_header.HB1 = 0x7;
 334                 if (dev_priv->psr.colorimetry_support) {
 335                         psr_vsc.sdp_header.HB2 = 0x5;
 336                         psr_vsc.sdp_header.HB3 = 0x13;
 337                 } else {
 338                         psr_vsc.sdp_header.HB2 = 0x4;
 339                         psr_vsc.sdp_header.HB3 = 0xe;
 340                 }
 341         } else {
 342                 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
 343                 memset(&psr_vsc, 0, sizeof(psr_vsc));
 344                 psr_vsc.sdp_header.HB0 = 0;
 345                 psr_vsc.sdp_header.HB1 = 0x7;
 346                 psr_vsc.sdp_header.HB2 = 0x2;
 347                 psr_vsc.sdp_header.HB3 = 0x8;
 348         }
 349
 350         intel_dig_port->write_infoframe(&intel_dig_port->base,
 351                                         crtc_state,
 352                                         DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc));
 353 }
 354
 355 static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
 356 {
 357         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 358         u32 aux_clock_divider, aux_ctl;
 359         int i;
 360         static const uint8_t aux_msg[] = {
 361                 [0] = DP_AUX_NATIVE_WRITE << 4,
 362                 [1] = DP_SET_POWER >> 8,
 363                 [2] = DP_SET_POWER & 0xff,
 364                 [3] = 1 - 1,
 365                 [4] = DP_SET_POWER_D0,
 366         };
 367         u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK |
 368                            EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK |
 369                            EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK |
 370                            EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK;
 371
 372         BUILD_BUG_ON(sizeof(aux_msg) > 20);
 373         for (i = 0; i < sizeof(aux_msg); i += 4)
 374                 I915_WRITE(EDP_PSR_AUX_DATA(i >> 2),
 375                            intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
 376
 377         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
 378
 379         /* Start with bits set for DDI_AUX_CTL register */
 380         aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg),
 381                                              aux_clock_divider);
 382
 383         /* Select only valid bits for SRD_AUX_CTL */
 384         aux_ctl &= psr_aux_mask;
 385         I915_WRITE(EDP_PSR_AUX_CTL, aux_ctl);
 386 }
 387
 388 static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 389 {
 390         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 391         u8 dpcd_val = DP_PSR_ENABLE;
 392
 393         /* Enable ALPM at sink for psr2 */
 394         if (dev_priv->psr.psr2_enabled) {
 395                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
 396                                    DP_ALPM_ENABLE);
 397                 dpcd_val |= DP_PSR_ENABLE_PSR2;
 398         }
 399
 400         if (dev_priv->psr.link_standby)
 401                 dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
 402         if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8)
 403                 dpcd_val |= DP_PSR_CRC_VERIFICATION;
 404         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
 405
 406         drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
 407 }
 408
 409 static void hsw_activate_psr1(struct intel_dp *intel_dp)
 410 {
 411         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 412         u32 max_sleep_time = 0x1f;
 413         u32 val = EDP_PSR_ENABLE;
 414
 415         /* Let's use 6 as the minimum to cover all known cases including the
 416          * off-by-one issue that HW has in some cases.
 417          */
 418         int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
 419
 420         /* sink_sync_latency of 8 means source has to wait for more than 8
 421          * frames, we'll go with 9 frames for now
 422          */
 423         idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
 424         val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 425
 426         val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
 427         if (IS_HASWELL(dev_priv))
 428                 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 429
 430         if (dev_priv->psr.link_standby)
 431                 val |= EDP_PSR_LINK_STANDBY;
 432
 433         if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
 434                 val |=  EDP_PSR_TP1_TIME_0us;
 435         else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
 436                 val |= EDP_PSR_TP1_TIME_100us;
 437         else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
 438                 val |= EDP_PSR_TP1_TIME_500us;
 439         else
 440                 val |= EDP_PSR_TP1_TIME_2500us;
 441
 442         if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
 443                 val |=  EDP_PSR_TP2_TP3_TIME_0us;
 444         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
 445                 val |= EDP_PSR_TP2_TP3_TIME_100us;
 446         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
 447                 val |= EDP_PSR_TP2_TP3_TIME_500us;
 448         else
 449                 val |= EDP_PSR_TP2_TP3_TIME_2500us;
 450
 451         if (intel_dp_source_supports_hbr2(intel_dp) &&
 452             drm_dp_tps3_supported(intel_dp->dpcd))
 453                 val |= EDP_PSR_TP1_TP3_SEL;
 454         else
 455                 val |= EDP_PSR_TP1_TP2_SEL;
 456
 457         if (INTEL_GEN(dev_priv) >= 8)
 458                 val |= EDP_PSR_CRC_ENABLE;
 459
 460         val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;
 461         I915_WRITE(EDP_PSR_CTL, val);
 462 }
 463
 464 static void hsw_activate_psr2(struct intel_dp *intel_dp)
 465 {
 466         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 467         u32 val;
 468
 469         /* Let's use 6 as the minimum to cover all known cases including the
 470          * off-by-one issue that HW has in some cases.
 471          */
 472         int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
 473
 474         idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
 475         val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
 476
 477         /* FIXME: selective update is probably totally broken because it doesn't
 478          * mesh at all with our frontbuffer tracking. And the hw alone isn't
 479          * good enough. */
 480         val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
 481         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 482                 val |= EDP_Y_COORDINATE_ENABLE;
 483
 484         val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
 485
 486         if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
 487             dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
 488                 val |= EDP_PSR2_TP2_TIME_50us;
 489         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
 490                 val |= EDP_PSR2_TP2_TIME_100us;
 491         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
 492                 val |= EDP_PSR2_TP2_TIME_500us;
 493         else
 494                 val |= EDP_PSR2_TP2_TIME_2500us;
 495
 496         I915_WRITE(EDP_PSR2_CTL, val);
 497 }
 498
 499 static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 500                                     struct intel_crtc_state *crtc_state)
 501 {
 502         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 503         int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay;
 504         int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay;
 505         int psr_max_h = 0, psr_max_v = 0;
 506
 507         /*
 508          * FIXME psr2_support is messed up. It's both computed
 509          * dynamically during PSR enable, and extracted from sink
 510          * caps during eDP detection.
 511          */
 512         if (!dev_priv->psr.sink_psr2_support)
 513                 return false;
 514
 515         /*
 516          * DSC and PSR2 cannot be enabled simultaneously. If a requested
 517          * resolution requires DSC to be enabled, priority is given to DSC
 518          * over PSR2.
 519          */
 520         if (crtc_state->dsc_params.compression_enable) {
 521                 DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n");
 522                 return false;
 523         }
 524
 525         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 526                 psr_max_h = 4096;
 527                 psr_max_v = 2304;
 528         } else if (IS_GEN9(dev_priv)) {
 529                 psr_max_h = 3640;
 530                 psr_max_v = 2304;
 531         }
 532
 533         if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) {
 534                 DRM_DEBUG_KMS("PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",
 535                               crtc_hdisplay, crtc_vdisplay,
 536                               psr_max_h, psr_max_v);
 537                 return false;
 538         }
 539
 540         return true;
 541 }
 542
 543 void intel_psr_compute_config(struct intel_dp *intel_dp,
 544                               struct intel_crtc_state *crtc_state)
 545 {
 546         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 547         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 548         const struct drm_display_mode *adjusted_mode =
 549                 &crtc_state->base.adjusted_mode;
 550         int psr_setup_time;
 551
 552         if (!CAN_PSR(dev_priv))
 553                 return;
 554
 555         if (intel_dp != dev_priv->psr.dp)
 556                 return;
 557
 558         /*
 559          * HSW spec explicitly says PSR is tied to port A.
 560          * BDW+ platforms with DDI implementation of PSR have different
 561          * PSR registers per transcoder and we only implement transcoder EDP
 562          * ones. Since by Display design transcoder EDP is tied to port A
 563          * we can safely escape based on the port A.
 564          */
 565         if (dig_port->base.port != PORT_A) {
 566                 DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
 567                 return;
 568         }
 569
 570         if (dev_priv->psr.sink_not_reliable) {
 571                 DRM_DEBUG_KMS("PSR sink implementation is not reliable\n");
 572                 return;
 573         }
 574
 575         if (IS_HASWELL(dev_priv) &&
 576             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 577                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
 578                 return;
 579         }
 580
 581         psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
 582         if (psr_setup_time < 0) {
 583                 DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
 584                               intel_dp->psr_dpcd[1]);
 585                 return;
 586         }
 587
 588         if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
 589             adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
 590                 DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
 591                               psr_setup_time);
 592                 return;
 593         }
 594
 595         crtc_state->has_psr = true;
 596         crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
 597 }
 598
 599 static void intel_psr_activate(struct intel_dp *intel_dp)
 600 {
 601         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 602
 603         if (INTEL_GEN(dev_priv) >= 9)
 604                 WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
 605         WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 606         WARN_ON(dev_priv->psr.active);
 607         lockdep_assert_held(&dev_priv->psr.lock);
 608
 609         /* psr1 and psr2 are mutually exclusive.*/
 610         if (dev_priv->psr.psr2_enabled)
 611                 hsw_activate_psr2(intel_dp);
 612         else
 613                 hsw_activate_psr1(intel_dp);
 614
 615         dev_priv->psr.active = true;
 616 }
 617
 618 static i915_reg_t gen9_chicken_trans_reg(struct drm_i915_private *dev_priv,
 619                                          enum transcoder cpu_transcoder)
 620 {
 621         static const i915_reg_t regs[] = {
 622                 [TRANSCODER_A] = CHICKEN_TRANS_A,
 623                 [TRANSCODER_B] = CHICKEN_TRANS_B,
 624                 [TRANSCODER_C] = CHICKEN_TRANS_C,
 625                 [TRANSCODER_EDP] = CHICKEN_TRANS_EDP,
 626         };
 627
 628         WARN_ON(INTEL_GEN(dev_priv) < 9);
 629
 630         if (WARN_ON(cpu_transcoder >= ARRAY_SIZE(regs) ||
 631                     !regs[cpu_transcoder].reg))
 632                 cpu_transcoder = TRANSCODER_A;
 633
 634         return regs[cpu_transcoder];
 635 }
 636
 637 static void intel_psr_enable_source(struct intel_dp *intel_dp,
 638                                     const struct intel_crtc_state *crtc_state)
 639 {
 640         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 641         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 642         u32 mask;
 643
 644         /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
 645          * use hardcoded values PSR AUX transactions
 646          */
 647         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 648                 hsw_psr_setup_aux(intel_dp);
 649
 650         if (dev_priv->psr.psr2_enabled) {
 651                 i915_reg_t reg = gen9_chicken_trans_reg(dev_priv,
 652                                                         cpu_transcoder);
 653                 u32 chicken = I915_READ(reg);
 654
 655                 if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
 656                         chicken |= (PSR2_VSC_ENABLE_PROG_HEADER
 657                                    | PSR2_ADD_VERTICAL_LINE_COUNT);
 658
 659                 else
 660                         chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL;
 661                 I915_WRITE(reg, chicken);
 662         }
 663
 664         /*
 665          * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
 666          * mask LPSP to avoid dependency on other drivers that might block
 667          * runtime_pm besides preventing  other hw tracking issues now we
 668          * can rely on frontbuffer tracking.
 669          */
 670         mask = EDP_PSR_DEBUG_MASK_MEMUP |
 671                EDP_PSR_DEBUG_MASK_HPD |
 672                EDP_PSR_DEBUG_MASK_LPSP |
 673                EDP_PSR_DEBUG_MASK_MAX_SLEEP;
 674
 675         if (INTEL_GEN(dev_priv) < 11)
 676                 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
 677
 678         I915_WRITE(EDP_PSR_DEBUG, mask);
 679 }
 680
 681 static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
 682                                     const struct intel_crtc_state *crtc_state)
 683 {
 684         struct intel_dp *intel_dp = dev_priv->psr.dp;
 685
 686         if (dev_priv->psr.enabled)
 687                 return;
 688
 689         DRM_DEBUG_KMS("Enabling PSR%s\n",
 690                       dev_priv->psr.psr2_enabled ? "2" : "1");
 691         intel_psr_setup_vsc(intel_dp, crtc_state);
 692         intel_psr_enable_sink(intel_dp);
 693         intel_psr_enable_source(intel_dp, crtc_state);
 694         dev_priv->psr.enabled = true;
 695
 696         intel_psr_activate(intel_dp);
 697 }
 698
 699 /**
 700  * intel_psr_enable - Enable PSR
 701  * @intel_dp: Intel DP
 702  * @crtc_state: new CRTC state
 703  *
 704  * This function can only be called after the pipe is fully trained and enabled.
 705  */
 706 void intel_psr_enable(struct intel_dp *intel_dp,
 707                       const struct intel_crtc_state *crtc_state)
 708 {
 709         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 710
 711         if (!crtc_state->has_psr)
 712                 return;
 713
 714         if (WARN_ON(!CAN_PSR(dev_priv)))
 715                 return;
 716
 717         WARN_ON(dev_priv->drrs.dp);
 718
 719         mutex_lock(&dev_priv->psr.lock);
 720         if (dev_priv->psr.prepared) {
 721                 DRM_DEBUG_KMS("PSR already in use\n");
 722                 goto unlock;
 723         }
 724
 725         dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
 726         dev_priv->psr.busy_frontbuffer_bits = 0;
 727         dev_priv->psr.prepared = true;
 728         dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
 729
 730         if (psr_global_enabled(dev_priv->psr.debug))
 731                 intel_psr_enable_locked(dev_priv, crtc_state);
 732         else
 733                 DRM_DEBUG_KMS("PSR disabled by flag\n");
 734
 735 unlock:
 736         mutex_unlock(&dev_priv->psr.lock);
 737 }
 738
 739 static void intel_psr_exit(struct drm_i915_private *dev_priv)
 740 {
 741         u32 val;
 742
 743         if (!dev_priv->psr.active) {
 744                 if (INTEL_GEN(dev_priv) >= 9)
 745                         WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
 746                 WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 747                 return;
 748         }
 749
 750         if (dev_priv->psr.psr2_enabled) {
 751                 val = I915_READ(EDP_PSR2_CTL);
 752                 WARN_ON(!(val & EDP_PSR2_ENABLE));
 753                 I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
 754         } else {
 755                 val = I915_READ(EDP_PSR_CTL);
 756                 WARN_ON(!(val & EDP_PSR_ENABLE));
 757                 I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
 758         }
 759         dev_priv->psr.active = false;
 760 }
 761
 762 static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 763 {
 764         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 765         i915_reg_t psr_status;
 766         u32 psr_status_mask;
 767
 768         lockdep_assert_held(&dev_priv->psr.lock);
 769
 770         if (!dev_priv->psr.enabled)
 771                 return;
 772
 773         DRM_DEBUG_KMS("Disabling PSR%s\n",
 774                       dev_priv->psr.psr2_enabled ? "2" : "1");
 775
 776         intel_psr_exit(dev_priv);
 777
 778         if (dev_priv->psr.psr2_enabled) {
 779                 psr_status = EDP_PSR2_STATUS;
 780                 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
 781         } else {
 782                 psr_status = EDP_PSR_STATUS;
 783                 psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
 784         }
 785
 786         /* Wait till PSR is idle */
 787         if (intel_wait_for_register(dev_priv, psr_status, psr_status_mask, 0,
 788                                     2000))
 789                 DRM_ERROR("Timed out waiting PSR idle state\n");
 790
 791         /* Disable PSR on Sink */
 792         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
 793
 794         dev_priv->psr.enabled = false;
 795 }
 796
 797 /**
 798  * intel_psr_disable - Disable PSR
 799  * @intel_dp: Intel DP
 800  * @old_crtc_state: old CRTC state
 801  *
 802  * This function needs to be called before disabling pipe.
 803  */
 804 void intel_psr_disable(struct intel_dp *intel_dp,
 805                        const struct intel_crtc_state *old_crtc_state)
 806 {
 807         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 808
 809         if (!old_crtc_state->has_psr)
 810                 return;
 811
 812         if (WARN_ON(!CAN_PSR(dev_priv)))
 813                 return;
 814
 815         mutex_lock(&dev_priv->psr.lock);
 816         if (!dev_priv->psr.prepared) {
 817                 mutex_unlock(&dev_priv->psr.lock);
 818                 return;
 819         }
 820
 821         intel_psr_disable_locked(intel_dp);
 822
 823         dev_priv->psr.prepared = false;
 824         mutex_unlock(&dev_priv->psr.lock);
 825         cancel_work_sync(&dev_priv->psr.work);
 826 }
 827
 828 /**
 829  * intel_psr_wait_for_idle - wait for PSR1 to idle
 830  * @new_crtc_state: new CRTC state
 831  * @out_value: PSR status in case of failure
 832  *
 833  * This function is expected to be called from pipe_update_start() where it is
 834  * not expected to race with PSR enable or disable.
 835  *
 836  * Returns: 0 on success or -ETIMEOUT if PSR status does not idle.
 837  */
 838 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
 839                             u32 *out_value)
 840 {
 841         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
 842         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 843
 844         if (!dev_priv->psr.enabled || !new_crtc_state->has_psr)
 845                 return 0;
 846
 847         /* FIXME: Update this for PSR2 if we need to wait for idle */
 848         if (READ_ONCE(dev_priv->psr.psr2_enabled))
 849                 return 0;
 850
 851         /*
 852          * From bspec: Panel Self Refresh (BDW+)
 853          * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of
 854          * exit training time + 1.5 ms of aux channel handshake. 50 ms is
 855          * defensive enough to cover everything.
 856          */
 857
 858         return __intel_wait_for_register(dev_priv, EDP_PSR_STATUS,
 859                                          EDP_PSR_STATUS_STATE_MASK,
 860                                          EDP_PSR_STATUS_STATE_IDLE, 2, 50,
 861                                          out_value);
 862 }
 863
 864 static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)
 865 {
 866         i915_reg_t reg;
 867         u32 mask;
 868         int err;
 869
 870         if (!dev_priv->psr.enabled)
 871                 return false;
 872
 873         if (dev_priv->psr.psr2_enabled) {
 874                 reg = EDP_PSR2_STATUS;
 875                 mask = EDP_PSR2_STATUS_STATE_MASK;
 876         } else {
 877                 reg = EDP_PSR_STATUS;
 878                 mask = EDP_PSR_STATUS_STATE_MASK;
 879         }
 880
 881         mutex_unlock(&dev_priv->psr.lock);
 882
 883         err = intel_wait_for_register(dev_priv, reg, mask, 0, 50);
 884         if (err)
 885                 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
 886
 887         /* After the unlocked wait, verify that PSR is still wanted! */
 888         mutex_lock(&dev_priv->psr.lock);
 889         return err == 0 && dev_priv->psr.enabled;
 890 }
 891
 892 static bool switching_psr(struct drm_i915_private *dev_priv,
 893                           struct intel_crtc_state *crtc_state,
 894                           u32 mode)
 895 {
 896         /* Can't switch psr state anyway if PSR2 is not supported. */
 897         if (!crtc_state || !crtc_state->has_psr2)
 898                 return false;
 899
 900         if (dev_priv->psr.psr2_enabled && mode == I915_PSR_DEBUG_FORCE_PSR1)
 901                 return true;
 902
 903         if (!dev_priv->psr.psr2_enabled && mode != I915_PSR_DEBUG_FORCE_PSR1)
 904                 return true;
 905
 906         return false;
 907 }
 908
 909 int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
 910                                struct drm_modeset_acquire_ctx *ctx,
 911                                u64 val)
 912 {
 913         struct drm_device *dev = &dev_priv->drm;
 914         struct drm_connector_state *conn_state;
 915         struct intel_crtc_state *crtc_state = NULL;
 916         struct drm_crtc_commit *commit;
 917         struct drm_crtc *crtc;
 918         struct intel_dp *dp;
 919         int ret;
 920         bool enable;
 921         u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
 922
 923         if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||
 924             mode > I915_PSR_DEBUG_FORCE_PSR1) {
 925                 DRM_DEBUG_KMS("Invalid debug mask %llx\n", val);
 926                 return -EINVAL;
 927         }
 928
 929         ret = drm_modeset_lock(&dev->mode_config.connection_mutex, ctx);
 930         if (ret)
 931                 return ret;
 932
 933         /* dev_priv->psr.dp should be set once and then never touched again. */
 934         dp = READ_ONCE(dev_priv->psr.dp);
 935         conn_state = dp->attached_connector->base.state;
 936         crtc = conn_state->crtc;
 937         if (crtc) {
 938                 ret = drm_modeset_lock(&crtc->mutex, ctx);
 939                 if (ret)
 940                         return ret;
 941
 942                 crtc_state = to_intel_crtc_state(crtc->state);
 943                 commit = crtc_state->base.commit;
 944         } else {
 945                 commit = conn_state->commit;
 946         }
 947         if (commit) {
 948                 ret = wait_for_completion_interruptible(&commit->hw_done);
 949                 if (ret)
 950                         return ret;
 951         }
 952
 953         ret = mutex_lock_interruptible(&dev_priv->psr.lock);
 954         if (ret)
 955                 return ret;
 956
 957         enable = psr_global_enabled(val);
 958
 959         if (!enable || switching_psr(dev_priv, crtc_state, mode))
 960                 intel_psr_disable_locked(dev_priv->psr.dp);
 961
 962         dev_priv->psr.debug = val;
 963         if (crtc)
 964                 dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
 965
 966         intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
 967
 968         if (dev_priv->psr.prepared && enable)
 969                 intel_psr_enable_locked(dev_priv, crtc_state);
 970
 971         mutex_unlock(&dev_priv->psr.lock);
 972         return ret;
 973 }
 974
 975 static void intel_psr_handle_irq(struct drm_i915_private *dev_priv)
 976 {
 977         struct i915_psr *psr = &dev_priv->psr;
 978
 979         intel_psr_disable_locked(psr->dp);
 980         psr->sink_not_reliable = true;
 981         /* let's make sure that sink is awaken */
 982         drm_dp_dpcd_writeb(&psr->dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
 983 }
 984
 985 static void intel_psr_work(struct work_struct *work)
 986 {
 987         struct drm_i915_private *dev_priv =
 988                 container_of(work, typeof(*dev_priv), psr.work);
 989
 990         mutex_lock(&dev_priv->psr.lock);
 991
 992         if (!dev_priv->psr.enabled)
 993                 goto unlock;
 994
 995         if (READ_ONCE(dev_priv->psr.irq_aux_error))
 996                 intel_psr_handle_irq(dev_priv);
 997
 998         /*
 999          * We have to make sure PSR is ready for re-enable
1000          * otherwise it keeps disabled until next full enable/disable cycle.
1001          * PSR might take some time to get fully disabled
1002          * and be ready for re-enable.
1003          */
1004         if (!__psr_wait_for_idle_locked(dev_priv))
1005                 goto unlock;
1006
1007         /*
1008          * The delayed work can race with an invalidate hence we need to
1009          * recheck. Since psr_flush first clears this and then reschedules we
1010          * won't ever miss a flush when bailing out here.
1011          */
1012         if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active)
1013                 goto unlock;
1014
1015         intel_psr_activate(dev_priv->psr.dp);
1016 unlock:
1017         mutex_unlock(&dev_priv->psr.lock);
1018 }
1019
1020 /**
1021  * intel_psr_invalidate - Invalidade PSR
1022  * @dev_priv: i915 device
1023  * @frontbuffer_bits: frontbuffer plane tracking bits
1024  * @origin: which operation caused the invalidate
1025  *
1026  * Since the hardware frontbuffer tracking has gaps we need to integrate
1027  * with the software frontbuffer tracking. This function gets called every
1028  * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
1029  * disabled if the frontbuffer mask contains a buffer relevant to PSR.
1030  *
1031  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
1032  */
1033 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1034                           unsigned frontbuffer_bits, enum fb_op_origin origin)
1035 {
1036         if (!CAN_PSR(dev_priv))
1037                 return;
1038
1039         if (origin == ORIGIN_FLIP)
1040                 return;
1041
1042         mutex_lock(&dev_priv->psr.lock);
1043         if (!dev_priv->psr.enabled) {
1044                 mutex_unlock(&dev_priv->psr.lock);
1045                 return;
1046         }
1047
1048         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe);
1049         dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
1050
1051         if (frontbuffer_bits)
1052                 intel_psr_exit(dev_priv);
1053
1054         mutex_unlock(&dev_priv->psr.lock);
1055 }
1056
1057 /**
1058  * intel_psr_flush - Flush PSR
1059  * @dev_priv: i915 device
1060  * @frontbuffer_bits: frontbuffer plane tracking bits
1061  * @origin: which operation caused the flush
1062  *
1063  * Since the hardware frontbuffer tracking has gaps we need to integrate
1064  * with the software frontbuffer tracking. This function gets called every
1065  * time frontbuffer rendering has completed and flushed out to memory. PSR
1066  * can be enabled again if no other frontbuffer relevant to PSR is dirty.
1067  *
1068  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
1069  */
1070 void intel_psr_flush(struct drm_i915_private *dev_priv,
1071                      unsigned frontbuffer_bits, enum fb_op_origin origin)
1072 {
1073         if (!CAN_PSR(dev_priv))
1074                 return;
1075
1076         if (origin == ORIGIN_FLIP)
1077                 return;
1078
1079         mutex_lock(&dev_priv->psr.lock);
1080         if (!dev_priv->psr.enabled) {
1081                 mutex_unlock(&dev_priv->psr.lock);
1082                 return;
1083         }
1084
1085         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe);
1086         dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
1087
1088         /* By definition flush = invalidate + flush */
1089         if (frontbuffer_bits) {
1090                 /*
1091                  * Display WA #0884: all
1092                  * This documented WA for bxt can be safely applied
1093                  * broadly so we can force HW tracking to exit PSR
1094                  * instead of disabling and re-enabling.
1095                  * Workaround tells us to write 0 to CUR_SURFLIVE_A,
1096                  * but it makes more sense write to the current active
1097                  * pipe.
1098                  */
1099                 I915_WRITE(CURSURFLIVE(dev_priv->psr.pipe), 0);
1100         }
1101
1102         if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
1103                 schedule_work(&dev_priv->psr.work);
1104         mutex_unlock(&dev_priv->psr.lock);
1105 }
1106
1107 /**
1108  * intel_psr_init - Init basic PSR work and mutex.
1109  * @dev_priv: i915 device private
1110  *
1111  * This function is  called only once at driver load to initialize basic
1112  * PSR stuff.
1113  */
1114 void intel_psr_init(struct drm_i915_private *dev_priv)
1115 {
1116         u32 val;
1117
1118         if (!HAS_PSR(dev_priv))
1119                 return;
1120
1121         dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
1122                 HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
1123
1124         if (!dev_priv->psr.sink_support)
1125                 return;
1126
1127         if (i915_modparams.enable_psr == -1)
1128                 if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable)
1129                         i915_modparams.enable_psr = 0;
1130
1131         /*
1132          * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
1133          * will still keep the error set even after the reset done in the
1134          * irq_preinstall and irq_uninstall hooks.
1135          * And enabling in this situation cause the screen to freeze in the
1136          * first time that PSR HW tries to activate so lets keep PSR disabled
1137          * to avoid any rendering problems.
1138          */
1139         val = I915_READ(EDP_PSR_IIR);
1140         val &= EDP_PSR_ERROR(edp_psr_shift(TRANSCODER_EDP));
1141         if (val) {
1142                 DRM_DEBUG_KMS("PSR interruption error set\n");
1143                 dev_priv->psr.sink_not_reliable = true;
1144                 return;
1145         }
1146
1147         /* Set link_standby x link_off defaults */
1148         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1149                 /* HSW and BDW require workarounds that we don't implement. */
1150                 dev_priv->psr.link_standby = false;
1151         else
1152                 /* For new platforms let's respect VBT back again */
1153                 dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
1154
1155         INIT_WORK(&dev_priv->psr.work, intel_psr_work);
1156         mutex_init(&dev_priv->psr.lock);
1157 }
1158
1159 void intel_psr_short_pulse(struct intel_dp *intel_dp)
1160 {
1161         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1162         struct i915_psr *psr = &dev_priv->psr;
1163         u8 val;
1164         const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
1165                           DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
1166                           DP_PSR_LINK_CRC_ERROR;
1167
1168         if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
1169                 return;
1170
1171         mutex_lock(&psr->lock);
1172
1173         if (!psr->enabled || psr->dp != intel_dp)
1174                 goto exit;
1175
1176         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) != 1) {
1177                 DRM_ERROR("PSR_STATUS dpcd read failed\n");
1178                 goto exit;
1179         }
1180
1181         if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR) {
1182                 DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n");
1183                 intel_psr_disable_locked(intel_dp);
1184                 psr->sink_not_reliable = true;
1185         }
1186
1187         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ERROR_STATUS, &val) != 1) {
1188                 DRM_ERROR("PSR_ERROR_STATUS dpcd read failed\n");
1189                 goto exit;
1190         }
1191
1192         if (val & DP_PSR_RFB_STORAGE_ERROR)
1193                 DRM_DEBUG_KMS("PSR RFB storage error, disabling PSR\n");
1194         if (val & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
1195                 DRM_DEBUG_KMS("PSR VSC SDP uncorrectable error, disabling PSR\n");
1196         if (val & DP_PSR_LINK_CRC_ERROR)
1197                 DRM_ERROR("PSR Link CRC error, disabling PSR\n");
1198
1199         if (val & ~errors)
1200                 DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n",
1201                           val & ~errors);
1202         if (val & errors) {
1203                 intel_psr_disable_locked(intel_dp);
1204                 psr->sink_not_reliable = true;
1205         }
1206         /* clear status register */
1207         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
1208 exit:
1209         mutex_unlock(&psr->lock);
1210 }
1211
1212 bool intel_psr_enabled(struct intel_dp *intel_dp)
1213 {
1214         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1215         bool ret;
1216
1217         if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
1218                 return false;
1219
1220         mutex_lock(&dev_priv->psr.lock);
1221         ret = (dev_priv->psr.dp == intel_dp && dev_priv->psr.enabled);
1222         mutex_unlock(&dev_priv->psr.lock);
1223
1224         return ret;
1225 }