drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include "i915_drv.h"
  31 #include "intel_drv.h"
  32 #include "../../../platform/x86/intel_ips.h"
  33 #include <linux/module.h>
  34
  35 /**
  36  * DOC: RC6
  37  *
  38  * RC6 is a special power stage which allows the GPU to enter an very
  39  * low-voltage mode when idle, using down to 0V while at this stage.  This
  40  * stage is entered automatically when the GPU is idle when RC6 support is
  41  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  42  *
  43  * There are different RC6 modes available in Intel GPU, which differentiate
  44  * among each other with the latency required to enter and leave RC6 and
  45  * voltage consumed by the GPU in different states.
  46  *
  47  * The combination of the following flags define which states GPU is allowed
  48  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  49  * RC6pp is deepest RC6. Their support by hardware varies according to the
  50  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  51  * which brings the most power savings; deeper states save more power, but
  52  * require higher latency to switch to and wake up.
  53  */
  54 #define INTEL_RC6_ENABLE                        (1<<0)
  55 #define INTEL_RC6p_ENABLE                       (1<<1)
  56 #define INTEL_RC6pp_ENABLE                      (1<<2)
  57
  58 static void gen9_init_clock_gating(struct drm_device *dev)
  59 {
  60         struct drm_i915_private *dev_priv = dev->dev_private;
  61
  62         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
  63         I915_WRITE(CHICKEN_PAR1_1,
  64                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  65
  66         I915_WRITE(GEN8_CONFIG0,
  67                    I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
  68
  69         /* WaEnableChickenDCPR:skl,bxt,kbl */
  70         I915_WRITE(GEN8_CHICKEN_DCPR_1,
  71                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  72
  73         /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
  74         /* WaFbcWakeMemOn:skl,bxt,kbl */
  75         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
  76                    DISP_FBC_WM_DIS |
  77                    DISP_FBC_MEMORY_WAKE);
  78
  79         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
  80         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
  81                    ILK_DPFC_DISABLE_DUMMY0);
  82 }
  83
  84 static void bxt_init_clock_gating(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = to_i915(dev);
  87
  88         gen9_init_clock_gating(dev);
  89
  90         /* WaDisableSDEUnitClockGating:bxt */
  91         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  92                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  93
  94         /*
  95          * FIXME:
  96          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  97          */
  98         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  99                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 100
 101         /*
 102          * Wa: Backlight PWM may stop in the asserted state, causing backlight
 103          * to stay fully on.
 104          */
 105         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
 106                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 107                            PWM1_GATING_DIS | PWM2_GATING_DIS);
 108 }
 109
 110 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 111 {
 112         struct drm_i915_private *dev_priv = to_i915(dev);
 113         u32 tmp;
 114
 115         tmp = I915_READ(CLKCFG);
 116
 117         switch (tmp & CLKCFG_FSB_MASK) {
 118         case CLKCFG_FSB_533:
 119                 dev_priv->fsb_freq = 533; /* 133*4 */
 120                 break;
 121         case CLKCFG_FSB_800:
 122                 dev_priv->fsb_freq = 800; /* 200*4 */
 123                 break;
 124         case CLKCFG_FSB_667:
 125                 dev_priv->fsb_freq =  667; /* 167*4 */
 126                 break;
 127         case CLKCFG_FSB_400:
 128                 dev_priv->fsb_freq = 400; /* 100*4 */
 129                 break;
 130         }
 131
 132         switch (tmp & CLKCFG_MEM_MASK) {
 133         case CLKCFG_MEM_533:
 134                 dev_priv->mem_freq = 533;
 135                 break;
 136         case CLKCFG_MEM_667:
 137                 dev_priv->mem_freq = 667;
 138                 break;
 139         case CLKCFG_MEM_800:
 140                 dev_priv->mem_freq = 800;
 141                 break;
 142         }
 143
 144         /* detect pineview DDR3 setting */
 145         tmp = I915_READ(CSHRDDR3CTL);
 146         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 147 }
 148
 149 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 150 {
 151         struct drm_i915_private *dev_priv = to_i915(dev);
 152         u16 ddrpll, csipll;
 153
 154         ddrpll = I915_READ16(DDRMPLL1);
 155         csipll = I915_READ16(CSIPLL0);
 156
 157         switch (ddrpll & 0xff) {
 158         case 0xc:
 159                 dev_priv->mem_freq = 800;
 160                 break;
 161         case 0x10:
 162                 dev_priv->mem_freq = 1066;
 163                 break;
 164         case 0x14:
 165                 dev_priv->mem_freq = 1333;
 166                 break;
 167         case 0x18:
 168                 dev_priv->mem_freq = 1600;
 169                 break;
 170         default:
 171                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 172                                  ddrpll & 0xff);
 173                 dev_priv->mem_freq = 0;
 174                 break;
 175         }
 176
 177         dev_priv->ips.r_t = dev_priv->mem_freq;
 178
 179         switch (csipll & 0x3ff) {
 180         case 0x00c:
 181                 dev_priv->fsb_freq = 3200;
 182                 break;
 183         case 0x00e:
 184                 dev_priv->fsb_freq = 3733;
 185                 break;
 186         case 0x010:
 187                 dev_priv->fsb_freq = 4266;
 188                 break;
 189         case 0x012:
 190                 dev_priv->fsb_freq = 4800;
 191                 break;
 192         case 0x014:
 193                 dev_priv->fsb_freq = 5333;
 194                 break;
 195         case 0x016:
 196                 dev_priv->fsb_freq = 5866;
 197                 break;
 198         case 0x018:
 199                 dev_priv->fsb_freq = 6400;
 200                 break;
 201         default:
 202                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 203                                  csipll & 0x3ff);
 204                 dev_priv->fsb_freq = 0;
 205                 break;
 206         }
 207
 208         if (dev_priv->fsb_freq == 3200) {
 209                 dev_priv->ips.c_m = 0;
 210         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 211                 dev_priv->ips.c_m = 1;
 212         } else {
 213                 dev_priv->ips.c_m = 2;
 214         }
 215 }
 216
 217 static const struct cxsr_latency cxsr_latency_table[] = {
 218         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 219         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 220         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 221         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 222         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 223
 224         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 225         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 226         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 227         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 228         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 229
 230         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 231         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 232         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 233         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 234         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 235
 236         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 237         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 238         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 239         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 240         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 241
 242         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 243         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 244         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 245         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 246         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 247
 248         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 249         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 250         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 251         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 252         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 253 };
 254
 255 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
 256                                                          bool is_ddr3,
 257                                                          int fsb,
 258                                                          int mem)
 259 {
 260         const struct cxsr_latency *latency;
 261         int i;
 262
 263         if (fsb == 0 || mem == 0)
 264                 return NULL;
 265
 266         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 267                 latency = &cxsr_latency_table[i];
 268                 if (is_desktop == latency->is_desktop &&
 269                     is_ddr3 == latency->is_ddr3 &&
 270                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 271                         return latency;
 272         }
 273
 274         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 275
 276         return NULL;
 277 }
 278
 279 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 280 {
 281         u32 val;
 282
 283         mutex_lock(&dev_priv->rps.hw_lock);
 284
 285         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 286         if (enable)
 287                 val &= ~FORCE_DDR_HIGH_FREQ;
 288         else
 289                 val |= FORCE_DDR_HIGH_FREQ;
 290         val &= ~FORCE_DDR_LOW_FREQ;
 291         val |= FORCE_DDR_FREQ_REQ_ACK;
 292         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 293
 294         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 295                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 296                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 297
 298         mutex_unlock(&dev_priv->rps.hw_lock);
 299 }
 300
 301 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 302 {
 303         u32 val;
 304
 305         mutex_lock(&dev_priv->rps.hw_lock);
 306
 307         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 308         if (enable)
 309                 val |= DSP_MAXFIFO_PM5_ENABLE;
 310         else
 311                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 312         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 313
 314         mutex_unlock(&dev_priv->rps.hw_lock);
 315 }
 316
 317 #define FW_WM(value, plane) \
 318         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 319
 320 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 321 {
 322         struct drm_device *dev = &dev_priv->drm;
 323         u32 val;
 324
 325         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 326                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 327                 POSTING_READ(FW_BLC_SELF_VLV);
 328                 dev_priv->wm.vlv.cxsr = enable;
 329         } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
 330                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 331                 POSTING_READ(FW_BLC_SELF);
 332         } else if (IS_PINEVIEW(dev)) {
 333                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 334                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 335                 I915_WRITE(DSPFW3, val);
 336                 POSTING_READ(DSPFW3);
 337         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
 338                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 339                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 340                 I915_WRITE(FW_BLC_SELF, val);
 341                 POSTING_READ(FW_BLC_SELF);
 342         } else if (IS_I915GM(dev_priv)) {
 343                 /*
 344                  * FIXME can't find a bit like this for 915G, and
 345                  * and yet it does have the related watermark in
 346                  * FW_BLC_SELF. What's going on?
 347                  */
 348                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 349                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 350                 I915_WRITE(INSTPM, val);
 351                 POSTING_READ(INSTPM);
 352         } else {
 353                 return;
 354         }
 355
 356         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 357                       enable ? "enabled" : "disabled");
 358 }
 359
 360
 361 /*
 362  * Latency for FIFO fetches is dependent on several factors:
 363  *   - memory configuration (speed, channels)
 364  *   - chipset
 365  *   - current MCH state
 366  * It can be fairly high in some situations, so here we assume a fairly
 367  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 368  * set this value too high, the FIFO will fetch frequently to stay full)
 369  * and power consumption (set it too low to save power and we might see
 370  * FIFO underruns and display "flicker").
 371  *
 372  * A value of 5us seems to be a good balance; safe for very low end
 373  * platforms but not overly aggressive on lower latency configs.
 374  */
 375 static const int pessimal_latency_ns = 5000;
 376
 377 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 378         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 379
 380 static int vlv_get_fifo_size(struct drm_device *dev,
 381                               enum pipe pipe, int plane)
 382 {
 383         struct drm_i915_private *dev_priv = to_i915(dev);
 384         int sprite0_start, sprite1_start, size;
 385
 386         switch (pipe) {
 387                 uint32_t dsparb, dsparb2, dsparb3;
 388         case PIPE_A:
 389                 dsparb = I915_READ(DSPARB);
 390                 dsparb2 = I915_READ(DSPARB2);
 391                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 392                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 393                 break;
 394         case PIPE_B:
 395                 dsparb = I915_READ(DSPARB);
 396                 dsparb2 = I915_READ(DSPARB2);
 397                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 398                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 399                 break;
 400         case PIPE_C:
 401                 dsparb2 = I915_READ(DSPARB2);
 402                 dsparb3 = I915_READ(DSPARB3);
 403                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 404                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 405                 break;
 406         default:
 407                 return 0;
 408         }
 409
 410         switch (plane) {
 411         case 0:
 412                 size = sprite0_start;
 413                 break;
 414         case 1:
 415                 size = sprite1_start - sprite0_start;
 416                 break;
 417         case 2:
 418                 size = 512 - 1 - sprite1_start;
 419                 break;
 420         default:
 421                 return 0;
 422         }
 423
 424         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 425                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 426                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 427                       size);
 428
 429         return size;
 430 }
 431
 432 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 433 {
 434         struct drm_i915_private *dev_priv = to_i915(dev);
 435         uint32_t dsparb = I915_READ(DSPARB);
 436         int size;
 437
 438         size = dsparb & 0x7f;
 439         if (plane)
 440                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 441
 442         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 443                       plane ? "B" : "A", size);
 444
 445         return size;
 446 }
 447
 448 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 449 {
 450         struct drm_i915_private *dev_priv = to_i915(dev);
 451         uint32_t dsparb = I915_READ(DSPARB);
 452         int size;
 453
 454         size = dsparb & 0x1ff;
 455         if (plane)
 456                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 457         size >>= 1; /* Convert to cachelines */
 458
 459         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 460                       plane ? "B" : "A", size);
 461
 462         return size;
 463 }
 464
 465 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 466 {
 467         struct drm_i915_private *dev_priv = to_i915(dev);
 468         uint32_t dsparb = I915_READ(DSPARB);
 469         int size;
 470
 471         size = dsparb & 0x7f;
 472         size >>= 2; /* Convert to cachelines */
 473
 474         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 475                       plane ? "B" : "A",
 476                       size);
 477
 478         return size;
 479 }
 480
 481 /* Pineview has different values for various configs */
 482 static const struct intel_watermark_params pineview_display_wm = {
 483         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 484         .max_wm = PINEVIEW_MAX_WM,
 485         .default_wm = PINEVIEW_DFT_WM,
 486         .guard_size = PINEVIEW_GUARD_WM,
 487         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 488 };
 489 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 490         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 491         .max_wm = PINEVIEW_MAX_WM,
 492         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 493         .guard_size = PINEVIEW_GUARD_WM,
 494         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 495 };
 496 static const struct intel_watermark_params pineview_cursor_wm = {
 497         .fifo_size = PINEVIEW_CURSOR_FIFO,
 498         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 499         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 500         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 501         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 502 };
 503 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 504         .fifo_size = PINEVIEW_CURSOR_FIFO,
 505         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 506         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 507         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 508         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 509 };
 510 static const struct intel_watermark_params g4x_wm_info = {
 511         .fifo_size = G4X_FIFO_SIZE,
 512         .max_wm = G4X_MAX_WM,
 513         .default_wm = G4X_MAX_WM,
 514         .guard_size = 2,
 515         .cacheline_size = G4X_FIFO_LINE_SIZE,
 516 };
 517 static const struct intel_watermark_params g4x_cursor_wm_info = {
 518         .fifo_size = I965_CURSOR_FIFO,
 519         .max_wm = I965_CURSOR_MAX_WM,
 520         .default_wm = I965_CURSOR_DFT_WM,
 521         .guard_size = 2,
 522         .cacheline_size = G4X_FIFO_LINE_SIZE,
 523 };
 524 static const struct intel_watermark_params i965_cursor_wm_info = {
 525         .fifo_size = I965_CURSOR_FIFO,
 526         .max_wm = I965_CURSOR_MAX_WM,
 527         .default_wm = I965_CURSOR_DFT_WM,
 528         .guard_size = 2,
 529         .cacheline_size = I915_FIFO_LINE_SIZE,
 530 };
 531 static const struct intel_watermark_params i945_wm_info = {
 532         .fifo_size = I945_FIFO_SIZE,
 533         .max_wm = I915_MAX_WM,
 534         .default_wm = 1,
 535         .guard_size = 2,
 536         .cacheline_size = I915_FIFO_LINE_SIZE,
 537 };
 538 static const struct intel_watermark_params i915_wm_info = {
 539         .fifo_size = I915_FIFO_SIZE,
 540         .max_wm = I915_MAX_WM,
 541         .default_wm = 1,
 542         .guard_size = 2,
 543         .cacheline_size = I915_FIFO_LINE_SIZE,
 544 };
 545 static const struct intel_watermark_params i830_a_wm_info = {
 546         .fifo_size = I855GM_FIFO_SIZE,
 547         .max_wm = I915_MAX_WM,
 548         .default_wm = 1,
 549         .guard_size = 2,
 550         .cacheline_size = I830_FIFO_LINE_SIZE,
 551 };
 552 static const struct intel_watermark_params i830_bc_wm_info = {
 553         .fifo_size = I855GM_FIFO_SIZE,
 554         .max_wm = I915_MAX_WM/2,
 555         .default_wm = 1,
 556         .guard_size = 2,
 557         .cacheline_size = I830_FIFO_LINE_SIZE,
 558 };
 559 static const struct intel_watermark_params i845_wm_info = {
 560         .fifo_size = I830_FIFO_SIZE,
 561         .max_wm = I915_MAX_WM,
 562         .default_wm = 1,
 563         .guard_size = 2,
 564         .cacheline_size = I830_FIFO_LINE_SIZE,
 565 };
 566
 567 /**
 568  * intel_calculate_wm - calculate watermark level
 569  * @clock_in_khz: pixel clock
 570  * @wm: chip FIFO params
 571  * @cpp: bytes per pixel
 572  * @latency_ns: memory latency for the platform
 573  *
 574  * Calculate the watermark level (the level at which the display plane will
 575  * start fetching from memory again).  Each chip has a different display
 576  * FIFO size and allocation, so the caller needs to figure that out and pass
 577  * in the correct intel_watermark_params structure.
 578  *
 579  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 580  * on the pixel size.  When it reaches the watermark level, it'll start
 581  * fetching FIFO line sized based chunks from memory until the FIFO fills
 582  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 583  * will occur, and a display engine hang could result.
 584  */
 585 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 586                                         const struct intel_watermark_params *wm,
 587                                         int fifo_size, int cpp,
 588                                         unsigned long latency_ns)
 589 {
 590         long entries_required, wm_size;
 591
 592         /*
 593          * Note: we need to make sure we don't overflow for various clock &
 594          * latency values.
 595          * clocks go from a few thousand to several hundred thousand.
 596          * latency is usually a few thousand
 597          */
 598         entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
 599                 1000;
 600         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 601
 602         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 603
 604         wm_size = fifo_size - (entries_required + wm->guard_size);
 605
 606         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 607
 608         /* Don't promote wm_size to unsigned... */
 609         if (wm_size > (long)wm->max_wm)
 610                 wm_size = wm->max_wm;
 611         if (wm_size <= 0)
 612                 wm_size = wm->default_wm;
 613
 614         /*
 615          * Bspec seems to indicate that the value shouldn't be lower than
 616          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 617          * Lets go for 8 which is the burst size since certain platforms
 618          * already use a hardcoded 8 (which is what the spec says should be
 619          * done).
 620          */
 621         if (wm_size <= 8)
 622                 wm_size = 8;
 623
 624         return wm_size;
 625 }
 626
 627 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 628 {
 629         struct drm_crtc *crtc, *enabled = NULL;
 630
 631         for_each_crtc(dev, crtc) {
 632                 if (intel_crtc_active(crtc)) {
 633                         if (enabled)
 634                                 return NULL;
 635                         enabled = crtc;
 636                 }
 637         }
 638
 639         return enabled;
 640 }
 641
 642 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 643 {
 644         struct drm_device *dev = unused_crtc->dev;
 645         struct drm_i915_private *dev_priv = to_i915(dev);
 646         struct drm_crtc *crtc;
 647         const struct cxsr_latency *latency;
 648         u32 reg;
 649         unsigned long wm;
 650
 651         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
 652                                          dev_priv->is_ddr3,
 653                                          dev_priv->fsb_freq,
 654                                          dev_priv->mem_freq);
 655         if (!latency) {
 656                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 657                 intel_set_memory_cxsr(dev_priv, false);
 658                 return;
 659         }
 660
 661         crtc = single_enabled_crtc(dev);
 662         if (crtc) {
 663                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 664                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 665                 int clock = adjusted_mode->crtc_clock;
 666
 667                 /* Display SR */
 668                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 669                                         pineview_display_wm.fifo_size,
 670                                         cpp, latency->display_sr);
 671                 reg = I915_READ(DSPFW1);
 672                 reg &= ~DSPFW_SR_MASK;
 673                 reg |= FW_WM(wm, SR);
 674                 I915_WRITE(DSPFW1, reg);
 675                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 676
 677                 /* cursor SR */
 678                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 679                                         pineview_display_wm.fifo_size,
 680                                         cpp, latency->cursor_sr);
 681                 reg = I915_READ(DSPFW3);
 682                 reg &= ~DSPFW_CURSOR_SR_MASK;
 683                 reg |= FW_WM(wm, CURSOR_SR);
 684                 I915_WRITE(DSPFW3, reg);
 685
 686                 /* Display HPLL off SR */
 687                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 688                                         pineview_display_hplloff_wm.fifo_size,
 689                                         cpp, latency->display_hpll_disable);
 690                 reg = I915_READ(DSPFW3);
 691                 reg &= ~DSPFW_HPLL_SR_MASK;
 692                 reg |= FW_WM(wm, HPLL_SR);
 693                 I915_WRITE(DSPFW3, reg);
 694
 695                 /* cursor HPLL off SR */
 696                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 697                                         pineview_display_hplloff_wm.fifo_size,
 698                                         cpp, latency->cursor_hpll_disable);
 699                 reg = I915_READ(DSPFW3);
 700                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 701                 reg |= FW_WM(wm, HPLL_CURSOR);
 702                 I915_WRITE(DSPFW3, reg);
 703                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 704
 705                 intel_set_memory_cxsr(dev_priv, true);
 706         } else {
 707                 intel_set_memory_cxsr(dev_priv, false);
 708         }
 709 }
 710
 711 static bool g4x_compute_wm0(struct drm_device *dev,
 712                             int plane,
 713                             const struct intel_watermark_params *display,
 714                             int display_latency_ns,
 715                             const struct intel_watermark_params *cursor,
 716                             int cursor_latency_ns,
 717                             int *plane_wm,
 718                             int *cursor_wm)
 719 {
 720         struct drm_crtc *crtc;
 721         const struct drm_display_mode *adjusted_mode;
 722         int htotal, hdisplay, clock, cpp;
 723         int line_time_us, line_count;
 724         int entries, tlb_miss;
 725
 726         crtc = intel_get_crtc_for_plane(dev, plane);
 727         if (!intel_crtc_active(crtc)) {
 728                 *cursor_wm = cursor->guard_size;
 729                 *plane_wm = display->guard_size;
 730                 return false;
 731         }
 732
 733         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 734         clock = adjusted_mode->crtc_clock;
 735         htotal = adjusted_mode->crtc_htotal;
 736         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 737         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 738
 739         /* Use the small buffer method to calculate plane watermark */
 740         entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
 741         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 742         if (tlb_miss > 0)
 743                 entries += tlb_miss;
 744         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 745         *plane_wm = entries + display->guard_size;
 746         if (*plane_wm > (int)display->max_wm)
 747                 *plane_wm = display->max_wm;
 748
 749         /* Use the large buffer method to calculate cursor watermark */
 750         line_time_us = max(htotal * 1000 / clock, 1);
 751         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 752         entries = line_count * crtc->cursor->state->crtc_w * cpp;
 753         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 754         if (tlb_miss > 0)
 755                 entries += tlb_miss;
 756         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 757         *cursor_wm = entries + cursor->guard_size;
 758         if (*cursor_wm > (int)cursor->max_wm)
 759                 *cursor_wm = (int)cursor->max_wm;
 760
 761         return true;
 762 }
 763
 764 /*
 765  * Check the wm result.
 766  *
 767  * If any calculated watermark values is larger than the maximum value that
 768  * can be programmed into the associated watermark register, that watermark
 769  * must be disabled.
 770  */
 771 static bool g4x_check_srwm(struct drm_device *dev,
 772                            int display_wm, int cursor_wm,
 773                            const struct intel_watermark_params *display,
 774                            const struct intel_watermark_params *cursor)
 775 {
 776         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 777                       display_wm, cursor_wm);
 778
 779         if (display_wm > display->max_wm) {
 780                 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
 781                               display_wm, display->max_wm);
 782                 return false;
 783         }
 784
 785         if (cursor_wm > cursor->max_wm) {
 786                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
 787                               cursor_wm, cursor->max_wm);
 788                 return false;
 789         }
 790
 791         if (!(display_wm || cursor_wm)) {
 792                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 793                 return false;
 794         }
 795
 796         return true;
 797 }
 798
 799 static bool g4x_compute_srwm(struct drm_device *dev,
 800                              int plane,
 801                              int latency_ns,
 802                              const struct intel_watermark_params *display,
 803                              const struct intel_watermark_params *cursor,
 804                              int *display_wm, int *cursor_wm)
 805 {
 806         struct drm_crtc *crtc;
 807         const struct drm_display_mode *adjusted_mode;
 808         int hdisplay, htotal, cpp, clock;
 809         unsigned long line_time_us;
 810         int line_count, line_size;
 811         int small, large;
 812         int entries;
 813
 814         if (!latency_ns) {
 815                 *display_wm = *cursor_wm = 0;
 816                 return false;
 817         }
 818
 819         crtc = intel_get_crtc_for_plane(dev, plane);
 820         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 821         clock = adjusted_mode->crtc_clock;
 822         htotal = adjusted_mode->crtc_htotal;
 823         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 824         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 825
 826         line_time_us = max(htotal * 1000 / clock, 1);
 827         line_count = (latency_ns / line_time_us + 1000) / 1000;
 828         line_size = hdisplay * cpp;
 829
 830         /* Use the minimum of the small and large buffer method for primary */
 831         small = ((clock * cpp / 1000) * latency_ns) / 1000;
 832         large = line_count * line_size;
 833
 834         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 835         *display_wm = entries + display->guard_size;
 836
 837         /* calculate the self-refresh watermark for display cursor */
 838         entries = line_count * cpp * crtc->cursor->state->crtc_w;
 839         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 840         *cursor_wm = entries + cursor->guard_size;
 841
 842         return g4x_check_srwm(dev,
 843                               *display_wm, *cursor_wm,
 844                               display, cursor);
 845 }
 846
 847 #define FW_WM_VLV(value, plane) \
 848         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 849
 850 static void vlv_write_wm_values(struct intel_crtc *crtc,
 851                                 const struct vlv_wm_values *wm)
 852 {
 853         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 854         enum pipe pipe = crtc->pipe;
 855
 856         I915_WRITE(VLV_DDL(pipe),
 857                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 858                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 859                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 860                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 861
 862         I915_WRITE(DSPFW1,
 863                    FW_WM(wm->sr.plane, SR) |
 864                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 865                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 866                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 867         I915_WRITE(DSPFW2,
 868                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 869                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 870                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 871         I915_WRITE(DSPFW3,
 872                    FW_WM(wm->sr.cursor, CURSOR_SR));
 873
 874         if (IS_CHERRYVIEW(dev_priv)) {
 875                 I915_WRITE(DSPFW7_CHV,
 876                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 877                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 878                 I915_WRITE(DSPFW8_CHV,
 879                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 880                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 881                 I915_WRITE(DSPFW9_CHV,
 882                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 883                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 884                 I915_WRITE(DSPHOWM,
 885                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 886                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 887                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 888                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 889                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 890                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 891                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 892                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 893                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 894                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 895         } else {
 896                 I915_WRITE(DSPFW7,
 897                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 898                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 899                 I915_WRITE(DSPHOWM,
 900                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 901                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 902                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 903                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 904                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 905                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 906                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 907         }
 908
 909         /* zero (unused) WM1 watermarks */
 910         I915_WRITE(DSPFW4, 0);
 911         I915_WRITE(DSPFW5, 0);
 912         I915_WRITE(DSPFW6, 0);
 913         I915_WRITE(DSPHOWM1, 0);
 914
 915         POSTING_READ(DSPFW1);
 916 }
 917
 918 #undef FW_WM_VLV
 919
 920 enum vlv_wm_level {
 921         VLV_WM_LEVEL_PM2,
 922         VLV_WM_LEVEL_PM5,
 923         VLV_WM_LEVEL_DDR_DVFS,
 924 };
 925
 926 /* latency must be in 0.1us units. */
 927 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 928                                    unsigned int pipe_htotal,
 929                                    unsigned int horiz_pixels,
 930                                    unsigned int cpp,
 931                                    unsigned int latency)
 932 {
 933         unsigned int ret;
 934
 935         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 936         ret = (ret + 1) * horiz_pixels * cpp;
 937         ret = DIV_ROUND_UP(ret, 64);
 938
 939         return ret;
 940 }
 941
 942 static void vlv_setup_wm_latency(struct drm_device *dev)
 943 {
 944         struct drm_i915_private *dev_priv = to_i915(dev);
 945
 946         /* all latencies in usec */
 947         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 948
 949         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 950
 951         if (IS_CHERRYVIEW(dev_priv)) {
 952                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 953                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 954
 955                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 956         }
 957 }
 958
 959 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 960                                      struct intel_crtc *crtc,
 961                                      const struct intel_plane_state *state,
 962                                      int level)
 963 {
 964         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 965         int clock, htotal, cpp, width, wm;
 966
 967         if (dev_priv->wm.pri_latency[level] == 0)
 968                 return USHRT_MAX;
 969
 970         if (!state->base.visible)
 971                 return 0;
 972
 973         cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 974         clock = crtc->config->base.adjusted_mode.crtc_clock;
 975         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 976         width = crtc->config->pipe_src_w;
 977         if (WARN_ON(htotal == 0))
 978                 htotal = 1;
 979
 980         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 981                 /*
 982                  * FIXME the formula gives values that are
 983                  * too big for the cursor FIFO, and hence we
 984                  * would never be able to use cursors. For
 985                  * now just hardcode the watermark.
 986                  */
 987                 wm = 63;
 988         } else {
 989                 wm = vlv_wm_method2(clock, htotal, width, cpp,
 990                                     dev_priv->wm.pri_latency[level] * 10);
 991         }
 992
 993         return min_t(int, wm, USHRT_MAX);
 994 }
 995
 996 static void vlv_compute_fifo(struct intel_crtc *crtc)
 997 {
 998         struct drm_device *dev = crtc->base.dev;
 999         struct vlv_wm_state *wm_state = &crtc->wm_state;
1000         struct intel_plane *plane;
1001         unsigned int total_rate = 0;
1002         const int fifo_size = 512 - 1;
1003         int fifo_extra, fifo_left = fifo_size;
1004
1005         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1006                 struct intel_plane_state *state =
1007                         to_intel_plane_state(plane->base.state);
1008
1009                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1010                         continue;
1011
1012                 if (state->base.visible) {
1013                         wm_state->num_active_planes++;
1014                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1015                 }
1016         }
1017
1018         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1019                 struct intel_plane_state *state =
1020                         to_intel_plane_state(plane->base.state);
1021                 unsigned int rate;
1022
1023                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1024                         plane->wm.fifo_size = 63;
1025                         continue;
1026                 }
1027
1028                 if (!state->base.visible) {
1029                         plane->wm.fifo_size = 0;
1030                         continue;
1031                 }
1032
1033                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1034                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1035                 fifo_left -= plane->wm.fifo_size;
1036         }
1037
1038         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1039
1040         /* spread the remainder evenly */
1041         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1042                 int plane_extra;
1043
1044                 if (fifo_left == 0)
1045                         break;
1046
1047                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1048                         continue;
1049
1050                 /* give it all to the first plane if none are active */
1051                 if (plane->wm.fifo_size == 0 &&
1052                     wm_state->num_active_planes)
1053                         continue;
1054
1055                 plane_extra = min(fifo_extra, fifo_left);
1056                 plane->wm.fifo_size += plane_extra;
1057                 fifo_left -= plane_extra;
1058         }
1059
1060         WARN_ON(fifo_left != 0);
1061 }
1062
1063 static void vlv_invert_wms(struct intel_crtc *crtc)
1064 {
1065         struct vlv_wm_state *wm_state = &crtc->wm_state;
1066         int level;
1067
1068         for (level = 0; level < wm_state->num_levels; level++) {
1069                 struct drm_device *dev = crtc->base.dev;
1070                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1071                 struct intel_plane *plane;
1072
1073                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1074                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1075
1076                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1077                         switch (plane->base.type) {
1078                                 int sprite;
1079                         case DRM_PLANE_TYPE_CURSOR:
1080                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1081                                         wm_state->wm[level].cursor;
1082                                 break;
1083                         case DRM_PLANE_TYPE_PRIMARY:
1084                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1085                                         wm_state->wm[level].primary;
1086                                 break;
1087                         case DRM_PLANE_TYPE_OVERLAY:
1088                                 sprite = plane->plane;
1089                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1090                                         wm_state->wm[level].sprite[sprite];
1091                                 break;
1092                         }
1093                 }
1094         }
1095 }
1096
1097 static void vlv_compute_wm(struct intel_crtc *crtc)
1098 {
1099         struct drm_device *dev = crtc->base.dev;
1100         struct vlv_wm_state *wm_state = &crtc->wm_state;
1101         struct intel_plane *plane;
1102         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1103         int level;
1104
1105         memset(wm_state, 0, sizeof(*wm_state));
1106
1107         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1108         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1109
1110         wm_state->num_active_planes = 0;
1111
1112         vlv_compute_fifo(crtc);
1113
1114         if (wm_state->num_active_planes != 1)
1115                 wm_state->cxsr = false;
1116
1117         if (wm_state->cxsr) {
1118                 for (level = 0; level < wm_state->num_levels; level++) {
1119                         wm_state->sr[level].plane = sr_fifo_size;
1120                         wm_state->sr[level].cursor = 63;
1121                 }
1122         }
1123
1124         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1125                 struct intel_plane_state *state =
1126                         to_intel_plane_state(plane->base.state);
1127
1128                 if (!state->base.visible)
1129                         continue;
1130
1131                 /* normal watermarks */
1132                 for (level = 0; level < wm_state->num_levels; level++) {
1133                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1134                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1135
1136                         /* hack */
1137                         if (WARN_ON(level == 0 && wm > max_wm))
1138                                 wm = max_wm;
1139
1140                         if (wm > plane->wm.fifo_size)
1141                                 break;
1142
1143                         switch (plane->base.type) {
1144                                 int sprite;
1145                         case DRM_PLANE_TYPE_CURSOR:
1146                                 wm_state->wm[level].cursor = wm;
1147                                 break;
1148                         case DRM_PLANE_TYPE_PRIMARY:
1149                                 wm_state->wm[level].primary = wm;
1150                                 break;
1151                         case DRM_PLANE_TYPE_OVERLAY:
1152                                 sprite = plane->plane;
1153                                 wm_state->wm[level].sprite[sprite] = wm;
1154                                 break;
1155                         }
1156                 }
1157
1158                 wm_state->num_levels = level;
1159
1160                 if (!wm_state->cxsr)
1161                         continue;
1162
1163                 /* maxfifo watermarks */
1164                 switch (plane->base.type) {
1165                         int sprite, level;
1166                 case DRM_PLANE_TYPE_CURSOR:
1167                         for (level = 0; level < wm_state->num_levels; level++)
1168                                 wm_state->sr[level].cursor =
1169                                         wm_state->wm[level].cursor;
1170                         break;
1171                 case DRM_PLANE_TYPE_PRIMARY:
1172                         for (level = 0; level < wm_state->num_levels; level++)
1173                                 wm_state->sr[level].plane =
1174                                         min(wm_state->sr[level].plane,
1175                                             wm_state->wm[level].primary);
1176                         break;
1177                 case DRM_PLANE_TYPE_OVERLAY:
1178                         sprite = plane->plane;
1179                         for (level = 0; level < wm_state->num_levels; level++)
1180                                 wm_state->sr[level].plane =
1181                                         min(wm_state->sr[level].plane,
1182                                             wm_state->wm[level].sprite[sprite]);
1183                         break;
1184                 }
1185         }
1186
1187         /* clear any (partially) filled invalid levels */
1188         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1189                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1190                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1191         }
1192
1193         vlv_invert_wms(crtc);
1194 }
1195
1196 #define VLV_FIFO(plane, value) \
1197         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1198
1199 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1200 {
1201         struct drm_device *dev = crtc->base.dev;
1202         struct drm_i915_private *dev_priv = to_i915(dev);
1203         struct intel_plane *plane;
1204         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1205
1206         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1207                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1208                         WARN_ON(plane->wm.fifo_size != 63);
1209                         continue;
1210                 }
1211
1212                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1213                         sprite0_start = plane->wm.fifo_size;
1214                 else if (plane->plane == 0)
1215                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1216                 else
1217                         fifo_size = sprite1_start + plane->wm.fifo_size;
1218         }
1219
1220         WARN_ON(fifo_size != 512 - 1);
1221
1222         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1223                       pipe_name(crtc->pipe), sprite0_start,
1224                       sprite1_start, fifo_size);
1225
1226         switch (crtc->pipe) {
1227                 uint32_t dsparb, dsparb2, dsparb3;
1228         case PIPE_A:
1229                 dsparb = I915_READ(DSPARB);
1230                 dsparb2 = I915_READ(DSPARB2);
1231
1232                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1233                             VLV_FIFO(SPRITEB, 0xff));
1234                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1235                            VLV_FIFO(SPRITEB, sprite1_start));
1236
1237                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1238                              VLV_FIFO(SPRITEB_HI, 0x1));
1239                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1240                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1241
1242                 I915_WRITE(DSPARB, dsparb);
1243                 I915_WRITE(DSPARB2, dsparb2);
1244                 break;
1245         case PIPE_B:
1246                 dsparb = I915_READ(DSPARB);
1247                 dsparb2 = I915_READ(DSPARB2);
1248
1249                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1250                             VLV_FIFO(SPRITED, 0xff));
1251                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1252                            VLV_FIFO(SPRITED, sprite1_start));
1253
1254                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1255                              VLV_FIFO(SPRITED_HI, 0xff));
1256                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1257                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1258
1259                 I915_WRITE(DSPARB, dsparb);
1260                 I915_WRITE(DSPARB2, dsparb2);
1261                 break;
1262         case PIPE_C:
1263                 dsparb3 = I915_READ(DSPARB3);
1264                 dsparb2 = I915_READ(DSPARB2);
1265
1266                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1267                              VLV_FIFO(SPRITEF, 0xff));
1268                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1269                             VLV_FIFO(SPRITEF, sprite1_start));
1270
1271                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1272                              VLV_FIFO(SPRITEF_HI, 0xff));
1273                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1274                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1275
1276                 I915_WRITE(DSPARB3, dsparb3);
1277                 I915_WRITE(DSPARB2, dsparb2);
1278                 break;
1279         default:
1280                 break;
1281         }
1282 }
1283
1284 #undef VLV_FIFO
1285
1286 static void vlv_merge_wm(struct drm_device *dev,
1287                          struct vlv_wm_values *wm)
1288 {
1289         struct intel_crtc *crtc;
1290         int num_active_crtcs = 0;
1291
1292         wm->level = to_i915(dev)->wm.max_level;
1293         wm->cxsr = true;
1294
1295         for_each_intel_crtc(dev, crtc) {
1296                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1297
1298                 if (!crtc->active)
1299                         continue;
1300
1301                 if (!wm_state->cxsr)
1302                         wm->cxsr = false;
1303
1304                 num_active_crtcs++;
1305                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1306         }
1307
1308         if (num_active_crtcs != 1)
1309                 wm->cxsr = false;
1310
1311         if (num_active_crtcs > 1)
1312                 wm->level = VLV_WM_LEVEL_PM2;
1313
1314         for_each_intel_crtc(dev, crtc) {
1315                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1316                 enum pipe pipe = crtc->pipe;
1317
1318                 if (!crtc->active)
1319                         continue;
1320
1321                 wm->pipe[pipe] = wm_state->wm[wm->level];
1322                 if (wm->cxsr)
1323                         wm->sr = wm_state->sr[wm->level];
1324
1325                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1326                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1327                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1328                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1329         }
1330 }
1331
1332 static void vlv_update_wm(struct drm_crtc *crtc)
1333 {
1334         struct drm_device *dev = crtc->dev;
1335         struct drm_i915_private *dev_priv = to_i915(dev);
1336         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1337         enum pipe pipe = intel_crtc->pipe;
1338         struct vlv_wm_values wm = {};
1339
1340         vlv_compute_wm(intel_crtc);
1341         vlv_merge_wm(dev, &wm);
1342
1343         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1344                 /* FIXME should be part of crtc atomic commit */
1345                 vlv_pipe_set_fifo_size(intel_crtc);
1346                 return;
1347         }
1348
1349         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1350             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1351                 chv_set_memory_dvfs(dev_priv, false);
1352
1353         if (wm.level < VLV_WM_LEVEL_PM5 &&
1354             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1355                 chv_set_memory_pm5(dev_priv, false);
1356
1357         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1358                 intel_set_memory_cxsr(dev_priv, false);
1359
1360         /* FIXME should be part of crtc atomic commit */
1361         vlv_pipe_set_fifo_size(intel_crtc);
1362
1363         vlv_write_wm_values(intel_crtc, &wm);
1364
1365         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1366                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1367                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1368                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1369                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1370
1371         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1372                 intel_set_memory_cxsr(dev_priv, true);
1373
1374         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1375             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1376                 chv_set_memory_pm5(dev_priv, true);
1377
1378         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1379             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1380                 chv_set_memory_dvfs(dev_priv, true);
1381
1382         dev_priv->wm.vlv = wm;
1383 }
1384
1385 #define single_plane_enabled(mask) is_power_of_2(mask)
1386
1387 static void g4x_update_wm(struct drm_crtc *crtc)
1388 {
1389         struct drm_device *dev = crtc->dev;
1390         static const int sr_latency_ns = 12000;
1391         struct drm_i915_private *dev_priv = to_i915(dev);
1392         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1393         int plane_sr, cursor_sr;
1394         unsigned int enabled = 0;
1395         bool cxsr_enabled;
1396
1397         if (g4x_compute_wm0(dev, PIPE_A,
1398                             &g4x_wm_info, pessimal_latency_ns,
1399                             &g4x_cursor_wm_info, pessimal_latency_ns,
1400                             &planea_wm, &cursora_wm))
1401                 enabled |= 1 << PIPE_A;
1402
1403         if (g4x_compute_wm0(dev, PIPE_B,
1404                             &g4x_wm_info, pessimal_latency_ns,
1405                             &g4x_cursor_wm_info, pessimal_latency_ns,
1406                             &planeb_wm, &cursorb_wm))
1407                 enabled |= 1 << PIPE_B;
1408
1409         if (single_plane_enabled(enabled) &&
1410             g4x_compute_srwm(dev, ffs(enabled) - 1,
1411                              sr_latency_ns,
1412                              &g4x_wm_info,
1413                              &g4x_cursor_wm_info,
1414                              &plane_sr, &cursor_sr)) {
1415                 cxsr_enabled = true;
1416         } else {
1417                 cxsr_enabled = false;
1418                 intel_set_memory_cxsr(dev_priv, false);
1419                 plane_sr = cursor_sr = 0;
1420         }
1421
1422         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1423                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1424                       planea_wm, cursora_wm,
1425                       planeb_wm, cursorb_wm,
1426                       plane_sr, cursor_sr);
1427
1428         I915_WRITE(DSPFW1,
1429                    FW_WM(plane_sr, SR) |
1430                    FW_WM(cursorb_wm, CURSORB) |
1431                    FW_WM(planeb_wm, PLANEB) |
1432                    FW_WM(planea_wm, PLANEA));
1433         I915_WRITE(DSPFW2,
1434                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1435                    FW_WM(cursora_wm, CURSORA));
1436         /* HPLL off in SR has some issues on G4x... disable it */
1437         I915_WRITE(DSPFW3,
1438                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1439                    FW_WM(cursor_sr, CURSOR_SR));
1440
1441         if (cxsr_enabled)
1442                 intel_set_memory_cxsr(dev_priv, true);
1443 }
1444
1445 static void i965_update_wm(struct drm_crtc *unused_crtc)
1446 {
1447         struct drm_device *dev = unused_crtc->dev;
1448         struct drm_i915_private *dev_priv = to_i915(dev);
1449         struct drm_crtc *crtc;
1450         int srwm = 1;
1451         int cursor_sr = 16;
1452         bool cxsr_enabled;
1453
1454         /* Calc sr entries for one plane configs */
1455         crtc = single_enabled_crtc(dev);
1456         if (crtc) {
1457                 /* self-refresh has much higher latency */
1458                 static const int sr_latency_ns = 12000;
1459                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1460                 int clock = adjusted_mode->crtc_clock;
1461                 int htotal = adjusted_mode->crtc_htotal;
1462                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1463                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1464                 unsigned long line_time_us;
1465                 int entries;
1466
1467                 line_time_us = max(htotal * 1000 / clock, 1);
1468
1469                 /* Use ns/us then divide to preserve precision */
1470                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1471                         cpp * hdisplay;
1472                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1473                 srwm = I965_FIFO_SIZE - entries;
1474                 if (srwm < 0)
1475                         srwm = 1;
1476                 srwm &= 0x1ff;
1477                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1478                               entries, srwm);
1479
1480                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1481                         cpp * crtc->cursor->state->crtc_w;
1482                 entries = DIV_ROUND_UP(entries,
1483                                           i965_cursor_wm_info.cacheline_size);
1484                 cursor_sr = i965_cursor_wm_info.fifo_size -
1485                         (entries + i965_cursor_wm_info.guard_size);
1486
1487                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1488                         cursor_sr = i965_cursor_wm_info.max_wm;
1489
1490                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1491                               "cursor %d\n", srwm, cursor_sr);
1492
1493                 cxsr_enabled = true;
1494         } else {
1495                 cxsr_enabled = false;
1496                 /* Turn off self refresh if both pipes are enabled */
1497                 intel_set_memory_cxsr(dev_priv, false);
1498         }
1499
1500         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1501                       srwm);
1502
1503         /* 965 has limitations... */
1504         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1505                    FW_WM(8, CURSORB) |
1506                    FW_WM(8, PLANEB) |
1507                    FW_WM(8, PLANEA));
1508         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1509                    FW_WM(8, PLANEC_OLD));
1510         /* update cursor SR watermark */
1511         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1512
1513         if (cxsr_enabled)
1514                 intel_set_memory_cxsr(dev_priv, true);
1515 }
1516
1517 #undef FW_WM
1518
1519 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1520 {
1521         struct drm_device *dev = unused_crtc->dev;
1522         struct drm_i915_private *dev_priv = to_i915(dev);
1523         const struct intel_watermark_params *wm_info;
1524         uint32_t fwater_lo;
1525         uint32_t fwater_hi;
1526         int cwm, srwm = 1;
1527         int fifo_size;
1528         int planea_wm, planeb_wm;
1529         struct drm_crtc *crtc, *enabled = NULL;
1530
1531         if (IS_I945GM(dev))
1532                 wm_info = &i945_wm_info;
1533         else if (!IS_GEN2(dev_priv))
1534                 wm_info = &i915_wm_info;
1535         else
1536                 wm_info = &i830_a_wm_info;
1537
1538         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1539         crtc = intel_get_crtc_for_plane(dev, 0);
1540         if (intel_crtc_active(crtc)) {
1541                 const struct drm_display_mode *adjusted_mode;
1542                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1543                 if (IS_GEN2(dev_priv))
1544                         cpp = 4;
1545
1546                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1547                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1548                                                wm_info, fifo_size, cpp,
1549                                                pessimal_latency_ns);
1550                 enabled = crtc;
1551         } else {
1552                 planea_wm = fifo_size - wm_info->guard_size;
1553                 if (planea_wm > (long)wm_info->max_wm)
1554                         planea_wm = wm_info->max_wm;
1555         }
1556
1557         if (IS_GEN2(dev_priv))
1558                 wm_info = &i830_bc_wm_info;
1559
1560         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1561         crtc = intel_get_crtc_for_plane(dev, 1);
1562         if (intel_crtc_active(crtc)) {
1563                 const struct drm_display_mode *adjusted_mode;
1564                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1565                 if (IS_GEN2(dev_priv))
1566                         cpp = 4;
1567
1568                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1569                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1570                                                wm_info, fifo_size, cpp,
1571                                                pessimal_latency_ns);
1572                 if (enabled == NULL)
1573                         enabled = crtc;
1574                 else
1575                         enabled = NULL;
1576         } else {
1577                 planeb_wm = fifo_size - wm_info->guard_size;
1578                 if (planeb_wm > (long)wm_info->max_wm)
1579                         planeb_wm = wm_info->max_wm;
1580         }
1581
1582         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1583
1584         if (IS_I915GM(dev_priv) && enabled) {
1585                 struct drm_i915_gem_object *obj;
1586
1587                 obj = intel_fb_obj(enabled->primary->state->fb);
1588
1589                 /* self-refresh seems busted with untiled */
1590                 if (!i915_gem_object_is_tiled(obj))
1591                         enabled = NULL;
1592         }
1593
1594         /*
1595          * Overlay gets an aggressive default since video jitter is bad.
1596          */
1597         cwm = 2;
1598
1599         /* Play safe and disable self-refresh before adjusting watermarks. */
1600         intel_set_memory_cxsr(dev_priv, false);
1601
1602         /* Calc sr entries for one plane configs */
1603         if (HAS_FW_BLC(dev) && enabled) {
1604                 /* self-refresh has much higher latency */
1605                 static const int sr_latency_ns = 6000;
1606                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1607                 int clock = adjusted_mode->crtc_clock;
1608                 int htotal = adjusted_mode->crtc_htotal;
1609                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1610                 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1611                 unsigned long line_time_us;
1612                 int entries;
1613
1614                 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
1615                         cpp = 4;
1616
1617                 line_time_us = max(htotal * 1000 / clock, 1);
1618
1619                 /* Use ns/us then divide to preserve precision */
1620                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1621                         cpp * hdisplay;
1622                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1623                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1624                 srwm = wm_info->fifo_size - entries;
1625                 if (srwm < 0)
1626                         srwm = 1;
1627
1628                 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1629                         I915_WRITE(FW_BLC_SELF,
1630                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1631                 else
1632                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1633         }
1634
1635         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1636                       planea_wm, planeb_wm, cwm, srwm);
1637
1638         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1639         fwater_hi = (cwm & 0x1f);
1640
1641         /* Set request length to 8 cachelines per fetch */
1642         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1643         fwater_hi = fwater_hi | (1 << 8);
1644
1645         I915_WRITE(FW_BLC, fwater_lo);
1646         I915_WRITE(FW_BLC2, fwater_hi);
1647
1648         if (enabled)
1649                 intel_set_memory_cxsr(dev_priv, true);
1650 }
1651
1652 static void i845_update_wm(struct drm_crtc *unused_crtc)
1653 {
1654         struct drm_device *dev = unused_crtc->dev;
1655         struct drm_i915_private *dev_priv = to_i915(dev);
1656         struct drm_crtc *crtc;
1657         const struct drm_display_mode *adjusted_mode;
1658         uint32_t fwater_lo;
1659         int planea_wm;
1660
1661         crtc = single_enabled_crtc(dev);
1662         if (crtc == NULL)
1663                 return;
1664
1665         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1666         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1667                                        &i845_wm_info,
1668                                        dev_priv->display.get_fifo_size(dev, 0),
1669                                        4, pessimal_latency_ns);
1670         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1671         fwater_lo |= (3<<8) | planea_wm;
1672
1673         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1674
1675         I915_WRITE(FW_BLC, fwater_lo);
1676 }
1677
1678 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1679 {
1680         uint32_t pixel_rate;
1681
1682         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1683
1684         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1685          * adjust the pixel_rate here. */
1686
1687         if (pipe_config->pch_pfit.enabled) {
1688                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1689                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1690
1691                 pipe_w = pipe_config->pipe_src_w;
1692                 pipe_h = pipe_config->pipe_src_h;
1693
1694                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1695                 pfit_h = pfit_size & 0xFFFF;
1696                 if (pipe_w < pfit_w)
1697                         pipe_w = pfit_w;
1698                 if (pipe_h < pfit_h)
1699                         pipe_h = pfit_h;
1700
1701                 if (WARN_ON(!pfit_w || !pfit_h))
1702                         return pixel_rate;
1703
1704                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1705                                      pfit_w * pfit_h);
1706         }
1707
1708         return pixel_rate;
1709 }
1710
1711 /* latency must be in 0.1us units. */
1712 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1713 {
1714         uint64_t ret;
1715
1716         if (WARN(latency == 0, "Latency value missing\n"))
1717                 return UINT_MAX;
1718
1719         ret = (uint64_t) pixel_rate * cpp * latency;
1720         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1721
1722         return ret;
1723 }
1724
1725 /* latency must be in 0.1us units. */
1726 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1727                                uint32_t horiz_pixels, uint8_t cpp,
1728                                uint32_t latency)
1729 {
1730         uint32_t ret;
1731
1732         if (WARN(latency == 0, "Latency value missing\n"))
1733                 return UINT_MAX;
1734         if (WARN_ON(!pipe_htotal))
1735                 return UINT_MAX;
1736
1737         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1738         ret = (ret + 1) * horiz_pixels * cpp;
1739         ret = DIV_ROUND_UP(ret, 64) + 2;
1740         return ret;
1741 }
1742
1743 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1744                            uint8_t cpp)
1745 {
1746         /*
1747          * Neither of these should be possible since this function shouldn't be
1748          * called if the CRTC is off or the plane is invisible.  But let's be
1749          * extra paranoid to avoid a potential divide-by-zero if we screw up
1750          * elsewhere in the driver.
1751          */
1752         if (WARN_ON(!cpp))
1753                 return 0;
1754         if (WARN_ON(!horiz_pixels))
1755                 return 0;
1756
1757         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1758 }
1759
1760 struct ilk_wm_maximums {
1761         uint16_t pri;
1762         uint16_t spr;
1763         uint16_t cur;
1764         uint16_t fbc;
1765 };
1766
1767 /*
1768  * For both WM_PIPE and WM_LP.
1769  * mem_value must be in 0.1us units.
1770  */
1771 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1772                                    const struct intel_plane_state *pstate,
1773                                    uint32_t mem_value,
1774                                    bool is_lp)
1775 {
1776         int cpp = pstate->base.fb ?
1777                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1778         uint32_t method1, method2;
1779
1780         if (!cstate->base.active || !pstate->base.visible)
1781                 return 0;
1782
1783         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1784
1785         if (!is_lp)
1786                 return method1;
1787
1788         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1789                                  cstate->base.adjusted_mode.crtc_htotal,
1790                                  drm_rect_width(&pstate->base.dst),
1791                                  cpp, mem_value);
1792
1793         return min(method1, method2);
1794 }
1795
1796 /*
1797  * For both WM_PIPE and WM_LP.
1798  * mem_value must be in 0.1us units.
1799  */
1800 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1801                                    const struct intel_plane_state *pstate,
1802                                    uint32_t mem_value)
1803 {
1804         int cpp = pstate->base.fb ?
1805                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1806         uint32_t method1, method2;
1807
1808         if (!cstate->base.active || !pstate->base.visible)
1809                 return 0;
1810
1811         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1812         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1813                                  cstate->base.adjusted_mode.crtc_htotal,
1814                                  drm_rect_width(&pstate->base.dst),
1815                                  cpp, mem_value);
1816         return min(method1, method2);
1817 }
1818
1819 /*
1820  * For both WM_PIPE and WM_LP.
1821  * mem_value must be in 0.1us units.
1822  */
1823 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1824                                    const struct intel_plane_state *pstate,
1825                                    uint32_t mem_value)
1826 {
1827         /*
1828          * We treat the cursor plane as always-on for the purposes of watermark
1829          * calculation.  Until we have two-stage watermark programming merged,
1830          * this is necessary to avoid flickering.
1831          */
1832         int cpp = 4;
1833         int width = pstate->base.visible ? pstate->base.crtc_w : 64;
1834
1835         if (!cstate->base.active)
1836                 return 0;
1837
1838         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1839                               cstate->base.adjusted_mode.crtc_htotal,
1840                               width, cpp, mem_value);
1841 }
1842
1843 /* Only for WM_LP. */
1844 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1845                                    const struct intel_plane_state *pstate,
1846                                    uint32_t pri_val)
1847 {
1848         int cpp = pstate->base.fb ?
1849                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1850
1851         if (!cstate->base.active || !pstate->base.visible)
1852                 return 0;
1853
1854         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
1855 }
1856
1857 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1858 {
1859         if (INTEL_INFO(dev)->gen >= 8)
1860                 return 3072;
1861         else if (INTEL_INFO(dev)->gen >= 7)
1862                 return 768;
1863         else
1864                 return 512;
1865 }
1866
1867 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1868                                          int level, bool is_sprite)
1869 {
1870         if (INTEL_INFO(dev)->gen >= 8)
1871                 /* BDW primary/sprite plane watermarks */
1872                 return level == 0 ? 255 : 2047;
1873         else if (INTEL_INFO(dev)->gen >= 7)
1874                 /* IVB/HSW primary/sprite plane watermarks */
1875                 return level == 0 ? 127 : 1023;
1876         else if (!is_sprite)
1877                 /* ILK/SNB primary plane watermarks */
1878                 return level == 0 ? 127 : 511;
1879         else
1880                 /* ILK/SNB sprite plane watermarks */
1881                 return level == 0 ? 63 : 255;
1882 }
1883
1884 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1885                                           int level)
1886 {
1887         if (INTEL_INFO(dev)->gen >= 7)
1888                 return level == 0 ? 63 : 255;
1889         else
1890                 return level == 0 ? 31 : 63;
1891 }
1892
1893 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1894 {
1895         if (INTEL_INFO(dev)->gen >= 8)
1896                 return 31;
1897         else
1898                 return 15;
1899 }
1900
1901 /* Calculate the maximum primary/sprite plane watermark */
1902 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1903                                      int level,
1904                                      const struct intel_wm_config *config,
1905                                      enum intel_ddb_partitioning ddb_partitioning,
1906                                      bool is_sprite)
1907 {
1908         unsigned int fifo_size = ilk_display_fifo_size(dev);
1909
1910         /* if sprites aren't enabled, sprites get nothing */
1911         if (is_sprite && !config->sprites_enabled)
1912                 return 0;
1913
1914         /* HSW allows LP1+ watermarks even with multiple pipes */
1915         if (level == 0 || config->num_pipes_active > 1) {
1916                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1917
1918                 /*
1919                  * For some reason the non self refresh
1920                  * FIFO size is only half of the self
1921                  * refresh FIFO size on ILK/SNB.
1922                  */
1923                 if (INTEL_INFO(dev)->gen <= 6)
1924                         fifo_size /= 2;
1925         }
1926
1927         if (config->sprites_enabled) {
1928                 /* level 0 is always calculated with 1:1 split */
1929                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1930                         if (is_sprite)
1931                                 fifo_size *= 5;
1932                         fifo_size /= 6;
1933                 } else {
1934                         fifo_size /= 2;
1935                 }
1936         }
1937
1938         /* clamp to max that the registers can hold */
1939         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1940 }
1941
1942 /* Calculate the maximum cursor plane watermark */
1943 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1944                                       int level,
1945                                       const struct intel_wm_config *config)
1946 {
1947         /* HSW LP1+ watermarks w/ multiple pipes */
1948         if (level > 0 && config->num_pipes_active > 1)
1949                 return 64;
1950
1951         /* otherwise just report max that registers can hold */
1952         return ilk_cursor_wm_reg_max(dev, level);
1953 }
1954
1955 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1956                                     int level,
1957                                     const struct intel_wm_config *config,
1958                                     enum intel_ddb_partitioning ddb_partitioning,
1959                                     struct ilk_wm_maximums *max)
1960 {
1961         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1962         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1963         max->cur = ilk_cursor_wm_max(dev, level, config);
1964         max->fbc = ilk_fbc_wm_reg_max(dev);
1965 }
1966
1967 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1968                                         int level,
1969                                         struct ilk_wm_maximums *max)
1970 {
1971         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1972         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1973         max->cur = ilk_cursor_wm_reg_max(dev, level);
1974         max->fbc = ilk_fbc_wm_reg_max(dev);
1975 }
1976
1977 static bool ilk_validate_wm_level(int level,
1978                                   const struct ilk_wm_maximums *max,
1979                                   struct intel_wm_level *result)
1980 {
1981         bool ret;
1982
1983         /* already determined to be invalid? */
1984         if (!result->enable)
1985                 return false;
1986
1987         result->enable = result->pri_val <= max->pri &&
1988                          result->spr_val <= max->spr &&
1989                          result->cur_val <= max->cur;
1990
1991         ret = result->enable;
1992
1993         /*
1994          * HACK until we can pre-compute everything,
1995          * and thus fail gracefully if LP0 watermarks
1996          * are exceeded...
1997          */
1998         if (level == 0 && !result->enable) {
1999                 if (result->pri_val > max->pri)
2000                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2001                                       level, result->pri_val, max->pri);
2002                 if (result->spr_val > max->spr)
2003                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2004                                       level, result->spr_val, max->spr);
2005                 if (result->cur_val > max->cur)
2006                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2007                                       level, result->cur_val, max->cur);
2008
2009                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2010                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2011                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2012                 result->enable = true;
2013         }
2014
2015         return ret;
2016 }
2017
2018 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2019                                  const struct intel_crtc *intel_crtc,
2020                                  int level,
2021                                  struct intel_crtc_state *cstate,
2022                                  struct intel_plane_state *pristate,
2023                                  struct intel_plane_state *sprstate,
2024                                  struct intel_plane_state *curstate,
2025                                  struct intel_wm_level *result)
2026 {
2027         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2028         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2029         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2030
2031         /* WM1+ latency values stored in 0.5us units */
2032         if (level > 0) {
2033                 pri_latency *= 5;
2034                 spr_latency *= 5;
2035                 cur_latency *= 5;
2036         }
2037
2038         if (pristate) {
2039                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2040                                                      pri_latency, level);
2041                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2042         }
2043
2044         if (sprstate)
2045                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2046
2047         if (curstate)
2048                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2049
2050         result->enable = true;
2051 }
2052
2053 static uint32_t
2054 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2055 {
2056         const struct intel_atomic_state *intel_state =
2057                 to_intel_atomic_state(cstate->base.state);
2058         const struct drm_display_mode *adjusted_mode =
2059                 &cstate->base.adjusted_mode;
2060         u32 linetime, ips_linetime;
2061
2062         if (!cstate->base.active)
2063                 return 0;
2064         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2065                 return 0;
2066         if (WARN_ON(intel_state->cdclk == 0))
2067                 return 0;
2068
2069         /* The WM are computed with base on how long it takes to fill a single
2070          * row at the given clock rate, multiplied by 8.
2071          * */
2072         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2073                                      adjusted_mode->crtc_clock);
2074         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2075                                          intel_state->cdclk);
2076
2077         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2078                PIPE_WM_LINETIME_TIME(linetime);
2079 }
2080
2081 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2082 {
2083         struct drm_i915_private *dev_priv = to_i915(dev);
2084
2085         if (IS_GEN9(dev_priv)) {
2086                 uint32_t val;
2087                 int ret, i;
2088                 int level, max_level = ilk_wm_max_level(dev_priv);
2089
2090                 /* read the first set of memory latencies[0:3] */
2091                 val = 0; /* data0 to be programmed to 0 for first set */
2092                 mutex_lock(&dev_priv->rps.hw_lock);
2093                 ret = sandybridge_pcode_read(dev_priv,
2094                                              GEN9_PCODE_READ_MEM_LATENCY,
2095                                              &val);
2096                 mutex_unlock(&dev_priv->rps.hw_lock);
2097
2098                 if (ret) {
2099                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2100                         return;
2101                 }
2102
2103                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2104                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2105                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2106                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2107                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2108                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2109                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2110
2111                 /* read the second set of memory latencies[4:7] */
2112                 val = 1; /* data0 to be programmed to 1 for second set */
2113                 mutex_lock(&dev_priv->rps.hw_lock);
2114                 ret = sandybridge_pcode_read(dev_priv,
2115                                              GEN9_PCODE_READ_MEM_LATENCY,
2116                                              &val);
2117                 mutex_unlock(&dev_priv->rps.hw_lock);
2118                 if (ret) {
2119                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2120                         return;
2121                 }
2122
2123                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2124                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2125                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2126                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2127                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2128                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2129                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2130
2131                 /*
2132                  * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2133                  * need to be disabled. We make sure to sanitize the values out
2134                  * of the punit to satisfy this requirement.
2135                  */
2136                 for (level = 1; level <= max_level; level++) {
2137                         if (wm[level] == 0) {
2138                                 for (i = level + 1; i <= max_level; i++)
2139                                         wm[i] = 0;
2140                                 break;
2141                         }
2142                 }
2143
2144                 /*
2145                  * WaWmMemoryReadLatency:skl
2146                  *
2147                  * punit doesn't take into account the read latency so we need
2148                  * to add 2us to the various latency levels we retrieve from the
2149                  * punit when level 0 response data us 0us.
2150                  */
2151                 if (wm[0] == 0) {
2152                         wm[0] += 2;
2153                         for (level = 1; level <= max_level; level++) {
2154                                 if (wm[level] == 0)
2155                                         break;
2156                                 wm[level] += 2;
2157                         }
2158                 }
2159
2160         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2161                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2162
2163                 wm[0] = (sskpd >> 56) & 0xFF;
2164                 if (wm[0] == 0)
2165                         wm[0] = sskpd & 0xF;
2166                 wm[1] = (sskpd >> 4) & 0xFF;
2167                 wm[2] = (sskpd >> 12) & 0xFF;
2168                 wm[3] = (sskpd >> 20) & 0x1FF;
2169                 wm[4] = (sskpd >> 32) & 0x1FF;
2170         } else if (INTEL_INFO(dev)->gen >= 6) {
2171                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2172
2173                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2174                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2175                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2176                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2177         } else if (INTEL_INFO(dev)->gen >= 5) {
2178                 uint32_t mltr = I915_READ(MLTR_ILK);
2179
2180                 /* ILK primary LP0 latency is 700 ns */
2181                 wm[0] = 7;
2182                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2183                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2184         }
2185 }
2186
2187 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2188                                        uint16_t wm[5])
2189 {
2190         /* ILK sprite LP0 latency is 1300 ns */
2191         if (IS_GEN5(dev_priv))
2192                 wm[0] = 13;
2193 }
2194
2195 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2196                                        uint16_t wm[5])
2197 {
2198         /* ILK cursor LP0 latency is 1300 ns */
2199         if (IS_GEN5(dev_priv))
2200                 wm[0] = 13;
2201
2202         /* WaDoubleCursorLP3Latency:ivb */
2203         if (IS_IVYBRIDGE(dev_priv))
2204                 wm[3] *= 2;
2205 }
2206
2207 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2208 {
2209         /* how many WM levels are we expecting */
2210         if (INTEL_GEN(dev_priv) >= 9)
2211                 return 7;
2212         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2213                 return 4;
2214         else if (INTEL_GEN(dev_priv) >= 6)
2215                 return 3;
2216         else
2217                 return 2;
2218 }
2219
2220 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2221                                    const char *name,
2222                                    const uint16_t wm[8])
2223 {
2224         int level, max_level = ilk_wm_max_level(dev_priv);
2225
2226         for (level = 0; level <= max_level; level++) {
2227                 unsigned int latency = wm[level];
2228
2229                 if (latency == 0) {
2230                         DRM_ERROR("%s WM%d latency not provided\n",
2231                                   name, level);
2232                         continue;
2233                 }
2234
2235                 /*
2236                  * - latencies are in us on gen9.
2237                  * - before then, WM1+ latency values are in 0.5us units
2238                  */
2239                 if (IS_GEN9(dev_priv))
2240                         latency *= 10;
2241                 else if (level > 0)
2242                         latency *= 5;
2243
2244                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2245                               name, level, wm[level],
2246                               latency / 10, latency % 10);
2247         }
2248 }
2249
2250 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2251                                     uint16_t wm[5], uint16_t min)
2252 {
2253         int level, max_level = ilk_wm_max_level(dev_priv);
2254
2255         if (wm[0] >= min)
2256                 return false;
2257
2258         wm[0] = max(wm[0], min);
2259         for (level = 1; level <= max_level; level++)
2260                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2261
2262         return true;
2263 }
2264
2265 static void snb_wm_latency_quirk(struct drm_device *dev)
2266 {
2267         struct drm_i915_private *dev_priv = to_i915(dev);
2268         bool changed;
2269
2270         /*
2271          * The BIOS provided WM memory latency values are often
2272          * inadequate for high resolution displays. Adjust them.
2273          */
2274         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2275                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2276                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2277
2278         if (!changed)
2279                 return;
2280
2281         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2282         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2283         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2284         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2285 }
2286
2287 static void ilk_setup_wm_latency(struct drm_device *dev)
2288 {
2289         struct drm_i915_private *dev_priv = to_i915(dev);
2290
2291         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2292
2293         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2294                sizeof(dev_priv->wm.pri_latency));
2295         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2296                sizeof(dev_priv->wm.pri_latency));
2297
2298         intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
2299         intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
2300
2301         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2302         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2303         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2304
2305         if (IS_GEN6(dev_priv))
2306                 snb_wm_latency_quirk(dev);
2307 }
2308
2309 static void skl_setup_wm_latency(struct drm_device *dev)
2310 {
2311         struct drm_i915_private *dev_priv = to_i915(dev);
2312
2313         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2314         intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2315 }
2316
2317 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2318                                  struct intel_pipe_wm *pipe_wm)
2319 {
2320         /* LP0 watermark maximums depend on this pipe alone */
2321         const struct intel_wm_config config = {
2322                 .num_pipes_active = 1,
2323                 .sprites_enabled = pipe_wm->sprites_enabled,
2324                 .sprites_scaled = pipe_wm->sprites_scaled,
2325         };
2326         struct ilk_wm_maximums max;
2327
2328         /* LP0 watermarks always use 1/2 DDB partitioning */
2329         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2330
2331         /* At least LP0 must be valid */
2332         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2333                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2334                 return false;
2335         }
2336
2337         return true;
2338 }
2339
2340 /* Compute new watermarks for the pipe */
2341 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2342 {
2343         struct drm_atomic_state *state = cstate->base.state;
2344         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2345         struct intel_pipe_wm *pipe_wm;
2346         struct drm_device *dev = state->dev;
2347         const struct drm_i915_private *dev_priv = to_i915(dev);
2348         struct intel_plane *intel_plane;
2349         struct intel_plane_state *pristate = NULL;
2350         struct intel_plane_state *sprstate = NULL;
2351         struct intel_plane_state *curstate = NULL;
2352         int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
2353         struct ilk_wm_maximums max;
2354
2355         pipe_wm = &cstate->wm.ilk.optimal;
2356
2357         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2358                 struct intel_plane_state *ps;
2359
2360                 ps = intel_atomic_get_existing_plane_state(state,
2361                                                            intel_plane);
2362                 if (!ps)
2363                         continue;
2364
2365                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2366                         pristate = ps;
2367                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2368                         sprstate = ps;
2369                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2370                         curstate = ps;
2371         }
2372
2373         pipe_wm->pipe_enabled = cstate->base.active;
2374         if (sprstate) {
2375                 pipe_wm->sprites_enabled = sprstate->base.visible;
2376                 pipe_wm->sprites_scaled = sprstate->base.visible &&
2377                         (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2378                          drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
2379         }
2380
2381         usable_level = max_level;
2382
2383         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2384         if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
2385                 usable_level = 1;
2386
2387         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2388         if (pipe_wm->sprites_scaled)
2389                 usable_level = 0;
2390
2391         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2392                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2393
2394         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2395         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2396
2397         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2398                 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2399
2400         if (!ilk_validate_pipe_wm(dev, pipe_wm))
2401                 return -EINVAL;
2402
2403         ilk_compute_wm_reg_maximums(dev, 1, &max);
2404
2405         for (level = 1; level <= max_level; level++) {
2406                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2407
2408                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2409                                      pristate, sprstate, curstate, wm);
2410
2411                 /*
2412                  * Disable any watermark level that exceeds the
2413                  * register maximums since such watermarks are
2414                  * always invalid.
2415                  */
2416                 if (level > usable_level)
2417                         continue;
2418
2419                 if (ilk_validate_wm_level(level, &max, wm))
2420                         pipe_wm->wm[level] = *wm;
2421                 else
2422                         usable_level = level;
2423         }
2424
2425         return 0;
2426 }
2427
2428 /*
2429  * Build a set of 'intermediate' watermark values that satisfy both the old
2430  * state and the new state.  These can be programmed to the hardware
2431  * immediately.
2432  */
2433 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2434                                        struct intel_crtc *intel_crtc,
2435                                        struct intel_crtc_state *newstate)
2436 {
2437         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2438         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2439         int level, max_level = ilk_wm_max_level(to_i915(dev));
2440
2441         /*
2442          * Start with the final, target watermarks, then combine with the
2443          * currently active watermarks to get values that are safe both before
2444          * and after the vblank.
2445          */
2446         *a = newstate->wm.ilk.optimal;
2447         a->pipe_enabled |= b->pipe_enabled;
2448         a->sprites_enabled |= b->sprites_enabled;
2449         a->sprites_scaled |= b->sprites_scaled;
2450
2451         for (level = 0; level <= max_level; level++) {
2452                 struct intel_wm_level *a_wm = &a->wm[level];
2453                 const struct intel_wm_level *b_wm = &b->wm[level];
2454
2455                 a_wm->enable &= b_wm->enable;
2456                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2457                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2458                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2459                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2460         }
2461
2462         /*
2463          * We need to make sure that these merged watermark values are
2464          * actually a valid configuration themselves.  If they're not,
2465          * there's no safe way to transition from the old state to
2466          * the new state, so we need to fail the atomic transaction.
2467          */
2468         if (!ilk_validate_pipe_wm(dev, a))
2469                 return -EINVAL;
2470
2471         /*
2472          * If our intermediate WM are identical to the final WM, then we can
2473          * omit the post-vblank programming; only update if it's different.
2474          */
2475         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2476                 newstate->wm.need_postvbl_update = false;
2477
2478         return 0;
2479 }
2480
2481 /*
2482  * Merge the watermarks from all active pipes for a specific level.
2483  */
2484 static void ilk_merge_wm_level(struct drm_device *dev,
2485                                int level,
2486                                struct intel_wm_level *ret_wm)
2487 {
2488         const struct intel_crtc *intel_crtc;
2489
2490         ret_wm->enable = true;
2491
2492         for_each_intel_crtc(dev, intel_crtc) {
2493                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2494                 const struct intel_wm_level *wm = &active->wm[level];
2495
2496                 if (!active->pipe_enabled)
2497                         continue;
2498
2499                 /*
2500                  * The watermark values may have been used in the past,
2501                  * so we must maintain them in the registers for some
2502                  * time even if the level is now disabled.
2503                  */
2504                 if (!wm->enable)
2505                         ret_wm->enable = false;
2506
2507                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2508                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2509                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2510                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2511         }
2512 }
2513
2514 /*
2515  * Merge all low power watermarks for all active pipes.
2516  */
2517 static void ilk_wm_merge(struct drm_device *dev,
2518                          const struct intel_wm_config *config,
2519                          const struct ilk_wm_maximums *max,
2520                          struct intel_pipe_wm *merged)
2521 {
2522         struct drm_i915_private *dev_priv = to_i915(dev);
2523         int level, max_level = ilk_wm_max_level(dev_priv);
2524         int last_enabled_level = max_level;
2525
2526         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2527         if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
2528             config->num_pipes_active > 1)
2529                 last_enabled_level = 0;
2530
2531         /* ILK: FBC WM must be disabled always */
2532         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2533
2534         /* merge each WM1+ level */
2535         for (level = 1; level <= max_level; level++) {
2536                 struct intel_wm_level *wm = &merged->wm[level];
2537
2538                 ilk_merge_wm_level(dev, level, wm);
2539
2540                 if (level > last_enabled_level)
2541                         wm->enable = false;
2542                 else if (!ilk_validate_wm_level(level, max, wm))
2543                         /* make sure all following levels get disabled */
2544                         last_enabled_level = level - 1;
2545
2546                 /*
2547                  * The spec says it is preferred to disable
2548                  * FBC WMs instead of disabling a WM level.
2549                  */
2550                 if (wm->fbc_val > max->fbc) {
2551                         if (wm->enable)
2552                                 merged->fbc_wm_enabled = false;
2553                         wm->fbc_val = 0;
2554                 }
2555         }
2556
2557         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2558         /*
2559          * FIXME this is racy. FBC might get enabled later.
2560          * What we should check here is whether FBC can be
2561          * enabled sometime later.
2562          */
2563         if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
2564             intel_fbc_is_active(dev_priv)) {
2565                 for (level = 2; level <= max_level; level++) {
2566                         struct intel_wm_level *wm = &merged->wm[level];
2567
2568                         wm->enable = false;
2569                 }
2570         }
2571 }
2572
2573 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2574 {
2575         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2576         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2577 }
2578
2579 /* The value we need to program into the WM_LPx latency field */
2580 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2581 {
2582         struct drm_i915_private *dev_priv = to_i915(dev);
2583
2584         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2585                 return 2 * level;
2586         else
2587                 return dev_priv->wm.pri_latency[level];
2588 }
2589
2590 static void ilk_compute_wm_results(struct drm_device *dev,
2591                                    const struct intel_pipe_wm *merged,
2592                                    enum intel_ddb_partitioning partitioning,
2593                                    struct ilk_wm_values *results)
2594 {
2595         struct intel_crtc *intel_crtc;
2596         int level, wm_lp;
2597
2598         results->enable_fbc_wm = merged->fbc_wm_enabled;
2599         results->partitioning = partitioning;
2600
2601         /* LP1+ register values */
2602         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2603                 const struct intel_wm_level *r;
2604
2605                 level = ilk_wm_lp_to_level(wm_lp, merged);
2606
2607                 r = &merged->wm[level];
2608
2609                 /*
2610                  * Maintain the watermark values even if the level is
2611                  * disabled. Doing otherwise could cause underruns.
2612                  */
2613                 results->wm_lp[wm_lp - 1] =
2614                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2615                         (r->pri_val << WM1_LP_SR_SHIFT) |
2616                         r->cur_val;
2617
2618                 if (r->enable)
2619                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2620
2621                 if (INTEL_INFO(dev)->gen >= 8)
2622                         results->wm_lp[wm_lp - 1] |=
2623                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2624                 else
2625                         results->wm_lp[wm_lp - 1] |=
2626                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2627
2628                 /*
2629                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2630                  * level is disabled. Doing otherwise could cause underruns.
2631                  */
2632                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2633                         WARN_ON(wm_lp != 1);
2634                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2635                 } else
2636                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2637         }
2638
2639         /* LP0 register values */
2640         for_each_intel_crtc(dev, intel_crtc) {
2641                 enum pipe pipe = intel_crtc->pipe;
2642                 const struct intel_wm_level *r =
2643                         &intel_crtc->wm.active.ilk.wm[0];
2644
2645                 if (WARN_ON(!r->enable))
2646                         continue;
2647
2648                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2649
2650                 results->wm_pipe[pipe] =
2651                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2652                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2653                         r->cur_val;
2654         }
2655 }
2656
2657 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2658  * case both are at the same level. Prefer r1 in case they're the same. */
2659 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2660                                                   struct intel_pipe_wm *r1,
2661                                                   struct intel_pipe_wm *r2)
2662 {
2663         int level, max_level = ilk_wm_max_level(to_i915(dev));
2664         int level1 = 0, level2 = 0;
2665
2666         for (level = 1; level <= max_level; level++) {
2667                 if (r1->wm[level].enable)
2668                         level1 = level;
2669                 if (r2->wm[level].enable)
2670                         level2 = level;
2671         }
2672
2673         if (level1 == level2) {
2674                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2675                         return r2;
2676                 else
2677                         return r1;
2678         } else if (level1 > level2) {
2679                 return r1;
2680         } else {
2681                 return r2;
2682         }
2683 }
2684
2685 /* dirty bits used to track which watermarks need changes */
2686 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2687 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2688 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2689 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2690 #define WM_DIRTY_FBC (1 << 24)
2691 #define WM_DIRTY_DDB (1 << 25)
2692
2693 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2694                                          const struct ilk_wm_values *old,
2695                                          const struct ilk_wm_values *new)
2696 {
2697         unsigned int dirty = 0;
2698         enum pipe pipe;
2699         int wm_lp;
2700
2701         for_each_pipe(dev_priv, pipe) {
2702                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2703                         dirty |= WM_DIRTY_LINETIME(pipe);
2704                         /* Must disable LP1+ watermarks too */
2705                         dirty |= WM_DIRTY_LP_ALL;
2706                 }
2707
2708                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2709                         dirty |= WM_DIRTY_PIPE(pipe);
2710                         /* Must disable LP1+ watermarks too */
2711                         dirty |= WM_DIRTY_LP_ALL;
2712                 }
2713         }
2714
2715         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2716                 dirty |= WM_DIRTY_FBC;
2717                 /* Must disable LP1+ watermarks too */
2718                 dirty |= WM_DIRTY_LP_ALL;
2719         }
2720
2721         if (old->partitioning != new->partitioning) {
2722                 dirty |= WM_DIRTY_DDB;
2723                 /* Must disable LP1+ watermarks too */
2724                 dirty |= WM_DIRTY_LP_ALL;
2725         }
2726
2727         /* LP1+ watermarks already deemed dirty, no need to continue */
2728         if (dirty & WM_DIRTY_LP_ALL)
2729                 return dirty;
2730
2731         /* Find the lowest numbered LP1+ watermark in need of an update... */
2732         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2733                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2734                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2735                         break;
2736         }
2737
2738         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2739         for (; wm_lp <= 3; wm_lp++)
2740                 dirty |= WM_DIRTY_LP(wm_lp);
2741
2742         return dirty;
2743 }
2744
2745 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2746                                unsigned int dirty)
2747 {
2748         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2749         bool changed = false;
2750
2751         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2752                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2753                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2754                 changed = true;
2755         }
2756         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2757                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2758                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2759                 changed = true;
2760         }
2761         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2762                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2763                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2764                 changed = true;
2765         }
2766
2767         /*
2768          * Don't touch WM1S_LP_EN here.
2769          * Doing so could cause underruns.
2770          */
2771
2772         return changed;
2773 }
2774
2775 /*
2776  * The spec says we shouldn't write when we don't need, because every write
2777  * causes WMs to be re-evaluated, expending some power.
2778  */
2779 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2780                                 struct ilk_wm_values *results)
2781 {
2782         struct drm_device *dev = &dev_priv->drm;
2783         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2784         unsigned int dirty;
2785         uint32_t val;
2786
2787         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2788         if (!dirty)
2789                 return;
2790
2791         _ilk_disable_lp_wm(dev_priv, dirty);
2792
2793         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2794                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2795         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2796                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2797         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2798                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2799
2800         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2801                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2802         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2803                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2804         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2805                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2806
2807         if (dirty & WM_DIRTY_DDB) {
2808                 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2809                         val = I915_READ(WM_MISC);
2810                         if (results->partitioning == INTEL_DDB_PART_1_2)
2811                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2812                         else
2813                                 val |= WM_MISC_DATA_PARTITION_5_6;
2814                         I915_WRITE(WM_MISC, val);
2815                 } else {
2816                         val = I915_READ(DISP_ARB_CTL2);
2817                         if (results->partitioning == INTEL_DDB_PART_1_2)
2818                                 val &= ~DISP_DATA_PARTITION_5_6;
2819                         else
2820                                 val |= DISP_DATA_PARTITION_5_6;
2821                         I915_WRITE(DISP_ARB_CTL2, val);
2822                 }
2823         }
2824
2825         if (dirty & WM_DIRTY_FBC) {
2826                 val = I915_READ(DISP_ARB_CTL);
2827                 if (results->enable_fbc_wm)
2828                         val &= ~DISP_FBC_WM_DIS;
2829                 else
2830                         val |= DISP_FBC_WM_DIS;
2831                 I915_WRITE(DISP_ARB_CTL, val);
2832         }
2833
2834         if (dirty & WM_DIRTY_LP(1) &&
2835             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2836                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2837
2838         if (INTEL_INFO(dev)->gen >= 7) {
2839                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2840                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2841                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2842                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2843         }
2844
2845         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2846                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2847         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2848                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2849         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2850                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2851
2852         dev_priv->wm.hw = *results;
2853 }
2854
2855 bool ilk_disable_lp_wm(struct drm_device *dev)
2856 {
2857         struct drm_i915_private *dev_priv = to_i915(dev);
2858
2859         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2860 }
2861
2862 #define SKL_SAGV_BLOCK_TIME     30 /* µs */
2863
2864 /*
2865  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2866  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2867  * other universal planes are in indices 1..n.  Note that this may leave unused
2868  * indices between the top "sprite" plane and the cursor.
2869  */
2870 static int
2871 skl_wm_plane_id(const struct intel_plane *plane)
2872 {
2873         switch (plane->base.type) {
2874         case DRM_PLANE_TYPE_PRIMARY:
2875                 return 0;
2876         case DRM_PLANE_TYPE_CURSOR:
2877                 return PLANE_CURSOR;
2878         case DRM_PLANE_TYPE_OVERLAY:
2879                 return plane->plane + 1;
2880         default:
2881                 MISSING_CASE(plane->base.type);
2882                 return plane->plane;
2883         }
2884 }
2885
2886 static bool
2887 intel_has_sagv(struct drm_i915_private *dev_priv)
2888 {
2889         if (IS_KABYLAKE(dev_priv))
2890                 return true;
2891
2892         if (IS_SKYLAKE(dev_priv) &&
2893             dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2894                 return true;
2895
2896         return false;
2897 }
2898
2899 /*
2900  * SAGV dynamically adjusts the system agent voltage and clock frequencies
2901  * depending on power and performance requirements. The display engine access
2902  * to system memory is blocked during the adjustment time. Because of the
2903  * blocking time, having this enabled can cause full system hangs and/or pipe
2904  * underruns if we don't meet all of the following requirements:
2905  *
2906  *  - <= 1 pipe enabled
2907  *  - All planes can enable watermarks for latencies >= SAGV engine block time
2908  *  - We're not using an interlaced display configuration
2909  */
2910 int
2911 intel_enable_sagv(struct drm_i915_private *dev_priv)
2912 {
2913         int ret;
2914
2915         if (!intel_has_sagv(dev_priv))
2916                 return 0;
2917
2918         if (dev_priv->sagv_status == I915_SAGV_ENABLED)
2919                 return 0;
2920
2921         DRM_DEBUG_KMS("Enabling the SAGV\n");
2922         mutex_lock(&dev_priv->rps.hw_lock);
2923
2924         ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2925                                       GEN9_SAGV_ENABLE);
2926
2927         /* We don't need to wait for the SAGV when enabling */
2928         mutex_unlock(&dev_priv->rps.hw_lock);
2929
2930         /*
2931          * Some skl systems, pre-release machines in particular,
2932          * don't actually have an SAGV.
2933          */
2934         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2935                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2936                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2937                 return 0;
2938         } else if (ret < 0) {
2939                 DRM_ERROR("Failed to enable the SAGV\n");
2940                 return ret;
2941         }
2942
2943         dev_priv->sagv_status = I915_SAGV_ENABLED;
2944         return 0;
2945 }
2946
2947 static int
2948 intel_do_sagv_disable(struct drm_i915_private *dev_priv)
2949 {
2950         int ret;
2951         uint32_t temp = GEN9_SAGV_DISABLE;
2952
2953         ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2954                                      &temp);
2955         if (ret)
2956                 return ret;
2957         else
2958                 return temp & GEN9_SAGV_IS_DISABLED;
2959 }
2960
2961 int
2962 intel_disable_sagv(struct drm_i915_private *dev_priv)
2963 {
2964         int ret, result;
2965
2966         if (!intel_has_sagv(dev_priv))
2967                 return 0;
2968
2969         if (dev_priv->sagv_status == I915_SAGV_DISABLED)
2970                 return 0;
2971
2972         DRM_DEBUG_KMS("Disabling the SAGV\n");
2973         mutex_lock(&dev_priv->rps.hw_lock);
2974
2975         /* bspec says to keep retrying for at least 1 ms */
2976         ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
2977         mutex_unlock(&dev_priv->rps.hw_lock);
2978
2979         if (ret == -ETIMEDOUT) {
2980                 DRM_ERROR("Request to disable SAGV timed out\n");
2981                 return -ETIMEDOUT;
2982         }
2983
2984         /*
2985          * Some skl systems, pre-release machines in particular,
2986          * don't actually have an SAGV.
2987          */
2988         if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
2989                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2990                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2991                 return 0;
2992         } else if (result < 0) {
2993                 DRM_ERROR("Failed to disable the SAGV\n");
2994                 return result;
2995         }
2996
2997         dev_priv->sagv_status = I915_SAGV_DISABLED;
2998         return 0;
2999 }
3000
3001 bool intel_can_enable_sagv(struct drm_atomic_state *state)
3002 {
3003         struct drm_device *dev = state->dev;
3004         struct drm_i915_private *dev_priv = to_i915(dev);
3005         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3006         struct drm_crtc *crtc;
3007         enum pipe pipe;
3008         int level, plane;
3009
3010         if (!intel_has_sagv(dev_priv))
3011                 return false;
3012
3013         /*
3014          * SKL workaround: bspec recommends we disable the SAGV when we have
3015          * more then one pipe enabled
3016          *
3017          * If there are no active CRTCs, no additional checks need be performed
3018          */
3019         if (hweight32(intel_state->active_crtcs) == 0)
3020                 return true;
3021         else if (hweight32(intel_state->active_crtcs) > 1)
3022                 return false;
3023
3024         /* Since we're now guaranteed to only have one active CRTC... */
3025         pipe = ffs(intel_state->active_crtcs) - 1;
3026         crtc = dev_priv->pipe_to_crtc_mapping[pipe];
3027
3028         if (crtc->state->mode.flags & DRM_MODE_FLAG_INTERLACE)
3029                 return false;
3030
3031         for_each_plane(dev_priv, pipe, plane) {
3032                 /* Skip this plane if it's not enabled */
3033                 if (intel_state->wm_results.plane[pipe][plane][0] == 0)
3034                         continue;
3035
3036                 /* Find the highest enabled wm level for this plane */
3037                 for (level = ilk_wm_max_level(dev_priv);
3038                      intel_state->wm_results.plane[pipe][plane][level] == 0; --level)
3039                      { }
3040
3041                 /*
3042                  * If any of the planes on this pipe don't enable wm levels
3043                  * that incur memory latencies higher then 30µs we can't enable
3044                  * the SAGV
3045                  */
3046                 if (dev_priv->wm.skl_latency[level] < SKL_SAGV_BLOCK_TIME)
3047                         return false;
3048         }
3049
3050         return true;
3051 }
3052
3053 static void
3054 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3055                                    const struct intel_crtc_state *cstate,
3056                                    struct skl_ddb_entry *alloc, /* out */
3057                                    int *num_active /* out */)
3058 {
3059         struct drm_atomic_state *state = cstate->base.state;
3060         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3061         struct drm_i915_private *dev_priv = to_i915(dev);
3062         struct drm_crtc *for_crtc = cstate->base.crtc;
3063         unsigned int pipe_size, ddb_size;
3064         int nth_active_pipe;
3065
3066         if (WARN_ON(!state) || !cstate->base.active) {
3067                 alloc->start = 0;
3068                 alloc->end = 0;
3069                 *num_active = hweight32(dev_priv->active_crtcs);
3070                 return;
3071         }
3072
3073         if (intel_state->active_pipe_changes)
3074                 *num_active = hweight32(intel_state->active_crtcs);
3075         else
3076                 *num_active = hweight32(dev_priv->active_crtcs);
3077
3078         ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3079         WARN_ON(ddb_size == 0);
3080
3081         ddb_size -= 4; /* 4 blocks for bypass path allocation */
3082
3083         /*
3084          * If the state doesn't change the active CRTC's, then there's
3085          * no need to recalculate; the existing pipe allocation limits
3086          * should remain unchanged.  Note that we're safe from racing
3087          * commits since any racing commit that changes the active CRTC
3088          * list would need to grab _all_ crtc locks, including the one
3089          * we currently hold.
3090          */
3091         if (!intel_state->active_pipe_changes) {
3092                 *alloc = to_intel_crtc(for_crtc)->hw_ddb;
3093                 return;
3094         }
3095
3096         nth_active_pipe = hweight32(intel_state->active_crtcs &
3097                                     (drm_crtc_mask(for_crtc) - 1));
3098         pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3099         alloc->start = nth_active_pipe * ddb_size / *num_active;
3100         alloc->end = alloc->start + pipe_size;
3101 }
3102
3103 static unsigned int skl_cursor_allocation(int num_active)
3104 {
3105         if (num_active == 1)
3106                 return 32;
3107
3108         return 8;
3109 }
3110
3111 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3112 {
3113         entry->start = reg & 0x3ff;
3114         entry->end = (reg >> 16) & 0x3ff;
3115         if (entry->end)
3116                 entry->end += 1;
3117 }
3118
3119 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3120                           struct skl_ddb_allocation *ddb /* out */)
3121 {
3122         enum pipe pipe;
3123         int plane;
3124         u32 val;
3125
3126         memset(ddb, 0, sizeof(*ddb));
3127
3128         for_each_pipe(dev_priv, pipe) {
3129                 enum intel_display_power_domain power_domain;
3130
3131                 power_domain = POWER_DOMAIN_PIPE(pipe);
3132                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3133                         continue;
3134
3135                 for_each_plane(dev_priv, pipe, plane) {
3136                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3137                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3138                                                    val);
3139                 }
3140
3141                 val = I915_READ(CUR_BUF_CFG(pipe));
3142                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3143                                            val);
3144
3145                 intel_display_power_put(dev_priv, power_domain);
3146         }
3147 }
3148
3149 /*
3150  * Determines the downscale amount of a plane for the purposes of watermark calculations.
3151  * The bspec defines downscale amount as:
3152  *
3153  * """
3154  * Horizontal down scale amount = maximum[1, Horizontal source size /
3155  *                                           Horizontal destination size]
3156  * Vertical down scale amount = maximum[1, Vertical source size /
3157  *                                         Vertical destination size]
3158  * Total down scale amount = Horizontal down scale amount *
3159  *                           Vertical down scale amount
3160  * """
3161  *
3162  * Return value is provided in 16.16 fixed point form to retain fractional part.
3163  * Caller should take care of dividing & rounding off the value.
3164  */
3165 static uint32_t
3166 skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3167 {
3168         uint32_t downscale_h, downscale_w;
3169         uint32_t src_w, src_h, dst_w, dst_h;
3170
3171         if (WARN_ON(!pstate->base.visible))
3172                 return DRM_PLANE_HELPER_NO_SCALING;
3173
3174         /* n.b., src is 16.16 fixed point, dst is whole integer */
3175         src_w = drm_rect_width(&pstate->base.src);
3176         src_h = drm_rect_height(&pstate->base.src);
3177         dst_w = drm_rect_width(&pstate->base.dst);
3178         dst_h = drm_rect_height(&pstate->base.dst);
3179         if (intel_rotation_90_or_270(pstate->base.rotation))
3180                 swap(dst_w, dst_h);
3181
3182         downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3183         downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3184
3185         /* Provide result in 16.16 fixed point */
3186         return (uint64_t)downscale_w * downscale_h >> 16;
3187 }
3188
3189 static unsigned int
3190 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3191                              const struct drm_plane_state *pstate,
3192                              int y)
3193 {
3194         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3195         struct drm_framebuffer *fb = pstate->fb;
3196         uint32_t down_scale_amount, data_rate;
3197         uint32_t width = 0, height = 0;
3198         unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3199
3200         if (!intel_pstate->base.visible)
3201                 return 0;
3202         if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3203                 return 0;
3204         if (y && format != DRM_FORMAT_NV12)
3205                 return 0;
3206
3207         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3208         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3209
3210         if (intel_rotation_90_or_270(pstate->rotation))
3211                 swap(width, height);
3212
3213         /* for planar format */
3214         if (format == DRM_FORMAT_NV12) {
3215                 if (y)  /* y-plane data rate */
3216                         data_rate = width * height *
3217                                 drm_format_plane_cpp(format, 0);
3218                 else    /* uv-plane data rate */
3219                         data_rate = (width / 2) * (height / 2) *
3220                                 drm_format_plane_cpp(format, 1);
3221         } else {
3222                 /* for packed formats */
3223                 data_rate = width * height * drm_format_plane_cpp(format, 0);
3224         }
3225
3226         down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3227
3228         return (uint64_t)data_rate * down_scale_amount >> 16;
3229 }
3230
3231 /*
3232  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3233  * a 8192x4096@32bpp framebuffer:
3234  *   3 * 4096 * 8192  * 4 < 2^32
3235  */
3236 static unsigned int
3237 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
3238 {
3239         struct drm_crtc_state *cstate = &intel_cstate->base;
3240         struct drm_atomic_state *state = cstate->state;
3241         struct drm_crtc *crtc = cstate->crtc;
3242         struct drm_device *dev = crtc->dev;
3243         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3244         const struct drm_plane *plane;
3245         const struct intel_plane *intel_plane;
3246         struct drm_plane_state *pstate;
3247         unsigned int rate, total_data_rate = 0;
3248         int id;
3249         int i;
3250
3251         if (WARN_ON(!state))
3252                 return 0;
3253
3254         /* Calculate and cache data rate for each plane */
3255         for_each_plane_in_state(state, plane, pstate, i) {
3256                 id = skl_wm_plane_id(to_intel_plane(plane));
3257                 intel_plane = to_intel_plane(plane);
3258
3259                 if (intel_plane->pipe != intel_crtc->pipe)
3260                         continue;
3261
3262                 /* packed/uv */
3263                 rate = skl_plane_relative_data_rate(intel_cstate,
3264                                                     pstate, 0);
3265                 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3266
3267                 /* y-plane */
3268                 rate = skl_plane_relative_data_rate(intel_cstate,
3269                                                     pstate, 1);
3270                 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
3271         }
3272
3273         /* Calculate CRTC's total data rate from cached values */
3274         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3275                 int id = skl_wm_plane_id(intel_plane);
3276
3277                 /* packed/uv */
3278                 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3279                 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
3280         }
3281
3282         return total_data_rate;
3283 }
3284
3285 static uint16_t
3286 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3287                   const int y)
3288 {
3289         struct drm_framebuffer *fb = pstate->fb;
3290         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3291         uint32_t src_w, src_h;
3292         uint32_t min_scanlines = 8;
3293         uint8_t plane_bpp;
3294
3295         if (WARN_ON(!fb))
3296                 return 0;
3297
3298         /* For packed formats, no y-plane, return 0 */
3299         if (y && fb->pixel_format != DRM_FORMAT_NV12)
3300                 return 0;
3301
3302         /* For Non Y-tile return 8-blocks */
3303         if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3304             fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3305                 return 8;
3306
3307         src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3308         src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
3309
3310         if (intel_rotation_90_or_270(pstate->rotation))
3311                 swap(src_w, src_h);
3312
3313         /* Halve UV plane width and height for NV12 */
3314         if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3315                 src_w /= 2;
3316                 src_h /= 2;
3317         }
3318
3319         if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3320                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3321         else
3322                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3323
3324         if (intel_rotation_90_or_270(pstate->rotation)) {
3325                 switch (plane_bpp) {
3326                 case 1:
3327                         min_scanlines = 32;
3328                         break;
3329                 case 2:
3330                         min_scanlines = 16;
3331                         break;
3332                 case 4:
3333                         min_scanlines = 8;
3334                         break;
3335                 case 8:
3336                         min_scanlines = 4;
3337                         break;
3338                 default:
3339                         WARN(1, "Unsupported pixel depth %u for rotation",
3340                              plane_bpp);
3341                         min_scanlines = 32;
3342                 }
3343         }
3344
3345         return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3346 }
3347
3348 static int
3349 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3350                       struct skl_ddb_allocation *ddb /* out */)
3351 {
3352         struct drm_atomic_state *state = cstate->base.state;
3353         struct drm_crtc *crtc = cstate->base.crtc;
3354         struct drm_device *dev = crtc->dev;
3355         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3356         struct intel_plane *intel_plane;
3357         struct drm_plane *plane;
3358         struct drm_plane_state *pstate;
3359         enum pipe pipe = intel_crtc->pipe;
3360         struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
3361         uint16_t alloc_size, start, cursor_blocks;
3362         uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3363         uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
3364         unsigned int total_data_rate;
3365         int num_active;
3366         int id, i;
3367
3368         /* Clear the partitioning for disabled planes. */
3369         memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3370         memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3371
3372         if (WARN_ON(!state))
3373                 return 0;
3374
3375         if (!cstate->base.active) {
3376                 alloc->start = alloc->end = 0;
3377                 return 0;
3378         }
3379
3380         skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3381         alloc_size = skl_ddb_entry_size(alloc);
3382         if (alloc_size == 0) {
3383                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3384                 return 0;
3385         }
3386
3387         cursor_blocks = skl_cursor_allocation(num_active);
3388         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3389         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3390
3391         alloc_size -= cursor_blocks;
3392
3393         /* 1. Allocate the mininum required blocks for each active plane */
3394         for_each_plane_in_state(state, plane, pstate, i) {
3395                 intel_plane = to_intel_plane(plane);
3396                 id = skl_wm_plane_id(intel_plane);
3397
3398                 if (intel_plane->pipe != pipe)
3399                         continue;
3400
3401                 if (!to_intel_plane_state(pstate)->base.visible) {
3402                         minimum[id] = 0;
3403                         y_minimum[id] = 0;
3404                         continue;
3405                 }
3406                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3407                         minimum[id] = 0;
3408                         y_minimum[id] = 0;
3409                         continue;
3410                 }
3411
3412                 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3413                 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3414         }
3415
3416         for (i = 0; i < PLANE_CURSOR; i++) {
3417                 alloc_size -= minimum[i];
3418                 alloc_size -= y_minimum[i];
3419         }
3420
3421         /*
3422          * 2. Distribute the remaining space in proportion to the amount of
3423          * data each plane needs to fetch from memory.
3424          *
3425          * FIXME: we may not allocate every single block here.
3426          */
3427         total_data_rate = skl_get_total_relative_data_rate(cstate);
3428         if (total_data_rate == 0)
3429                 return 0;
3430
3431         start = alloc->start;
3432         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3433                 unsigned int data_rate, y_data_rate;
3434                 uint16_t plane_blocks, y_plane_blocks = 0;
3435                 int id = skl_wm_plane_id(intel_plane);
3436
3437                 data_rate = cstate->wm.skl.plane_data_rate[id];
3438
3439                 /*
3440                  * allocation for (packed formats) or (uv-plane part of planar format):
3441                  * promote the expression to 64 bits to avoid overflowing, the
3442                  * result is < available as data_rate / total_data_rate < 1
3443                  */
3444                 plane_blocks = minimum[id];
3445                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3446                                         total_data_rate);
3447
3448                 /* Leave disabled planes at (0,0) */
3449                 if (data_rate) {
3450                         ddb->plane[pipe][id].start = start;
3451                         ddb->plane[pipe][id].end = start + plane_blocks;
3452                 }
3453
3454                 start += plane_blocks;
3455
3456                 /*
3457                  * allocation for y_plane part of planar format:
3458                  */
3459                 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3460
3461                 y_plane_blocks = y_minimum[id];
3462                 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3463                                         total_data_rate);
3464
3465                 if (y_data_rate) {
3466                         ddb->y_plane[pipe][id].start = start;
3467                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3468                 }
3469
3470                 start += y_plane_blocks;
3471         }
3472
3473         return 0;
3474 }
3475
3476 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3477 {
3478         /* TODO: Take into account the scalers once we support them */
3479         return config->base.adjusted_mode.crtc_clock;
3480 }
3481
3482 /*
3483  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3484  * for the read latency) and cpp should always be <= 8, so that
3485  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3486  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3487 */
3488 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3489 {
3490         uint32_t wm_intermediate_val, ret;
3491
3492         if (latency == 0)
3493                 return UINT_MAX;
3494
3495         wm_intermediate_val = latency * pixel_rate * cpp / 512;
3496         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3497
3498         return ret;
3499 }
3500
3501 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3502                                uint32_t latency, uint32_t plane_blocks_per_line)
3503 {
3504         uint32_t ret;
3505         uint32_t wm_intermediate_val;
3506
3507         if (latency == 0)
3508                 return UINT_MAX;
3509
3510         wm_intermediate_val = latency * pixel_rate;
3511         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3512                                 plane_blocks_per_line;
3513
3514         return ret;
3515 }
3516
3517 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3518                                               struct intel_plane_state *pstate)
3519 {
3520         uint64_t adjusted_pixel_rate;
3521         uint64_t downscale_amount;
3522         uint64_t pixel_rate;
3523
3524         /* Shouldn't reach here on disabled planes... */
3525         if (WARN_ON(!pstate->base.visible))
3526                 return 0;
3527
3528         /*
3529          * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3530          * with additional adjustments for plane-specific scaling.
3531          */
3532         adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
3533         downscale_amount = skl_plane_downscale_amount(pstate);
3534
3535         pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3536         WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3537
3538         return pixel_rate;
3539 }
3540
3541 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3542                                 struct intel_crtc_state *cstate,
3543                                 struct intel_plane_state *intel_pstate,
3544                                 uint16_t ddb_allocation,
3545                                 int level,
3546                                 uint16_t *out_blocks, /* out */
3547                                 uint8_t *out_lines, /* out */
3548                                 bool *enabled /* out */)
3549 {
3550         struct drm_plane_state *pstate = &intel_pstate->base;
3551         struct drm_framebuffer *fb = pstate->fb;
3552         uint32_t latency = dev_priv->wm.skl_latency[level];
3553         uint32_t method1, method2;
3554         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3555         uint32_t res_blocks, res_lines;
3556         uint32_t selected_result;
3557         uint8_t cpp;
3558         uint32_t width = 0, height = 0;
3559         uint32_t plane_pixel_rate;
3560         uint32_t y_tile_minimum, y_min_scanlines;
3561
3562         if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
3563                 *enabled = false;
3564                 return 0;
3565         }
3566
3567         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3568         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3569
3570         if (intel_rotation_90_or_270(pstate->rotation))
3571                 swap(width, height);
3572
3573         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3574         plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3575
3576         if (intel_rotation_90_or_270(pstate->rotation)) {
3577                 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3578                         drm_format_plane_cpp(fb->pixel_format, 1) :
3579                         drm_format_plane_cpp(fb->pixel_format, 0);
3580
3581                 switch (cpp) {
3582                 case 1:
3583                         y_min_scanlines = 16;
3584                         break;
3585                 case 2:
3586                         y_min_scanlines = 8;
3587                         break;
3588                 case 4:
3589                         y_min_scanlines = 4;
3590                         break;
3591                 default:
3592                         MISSING_CASE(cpp);
3593                         return -EINVAL;
3594                 }
3595         } else {
3596                 y_min_scanlines = 4;
3597         }
3598
3599         plane_bytes_per_line = width * cpp;
3600         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3601             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3602                 plane_blocks_per_line =
3603                       DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3604                 plane_blocks_per_line /= y_min_scanlines;
3605         } else if (fb->modifier[0] == DRM_FORMAT_MOD_NONE) {
3606                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3607                                         + 1;
3608         } else {
3609                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3610         }
3611
3612         method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3613         method2 = skl_wm_method2(plane_pixel_rate,
3614                                  cstate->base.adjusted_mode.crtc_htotal,
3615                                  latency,
3616                                  plane_blocks_per_line);
3617
3618         y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
3619
3620         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3621             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3622                 selected_result = max(method2, y_tile_minimum);
3623         } else {
3624                 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3625                     (plane_bytes_per_line / 512 < 1))
3626                         selected_result = method2;
3627                 else if ((ddb_allocation / plane_blocks_per_line) >= 1)
3628                         selected_result = min(method1, method2);
3629                 else
3630                         selected_result = method1;
3631         }
3632
3633         res_blocks = selected_result + 1;
3634         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3635
3636         if (level >= 1 && level <= 7) {
3637                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3638                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3639                         res_blocks += y_tile_minimum;
3640                         res_lines += y_min_scanlines;
3641                 } else {
3642                         res_blocks++;
3643                 }
3644         }
3645
3646         if (res_blocks >= ddb_allocation || res_lines > 31) {
3647                 *enabled = false;
3648
3649                 /*
3650                  * If there are no valid level 0 watermarks, then we can't
3651                  * support this display configuration.
3652                  */
3653                 if (level) {
3654                         return 0;
3655                 } else {
3656                         DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3657                         DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3658                                       to_intel_crtc(cstate->base.crtc)->pipe,
3659                                       skl_wm_plane_id(to_intel_plane(pstate->plane)),
3660                                       res_blocks, ddb_allocation, res_lines);
3661
3662                         return -EINVAL;
3663                 }
3664         }
3665
3666         *out_blocks = res_blocks;
3667         *out_lines = res_lines;
3668         *enabled = true;
3669
3670         return 0;
3671 }
3672
3673 static int
3674 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3675                      struct skl_ddb_allocation *ddb,
3676                      struct intel_crtc_state *cstate,
3677                      struct intel_plane *intel_plane,
3678                      int level,
3679                      struct skl_wm_level *result)
3680 {
3681         struct drm_atomic_state *state = cstate->base.state;
3682         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3683         struct drm_plane *plane = &intel_plane->base;
3684         struct intel_plane_state *intel_pstate = NULL;
3685         uint16_t ddb_blocks;
3686         enum pipe pipe = intel_crtc->pipe;
3687         int ret;
3688         int i = skl_wm_plane_id(intel_plane);
3689
3690         if (state)
3691                 intel_pstate =
3692                         intel_atomic_get_existing_plane_state(state,
3693                                                               intel_plane);
3694
3695         /*
3696          * Note: If we start supporting multiple pending atomic commits against
3697          * the same planes/CRTC's in the future, plane->state will no longer be
3698          * the correct pre-state to use for the calculations here and we'll
3699          * need to change where we get the 'unchanged' plane data from.
3700          *
3701          * For now this is fine because we only allow one queued commit against
3702          * a CRTC.  Even if the plane isn't modified by this transaction and we
3703          * don't have a plane lock, we still have the CRTC's lock, so we know
3704          * that no other transactions are racing with us to update it.
3705          */
3706         if (!intel_pstate)
3707                 intel_pstate = to_intel_plane_state(plane->state);
3708
3709         WARN_ON(!intel_pstate->base.fb);
3710
3711         ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3712
3713         ret = skl_compute_plane_wm(dev_priv,
3714                                    cstate,
3715                                    intel_pstate,
3716                                    ddb_blocks,
3717                                    level,
3718                                    &result->plane_res_b,
3719                                    &result->plane_res_l,
3720                                    &result->plane_en);
3721         if (ret)
3722                 return ret;
3723
3724         return 0;
3725 }
3726
3727 static uint32_t
3728 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3729 {
3730         if (!cstate->base.active)
3731                 return 0;
3732
3733         if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3734                 return 0;
3735
3736         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3737                             skl_pipe_pixel_rate(cstate));
3738 }
3739
3740 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3741                                       struct skl_wm_level *trans_wm /* out */)
3742 {
3743         if (!cstate->base.active)
3744                 return;
3745
3746         /* Until we know more, just disable transition WMs */
3747         trans_wm->plane_en = false;
3748 }
3749
3750 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3751                              struct skl_ddb_allocation *ddb,
3752                              struct skl_pipe_wm *pipe_wm)
3753 {
3754         struct drm_device *dev = cstate->base.crtc->dev;
3755         const struct drm_i915_private *dev_priv = to_i915(dev);
3756         struct intel_plane *intel_plane;
3757         struct skl_plane_wm *wm;
3758         int level, max_level = ilk_wm_max_level(dev_priv);
3759         int ret;
3760
3761         /*
3762          * We'll only calculate watermarks for planes that are actually
3763          * enabled, so make sure all other planes are set as disabled.
3764          */
3765         memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
3766
3767         for_each_intel_plane_mask(&dev_priv->drm,
3768                                   intel_plane,
3769                                   cstate->base.plane_mask) {
3770                 wm = &pipe_wm->planes[skl_wm_plane_id(intel_plane)];
3771
3772                 for (level = 0; level <= max_level; level++) {
3773                         ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3774                                                    intel_plane, level,
3775                                                    &wm->wm[level]);
3776                         if (ret)
3777                                 return ret;
3778                 }
3779                 skl_compute_transition_wm(cstate, &wm->trans_wm);
3780         }
3781         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3782
3783         return 0;
3784 }
3785
3786 static void skl_compute_wm_results(struct drm_device *dev,
3787                                    struct skl_pipe_wm *p_wm,
3788                                    struct skl_wm_values *r,
3789                                    struct intel_crtc *intel_crtc)
3790 {
3791         int level, max_level = ilk_wm_max_level(to_i915(dev));
3792         struct skl_plane_wm *plane_wm;
3793         enum pipe pipe = intel_crtc->pipe;
3794         uint32_t temp;
3795         int i;
3796
3797         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3798                 plane_wm = &p_wm->planes[i];
3799
3800                 for (level = 0; level <= max_level; level++) {
3801                         temp = 0;
3802
3803                         temp |= plane_wm->wm[level].plane_res_l <<
3804                                         PLANE_WM_LINES_SHIFT;
3805                         temp |= plane_wm->wm[level].plane_res_b;
3806                         if (plane_wm->wm[level].plane_en)
3807                                 temp |= PLANE_WM_EN;
3808
3809                         r->plane[pipe][i][level] = temp;
3810                 }
3811         }
3812
3813         for (level = 0; level <= max_level; level++) {
3814                 plane_wm = &p_wm->planes[PLANE_CURSOR];
3815                 temp = 0;
3816                 temp |= plane_wm->wm[level].plane_res_l << PLANE_WM_LINES_SHIFT;
3817                 temp |= plane_wm->wm[level].plane_res_b;
3818                 if (plane_wm->wm[level].plane_en)
3819                         temp |= PLANE_WM_EN;
3820
3821                 r->plane[pipe][PLANE_CURSOR][level] = temp;
3822         }
3823
3824         /* transition WMs */
3825         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3826                 plane_wm = &p_wm->planes[i];
3827                 temp = 0;
3828                 temp |= plane_wm->trans_wm.plane_res_l << PLANE_WM_LINES_SHIFT;
3829                 temp |= plane_wm->trans_wm.plane_res_b;
3830                 if (plane_wm->trans_wm.plane_en)
3831                         temp |= PLANE_WM_EN;
3832
3833                 r->plane_trans[pipe][i] = temp;
3834         }
3835
3836         plane_wm = &p_wm->planes[PLANE_CURSOR];
3837         temp = 0;
3838         temp |= plane_wm->trans_wm.plane_res_l << PLANE_WM_LINES_SHIFT;
3839         temp |= plane_wm->trans_wm.plane_res_b;
3840         if (plane_wm->trans_wm.plane_en)
3841                 temp |= PLANE_WM_EN;
3842
3843         r->plane_trans[pipe][PLANE_CURSOR] = temp;
3844 }
3845
3846 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3847                                 i915_reg_t reg,
3848                                 const struct skl_ddb_entry *entry)
3849 {
3850         if (entry->end)
3851                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3852         else
3853                 I915_WRITE(reg, 0);
3854 }
3855
3856 void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3857                         const struct skl_wm_values *wm,
3858                         int plane)
3859 {
3860         struct drm_crtc *crtc = &intel_crtc->base;
3861         struct drm_device *dev = crtc->dev;
3862         struct drm_i915_private *dev_priv = to_i915(dev);
3863         int level, max_level = ilk_wm_max_level(dev_priv);
3864         enum pipe pipe = intel_crtc->pipe;
3865
3866         for (level = 0; level <= max_level; level++) {
3867                 I915_WRITE(PLANE_WM(pipe, plane, level),
3868                            wm->plane[pipe][plane][level]);
3869         }
3870         I915_WRITE(PLANE_WM_TRANS(pipe, plane), wm->plane_trans[pipe][plane]);
3871
3872         skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
3873                             &wm->ddb.plane[pipe][plane]);
3874         skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
3875                             &wm->ddb.y_plane[pipe][plane]);
3876 }
3877
3878 void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3879                          const struct skl_wm_values *wm)
3880 {
3881         struct drm_crtc *crtc = &intel_crtc->base;
3882         struct drm_device *dev = crtc->dev;
3883         struct drm_i915_private *dev_priv = to_i915(dev);
3884         int level, max_level = ilk_wm_max_level(dev_priv);
3885         enum pipe pipe = intel_crtc->pipe;
3886
3887         for (level = 0; level <= max_level; level++) {
3888                 I915_WRITE(CUR_WM(pipe, level),
3889                            wm->plane[pipe][PLANE_CURSOR][level]);
3890         }
3891         I915_WRITE(CUR_WM_TRANS(pipe), wm->plane_trans[pipe][PLANE_CURSOR]);
3892
3893         skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3894                             &wm->ddb.plane[pipe][PLANE_CURSOR]);
3895 }
3896
3897 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3898                                            const struct skl_ddb_entry *b)
3899 {
3900         return a->start < b->end && b->start < a->end;
3901 }
3902
3903 bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
3904                                  struct intel_crtc *intel_crtc)
3905 {
3906         struct drm_crtc *other_crtc;
3907         struct drm_crtc_state *other_cstate;
3908         struct intel_crtc *other_intel_crtc;
3909         const struct skl_ddb_entry *ddb =
3910                 &to_intel_crtc_state(intel_crtc->base.state)->wm.skl.ddb;
3911         int i;
3912
3913         for_each_crtc_in_state(state, other_crtc, other_cstate, i) {
3914                 other_intel_crtc = to_intel_crtc(other_crtc);
3915
3916                 if (other_intel_crtc == intel_crtc)
3917                         continue;
3918
3919                 if (skl_ddb_entries_overlap(ddb, &other_intel_crtc->hw_ddb))
3920                         return true;
3921         }
3922
3923         return false;
3924 }
3925
3926 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3927                               struct skl_ddb_allocation *ddb, /* out */
3928                               struct skl_pipe_wm *pipe_wm, /* out */
3929                               bool *changed /* out */)
3930 {
3931         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3932         struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3933         int ret;
3934
3935         ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3936         if (ret)
3937                 return ret;
3938
3939         if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3940                 *changed = false;
3941         else
3942                 *changed = true;
3943
3944         return 0;
3945 }
3946
3947 static uint32_t
3948 pipes_modified(struct drm_atomic_state *state)
3949 {
3950         struct drm_crtc *crtc;
3951         struct drm_crtc_state *cstate;
3952         uint32_t i, ret = 0;
3953
3954         for_each_crtc_in_state(state, crtc, cstate, i)
3955                 ret |= drm_crtc_mask(crtc);
3956
3957         return ret;
3958 }
3959
3960 static int
3961 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3962 {
3963         struct drm_atomic_state *state = cstate->base.state;
3964         struct drm_device *dev = state->dev;
3965         struct drm_crtc *crtc = cstate->base.crtc;
3966         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3967         struct drm_i915_private *dev_priv = to_i915(dev);
3968         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3969         struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3970         struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3971         struct drm_plane_state *plane_state;
3972         struct drm_plane *plane;
3973         enum pipe pipe = intel_crtc->pipe;
3974         int id;
3975
3976         WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3977
3978         drm_for_each_plane_mask(plane, dev, crtc->state->plane_mask) {
3979                 id = skl_wm_plane_id(to_intel_plane(plane));
3980
3981                 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
3982                                         &new_ddb->plane[pipe][id]) &&
3983                     skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
3984                                         &new_ddb->y_plane[pipe][id]))
3985                         continue;
3986
3987                 plane_state = drm_atomic_get_plane_state(state, plane);
3988                 if (IS_ERR(plane_state))
3989                         return PTR_ERR(plane_state);
3990         }
3991
3992         return 0;
3993 }
3994
3995 static int
3996 skl_compute_ddb(struct drm_atomic_state *state)
3997 {
3998         struct drm_device *dev = state->dev;
3999         struct drm_i915_private *dev_priv = to_i915(dev);
4000         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4001         struct intel_crtc *intel_crtc;
4002         struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
4003         uint32_t realloc_pipes = pipes_modified(state);
4004         int ret;
4005
4006         /*
4007          * If this is our first atomic update following hardware readout,
4008          * we can't trust the DDB that the BIOS programmed for us.  Let's
4009          * pretend that all pipes switched active status so that we'll
4010          * ensure a full DDB recompute.
4011          */
4012         if (dev_priv->wm.distrust_bios_wm) {
4013                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4014                                        state->acquire_ctx);
4015                 if (ret)
4016                         return ret;
4017
4018                 intel_state->active_pipe_changes = ~0;
4019
4020                 /*
4021                  * We usually only initialize intel_state->active_crtcs if we
4022                  * we're doing a modeset; make sure this field is always
4023                  * initialized during the sanitization process that happens
4024                  * on the first commit too.
4025                  */
4026                 if (!intel_state->modeset)
4027                         intel_state->active_crtcs = dev_priv->active_crtcs;
4028         }
4029
4030         /*
4031          * If the modeset changes which CRTC's are active, we need to
4032          * recompute the DDB allocation for *all* active pipes, even
4033          * those that weren't otherwise being modified in any way by this
4034          * atomic commit.  Due to the shrinking of the per-pipe allocations
4035          * when new active CRTC's are added, it's possible for a pipe that
4036          * we were already using and aren't changing at all here to suddenly
4037          * become invalid if its DDB needs exceeds its new allocation.
4038          *
4039          * Note that if we wind up doing a full DDB recompute, we can't let
4040          * any other display updates race with this transaction, so we need
4041          * to grab the lock on *all* CRTC's.
4042          */
4043         if (intel_state->active_pipe_changes) {
4044                 realloc_pipes = ~0;
4045                 intel_state->wm_results.dirty_pipes = ~0;
4046         }
4047
4048         /*
4049          * We're not recomputing for the pipes not included in the commit, so
4050          * make sure we start with the current state.
4051          */
4052         memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4053
4054         for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4055                 struct intel_crtc_state *cstate;
4056
4057                 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4058                 if (IS_ERR(cstate))
4059                         return PTR_ERR(cstate);
4060
4061                 ret = skl_allocate_pipe_ddb(cstate, ddb);
4062                 if (ret)
4063                         return ret;
4064
4065                 ret = skl_ddb_add_affected_planes(cstate);
4066                 if (ret)
4067                         return ret;
4068         }
4069
4070         return 0;
4071 }
4072
4073 static void
4074 skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4075                      struct skl_wm_values *src,
4076                      enum pipe pipe)
4077 {
4078         memcpy(dst->plane[pipe], src->plane[pipe],
4079                sizeof(dst->plane[pipe]));
4080         memcpy(dst->plane_trans[pipe], src->plane_trans[pipe],
4081                sizeof(dst->plane_trans[pipe]));
4082
4083         memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4084                sizeof(dst->ddb.y_plane[pipe]));
4085         memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4086                sizeof(dst->ddb.plane[pipe]));
4087 }
4088
4089 static int
4090 skl_compute_wm(struct drm_atomic_state *state)
4091 {
4092         struct drm_crtc *crtc;
4093         struct drm_crtc_state *cstate;
4094         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4095         struct skl_wm_values *results = &intel_state->wm_results;
4096         struct skl_pipe_wm *pipe_wm;
4097         bool changed = false;
4098         int ret, i;
4099
4100         /*
4101          * If this transaction isn't actually touching any CRTC's, don't
4102          * bother with watermark calculation.  Note that if we pass this
4103          * test, we're guaranteed to hold at least one CRTC state mutex,
4104          * which means we can safely use values like dev_priv->active_crtcs
4105          * since any racing commits that want to update them would need to
4106          * hold _all_ CRTC state mutexes.
4107          */
4108         for_each_crtc_in_state(state, crtc, cstate, i)
4109                 changed = true;
4110         if (!changed)
4111                 return 0;
4112
4113         /* Clear all dirty flags */
4114         results->dirty_pipes = 0;
4115
4116         ret = skl_compute_ddb(state);
4117         if (ret)
4118                 return ret;
4119
4120         /*
4121          * Calculate WM's for all pipes that are part of this transaction.
4122          * Note that the DDB allocation above may have added more CRTC's that
4123          * weren't otherwise being modified (and set bits in dirty_pipes) if
4124          * pipe allocations had to change.
4125          *
4126          * FIXME:  Now that we're doing this in the atomic check phase, we
4127          * should allow skl_update_pipe_wm() to return failure in cases where
4128          * no suitable watermark values can be found.
4129          */
4130         for_each_crtc_in_state(state, crtc, cstate, i) {
4131                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4132                 struct intel_crtc_state *intel_cstate =
4133                         to_intel_crtc_state(cstate);
4134
4135                 pipe_wm = &intel_cstate->wm.skl.optimal;
4136                 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
4137                                          &changed);
4138                 if (ret)
4139                         return ret;
4140
4141                 if (changed)
4142                         results->dirty_pipes |= drm_crtc_mask(crtc);
4143
4144                 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4145                         /* This pipe's WM's did not change */
4146                         continue;
4147
4148                 intel_cstate->update_wm_pre = true;
4149                 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
4150         }
4151
4152         return 0;
4153 }
4154
4155 static void skl_update_wm(struct drm_crtc *crtc)
4156 {
4157         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4158         struct drm_device *dev = crtc->dev;
4159         struct drm_i915_private *dev_priv = to_i915(dev);
4160         struct skl_wm_values *results = &dev_priv->wm.skl_results;
4161         struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4162         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4163         struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
4164         enum pipe pipe = intel_crtc->pipe;
4165
4166         if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4167                 return;
4168
4169         intel_crtc->wm.active.skl = *pipe_wm;
4170
4171         mutex_lock(&dev_priv->wm.wm_mutex);
4172
4173         /*
4174          * If this pipe isn't active already, we're going to be enabling it
4175          * very soon. Since it's safe to update a pipe's ddb allocation while
4176          * the pipe's shut off, just do so here. Already active pipes will have
4177          * their watermarks updated once we update their planes.
4178          */
4179         if (crtc->state->active_changed) {
4180                 int plane;
4181
4182                 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++)
4183                         skl_write_plane_wm(intel_crtc, results, plane);
4184
4185                 skl_write_cursor_wm(intel_crtc, results);
4186         }
4187
4188         skl_copy_wm_for_pipe(hw_vals, results, pipe);
4189
4190         intel_crtc->hw_ddb = cstate->wm.skl.ddb;
4191
4192         mutex_unlock(&dev_priv->wm.wm_mutex);
4193 }
4194
4195 static void ilk_compute_wm_config(struct drm_device *dev,
4196                                   struct intel_wm_config *config)
4197 {
4198         struct intel_crtc *crtc;
4199
4200         /* Compute the currently _active_ config */
4201         for_each_intel_crtc(dev, crtc) {
4202                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4203
4204                 if (!wm->pipe_enabled)
4205                         continue;
4206
4207                 config->sprites_enabled |= wm->sprites_enabled;
4208                 config->sprites_scaled |= wm->sprites_scaled;
4209                 config->num_pipes_active++;
4210         }
4211 }
4212
4213 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4214 {
4215         struct drm_device *dev = &dev_priv->drm;
4216         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4217         struct ilk_wm_maximums max;
4218         struct intel_wm_config config = {};
4219         struct ilk_wm_values results = {};
4220         enum intel_ddb_partitioning partitioning;
4221
4222         ilk_compute_wm_config(dev, &config);
4223
4224         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4225         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4226
4227         /* 5/6 split only in single pipe config on IVB+ */
4228         if (INTEL_INFO(dev)->gen >= 7 &&
4229             config.num_pipes_active == 1 && config.sprites_enabled) {
4230                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4231                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4232
4233                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4234         } else {
4235                 best_lp_wm = &lp_wm_1_2;
4236         }
4237
4238         partitioning = (best_lp_wm == &lp_wm_1_2) ?
4239                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4240
4241         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4242
4243         ilk_write_wm_values(dev_priv, &results);
4244 }
4245
4246 static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
4247 {
4248         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4249         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4250
4251         mutex_lock(&dev_priv->wm.wm_mutex);
4252         intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4253         ilk_program_watermarks(dev_priv);
4254         mutex_unlock(&dev_priv->wm.wm_mutex);
4255 }
4256
4257 static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4258 {
4259         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4260         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4261
4262         mutex_lock(&dev_priv->wm.wm_mutex);
4263         if (cstate->wm.need_postvbl_update) {
4264                 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4265                 ilk_program_watermarks(dev_priv);
4266         }
4267         mutex_unlock(&dev_priv->wm.wm_mutex);
4268 }
4269
4270 static void skl_pipe_wm_active_state(uint32_t val,
4271                                      struct skl_pipe_wm *active,
4272                                      bool is_transwm,
4273                                      bool is_cursor,
4274                                      int i,
4275                                      int level)
4276 {
4277         bool is_enabled = (val & PLANE_WM_EN) != 0;
4278
4279         if (!is_transwm) {
4280                 if (!is_cursor) {
4281                         active->planes[i].wm[level].plane_en = is_enabled;
4282                         active->planes[i].wm[level].plane_res_b =
4283                                 val & PLANE_WM_BLOCKS_MASK;
4284                         active->planes[i].wm[level].plane_res_l =
4285                                 (val >> PLANE_WM_LINES_SHIFT) &
4286                                 PLANE_WM_LINES_MASK;
4287                 } else {
4288                         active->planes[PLANE_CURSOR].wm[level].plane_en =
4289                                 is_enabled;
4290                         active->planes[PLANE_CURSOR].wm[level].plane_res_b =
4291                                 val & PLANE_WM_BLOCKS_MASK;
4292                         active->planes[PLANE_CURSOR].wm[level].plane_res_l =
4293                                 (val >> PLANE_WM_LINES_SHIFT) &
4294                                 PLANE_WM_LINES_MASK;
4295                 }
4296         } else {
4297                 if (!is_cursor) {
4298                         active->planes[i].trans_wm.plane_en = is_enabled;
4299                         active->planes[i].trans_wm.plane_res_b =
4300                                 val & PLANE_WM_BLOCKS_MASK;
4301                         active->planes[i].trans_wm.plane_res_l =
4302                                 (val >> PLANE_WM_LINES_SHIFT) &
4303                                 PLANE_WM_LINES_MASK;
4304                 } else {
4305                         active->planes[PLANE_CURSOR].trans_wm.plane_en =
4306                                 is_enabled;
4307                         active->planes[PLANE_CURSOR].trans_wm.plane_res_b =
4308                                 val & PLANE_WM_BLOCKS_MASK;
4309                         active->planes[PLANE_CURSOR].trans_wm.plane_res_l =
4310                                 (val >> PLANE_WM_LINES_SHIFT) &
4311                                 PLANE_WM_LINES_MASK;
4312                 }
4313         }
4314 }
4315
4316 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4317 {
4318         struct drm_device *dev = crtc->dev;
4319         struct drm_i915_private *dev_priv = to_i915(dev);
4320         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4321         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4322         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4323         struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
4324         enum pipe pipe = intel_crtc->pipe;
4325         int level, i, max_level;
4326         uint32_t temp;
4327
4328         max_level = ilk_wm_max_level(dev_priv);
4329
4330         for (level = 0; level <= max_level; level++) {
4331                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4332                         hw->plane[pipe][i][level] =
4333                                         I915_READ(PLANE_WM(pipe, i, level));
4334                 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
4335         }
4336
4337         for (i = 0; i < intel_num_planes(intel_crtc); i++)
4338                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4339         hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
4340
4341         if (!intel_crtc->active)
4342                 return;
4343
4344         hw->dirty_pipes |= drm_crtc_mask(crtc);
4345
4346         active->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
4347
4348         for (level = 0; level <= max_level; level++) {
4349                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4350                         temp = hw->plane[pipe][i][level];
4351                         skl_pipe_wm_active_state(temp, active, false,
4352                                                 false, i, level);
4353                 }
4354                 temp = hw->plane[pipe][PLANE_CURSOR][level];
4355                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4356         }
4357
4358         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4359                 temp = hw->plane_trans[pipe][i];
4360                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4361         }
4362
4363         temp = hw->plane_trans[pipe][PLANE_CURSOR];
4364         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4365
4366         intel_crtc->wm.active.skl = *active;
4367 }
4368
4369 void skl_wm_get_hw_state(struct drm_device *dev)
4370 {
4371         struct drm_i915_private *dev_priv = to_i915(dev);
4372         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4373         struct drm_crtc *crtc;
4374
4375         skl_ddb_get_hw_state(dev_priv, ddb);
4376         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4377                 skl_pipe_wm_get_hw_state(crtc);
4378
4379         if (dev_priv->active_crtcs) {
4380                 /* Fully recompute DDB on first atomic commit */
4381                 dev_priv->wm.distrust_bios_wm = true;
4382         } else {
4383                 /* Easy/common case; just sanitize DDB now if everything off */
4384                 memset(ddb, 0, sizeof(*ddb));
4385         }
4386 }
4387
4388 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4389 {
4390         struct drm_device *dev = crtc->dev;
4391         struct drm_i915_private *dev_priv = to_i915(dev);
4392         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4393         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4394         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4395         struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4396         enum pipe pipe = intel_crtc->pipe;
4397         static const i915_reg_t wm0_pipe_reg[] = {
4398                 [PIPE_A] = WM0_PIPEA_ILK,
4399                 [PIPE_B] = WM0_PIPEB_ILK,
4400                 [PIPE_C] = WM0_PIPEC_IVB,
4401         };
4402
4403         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4404         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4405                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4406
4407         memset(active, 0, sizeof(*active));
4408
4409         active->pipe_enabled = intel_crtc->active;
4410
4411         if (active->pipe_enabled) {
4412                 u32 tmp = hw->wm_pipe[pipe];
4413
4414                 /*
4415                  * For active pipes LP0 watermark is marked as
4416                  * enabled, and LP1+ watermaks as disabled since
4417                  * we can't really reverse compute them in case
4418                  * multiple pipes are active.
4419                  */
4420                 active->wm[0].enable = true;
4421                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4422                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4423                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4424                 active->linetime = hw->wm_linetime[pipe];
4425         } else {
4426                 int level, max_level = ilk_wm_max_level(dev_priv);
4427
4428                 /*
4429                  * For inactive pipes, all watermark levels
4430                  * should be marked as enabled but zeroed,
4431                  * which is what we'd compute them to.
4432                  */
4433                 for (level = 0; level <= max_level; level++)
4434                         active->wm[level].enable = true;
4435         }
4436
4437         intel_crtc->wm.active.ilk = *active;
4438 }
4439
4440 #define _FW_WM(value, plane) \
4441         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4442 #define _FW_WM_VLV(value, plane) \
4443         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4444
4445 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4446                                struct vlv_wm_values *wm)
4447 {
4448         enum pipe pipe;
4449         uint32_t tmp;
4450
4451         for_each_pipe(dev_priv, pipe) {
4452                 tmp = I915_READ(VLV_DDL(pipe));
4453
4454                 wm->ddl[pipe].primary =
4455                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4456                 wm->ddl[pipe].cursor =
4457                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4458                 wm->ddl[pipe].sprite[0] =
4459                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4460                 wm->ddl[pipe].sprite[1] =
4461                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4462         }
4463
4464         tmp = I915_READ(DSPFW1);
4465         wm->sr.plane = _FW_WM(tmp, SR);
4466         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4467         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4468         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4469
4470         tmp = I915_READ(DSPFW2);
4471         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4472         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4473         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4474
4475         tmp = I915_READ(DSPFW3);
4476         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4477
4478         if (IS_CHERRYVIEW(dev_priv)) {
4479                 tmp = I915_READ(DSPFW7_CHV);
4480                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4481                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4482
4483                 tmp = I915_READ(DSPFW8_CHV);
4484                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4485                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4486
4487                 tmp = I915_READ(DSPFW9_CHV);
4488                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4489                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4490
4491                 tmp = I915_READ(DSPHOWM);
4492                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4493                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4494                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4495                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4496                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4497                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4498                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4499                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4500                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4501                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4502         } else {
4503                 tmp = I915_READ(DSPFW7);
4504                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4505                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4506
4507                 tmp = I915_READ(DSPHOWM);
4508                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4509                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4510                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4511                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4512                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4513                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4514                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4515         }
4516 }
4517
4518 #undef _FW_WM
4519 #undef _FW_WM_VLV
4520
4521 void vlv_wm_get_hw_state(struct drm_device *dev)
4522 {
4523         struct drm_i915_private *dev_priv = to_i915(dev);
4524         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4525         struct intel_plane *plane;
4526         enum pipe pipe;
4527         u32 val;
4528
4529         vlv_read_wm_values(dev_priv, wm);
4530
4531         for_each_intel_plane(dev, plane) {
4532                 switch (plane->base.type) {
4533                         int sprite;
4534                 case DRM_PLANE_TYPE_CURSOR:
4535                         plane->wm.fifo_size = 63;
4536                         break;
4537                 case DRM_PLANE_TYPE_PRIMARY:
4538                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4539                         break;
4540                 case DRM_PLANE_TYPE_OVERLAY:
4541                         sprite = plane->plane;
4542                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4543                         break;
4544                 }
4545         }
4546
4547         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4548         wm->level = VLV_WM_LEVEL_PM2;
4549
4550         if (IS_CHERRYVIEW(dev_priv)) {
4551                 mutex_lock(&dev_priv->rps.hw_lock);
4552
4553                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4554                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4555                         wm->level = VLV_WM_LEVEL_PM5;
4556
4557                 /*
4558                  * If DDR DVFS is disabled in the BIOS, Punit
4559                  * will never ack the request. So if that happens
4560                  * assume we don't have to enable/disable DDR DVFS
4561                  * dynamically. To test that just set the REQ_ACK
4562                  * bit to poke the Punit, but don't change the
4563                  * HIGH/LOW bits so that we don't actually change
4564                  * the current state.
4565                  */
4566                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4567                 val |= FORCE_DDR_FREQ_REQ_ACK;
4568                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4569
4570                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4571                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4572                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4573                                       "assuming DDR DVFS is disabled\n");
4574                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4575                 } else {
4576                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4577                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4578                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4579                 }
4580
4581                 mutex_unlock(&dev_priv->rps.hw_lock);
4582         }
4583
4584         for_each_pipe(dev_priv, pipe)
4585                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4586                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4587                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4588
4589         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4590                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4591 }
4592
4593 void ilk_wm_get_hw_state(struct drm_device *dev)
4594 {
4595         struct drm_i915_private *dev_priv = to_i915(dev);
4596         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4597         struct drm_crtc *crtc;
4598
4599         for_each_crtc(dev, crtc)
4600                 ilk_pipe_wm_get_hw_state(crtc);
4601
4602         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4603         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4604         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4605
4606         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4607         if (INTEL_INFO(dev)->gen >= 7) {
4608                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4609                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4610         }
4611
4612         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4613                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4614                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4615         else if (IS_IVYBRIDGE(dev_priv))
4616                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4617                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4618
4619         hw->enable_fbc_wm =
4620                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4621 }
4622
4623 /**
4624  * intel_update_watermarks - update FIFO watermark values based on current modes
4625  *
4626  * Calculate watermark values for the various WM regs based on current mode
4627  * and plane configuration.
4628  *
4629  * There are several cases to deal with here:
4630  *   - normal (i.e. non-self-refresh)
4631  *   - self-refresh (SR) mode
4632  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4633  *   - lines are small relative to FIFO size (buffer can hold more than 2
4634  *     lines), so need to account for TLB latency
4635  *
4636  *   The normal calculation is:
4637  *     watermark = dotclock * bytes per pixel * latency
4638  *   where latency is platform & configuration dependent (we assume pessimal
4639  *   values here).
4640  *
4641  *   The SR calculation is:
4642  *     watermark = (trunc(latency/line time)+1) * surface width *
4643  *       bytes per pixel
4644  *   where
4645  *     line time = htotal / dotclock
4646  *     surface width = hdisplay for normal plane and 64 for cursor
4647  *   and latency is assumed to be high, as above.
4648  *
4649  * The final value programmed to the register should always be rounded up,
4650  * and include an extra 2 entries to account for clock crossings.
4651  *
4652  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4653  * to set the non-SR watermarks to 8.
4654  */
4655 void intel_update_watermarks(struct drm_crtc *crtc)
4656 {
4657         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4658
4659         if (dev_priv->display.update_wm)
4660                 dev_priv->display.update_wm(crtc);
4661 }
4662
4663 /*
4664  * Lock protecting IPS related data structures
4665  */
4666 DEFINE_SPINLOCK(mchdev_lock);
4667
4668 /* Global for IPS driver to get at the current i915 device. Protected by
4669  * mchdev_lock. */
4670 static struct drm_i915_private *i915_mch_dev;
4671
4672 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4673 {
4674         u16 rgvswctl;
4675
4676         assert_spin_locked(&mchdev_lock);
4677
4678         rgvswctl = I915_READ16(MEMSWCTL);
4679         if (rgvswctl & MEMCTL_CMD_STS) {
4680                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4681                 return false; /* still busy with another command */
4682         }
4683
4684         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4685                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4686         I915_WRITE16(MEMSWCTL, rgvswctl);
4687         POSTING_READ16(MEMSWCTL);
4688
4689         rgvswctl |= MEMCTL_CMD_STS;
4690         I915_WRITE16(MEMSWCTL, rgvswctl);
4691
4692         return true;
4693 }
4694
4695 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4696 {
4697         u32 rgvmodectl;
4698         u8 fmax, fmin, fstart, vstart;
4699
4700         spin_lock_irq(&mchdev_lock);
4701
4702         rgvmodectl = I915_READ(MEMMODECTL);
4703
4704         /* Enable temp reporting */
4705         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4706         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4707
4708         /* 100ms RC evaluation intervals */
4709         I915_WRITE(RCUPEI, 100000);
4710         I915_WRITE(RCDNEI, 100000);
4711
4712         /* Set max/min thresholds to 90ms and 80ms respectively */
4713         I915_WRITE(RCBMAXAVG, 90000);
4714         I915_WRITE(RCBMINAVG, 80000);
4715
4716         I915_WRITE(MEMIHYST, 1);
4717
4718         /* Set up min, max, and cur for interrupt handling */
4719         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4720         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4721         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4722                 MEMMODE_FSTART_SHIFT;
4723
4724         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4725                 PXVFREQ_PX_SHIFT;
4726
4727         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4728         dev_priv->ips.fstart = fstart;
4729
4730         dev_priv->ips.max_delay = fstart;
4731         dev_priv->ips.min_delay = fmin;
4732         dev_priv->ips.cur_delay = fstart;
4733
4734         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4735                          fmax, fmin, fstart);
4736
4737         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4738
4739         /*
4740          * Interrupts will be enabled in ironlake_irq_postinstall
4741          */
4742
4743         I915_WRITE(VIDSTART, vstart);
4744         POSTING_READ(VIDSTART);
4745
4746         rgvmodectl |= MEMMODE_SWMODE_EN;
4747         I915_WRITE(MEMMODECTL, rgvmodectl);
4748
4749         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4750                 DRM_ERROR("stuck trying to change perf mode\n");
4751         mdelay(1);
4752
4753         ironlake_set_drps(dev_priv, fstart);
4754
4755         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4756                 I915_READ(DDREC) + I915_READ(CSIEC);
4757         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4758         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4759         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4760
4761         spin_unlock_irq(&mchdev_lock);
4762 }
4763
4764 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4765 {
4766         u16 rgvswctl;
4767
4768         spin_lock_irq(&mchdev_lock);
4769
4770         rgvswctl = I915_READ16(MEMSWCTL);
4771
4772         /* Ack interrupts, disable EFC interrupt */
4773         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4774         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4775         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4776         I915_WRITE(DEIIR, DE_PCU_EVENT);
4777         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4778
4779         /* Go back to the starting frequency */
4780         ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4781         mdelay(1);
4782         rgvswctl |= MEMCTL_CMD_STS;
4783         I915_WRITE(MEMSWCTL, rgvswctl);
4784         mdelay(1);
4785
4786         spin_unlock_irq(&mchdev_lock);
4787 }
4788
4789 /* There's a funny hw issue where the hw returns all 0 when reading from
4790  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4791  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4792  * all limits and the gpu stuck at whatever frequency it is at atm).
4793  */
4794 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4795 {
4796         u32 limits;
4797
4798         /* Only set the down limit when we've reached the lowest level to avoid
4799          * getting more interrupts, otherwise leave this clear. This prevents a
4800          * race in the hw when coming out of rc6: There's a tiny window where
4801          * the hw runs at the minimal clock before selecting the desired
4802          * frequency, if the down threshold expires in that window we will not
4803          * receive a down interrupt. */
4804         if (IS_GEN9(dev_priv)) {
4805                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4806                 if (val <= dev_priv->rps.min_freq_softlimit)
4807                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4808         } else {
4809                 limits = dev_priv->rps.max_freq_softlimit << 24;
4810                 if (val <= dev_priv->rps.min_freq_softlimit)
4811                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4812         }
4813
4814         return limits;
4815 }
4816
4817 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4818 {
4819         int new_power;
4820         u32 threshold_up = 0, threshold_down = 0; /* in % */
4821         u32 ei_up = 0, ei_down = 0;
4822
4823         new_power = dev_priv->rps.power;
4824         switch (dev_priv->rps.power) {
4825         case LOW_POWER:
4826                 if (val > dev_priv->rps.efficient_freq + 1 &&
4827                     val > dev_priv->rps.cur_freq)
4828                         new_power = BETWEEN;
4829                 break;
4830
4831         case BETWEEN:
4832                 if (val <= dev_priv->rps.efficient_freq &&
4833                     val < dev_priv->rps.cur_freq)
4834                         new_power = LOW_POWER;
4835                 else if (val >= dev_priv->rps.rp0_freq &&
4836                          val > dev_priv->rps.cur_freq)
4837                         new_power = HIGH_POWER;
4838                 break;
4839
4840         case HIGH_POWER:
4841                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4842                     val < dev_priv->rps.cur_freq)
4843                         new_power = BETWEEN;
4844                 break;
4845         }
4846         /* Max/min bins are special */
4847         if (val <= dev_priv->rps.min_freq_softlimit)
4848                 new_power = LOW_POWER;
4849         if (val >= dev_priv->rps.max_freq_softlimit)
4850                 new_power = HIGH_POWER;
4851         if (new_power == dev_priv->rps.power)
4852                 return;
4853
4854         /* Note the units here are not exactly 1us, but 1280ns. */
4855         switch (new_power) {
4856         case LOW_POWER:
4857                 /* Upclock if more than 95% busy over 16ms */
4858                 ei_up = 16000;
4859                 threshold_up = 95;
4860
4861                 /* Downclock if less than 85% busy over 32ms */
4862                 ei_down = 32000;
4863                 threshold_down = 85;
4864                 break;
4865
4866         case BETWEEN:
4867                 /* Upclock if more than 90% busy over 13ms */
4868                 ei_up = 13000;
4869                 threshold_up = 90;
4870
4871                 /* Downclock if less than 75% busy over 32ms */
4872                 ei_down = 32000;
4873                 threshold_down = 75;
4874                 break;
4875
4876         case HIGH_POWER:
4877                 /* Upclock if more than 85% busy over 10ms */
4878                 ei_up = 10000;
4879                 threshold_up = 85;
4880
4881                 /* Downclock if less than 60% busy over 32ms */
4882                 ei_down = 32000;
4883                 threshold_down = 60;
4884                 break;
4885         }
4886
4887         I915_WRITE(GEN6_RP_UP_EI,
4888                    GT_INTERVAL_FROM_US(dev_priv, ei_up));
4889         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4890                    GT_INTERVAL_FROM_US(dev_priv,
4891                                        ei_up * threshold_up / 100));
4892
4893         I915_WRITE(GEN6_RP_DOWN_EI,
4894                    GT_INTERVAL_FROM_US(dev_priv, ei_down));
4895         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4896                    GT_INTERVAL_FROM_US(dev_priv,
4897                                        ei_down * threshold_down / 100));
4898
4899         I915_WRITE(GEN6_RP_CONTROL,
4900                    GEN6_RP_MEDIA_TURBO |
4901                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4902                    GEN6_RP_MEDIA_IS_GFX |
4903                    GEN6_RP_ENABLE |
4904                    GEN6_RP_UP_BUSY_AVG |
4905                    GEN6_RP_DOWN_IDLE_AVG);
4906
4907         dev_priv->rps.power = new_power;
4908         dev_priv->rps.up_threshold = threshold_up;
4909         dev_priv->rps.down_threshold = threshold_down;
4910         dev_priv->rps.last_adj = 0;
4911 }
4912
4913 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4914 {
4915         u32 mask = 0;
4916
4917         if (val > dev_priv->rps.min_freq_softlimit)
4918                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4919         if (val < dev_priv->rps.max_freq_softlimit)
4920                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4921
4922         mask &= dev_priv->pm_rps_events;
4923
4924         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4925 }
4926
4927 /* gen6_set_rps is called to update the frequency request, but should also be
4928  * called when the range (min_delay and max_delay) is modified so that we can
4929  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4930 static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4931 {
4932         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4933         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4934                 return;
4935
4936         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4937         WARN_ON(val > dev_priv->rps.max_freq);
4938         WARN_ON(val < dev_priv->rps.min_freq);
4939
4940         /* min/max delay may still have been modified so be sure to
4941          * write the limits value.
4942          */
4943         if (val != dev_priv->rps.cur_freq) {
4944                 gen6_set_rps_thresholds(dev_priv, val);
4945
4946                 if (IS_GEN9(dev_priv))
4947                         I915_WRITE(GEN6_RPNSWREQ,
4948                                    GEN9_FREQUENCY(val));
4949                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4950                         I915_WRITE(GEN6_RPNSWREQ,
4951                                    HSW_FREQUENCY(val));
4952                 else
4953                         I915_WRITE(GEN6_RPNSWREQ,
4954                                    GEN6_FREQUENCY(val) |
4955                                    GEN6_OFFSET(0) |
4956                                    GEN6_AGGRESSIVE_TURBO);
4957         }
4958
4959         /* Make sure we continue to get interrupts
4960          * until we hit the minimum or maximum frequencies.
4961          */
4962         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4963         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4964
4965         POSTING_READ(GEN6_RPNSWREQ);
4966
4967         dev_priv->rps.cur_freq = val;
4968         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4969 }
4970
4971 static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4972 {
4973         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4974         WARN_ON(val > dev_priv->rps.max_freq);
4975         WARN_ON(val < dev_priv->rps.min_freq);
4976
4977         if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4978                       "Odd GPU freq value\n"))
4979                 val &= ~1;
4980
4981         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4982
4983         if (val != dev_priv->rps.cur_freq) {
4984                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4985                 if (!IS_CHERRYVIEW(dev_priv))
4986                         gen6_set_rps_thresholds(dev_priv, val);
4987         }
4988
4989         dev_priv->rps.cur_freq = val;
4990         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4991 }
4992
4993 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4994  *
4995  * * If Gfx is Idle, then
4996  * 1. Forcewake Media well.
4997  * 2. Request idle freq.
4998  * 3. Release Forcewake of Media well.
4999 */
5000 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5001 {
5002         u32 val = dev_priv->rps.idle_freq;
5003
5004         if (dev_priv->rps.cur_freq <= val)
5005                 return;
5006
5007         /* Wake up the media well, as that takes a lot less
5008          * power than the Render well. */
5009         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
5010         valleyview_set_rps(dev_priv, val);
5011         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
5012 }
5013
5014 void gen6_rps_busy(struct drm_i915_private *dev_priv)
5015 {
5016         mutex_lock(&dev_priv->rps.hw_lock);
5017         if (dev_priv->rps.enabled) {
5018                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5019                         gen6_rps_reset_ei(dev_priv);
5020                 I915_WRITE(GEN6_PMINTRMSK,
5021                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
5022
5023                 gen6_enable_rps_interrupts(dev_priv);
5024
5025                 /* Ensure we start at the user's desired frequency */
5026                 intel_set_rps(dev_priv,
5027                               clamp(dev_priv->rps.cur_freq,
5028                                     dev_priv->rps.min_freq_softlimit,
5029                                     dev_priv->rps.max_freq_softlimit));
5030         }
5031         mutex_unlock(&dev_priv->rps.hw_lock);
5032 }
5033
5034 void gen6_rps_idle(struct drm_i915_private *dev_priv)
5035 {
5036         /* Flush our bottom-half so that it does not race with us
5037          * setting the idle frequency and so that it is bounded by
5038          * our rpm wakeref. And then disable the interrupts to stop any
5039          * futher RPS reclocking whilst we are asleep.
5040          */
5041         gen6_disable_rps_interrupts(dev_priv);
5042
5043         mutex_lock(&dev_priv->rps.hw_lock);
5044         if (dev_priv->rps.enabled) {
5045                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5046                         vlv_set_rps_idle(dev_priv);
5047                 else
5048                         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5049                 dev_priv->rps.last_adj = 0;
5050                 I915_WRITE(GEN6_PMINTRMSK,
5051                            gen6_sanitize_rps_pm_mask(dev_priv, ~0));
5052         }
5053         mutex_unlock(&dev_priv->rps.hw_lock);
5054
5055         spin_lock(&dev_priv->rps.client_lock);
5056         while (!list_empty(&dev_priv->rps.clients))
5057                 list_del_init(dev_priv->rps.clients.next);
5058         spin_unlock(&dev_priv->rps.client_lock);
5059 }
5060
5061 void gen6_rps_boost(struct drm_i915_private *dev_priv,
5062                     struct intel_rps_client *rps,
5063                     unsigned long submitted)
5064 {
5065         /* This is intentionally racy! We peek at the state here, then
5066          * validate inside the RPS worker.
5067          */
5068         if (!(dev_priv->gt.awake &&
5069               dev_priv->rps.enabled &&
5070               dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
5071                 return;
5072
5073         /* Force a RPS boost (and don't count it against the client) if
5074          * the GPU is severely congested.
5075          */
5076         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
5077                 rps = NULL;
5078
5079         spin_lock(&dev_priv->rps.client_lock);
5080         if (rps == NULL || list_empty(&rps->link)) {
5081                 spin_lock_irq(&dev_priv->irq_lock);
5082                 if (dev_priv->rps.interrupts_enabled) {
5083                         dev_priv->rps.client_boost = true;
5084                         schedule_work(&dev_priv->rps.work);
5085                 }
5086                 spin_unlock_irq(&dev_priv->irq_lock);
5087
5088                 if (rps != NULL) {
5089                         list_add(&rps->link, &dev_priv->rps.clients);
5090                         rps->boosts++;
5091                 } else
5092                         dev_priv->rps.boosts++;
5093         }
5094         spin_unlock(&dev_priv->rps.client_lock);
5095 }
5096
5097 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
5098 {
5099         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5100                 valleyview_set_rps(dev_priv, val);
5101         else
5102                 gen6_set_rps(dev_priv, val);
5103 }
5104
5105 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
5106 {
5107         I915_WRITE(GEN6_RC_CONTROL, 0);
5108         I915_WRITE(GEN9_PG_ENABLE, 0);
5109 }
5110
5111 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
5112 {
5113         I915_WRITE(GEN6_RP_CONTROL, 0);
5114 }
5115
5116 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
5117 {
5118         I915_WRITE(GEN6_RC_CONTROL, 0);
5119         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
5120         I915_WRITE(GEN6_RP_CONTROL, 0);
5121 }
5122
5123 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
5124 {
5125         I915_WRITE(GEN6_RC_CONTROL, 0);
5126 }
5127
5128 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
5129 {
5130         /* we're doing forcewake before Disabling RC6,
5131          * This what the BIOS expects when going into suspend */
5132         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5133
5134         I915_WRITE(GEN6_RC_CONTROL, 0);
5135
5136         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5137 }
5138
5139 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
5140 {
5141         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5142                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5143                         mode = GEN6_RC_CTL_RC6_ENABLE;
5144                 else
5145                         mode = 0;
5146         }
5147         if (HAS_RC6p(dev_priv))
5148                 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5149                                  "RC6 %s RC6p %s RC6pp %s\n",
5150                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5151                                  onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5152                                  onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
5153
5154         else
5155                 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5156                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
5157 }
5158
5159 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
5160 {
5161         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5162         bool enable_rc6 = true;
5163         unsigned long rc6_ctx_base;
5164         u32 rc_ctl;
5165         int rc_sw_target;
5166
5167         rc_ctl = I915_READ(GEN6_RC_CONTROL);
5168         rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5169                        RC_SW_TARGET_STATE_SHIFT;
5170         DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5171                          "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5172                          onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5173                          onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5174                          rc_sw_target);
5175
5176         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
5177                 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5178                 enable_rc6 = false;
5179         }
5180
5181         /*
5182          * The exact context size is not known for BXT, so assume a page size
5183          * for this check.
5184          */
5185         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
5186         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5187               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5188                                         ggtt->stolen_reserved_size))) {
5189                 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5190                 enable_rc6 = false;
5191         }
5192
5193         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5194               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5195               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5196               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
5197                 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5198                 enable_rc6 = false;
5199         }
5200
5201         if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5202             !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5203             !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5204                 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5205                 enable_rc6 = false;
5206         }
5207
5208         if (!I915_READ(GEN6_GFXPAUSE)) {
5209                 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5210                 enable_rc6 = false;
5211         }
5212
5213         if (!I915_READ(GEN8_MISC_CTRL0)) {
5214                 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5215                 enable_rc6 = false;
5216         }
5217
5218         return enable_rc6;
5219 }
5220
5221 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
5222 {
5223         /* No RC6 before Ironlake and code is gone for ilk. */
5224         if (INTEL_INFO(dev_priv)->gen < 6)
5225                 return 0;
5226
5227         if (!enable_rc6)
5228                 return 0;
5229
5230         if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
5231                 DRM_INFO("RC6 disabled by BIOS\n");
5232                 return 0;
5233         }
5234
5235         /* Respect the kernel parameter if it is set */
5236         if (enable_rc6 >= 0) {
5237                 int mask;
5238
5239                 if (HAS_RC6p(dev_priv))
5240                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5241                                INTEL_RC6pp_ENABLE;
5242                 else
5243                         mask = INTEL_RC6_ENABLE;
5244
5245                 if ((enable_rc6 & mask) != enable_rc6)
5246                         DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5247                                          "(requested %d, valid %d)\n",
5248                                          enable_rc6 & mask, enable_rc6, mask);
5249
5250                 return enable_rc6 & mask;
5251         }
5252
5253         if (IS_IVYBRIDGE(dev_priv))
5254                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5255
5256         return INTEL_RC6_ENABLE;
5257 }
5258
5259 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5260 {
5261         /* All of these values are in units of 50MHz */
5262
5263         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5264         if (IS_BROXTON(dev_priv)) {
5265                 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5266                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5267                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5268                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
5269         } else {
5270                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5271                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
5272                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5273                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5274         }
5275         /* hw_max = RP0 until we check for overclocking */
5276         dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5277
5278         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5279         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5280             IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5281                 u32 ddcc_status = 0;
5282
5283                 if (sandybridge_pcode_read(dev_priv,
5284                                            HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5285                                            &ddcc_status) == 0)
5286                         dev_priv->rps.efficient_freq =
5287                                 clamp_t(u8,
5288                                         ((ddcc_status >> 8) & 0xff),
5289                                         dev_priv->rps.min_freq,
5290                                         dev_priv->rps.max_freq);
5291         }
5292
5293         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5294                 /* Store the frequency values in 16.66 MHZ units, which is
5295                  * the natural hardware unit for SKL
5296                  */
5297                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5298                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5299                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5300                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5301                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5302         }
5303 }
5304
5305 static void reset_rps(struct drm_i915_private *dev_priv,
5306                       void (*set)(struct drm_i915_private *, u8))
5307 {
5308         u8 freq = dev_priv->rps.cur_freq;
5309
5310         /* force a reset */
5311         dev_priv->rps.power = -1;
5312         dev_priv->rps.cur_freq = -1;
5313
5314         set(dev_priv, freq);
5315 }
5316
5317 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5318 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5319 {
5320         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5321
5322         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5323         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5324                 /*
5325                  * BIOS could leave the Hw Turbo enabled, so need to explicitly
5326                  * clear out the Control register just to avoid inconsitency
5327                  * with debugfs interface, which will show  Turbo as enabled
5328                  * only and that is not expected by the User after adding the
5329                  * WaGsvDisableTurbo. Apart from this there is no problem even
5330                  * if the Turbo is left enabled in the Control register, as the
5331                  * Up/Down interrupts would remain masked.
5332                  */
5333                 gen9_disable_rps(dev_priv);
5334                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5335                 return;
5336         }
5337
5338         /* Program defaults and thresholds for RPS*/
5339         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5340                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5341
5342         /* 1 second timeout*/
5343         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5344                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5345
5346         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5347
5348         /* Leaning on the below call to gen6_set_rps to program/setup the
5349          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5350          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5351         reset_rps(dev_priv, gen6_set_rps);
5352
5353         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5354 }
5355
5356 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5357 {
5358         struct intel_engine_cs *engine;
5359         enum intel_engine_id id;
5360         uint32_t rc6_mask = 0;
5361
5362         /* 1a: Software RC state - RC0 */
5363         I915_WRITE(GEN6_RC_STATE, 0);
5364
5365         /* 1b: Get forcewake during program sequence. Although the driver
5366          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5367         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5368
5369         /* 2a: Disable RC states. */
5370         I915_WRITE(GEN6_RC_CONTROL, 0);
5371
5372         /* 2b: Program RC6 thresholds.*/
5373
5374         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5375         if (IS_SKYLAKE(dev_priv))
5376                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5377         else
5378                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5379         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5380         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5381         for_each_engine(engine, dev_priv, id)
5382                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5383
5384         if (HAS_GUC(dev_priv))
5385                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5386
5387         I915_WRITE(GEN6_RC_SLEEP, 0);
5388
5389         /* 2c: Program Coarse Power Gating Policies. */
5390         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5391         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5392
5393         /* 3a: Enable RC6 */
5394         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5395                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5396         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5397         /* WaRsUseTimeoutMode:bxt */
5398         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5399                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
5400                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5401                            GEN7_RC_CTL_TO_MODE |
5402                            rc6_mask);
5403         } else {
5404                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5405                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5406                            GEN6_RC_CTL_EI_MODE(1) |
5407                            rc6_mask);
5408         }
5409
5410         /*
5411          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5412          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5413          */
5414         if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5415                 I915_WRITE(GEN9_PG_ENABLE, 0);
5416         else
5417                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5418                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5419
5420         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5421 }
5422
5423 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5424 {
5425         struct intel_engine_cs *engine;
5426         enum intel_engine_id id;
5427         uint32_t rc6_mask = 0;
5428
5429         /* 1a: Software RC state - RC0 */
5430         I915_WRITE(GEN6_RC_STATE, 0);
5431
5432         /* 1c & 1d: Get forcewake during program sequence. Although the driver
5433          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5434         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5435
5436         /* 2a: Disable RC states. */
5437         I915_WRITE(GEN6_RC_CONTROL, 0);
5438
5439         /* 2b: Program RC6 thresholds.*/
5440         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5441         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5442         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5443         for_each_engine(engine, dev_priv, id)
5444                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5445         I915_WRITE(GEN6_RC_SLEEP, 0);
5446         if (IS_BROADWELL(dev_priv))
5447                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5448         else
5449                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5450
5451         /* 3: Enable RC6 */
5452         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5453                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5454         intel_print_rc6_info(dev_priv, rc6_mask);
5455         if (IS_BROADWELL(dev_priv))
5456                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5457                                 GEN7_RC_CTL_TO_MODE |
5458                                 rc6_mask);
5459         else
5460                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5461                                 GEN6_RC_CTL_EI_MODE(1) |
5462                                 rc6_mask);
5463
5464         /* 4 Program defaults and thresholds for RPS*/
5465         I915_WRITE(GEN6_RPNSWREQ,
5466                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5467         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5468                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5469         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5470         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5471
5472         /* Docs recommend 900MHz, and 300 MHz respectively */
5473         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5474                    dev_priv->rps.max_freq_softlimit << 24 |
5475                    dev_priv->rps.min_freq_softlimit << 16);
5476
5477         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5478         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5479         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5480         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5481
5482         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5483
5484         /* 5: Enable RPS */
5485         I915_WRITE(GEN6_RP_CONTROL,
5486                    GEN6_RP_MEDIA_TURBO |
5487                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5488                    GEN6_RP_MEDIA_IS_GFX |
5489                    GEN6_RP_ENABLE |
5490                    GEN6_RP_UP_BUSY_AVG |
5491                    GEN6_RP_DOWN_IDLE_AVG);
5492
5493         /* 6: Ring frequency + overclocking (our driver does this later */
5494
5495         reset_rps(dev_priv, gen6_set_rps);
5496
5497         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5498 }
5499
5500 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5501 {
5502         struct intel_engine_cs *engine;
5503         enum intel_engine_id id;
5504         u32 rc6vids, rc6_mask = 0;
5505         u32 gtfifodbg;
5506         int rc6_mode;
5507         int ret;
5508
5509         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5510
5511         /* Here begins a magic sequence of register writes to enable
5512          * auto-downclocking.
5513          *
5514          * Perhaps there might be some value in exposing these to
5515          * userspace...
5516          */
5517         I915_WRITE(GEN6_RC_STATE, 0);
5518
5519         /* Clear the DBG now so we don't confuse earlier errors */
5520         gtfifodbg = I915_READ(GTFIFODBG);
5521         if (gtfifodbg) {
5522                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5523                 I915_WRITE(GTFIFODBG, gtfifodbg);
5524         }
5525
5526         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5527
5528         /* disable the counters and set deterministic thresholds */
5529         I915_WRITE(GEN6_RC_CONTROL, 0);
5530
5531         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5532         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5533         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5534         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5535         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5536
5537         for_each_engine(engine, dev_priv, id)
5538                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5539
5540         I915_WRITE(GEN6_RC_SLEEP, 0);
5541         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5542         if (IS_IVYBRIDGE(dev_priv))
5543                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5544         else
5545                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5546         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5547         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5548
5549         /* Check if we are enabling RC6 */
5550         rc6_mode = intel_enable_rc6();
5551         if (rc6_mode & INTEL_RC6_ENABLE)
5552                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5553
5554         /* We don't use those on Haswell */
5555         if (!IS_HASWELL(dev_priv)) {
5556                 if (rc6_mode & INTEL_RC6p_ENABLE)
5557                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5558
5559                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5560                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5561         }
5562
5563         intel_print_rc6_info(dev_priv, rc6_mask);
5564
5565         I915_WRITE(GEN6_RC_CONTROL,
5566                    rc6_mask |
5567                    GEN6_RC_CTL_EI_MODE(1) |
5568                    GEN6_RC_CTL_HW_ENABLE);
5569
5570         /* Power down if completely idle for over 50ms */
5571         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5572         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5573
5574         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5575         if (ret)
5576                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5577
5578         reset_rps(dev_priv, gen6_set_rps);
5579
5580         rc6vids = 0;
5581         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5582         if (IS_GEN6(dev_priv) && ret) {
5583                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5584         } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5585                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5586                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5587                 rc6vids &= 0xffff00;
5588                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5589                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5590                 if (ret)
5591                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5592         }
5593
5594         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5595 }
5596
5597 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5598 {
5599         int min_freq = 15;
5600         unsigned int gpu_freq;
5601         unsigned int max_ia_freq, min_ring_freq;
5602         unsigned int max_gpu_freq, min_gpu_freq;
5603         int scaling_factor = 180;
5604         struct cpufreq_policy *policy;
5605
5606         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5607
5608         policy = cpufreq_cpu_get(0);
5609         if (policy) {
5610                 max_ia_freq = policy->cpuinfo.max_freq;
5611                 cpufreq_cpu_put(policy);
5612         } else {
5613                 /*
5614                  * Default to measured freq if none found, PCU will ensure we
5615                  * don't go over
5616                  */
5617                 max_ia_freq = tsc_khz;
5618         }
5619
5620         /* Convert from kHz to MHz */
5621         max_ia_freq /= 1000;
5622
5623         min_ring_freq = I915_READ(DCLK) & 0xf;
5624         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5625         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5626
5627         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5628                 /* Convert GT frequency to 50 HZ units */
5629                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5630                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5631         } else {
5632                 min_gpu_freq = dev_priv->rps.min_freq;
5633                 max_gpu_freq = dev_priv->rps.max_freq;
5634         }
5635
5636         /*
5637          * For each potential GPU frequency, load a ring frequency we'd like
5638          * to use for memory access.  We do this by specifying the IA frequency
5639          * the PCU should use as a reference to determine the ring frequency.
5640          */
5641         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5642                 int diff = max_gpu_freq - gpu_freq;
5643                 unsigned int ia_freq = 0, ring_freq = 0;
5644
5645                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5646                         /*
5647                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5648                          * No floor required for ring frequency on SKL.
5649                          */
5650                         ring_freq = gpu_freq;
5651                 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5652                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5653                         ring_freq = max(min_ring_freq, gpu_freq);
5654                 } else if (IS_HASWELL(dev_priv)) {
5655                         ring_freq = mult_frac(gpu_freq, 5, 4);
5656                         ring_freq = max(min_ring_freq, ring_freq);
5657                         /* leave ia_freq as the default, chosen by cpufreq */
5658                 } else {
5659                         /* On older processors, there is no separate ring
5660                          * clock domain, so in order to boost the bandwidth
5661                          * of the ring, we need to upclock the CPU (ia_freq).
5662                          *
5663                          * For GPU frequencies less than 750MHz,
5664                          * just use the lowest ring freq.
5665                          */
5666                         if (gpu_freq < min_freq)
5667                                 ia_freq = 800;
5668                         else
5669                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5670                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5671                 }
5672
5673                 sandybridge_pcode_write(dev_priv,
5674                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5675                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5676                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5677                                         gpu_freq);
5678         }
5679 }
5680
5681 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5682 {
5683         u32 val, rp0;
5684
5685         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5686
5687         switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5688         case 8:
5689                 /* (2 * 4) config */
5690                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5691                 break;
5692         case 12:
5693                 /* (2 * 6) config */
5694                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5695                 break;
5696         case 16:
5697                 /* (2 * 8) config */
5698         default:
5699                 /* Setting (2 * 8) Min RP0 for any other combination */
5700                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5701                 break;
5702         }
5703
5704         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5705
5706         return rp0;
5707 }
5708
5709 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5710 {
5711         u32 val, rpe;
5712
5713         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5714         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5715
5716         return rpe;
5717 }
5718
5719 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5720 {
5721         u32 val, rp1;
5722
5723         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5724         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5725
5726         return rp1;
5727 }
5728
5729 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5730 {
5731         u32 val, rp1;
5732
5733         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5734
5735         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5736
5737         return rp1;
5738 }
5739
5740 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5741 {
5742         u32 val, rp0;
5743
5744         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5745
5746         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5747         /* Clamp to max */
5748         rp0 = min_t(u32, rp0, 0xea);
5749
5750         return rp0;
5751 }
5752
5753 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5754 {
5755         u32 val, rpe;
5756
5757         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5758         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5759         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5760         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5761
5762         return rpe;
5763 }
5764
5765 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5766 {
5767         u32 val;
5768
5769         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5770         /*
5771          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5772          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5773          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5774          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5775          * to make sure it matches what Punit accepts.
5776          */
5777         return max_t(u32, val, 0xc0);
5778 }
5779
5780 /* Check that the pctx buffer wasn't move under us. */
5781 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5782 {
5783         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5784
5785         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5786                              dev_priv->vlv_pctx->stolen->start);
5787 }
5788
5789
5790 /* Check that the pcbr address is not empty. */
5791 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5792 {
5793         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5794
5795         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5796 }
5797
5798 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5799 {
5800         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5801         unsigned long pctx_paddr, paddr;
5802         u32 pcbr;
5803         int pctx_size = 32*1024;
5804
5805         pcbr = I915_READ(VLV_PCBR);
5806         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5807                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5808                 paddr = (dev_priv->mm.stolen_base +
5809                          (ggtt->stolen_size - pctx_size));
5810
5811                 pctx_paddr = (paddr & (~4095));
5812                 I915_WRITE(VLV_PCBR, pctx_paddr);
5813         }
5814
5815         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5816 }
5817
5818 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5819 {
5820         struct drm_i915_gem_object *pctx;
5821         unsigned long pctx_paddr;
5822         u32 pcbr;
5823         int pctx_size = 24*1024;
5824
5825         pcbr = I915_READ(VLV_PCBR);
5826         if (pcbr) {
5827                 /* BIOS set it up already, grab the pre-alloc'd space */
5828                 int pcbr_offset;
5829
5830                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5831                 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
5832                                                                       pcbr_offset,
5833                                                                       I915_GTT_OFFSET_NONE,
5834                                                                       pctx_size);
5835                 goto out;
5836         }
5837
5838         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5839
5840         /*
5841          * From the Gunit register HAS:
5842          * The Gfx driver is expected to program this register and ensure
5843          * proper allocation within Gfx stolen memory.  For example, this
5844          * register should be programmed such than the PCBR range does not
5845          * overlap with other ranges, such as the frame buffer, protected
5846          * memory, or any other relevant ranges.
5847          */
5848         pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
5849         if (!pctx) {
5850                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5851                 goto out;
5852         }
5853
5854         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5855         I915_WRITE(VLV_PCBR, pctx_paddr);
5856
5857 out:
5858         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5859         dev_priv->vlv_pctx = pctx;
5860 }
5861
5862 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5863 {
5864         if (WARN_ON(!dev_priv->vlv_pctx))
5865                 return;
5866
5867         i915_gem_object_put_unlocked(dev_priv->vlv_pctx);
5868         dev_priv->vlv_pctx = NULL;
5869 }
5870
5871 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5872 {
5873         dev_priv->rps.gpll_ref_freq =
5874                 vlv_get_cck_clock(dev_priv, "GPLL ref",
5875                                   CCK_GPLL_CLOCK_CONTROL,
5876                                   dev_priv->czclk_freq);
5877
5878         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5879                          dev_priv->rps.gpll_ref_freq);
5880 }
5881
5882 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5883 {
5884         u32 val;
5885
5886         valleyview_setup_pctx(dev_priv);
5887
5888         vlv_init_gpll_ref_freq(dev_priv);
5889
5890         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5891         switch ((val >> 6) & 3) {
5892         case 0:
5893         case 1:
5894                 dev_priv->mem_freq = 800;
5895                 break;
5896         case 2:
5897                 dev_priv->mem_freq = 1066;
5898                 break;
5899         case 3:
5900                 dev_priv->mem_freq = 1333;
5901                 break;
5902         }
5903         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5904
5905         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5906         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5907         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5908                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5909                          dev_priv->rps.max_freq);
5910
5911         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5912         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5913                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5914                          dev_priv->rps.efficient_freq);
5915
5916         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5917         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5918                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5919                          dev_priv->rps.rp1_freq);
5920
5921         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5922         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5923                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5924                          dev_priv->rps.min_freq);
5925 }
5926
5927 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5928 {
5929         u32 val;
5930
5931         cherryview_setup_pctx(dev_priv);
5932
5933         vlv_init_gpll_ref_freq(dev_priv);
5934
5935         mutex_lock(&dev_priv->sb_lock);
5936         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5937         mutex_unlock(&dev_priv->sb_lock);
5938
5939         switch ((val >> 2) & 0x7) {
5940         case 3:
5941                 dev_priv->mem_freq = 2000;
5942                 break;
5943         default:
5944                 dev_priv->mem_freq = 1600;
5945                 break;
5946         }
5947         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5948
5949         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5950         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5951         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5952                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5953                          dev_priv->rps.max_freq);
5954
5955         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5956         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5957                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5958                          dev_priv->rps.efficient_freq);
5959
5960         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5961         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5962                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5963                          dev_priv->rps.rp1_freq);
5964
5965         /* PUnit validated range is only [RPe, RP0] */
5966         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5967         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5968                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5969                          dev_priv->rps.min_freq);
5970
5971         WARN_ONCE((dev_priv->rps.max_freq |
5972                    dev_priv->rps.efficient_freq |
5973                    dev_priv->rps.rp1_freq |
5974                    dev_priv->rps.min_freq) & 1,
5975                   "Odd GPU freq values\n");
5976 }
5977
5978 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5979 {
5980         valleyview_cleanup_pctx(dev_priv);
5981 }
5982
5983 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5984 {
5985         struct intel_engine_cs *engine;
5986         enum intel_engine_id id;
5987         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5988
5989         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5990
5991         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5992                                              GT_FIFO_FREE_ENTRIES_CHV);
5993         if (gtfifodbg) {
5994                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5995                                  gtfifodbg);
5996                 I915_WRITE(GTFIFODBG, gtfifodbg);
5997         }
5998
5999         cherryview_check_pctx(dev_priv);
6000
6001         /* 1a & 1b: Get forcewake during program sequence. Although the driver
6002          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6003         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6004
6005         /*  Disable RC states. */
6006         I915_WRITE(GEN6_RC_CONTROL, 0);
6007
6008         /* 2a: Program RC6 thresholds.*/
6009         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6010         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6011         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6012
6013         for_each_engine(engine, dev_priv, id)
6014                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6015         I915_WRITE(GEN6_RC_SLEEP, 0);
6016
6017         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6018         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
6019
6020         /* allows RC6 residency counter to work */
6021         I915_WRITE(VLV_COUNTER_CONTROL,
6022                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6023                                       VLV_MEDIA_RC6_COUNT_EN |
6024                                       VLV_RENDER_RC6_COUNT_EN));
6025
6026         /* For now we assume BIOS is allocating and populating the PCBR  */
6027         pcbr = I915_READ(VLV_PCBR);
6028
6029         /* 3: Enable RC6 */
6030         if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6031             (pcbr >> VLV_PCBR_ADDR_SHIFT))
6032                 rc6_mode = GEN7_RC_CTL_TO_MODE;
6033
6034         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6035
6036         /* 4 Program defaults and thresholds for RPS*/
6037         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6038         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6039         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6040         I915_WRITE(GEN6_RP_UP_EI, 66000);
6041         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6042
6043         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6044
6045         /* 5: Enable RPS */
6046         I915_WRITE(GEN6_RP_CONTROL,
6047                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6048                    GEN6_RP_MEDIA_IS_GFX |
6049                    GEN6_RP_ENABLE |
6050                    GEN6_RP_UP_BUSY_AVG |
6051                    GEN6_RP_DOWN_IDLE_AVG);
6052
6053         /* Setting Fixed Bias */
6054         val = VLV_OVERRIDE_EN |
6055                   VLV_SOC_TDP_EN |
6056                   CHV_BIAS_CPU_50_SOC_50;
6057         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6058
6059         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6060
6061         /* RPS code assumes GPLL is used */
6062         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6063
6064         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6065         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6066
6067         reset_rps(dev_priv, valleyview_set_rps);
6068
6069         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6070 }
6071
6072 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
6073 {
6074         struct intel_engine_cs *engine;
6075         enum intel_engine_id id;
6076         u32 gtfifodbg, val, rc6_mode = 0;
6077
6078         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6079
6080         valleyview_check_pctx(dev_priv);
6081
6082         gtfifodbg = I915_READ(GTFIFODBG);
6083         if (gtfifodbg) {
6084                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6085                                  gtfifodbg);
6086                 I915_WRITE(GTFIFODBG, gtfifodbg);
6087         }
6088
6089         /* If VLV, Forcewake all wells, else re-direct to regular path */
6090         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6091
6092         /*  Disable RC states. */
6093         I915_WRITE(GEN6_RC_CONTROL, 0);
6094
6095         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6096         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6097         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6098         I915_WRITE(GEN6_RP_UP_EI, 66000);
6099         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6100
6101         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6102
6103         I915_WRITE(GEN6_RP_CONTROL,
6104                    GEN6_RP_MEDIA_TURBO |
6105                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6106                    GEN6_RP_MEDIA_IS_GFX |
6107                    GEN6_RP_ENABLE |
6108                    GEN6_RP_UP_BUSY_AVG |
6109                    GEN6_RP_DOWN_IDLE_CONT);
6110
6111         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6112         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6113         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6114
6115         for_each_engine(engine, dev_priv, id)
6116                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6117
6118         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
6119
6120         /* allows RC6 residency counter to work */
6121         I915_WRITE(VLV_COUNTER_CONTROL,
6122                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6123                                       VLV_RENDER_RC0_COUNT_EN |
6124                                       VLV_MEDIA_RC6_COUNT_EN |
6125                                       VLV_RENDER_RC6_COUNT_EN));
6126
6127         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6128                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
6129
6130         intel_print_rc6_info(dev_priv, rc6_mode);
6131
6132         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6133
6134         /* Setting Fixed Bias */
6135         val = VLV_OVERRIDE_EN |
6136                   VLV_SOC_TDP_EN |
6137                   VLV_BIAS_CPU_125_SOC_875;
6138         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6139
6140         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6141
6142         /* RPS code assumes GPLL is used */
6143         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6144
6145         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6146         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6147
6148         reset_rps(dev_priv, valleyview_set_rps);
6149
6150         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6151 }
6152
6153 static unsigned long intel_pxfreq(u32 vidfreq)
6154 {
6155         unsigned long freq;
6156         int div = (vidfreq & 0x3f0000) >> 16;
6157         int post = (vidfreq & 0x3000) >> 12;
6158         int pre = (vidfreq & 0x7);
6159
6160         if (!pre)
6161                 return 0;
6162
6163         freq = ((div * 133333) / ((1<<post) * pre));
6164
6165         return freq;
6166 }
6167
6168 static const struct cparams {
6169         u16 i;
6170         u16 t;
6171         u16 m;
6172         u16 c;
6173 } cparams[] = {
6174         { 1, 1333, 301, 28664 },
6175         { 1, 1066, 294, 24460 },
6176         { 1, 800, 294, 25192 },
6177         { 0, 1333, 276, 27605 },
6178         { 0, 1066, 276, 27605 },
6179         { 0, 800, 231, 23784 },
6180 };
6181
6182 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6183 {
6184         u64 total_count, diff, ret;
6185         u32 count1, count2, count3, m = 0, c = 0;
6186         unsigned long now = jiffies_to_msecs(jiffies), diff1;
6187         int i;
6188
6189         assert_spin_locked(&mchdev_lock);
6190
6191         diff1 = now - dev_priv->ips.last_time1;
6192
6193         /* Prevent division-by-zero if we are asking too fast.
6194          * Also, we don't get interesting results if we are polling
6195          * faster than once in 10ms, so just return the saved value
6196          * in such cases.
6197          */
6198         if (diff1 <= 10)
6199                 return dev_priv->ips.chipset_power;
6200
6201         count1 = I915_READ(DMIEC);
6202         count2 = I915_READ(DDREC);
6203         count3 = I915_READ(CSIEC);
6204
6205         total_count = count1 + count2 + count3;
6206
6207         /* FIXME: handle per-counter overflow */
6208         if (total_count < dev_priv->ips.last_count1) {
6209                 diff = ~0UL - dev_priv->ips.last_count1;
6210                 diff += total_count;
6211         } else {
6212                 diff = total_count - dev_priv->ips.last_count1;
6213         }
6214
6215         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6216                 if (cparams[i].i == dev_priv->ips.c_m &&
6217                     cparams[i].t == dev_priv->ips.r_t) {
6218                         m = cparams[i].m;
6219                         c = cparams[i].c;
6220                         break;
6221                 }
6222         }
6223
6224         diff = div_u64(diff, diff1);
6225         ret = ((m * diff) + c);
6226         ret = div_u64(ret, 10);
6227
6228         dev_priv->ips.last_count1 = total_count;
6229         dev_priv->ips.last_time1 = now;
6230
6231         dev_priv->ips.chipset_power = ret;
6232
6233         return ret;
6234 }
6235
6236 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6237 {
6238         unsigned long val;
6239
6240         if (INTEL_INFO(dev_priv)->gen != 5)
6241                 return 0;
6242
6243         spin_lock_irq(&mchdev_lock);
6244
6245         val = __i915_chipset_val(dev_priv);
6246
6247         spin_unlock_irq(&mchdev_lock);
6248
6249         return val;
6250 }
6251
6252 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6253 {
6254         unsigned long m, x, b;
6255         u32 tsfs;
6256
6257         tsfs = I915_READ(TSFS);
6258
6259         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6260         x = I915_READ8(TR1);
6261
6262         b = tsfs & TSFS_INTR_MASK;
6263
6264         return ((m * x) / 127) - b;
6265 }
6266
6267 static int _pxvid_to_vd(u8 pxvid)
6268 {
6269         if (pxvid == 0)
6270                 return 0;
6271
6272         if (pxvid >= 8 && pxvid < 31)
6273                 pxvid = 31;
6274
6275         return (pxvid + 2) * 125;
6276 }
6277
6278 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6279 {
6280         const int vd = _pxvid_to_vd(pxvid);
6281         const int vm = vd - 1125;
6282
6283         if (INTEL_INFO(dev_priv)->is_mobile)
6284                 return vm > 0 ? vm : 0;
6285
6286         return vd;
6287 }
6288
6289 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6290 {
6291         u64 now, diff, diffms;
6292         u32 count;
6293
6294         assert_spin_locked(&mchdev_lock);
6295
6296         now = ktime_get_raw_ns();
6297         diffms = now - dev_priv->ips.last_time2;
6298         do_div(diffms, NSEC_PER_MSEC);
6299
6300         /* Don't divide by 0 */
6301         if (!diffms)
6302                 return;
6303
6304         count = I915_READ(GFXEC);
6305
6306         if (count < dev_priv->ips.last_count2) {
6307                 diff = ~0UL - dev_priv->ips.last_count2;
6308                 diff += count;
6309         } else {
6310                 diff = count - dev_priv->ips.last_count2;
6311         }
6312
6313         dev_priv->ips.last_count2 = count;
6314         dev_priv->ips.last_time2 = now;
6315
6316         /* More magic constants... */
6317         diff = diff * 1181;
6318         diff = div_u64(diff, diffms * 10);
6319         dev_priv->ips.gfx_power = diff;
6320 }
6321
6322 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6323 {
6324         if (INTEL_INFO(dev_priv)->gen != 5)
6325                 return;
6326
6327         spin_lock_irq(&mchdev_lock);
6328
6329         __i915_update_gfx_val(dev_priv);
6330
6331         spin_unlock_irq(&mchdev_lock);
6332 }
6333
6334 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6335 {
6336         unsigned long t, corr, state1, corr2, state2;
6337         u32 pxvid, ext_v;
6338
6339         assert_spin_locked(&mchdev_lock);
6340
6341         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6342         pxvid = (pxvid >> 24) & 0x7f;
6343         ext_v = pvid_to_extvid(dev_priv, pxvid);
6344
6345         state1 = ext_v;
6346
6347         t = i915_mch_val(dev_priv);
6348
6349         /* Revel in the empirically derived constants */
6350
6351         /* Correction factor in 1/100000 units */
6352         if (t > 80)
6353                 corr = ((t * 2349) + 135940);
6354         else if (t >= 50)
6355                 corr = ((t * 964) + 29317);
6356         else /* < 50 */
6357                 corr = ((t * 301) + 1004);
6358
6359         corr = corr * ((150142 * state1) / 10000 - 78642);
6360         corr /= 100000;
6361         corr2 = (corr * dev_priv->ips.corr);
6362
6363         state2 = (corr2 * state1) / 10000;
6364         state2 /= 100; /* convert to mW */
6365
6366         __i915_update_gfx_val(dev_priv);
6367
6368         return dev_priv->ips.gfx_power + state2;
6369 }
6370
6371 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6372 {
6373         unsigned long val;
6374
6375         if (INTEL_INFO(dev_priv)->gen != 5)
6376                 return 0;
6377
6378         spin_lock_irq(&mchdev_lock);
6379
6380         val = __i915_gfx_val(dev_priv);
6381
6382         spin_unlock_irq(&mchdev_lock);
6383
6384         return val;
6385 }
6386
6387 /**
6388  * i915_read_mch_val - return value for IPS use
6389  *
6390  * Calculate and return a value for the IPS driver to use when deciding whether
6391  * we have thermal and power headroom to increase CPU or GPU power budget.
6392  */
6393 unsigned long i915_read_mch_val(void)
6394 {
6395         struct drm_i915_private *dev_priv;
6396         unsigned long chipset_val, graphics_val, ret = 0;
6397
6398         spin_lock_irq(&mchdev_lock);
6399         if (!i915_mch_dev)
6400                 goto out_unlock;
6401         dev_priv = i915_mch_dev;
6402
6403         chipset_val = __i915_chipset_val(dev_priv);
6404         graphics_val = __i915_gfx_val(dev_priv);
6405
6406         ret = chipset_val + graphics_val;
6407
6408 out_unlock:
6409         spin_unlock_irq(&mchdev_lock);
6410
6411         return ret;
6412 }
6413 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6414
6415 /**
6416  * i915_gpu_raise - raise GPU frequency limit
6417  *
6418  * Raise the limit; IPS indicates we have thermal headroom.
6419  */
6420 bool i915_gpu_raise(void)
6421 {
6422         struct drm_i915_private *dev_priv;
6423         bool ret = true;
6424
6425         spin_lock_irq(&mchdev_lock);
6426         if (!i915_mch_dev) {
6427                 ret = false;
6428                 goto out_unlock;
6429         }
6430         dev_priv = i915_mch_dev;
6431
6432         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6433                 dev_priv->ips.max_delay--;
6434
6435 out_unlock:
6436         spin_unlock_irq(&mchdev_lock);
6437
6438         return ret;
6439 }
6440 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6441
6442 /**
6443  * i915_gpu_lower - lower GPU frequency limit
6444  *
6445  * IPS indicates we're close to a thermal limit, so throttle back the GPU
6446  * frequency maximum.
6447  */
6448 bool i915_gpu_lower(void)
6449 {
6450         struct drm_i915_private *dev_priv;
6451         bool ret = true;
6452
6453         spin_lock_irq(&mchdev_lock);
6454         if (!i915_mch_dev) {
6455                 ret = false;
6456                 goto out_unlock;
6457         }
6458         dev_priv = i915_mch_dev;
6459
6460         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6461                 dev_priv->ips.max_delay++;
6462
6463 out_unlock:
6464         spin_unlock_irq(&mchdev_lock);
6465
6466         return ret;
6467 }
6468 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6469
6470 /**
6471  * i915_gpu_busy - indicate GPU business to IPS
6472  *
6473  * Tell the IPS driver whether or not the GPU is busy.
6474  */
6475 bool i915_gpu_busy(void)
6476 {
6477         bool ret = false;
6478
6479         spin_lock_irq(&mchdev_lock);
6480         if (i915_mch_dev)
6481                 ret = i915_mch_dev->gt.awake;
6482         spin_unlock_irq(&mchdev_lock);
6483
6484         return ret;
6485 }
6486 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6487
6488 /**
6489  * i915_gpu_turbo_disable - disable graphics turbo
6490  *
6491  * Disable graphics turbo by resetting the max frequency and setting the
6492  * current frequency to the default.
6493  */
6494 bool i915_gpu_turbo_disable(void)
6495 {
6496         struct drm_i915_private *dev_priv;
6497         bool ret = true;
6498
6499         spin_lock_irq(&mchdev_lock);
6500         if (!i915_mch_dev) {
6501                 ret = false;
6502                 goto out_unlock;
6503         }
6504         dev_priv = i915_mch_dev;
6505
6506         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6507
6508         if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6509                 ret = false;
6510
6511 out_unlock:
6512         spin_unlock_irq(&mchdev_lock);
6513
6514         return ret;
6515 }
6516 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6517
6518 /**
6519  * Tells the intel_ips driver that the i915 driver is now loaded, if
6520  * IPS got loaded first.
6521  *
6522  * This awkward dance is so that neither module has to depend on the
6523  * other in order for IPS to do the appropriate communication of
6524  * GPU turbo limits to i915.
6525  */
6526 static void
6527 ips_ping_for_i915_load(void)
6528 {
6529         void (*link)(void);
6530
6531         link = symbol_get(ips_link_to_i915_driver);
6532         if (link) {
6533                 link();
6534                 symbol_put(ips_link_to_i915_driver);
6535         }
6536 }
6537
6538 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6539 {
6540         /* We only register the i915 ips part with intel-ips once everything is
6541          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6542         spin_lock_irq(&mchdev_lock);
6543         i915_mch_dev = dev_priv;
6544         spin_unlock_irq(&mchdev_lock);
6545
6546         ips_ping_for_i915_load();
6547 }
6548
6549 void intel_gpu_ips_teardown(void)
6550 {
6551         spin_lock_irq(&mchdev_lock);
6552         i915_mch_dev = NULL;
6553         spin_unlock_irq(&mchdev_lock);
6554 }
6555
6556 static void intel_init_emon(struct drm_i915_private *dev_priv)
6557 {
6558         u32 lcfuse;
6559         u8 pxw[16];
6560         int i;
6561
6562         /* Disable to program */
6563         I915_WRITE(ECR, 0);
6564         POSTING_READ(ECR);
6565
6566         /* Program energy weights for various events */
6567         I915_WRITE(SDEW, 0x15040d00);
6568         I915_WRITE(CSIEW0, 0x007f0000);
6569         I915_WRITE(CSIEW1, 0x1e220004);
6570         I915_WRITE(CSIEW2, 0x04000004);
6571
6572         for (i = 0; i < 5; i++)
6573                 I915_WRITE(PEW(i), 0);
6574         for (i = 0; i < 3; i++)
6575                 I915_WRITE(DEW(i), 0);
6576
6577         /* Program P-state weights to account for frequency power adjustment */
6578         for (i = 0; i < 16; i++) {
6579                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6580                 unsigned long freq = intel_pxfreq(pxvidfreq);
6581                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6582                         PXVFREQ_PX_SHIFT;
6583                 unsigned long val;
6584
6585                 val = vid * vid;
6586                 val *= (freq / 1000);
6587                 val *= 255;
6588                 val /= (127*127*900);
6589                 if (val > 0xff)
6590                         DRM_ERROR("bad pxval: %ld\n", val);
6591                 pxw[i] = val;
6592         }
6593         /* Render standby states get 0 weight */
6594         pxw[14] = 0;
6595         pxw[15] = 0;
6596
6597         for (i = 0; i < 4; i++) {
6598                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6599                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6600                 I915_WRITE(PXW(i), val);
6601         }
6602
6603         /* Adjust magic regs to magic values (more experimental results) */
6604         I915_WRITE(OGW0, 0);
6605         I915_WRITE(OGW1, 0);
6606         I915_WRITE(EG0, 0x00007f00);
6607         I915_WRITE(EG1, 0x0000000e);
6608         I915_WRITE(EG2, 0x000e0000);
6609         I915_WRITE(EG3, 0x68000300);
6610         I915_WRITE(EG4, 0x42000000);
6611         I915_WRITE(EG5, 0x00140031);
6612         I915_WRITE(EG6, 0);
6613         I915_WRITE(EG7, 0);
6614
6615         for (i = 0; i < 8; i++)
6616                 I915_WRITE(PXWL(i), 0);
6617
6618         /* Enable PMON + select events */
6619         I915_WRITE(ECR, 0x80000019);
6620
6621         lcfuse = I915_READ(LCFUSE02);
6622
6623         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6624 }
6625
6626 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6627 {
6628         /*
6629          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6630          * requirement.
6631          */
6632         if (!i915.enable_rc6) {
6633                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6634                 intel_runtime_pm_get(dev_priv);
6635         }
6636
6637         mutex_lock(&dev_priv->drm.struct_mutex);
6638         mutex_lock(&dev_priv->rps.hw_lock);
6639
6640         /* Initialize RPS limits (for userspace) */
6641         if (IS_CHERRYVIEW(dev_priv))
6642                 cherryview_init_gt_powersave(dev_priv);
6643         else if (IS_VALLEYVIEW(dev_priv))
6644                 valleyview_init_gt_powersave(dev_priv);
6645         else if (INTEL_GEN(dev_priv) >= 6)
6646                 gen6_init_rps_frequencies(dev_priv);
6647
6648         /* Derive initial user preferences/limits from the hardware limits */
6649         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6650         dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6651
6652         dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6653         dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6654
6655         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6656                 dev_priv->rps.min_freq_softlimit =
6657                         max_t(int,
6658                               dev_priv->rps.efficient_freq,
6659                               intel_freq_opcode(dev_priv, 450));
6660
6661         /* After setting max-softlimit, find the overclock max freq */
6662         if (IS_GEN6(dev_priv) ||
6663             IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6664                 u32 params = 0;
6665
6666                 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6667                 if (params & BIT(31)) { /* OC supported */
6668                         DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6669                                          (dev_priv->rps.max_freq & 0xff) * 50,
6670                                          (params & 0xff) * 50);
6671                         dev_priv->rps.max_freq = params & 0xff;
6672                 }
6673         }
6674
6675         /* Finally allow us to boost to max by default */
6676         dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6677
6678         mutex_unlock(&dev_priv->rps.hw_lock);
6679         mutex_unlock(&dev_priv->drm.struct_mutex);
6680
6681         intel_autoenable_gt_powersave(dev_priv);
6682 }
6683
6684 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6685 {
6686         if (IS_VALLEYVIEW(dev_priv))
6687                 valleyview_cleanup_gt_powersave(dev_priv);
6688
6689         if (!i915.enable_rc6)
6690                 intel_runtime_pm_put(dev_priv);
6691 }
6692
6693 /**
6694  * intel_suspend_gt_powersave - suspend PM work and helper threads
6695  * @dev_priv: i915 device
6696  *
6697  * We don't want to disable RC6 or other features here, we just want
6698  * to make sure any work we've queued has finished and won't bother
6699  * us while we're suspended.
6700  */
6701 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6702 {
6703         if (INTEL_GEN(dev_priv) < 6)
6704                 return;
6705
6706         if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6707                 intel_runtime_pm_put(dev_priv);
6708
6709         /* gen6_rps_idle() will be called later to disable interrupts */
6710 }
6711
6712 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6713 {
6714         dev_priv->rps.enabled = true; /* force disabling */
6715         intel_disable_gt_powersave(dev_priv);
6716
6717         gen6_reset_rps_interrupts(dev_priv);
6718 }
6719
6720 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6721 {
6722         if (!READ_ONCE(dev_priv->rps.enabled))
6723                 return;
6724
6725         mutex_lock(&dev_priv->rps.hw_lock);
6726
6727         if (INTEL_GEN(dev_priv) >= 9) {
6728                 gen9_disable_rc6(dev_priv);
6729                 gen9_disable_rps(dev_priv);
6730         } else if (IS_CHERRYVIEW(dev_priv)) {
6731                 cherryview_disable_rps(dev_priv);
6732         } else if (IS_VALLEYVIEW(dev_priv)) {
6733                 valleyview_disable_rps(dev_priv);
6734         } else if (INTEL_GEN(dev_priv) >= 6) {
6735                 gen6_disable_rps(dev_priv);
6736         }  else if (IS_IRONLAKE_M(dev_priv)) {
6737                 ironlake_disable_drps(dev_priv);
6738         }
6739
6740         dev_priv->rps.enabled = false;
6741         mutex_unlock(&dev_priv->rps.hw_lock);
6742 }
6743
6744 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6745 {
6746         /* We shouldn't be disabling as we submit, so this should be less
6747          * racy than it appears!
6748          */
6749         if (READ_ONCE(dev_priv->rps.enabled))
6750                 return;
6751
6752         /* Powersaving is controlled by the host when inside a VM */
6753         if (intel_vgpu_active(dev_priv))
6754                 return;
6755
6756         mutex_lock(&dev_priv->rps.hw_lock);
6757
6758         if (IS_CHERRYVIEW(dev_priv)) {
6759                 cherryview_enable_rps(dev_priv);
6760         } else if (IS_VALLEYVIEW(dev_priv)) {
6761                 valleyview_enable_rps(dev_priv);
6762         } else if (INTEL_GEN(dev_priv) >= 9) {
6763                 gen9_enable_rc6(dev_priv);
6764                 gen9_enable_rps(dev_priv);
6765                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6766                         gen6_update_ring_freq(dev_priv);
6767         } else if (IS_BROADWELL(dev_priv)) {
6768                 gen8_enable_rps(dev_priv);
6769                 gen6_update_ring_freq(dev_priv);
6770         } else if (INTEL_GEN(dev_priv) >= 6) {
6771                 gen6_enable_rps(dev_priv);
6772                 gen6_update_ring_freq(dev_priv);
6773         } else if (IS_IRONLAKE_M(dev_priv)) {
6774                 ironlake_enable_drps(dev_priv);
6775                 intel_init_emon(dev_priv);
6776         }
6777
6778         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6779         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6780
6781         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6782         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6783
6784         dev_priv->rps.enabled = true;
6785         mutex_unlock(&dev_priv->rps.hw_lock);
6786 }
6787
6788 static void __intel_autoenable_gt_powersave(struct work_struct *work)
6789 {
6790         struct drm_i915_private *dev_priv =
6791                 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6792         struct intel_engine_cs *rcs;
6793         struct drm_i915_gem_request *req;
6794
6795         if (READ_ONCE(dev_priv->rps.enabled))
6796                 goto out;
6797
6798         rcs = dev_priv->engine[RCS];
6799         if (rcs->last_context)
6800                 goto out;
6801
6802         if (!rcs->init_context)
6803                 goto out;
6804
6805         mutex_lock(&dev_priv->drm.struct_mutex);
6806
6807         req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6808         if (IS_ERR(req))
6809                 goto unlock;
6810
6811         if (!i915.enable_execlists && i915_switch_context(req) == 0)
6812                 rcs->init_context(req);
6813
6814         /* Mark the device busy, calling intel_enable_gt_powersave() */
6815         i915_add_request_no_flush(req);
6816
6817 unlock:
6818         mutex_unlock(&dev_priv->drm.struct_mutex);
6819 out:
6820         intel_runtime_pm_put(dev_priv);
6821 }
6822
6823 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6824 {
6825         if (READ_ONCE(dev_priv->rps.enabled))
6826                 return;
6827
6828         if (IS_IRONLAKE_M(dev_priv)) {
6829                 ironlake_enable_drps(dev_priv);
6830                 intel_init_emon(dev_priv);
6831         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6832                 /*
6833                  * PCU communication is slow and this doesn't need to be
6834                  * done at any specific time, so do this out of our fast path
6835                  * to make resume and init faster.
6836                  *
6837                  * We depend on the HW RC6 power context save/restore
6838                  * mechanism when entering D3 through runtime PM suspend. So
6839                  * disable RPM until RPS/RC6 is properly setup. We can only
6840                  * get here via the driver load/system resume/runtime resume
6841                  * paths, so the _noresume version is enough (and in case of
6842                  * runtime resume it's necessary).
6843                  */
6844                 if (queue_delayed_work(dev_priv->wq,
6845                                        &dev_priv->rps.autoenable_work,
6846                                        round_jiffies_up_relative(HZ)))
6847                         intel_runtime_pm_get_noresume(dev_priv);
6848         }
6849 }
6850
6851 static void ibx_init_clock_gating(struct drm_device *dev)
6852 {
6853         struct drm_i915_private *dev_priv = to_i915(dev);
6854
6855         /*
6856          * On Ibex Peak and Cougar Point, we need to disable clock
6857          * gating for the panel power sequencer or it will fail to
6858          * start up when no ports are active.
6859          */
6860         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6861 }
6862
6863 static void g4x_disable_trickle_feed(struct drm_device *dev)
6864 {
6865         struct drm_i915_private *dev_priv = to_i915(dev);
6866         enum pipe pipe;
6867
6868         for_each_pipe(dev_priv, pipe) {
6869                 I915_WRITE(DSPCNTR(pipe),
6870                            I915_READ(DSPCNTR(pipe)) |
6871                            DISPPLANE_TRICKLE_FEED_DISABLE);
6872
6873                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6874                 POSTING_READ(DSPSURF(pipe));
6875         }
6876 }
6877
6878 static void ilk_init_lp_watermarks(struct drm_device *dev)
6879 {
6880         struct drm_i915_private *dev_priv = to_i915(dev);
6881
6882         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6883         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6884         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6885
6886         /*
6887          * Don't touch WM1S_LP_EN here.
6888          * Doing so could cause underruns.
6889          */
6890 }
6891
6892 static void ironlake_init_clock_gating(struct drm_device *dev)
6893 {
6894         struct drm_i915_private *dev_priv = to_i915(dev);
6895         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6896
6897         /*
6898          * Required for FBC
6899          * WaFbcDisableDpfcClockGating:ilk
6900          */
6901         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6902                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6903                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6904
6905         I915_WRITE(PCH_3DCGDIS0,
6906                    MARIUNIT_CLOCK_GATE_DISABLE |
6907                    SVSMUNIT_CLOCK_GATE_DISABLE);
6908         I915_WRITE(PCH_3DCGDIS1,
6909                    VFMUNIT_CLOCK_GATE_DISABLE);
6910
6911         /*
6912          * According to the spec the following bits should be set in
6913          * order to enable memory self-refresh
6914          * The bit 22/21 of 0x42004
6915          * The bit 5 of 0x42020
6916          * The bit 15 of 0x45000
6917          */
6918         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6919                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6920                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6921         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6922         I915_WRITE(DISP_ARB_CTL,
6923                    (I915_READ(DISP_ARB_CTL) |
6924                     DISP_FBC_WM_DIS));
6925
6926         ilk_init_lp_watermarks(dev);
6927
6928         /*
6929          * Based on the document from hardware guys the following bits
6930          * should be set unconditionally in order to enable FBC.
6931          * The bit 22 of 0x42000
6932          * The bit 22 of 0x42004
6933          * The bit 7,8,9 of 0x42020.
6934          */
6935         if (IS_IRONLAKE_M(dev_priv)) {
6936                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6937                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6938                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6939                            ILK_FBCQ_DIS);
6940                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6941                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6942                            ILK_DPARB_GATE);
6943         }
6944
6945         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6946
6947         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6948                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6949                    ILK_ELPIN_409_SELECT);
6950         I915_WRITE(_3D_CHICKEN2,
6951                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6952                    _3D_CHICKEN2_WM_READ_PIPELINED);
6953
6954         /* WaDisableRenderCachePipelinedFlush:ilk */
6955         I915_WRITE(CACHE_MODE_0,
6956                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6957
6958         /* WaDisable_RenderCache_OperationalFlush:ilk */
6959         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6960
6961         g4x_disable_trickle_feed(dev);
6962
6963         ibx_init_clock_gating(dev);
6964 }
6965
6966 static void cpt_init_clock_gating(struct drm_device *dev)
6967 {
6968         struct drm_i915_private *dev_priv = to_i915(dev);
6969         int pipe;
6970         uint32_t val;
6971
6972         /*
6973          * On Ibex Peak and Cougar Point, we need to disable clock
6974          * gating for the panel power sequencer or it will fail to
6975          * start up when no ports are active.
6976          */
6977         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6978                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6979                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6980         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6981                    DPLS_EDP_PPS_FIX_DIS);
6982         /* The below fixes the weird display corruption, a few pixels shifted
6983          * downward, on (only) LVDS of some HP laptops with IVY.
6984          */
6985         for_each_pipe(dev_priv, pipe) {
6986                 val = I915_READ(TRANS_CHICKEN2(pipe));
6987                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6988                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6989                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6990                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6991                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6992                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6993                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6994                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6995         }
6996         /* WADP0ClockGatingDisable */
6997         for_each_pipe(dev_priv, pipe) {
6998                 I915_WRITE(TRANS_CHICKEN1(pipe),
6999                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7000         }
7001 }
7002
7003 static void gen6_check_mch_setup(struct drm_device *dev)
7004 {
7005         struct drm_i915_private *dev_priv = to_i915(dev);
7006         uint32_t tmp;
7007
7008         tmp = I915_READ(MCH_SSKPD);
7009         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7010                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7011                               tmp);
7012 }
7013
7014 static void gen6_init_clock_gating(struct drm_device *dev)
7015 {
7016         struct drm_i915_private *dev_priv = to_i915(dev);
7017         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7018
7019         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
7020
7021         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7022                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7023                    ILK_ELPIN_409_SELECT);
7024
7025         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
7026         I915_WRITE(_3D_CHICKEN,
7027                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7028
7029         /* WaDisable_RenderCache_OperationalFlush:snb */
7030         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7031
7032         /*
7033          * BSpec recoomends 8x4 when MSAA is used,
7034          * however in practice 16x4 seems fastest.
7035          *
7036          * Note that PS/WM thread counts depend on the WIZ hashing
7037          * disable bit, which we don't touch here, but it's good
7038          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7039          */
7040         I915_WRITE(GEN6_GT_MODE,
7041                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7042
7043         ilk_init_lp_watermarks(dev);
7044
7045         I915_WRITE(CACHE_MODE_0,
7046                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
7047
7048         I915_WRITE(GEN6_UCGCTL1,
7049                    I915_READ(GEN6_UCGCTL1) |
7050                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7051                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7052
7053         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7054          * gating disable must be set.  Failure to set it results in
7055          * flickering pixels due to Z write ordering failures after
7056          * some amount of runtime in the Mesa "fire" demo, and Unigine
7057          * Sanctuary and Tropics, and apparently anything else with
7058          * alpha test or pixel discard.
7059          *
7060          * According to the spec, bit 11 (RCCUNIT) must also be set,
7061          * but we didn't debug actual testcases to find it out.
7062          *
7063          * WaDisableRCCUnitClockGating:snb
7064          * WaDisableRCPBUnitClockGating:snb
7065          */
7066         I915_WRITE(GEN6_UCGCTL2,
7067                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7068                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7069
7070         /* WaStripsFansDisableFastClipPerformanceFix:snb */
7071         I915_WRITE(_3D_CHICKEN3,
7072                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
7073
7074         /*
7075          * Bspec says:
7076          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7077          * 3DSTATE_SF number of SF output attributes is more than 16."
7078          */
7079         I915_WRITE(_3D_CHICKEN3,
7080                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7081
7082         /*
7083          * According to the spec the following bits should be
7084          * set in order to enable memory self-refresh and fbc:
7085          * The bit21 and bit22 of 0x42000
7086          * The bit21 and bit22 of 0x42004
7087          * The bit5 and bit7 of 0x42020
7088          * The bit14 of 0x70180
7089          * The bit14 of 0x71180
7090          *
7091          * WaFbcAsynchFlipDisableFbcQueue:snb
7092          */
7093         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7094                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7095                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7096         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7097                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7098                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7099         I915_WRITE(ILK_DSPCLK_GATE_D,
7100                    I915_READ(ILK_DSPCLK_GATE_D) |
7101                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
7102                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7103
7104         g4x_disable_trickle_feed(dev);
7105
7106         cpt_init_clock_gating(dev);
7107
7108         gen6_check_mch_setup(dev);
7109 }
7110
7111 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7112 {
7113         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7114
7115         /*
7116          * WaVSThreadDispatchOverride:ivb,vlv
7117          *
7118          * This actually overrides the dispatch
7119          * mode for all thread types.
7120          */
7121         reg &= ~GEN7_FF_SCHED_MASK;
7122         reg |= GEN7_FF_TS_SCHED_HW;
7123         reg |= GEN7_FF_VS_SCHED_HW;
7124         reg |= GEN7_FF_DS_SCHED_HW;
7125
7126         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7127 }
7128
7129 static void lpt_init_clock_gating(struct drm_device *dev)
7130 {
7131         struct drm_i915_private *dev_priv = to_i915(dev);
7132
7133         /*
7134          * TODO: this bit should only be enabled when really needed, then
7135          * disabled when not needed anymore in order to save power.
7136          */
7137         if (HAS_PCH_LPT_LP(dev_priv))
7138                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7139                            I915_READ(SOUTH_DSPCLK_GATE_D) |
7140                            PCH_LP_PARTITION_LEVEL_DISABLE);
7141
7142         /* WADPOClockGatingDisable:hsw */
7143         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7144                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
7145                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7146 }
7147
7148 static void lpt_suspend_hw(struct drm_device *dev)
7149 {
7150         struct drm_i915_private *dev_priv = to_i915(dev);
7151
7152         if (HAS_PCH_LPT_LP(dev_priv)) {
7153                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7154
7155                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7156                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7157         }
7158 }
7159
7160 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7161                                    int general_prio_credits,
7162                                    int high_prio_credits)
7163 {
7164         u32 misccpctl;
7165
7166         /* WaTempDisableDOPClkGating:bdw */
7167         misccpctl = I915_READ(GEN7_MISCCPCTL);
7168         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7169
7170         I915_WRITE(GEN8_L3SQCREG1,
7171                    L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7172                    L3_HIGH_PRIO_CREDITS(high_prio_credits));
7173
7174         /*
7175          * Wait at least 100 clocks before re-enabling clock gating.
7176          * See the definition of L3SQCREG1 in BSpec.
7177          */
7178         POSTING_READ(GEN8_L3SQCREG1);
7179         udelay(1);
7180         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7181 }
7182
7183 static void kabylake_init_clock_gating(struct drm_device *dev)
7184 {
7185         struct drm_i915_private *dev_priv = dev->dev_private;
7186
7187         gen9_init_clock_gating(dev);
7188
7189         /* WaDisableSDEUnitClockGating:kbl */
7190         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7191                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7192                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7193
7194         /* WaDisableGamClockGating:kbl */
7195         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7196                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7197                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7198
7199         /* WaFbcNukeOnHostModify:kbl */
7200         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7201                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7202 }
7203
7204 static void skylake_init_clock_gating(struct drm_device *dev)
7205 {
7206         struct drm_i915_private *dev_priv = dev->dev_private;
7207
7208         gen9_init_clock_gating(dev);
7209
7210         /* WAC6entrylatency:skl */
7211         I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7212                    FBC_LLC_FULLY_OPEN);
7213
7214         /* WaFbcNukeOnHostModify:skl */
7215         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7216                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7217 }
7218
7219 static void broadwell_init_clock_gating(struct drm_device *dev)
7220 {
7221         struct drm_i915_private *dev_priv = to_i915(dev);
7222         enum pipe pipe;
7223
7224         ilk_init_lp_watermarks(dev);
7225
7226         /* WaSwitchSolVfFArbitrationPriority:bdw */
7227         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7228
7229         /* WaPsrDPAMaskVBlankInSRD:bdw */
7230         I915_WRITE(CHICKEN_PAR1_1,
7231                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7232
7233         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7234         for_each_pipe(dev_priv, pipe) {
7235                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7236                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
7237                            BDW_DPRS_MASK_VBLANK_SRD);
7238         }
7239
7240         /* WaVSRefCountFullforceMissDisable:bdw */
7241         /* WaDSRefCountFullforceMissDisable:bdw */
7242         I915_WRITE(GEN7_FF_THREAD_MODE,
7243                    I915_READ(GEN7_FF_THREAD_MODE) &
7244                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7245
7246         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7247                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7248
7249         /* WaDisableSDEUnitClockGating:bdw */
7250         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7251                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7252
7253         /* WaProgramL3SqcReg1Default:bdw */
7254         gen8_set_l3sqc_credits(dev_priv, 30, 2);
7255
7256         /*
7257          * WaGttCachingOffByDefault:bdw
7258          * GTT cache may not work with big pages, so if those
7259          * are ever enabled GTT cache may need to be disabled.
7260          */
7261         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7262
7263         /* WaKVMNotificationOnConfigChange:bdw */
7264         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7265                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7266
7267         lpt_init_clock_gating(dev);
7268 }
7269
7270 static void haswell_init_clock_gating(struct drm_device *dev)
7271 {
7272         struct drm_i915_private *dev_priv = to_i915(dev);
7273
7274         ilk_init_lp_watermarks(dev);
7275
7276         /* L3 caching of data atomics doesn't work -- disable it. */
7277         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7278         I915_WRITE(HSW_ROW_CHICKEN3,
7279                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7280
7281         /* This is required by WaCatErrorRejectionIssue:hsw */
7282         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7283                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7284                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7285
7286         /* WaVSRefCountFullforceMissDisable:hsw */
7287         I915_WRITE(GEN7_FF_THREAD_MODE,
7288                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7289
7290         /* WaDisable_RenderCache_OperationalFlush:hsw */
7291         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7292
7293         /* enable HiZ Raw Stall Optimization */
7294         I915_WRITE(CACHE_MODE_0_GEN7,
7295                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7296
7297         /* WaDisable4x2SubspanOptimization:hsw */
7298         I915_WRITE(CACHE_MODE_1,
7299                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7300
7301         /*
7302          * BSpec recommends 8x4 when MSAA is used,
7303          * however in practice 16x4 seems fastest.
7304          *
7305          * Note that PS/WM thread counts depend on the WIZ hashing
7306          * disable bit, which we don't touch here, but it's good
7307          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7308          */
7309         I915_WRITE(GEN7_GT_MODE,
7310                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7311
7312         /* WaSampleCChickenBitEnable:hsw */
7313         I915_WRITE(HALF_SLICE_CHICKEN3,
7314                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7315
7316         /* WaSwitchSolVfFArbitrationPriority:hsw */
7317         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7318
7319         /* WaRsPkgCStateDisplayPMReq:hsw */
7320         I915_WRITE(CHICKEN_PAR1_1,
7321                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7322
7323         lpt_init_clock_gating(dev);
7324 }
7325
7326 static void ivybridge_init_clock_gating(struct drm_device *dev)
7327 {
7328         struct drm_i915_private *dev_priv = to_i915(dev);
7329         uint32_t snpcr;
7330
7331         ilk_init_lp_watermarks(dev);
7332
7333         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7334
7335         /* WaDisableEarlyCull:ivb */
7336         I915_WRITE(_3D_CHICKEN3,
7337                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7338
7339         /* WaDisableBackToBackFlipFix:ivb */
7340         I915_WRITE(IVB_CHICKEN3,
7341                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7342                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7343
7344         /* WaDisablePSDDualDispatchEnable:ivb */
7345         if (IS_IVB_GT1(dev_priv))
7346                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7347                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7348
7349         /* WaDisable_RenderCache_OperationalFlush:ivb */
7350         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7351
7352         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7353         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7354                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7355
7356         /* WaApplyL3ControlAndL3ChickenMode:ivb */
7357         I915_WRITE(GEN7_L3CNTLREG1,
7358                         GEN7_WA_FOR_GEN7_L3_CONTROL);
7359         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7360                    GEN7_WA_L3_CHICKEN_MODE);
7361         if (IS_IVB_GT1(dev_priv))
7362                 I915_WRITE(GEN7_ROW_CHICKEN2,
7363                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7364         else {
7365                 /* must write both registers */
7366                 I915_WRITE(GEN7_ROW_CHICKEN2,
7367                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7368                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7369                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7370         }
7371
7372         /* WaForceL3Serialization:ivb */
7373         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7374                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7375
7376         /*
7377          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7378          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7379          */
7380         I915_WRITE(GEN6_UCGCTL2,
7381                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7382
7383         /* This is required by WaCatErrorRejectionIssue:ivb */
7384         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7385                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7386                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7387
7388         g4x_disable_trickle_feed(dev);
7389
7390         gen7_setup_fixed_func_scheduler(dev_priv);
7391
7392         if (0) { /* causes HiZ corruption on ivb:gt1 */
7393                 /* enable HiZ Raw Stall Optimization */
7394                 I915_WRITE(CACHE_MODE_0_GEN7,
7395                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7396         }
7397
7398         /* WaDisable4x2SubspanOptimization:ivb */
7399         I915_WRITE(CACHE_MODE_1,
7400                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7401
7402         /*
7403          * BSpec recommends 8x4 when MSAA is used,
7404          * however in practice 16x4 seems fastest.
7405          *
7406          * Note that PS/WM thread counts depend on the WIZ hashing
7407          * disable bit, which we don't touch here, but it's good
7408          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7409          */
7410         I915_WRITE(GEN7_GT_MODE,
7411                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7412
7413         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7414         snpcr &= ~GEN6_MBC_SNPCR_MASK;
7415         snpcr |= GEN6_MBC_SNPCR_MED;
7416         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7417
7418         if (!HAS_PCH_NOP(dev_priv))
7419                 cpt_init_clock_gating(dev);
7420
7421         gen6_check_mch_setup(dev);
7422 }
7423
7424 static void valleyview_init_clock_gating(struct drm_device *dev)
7425 {
7426         struct drm_i915_private *dev_priv = to_i915(dev);
7427
7428         /* WaDisableEarlyCull:vlv */
7429         I915_WRITE(_3D_CHICKEN3,
7430                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7431
7432         /* WaDisableBackToBackFlipFix:vlv */
7433         I915_WRITE(IVB_CHICKEN3,
7434                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7435                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7436
7437         /* WaPsdDispatchEnable:vlv */
7438         /* WaDisablePSDDualDispatchEnable:vlv */
7439         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7440                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7441                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7442
7443         /* WaDisable_RenderCache_OperationalFlush:vlv */
7444         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7445
7446         /* WaForceL3Serialization:vlv */
7447         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7448                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7449
7450         /* WaDisableDopClockGating:vlv */
7451         I915_WRITE(GEN7_ROW_CHICKEN2,
7452                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7453
7454         /* This is required by WaCatErrorRejectionIssue:vlv */
7455         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7456                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7457                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7458
7459         gen7_setup_fixed_func_scheduler(dev_priv);
7460
7461         /*
7462          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7463          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7464          */
7465         I915_WRITE(GEN6_UCGCTL2,
7466                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7467
7468         /* WaDisableL3Bank2xClockGate:vlv
7469          * Disabling L3 clock gating- MMIO 940c[25] = 1
7470          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7471         I915_WRITE(GEN7_UCGCTL4,
7472                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7473
7474         /*
7475          * BSpec says this must be set, even though
7476          * WaDisable4x2SubspanOptimization isn't listed for VLV.
7477          */
7478         I915_WRITE(CACHE_MODE_1,
7479                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7480
7481         /*
7482          * BSpec recommends 8x4 when MSAA is used,
7483          * however in practice 16x4 seems fastest.
7484          *
7485          * Note that PS/WM thread counts depend on the WIZ hashing
7486          * disable bit, which we don't touch here, but it's good
7487          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7488          */
7489         I915_WRITE(GEN7_GT_MODE,
7490                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7491
7492         /*
7493          * WaIncreaseL3CreditsForVLVB0:vlv
7494          * This is the hardware default actually.
7495          */
7496         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7497
7498         /*
7499          * WaDisableVLVClockGating_VBIIssue:vlv
7500          * Disable clock gating on th GCFG unit to prevent a delay
7501          * in the reporting of vblank events.
7502          */
7503         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7504 }
7505
7506 static void cherryview_init_clock_gating(struct drm_device *dev)
7507 {
7508         struct drm_i915_private *dev_priv = to_i915(dev);
7509
7510         /* WaVSRefCountFullforceMissDisable:chv */
7511         /* WaDSRefCountFullforceMissDisable:chv */
7512         I915_WRITE(GEN7_FF_THREAD_MODE,
7513                    I915_READ(GEN7_FF_THREAD_MODE) &
7514                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7515
7516         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7517         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7518                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7519
7520         /* WaDisableCSUnitClockGating:chv */
7521         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7522                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7523
7524         /* WaDisableSDEUnitClockGating:chv */
7525         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7526                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7527
7528         /*
7529          * WaProgramL3SqcReg1Default:chv
7530          * See gfxspecs/Related Documents/Performance Guide/
7531          * LSQC Setting Recommendations.
7532          */
7533         gen8_set_l3sqc_credits(dev_priv, 38, 2);
7534
7535         /*
7536          * GTT cache may not work with big pages, so if those
7537          * are ever enabled GTT cache may need to be disabled.
7538          */
7539         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7540 }
7541
7542 static void g4x_init_clock_gating(struct drm_device *dev)
7543 {
7544         struct drm_i915_private *dev_priv = to_i915(dev);
7545         uint32_t dspclk_gate;
7546
7547         I915_WRITE(RENCLK_GATE_D1, 0);
7548         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7549                    GS_UNIT_CLOCK_GATE_DISABLE |
7550                    CL_UNIT_CLOCK_GATE_DISABLE);
7551         I915_WRITE(RAMCLK_GATE_D, 0);
7552         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7553                 OVRUNIT_CLOCK_GATE_DISABLE |
7554                 OVCUNIT_CLOCK_GATE_DISABLE;
7555         if (IS_GM45(dev_priv))
7556                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7557         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7558
7559         /* WaDisableRenderCachePipelinedFlush */
7560         I915_WRITE(CACHE_MODE_0,
7561                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7562
7563         /* WaDisable_RenderCache_OperationalFlush:g4x */
7564         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7565
7566         g4x_disable_trickle_feed(dev);
7567 }
7568
7569 static void crestline_init_clock_gating(struct drm_device *dev)
7570 {
7571         struct drm_i915_private *dev_priv = to_i915(dev);
7572
7573         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7574         I915_WRITE(RENCLK_GATE_D2, 0);
7575         I915_WRITE(DSPCLK_GATE_D, 0);
7576         I915_WRITE(RAMCLK_GATE_D, 0);
7577         I915_WRITE16(DEUC, 0);
7578         I915_WRITE(MI_ARB_STATE,
7579                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7580
7581         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7582         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7583 }
7584
7585 static void broadwater_init_clock_gating(struct drm_device *dev)
7586 {
7587         struct drm_i915_private *dev_priv = to_i915(dev);
7588
7589         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7590                    I965_RCC_CLOCK_GATE_DISABLE |
7591                    I965_RCPB_CLOCK_GATE_DISABLE |
7592                    I965_ISC_CLOCK_GATE_DISABLE |
7593                    I965_FBC_CLOCK_GATE_DISABLE);
7594         I915_WRITE(RENCLK_GATE_D2, 0);
7595         I915_WRITE(MI_ARB_STATE,
7596                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7597
7598         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7599         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7600 }
7601
7602 static void gen3_init_clock_gating(struct drm_device *dev)
7603 {
7604         struct drm_i915_private *dev_priv = to_i915(dev);
7605         u32 dstate = I915_READ(D_STATE);
7606
7607         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7608                 DSTATE_DOT_CLOCK_GATING;
7609         I915_WRITE(D_STATE, dstate);
7610
7611         if (IS_PINEVIEW(dev))
7612                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7613
7614         /* IIR "flip pending" means done if this bit is set */
7615         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7616
7617         /* interrupts should cause a wake up from C3 */
7618         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7619
7620         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7621         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7622
7623         I915_WRITE(MI_ARB_STATE,
7624                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7625 }
7626
7627 static void i85x_init_clock_gating(struct drm_device *dev)
7628 {
7629         struct drm_i915_private *dev_priv = to_i915(dev);
7630
7631         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7632
7633         /* interrupts should cause a wake up from C3 */
7634         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7635                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7636
7637         I915_WRITE(MEM_MODE,
7638                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7639 }
7640
7641 static void i830_init_clock_gating(struct drm_device *dev)
7642 {
7643         struct drm_i915_private *dev_priv = to_i915(dev);
7644
7645         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7646
7647         I915_WRITE(MEM_MODE,
7648                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7649                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7650 }
7651
7652 void intel_init_clock_gating(struct drm_device *dev)
7653 {
7654         struct drm_i915_private *dev_priv = to_i915(dev);
7655
7656         dev_priv->display.init_clock_gating(dev);
7657 }
7658
7659 void intel_suspend_hw(struct drm_device *dev)
7660 {
7661         if (HAS_PCH_LPT(to_i915(dev)))
7662                 lpt_suspend_hw(dev);
7663 }
7664
7665 static void nop_init_clock_gating(struct drm_device *dev)
7666 {
7667         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7668 }
7669
7670 /**
7671  * intel_init_clock_gating_hooks - setup the clock gating hooks
7672  * @dev_priv: device private
7673  *
7674  * Setup the hooks that configure which clocks of a given platform can be
7675  * gated and also apply various GT and display specific workarounds for these
7676  * platforms. Note that some GT specific workarounds are applied separately
7677  * when GPU contexts or batchbuffers start their execution.
7678  */
7679 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7680 {
7681         if (IS_SKYLAKE(dev_priv))
7682                 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7683         else if (IS_KABYLAKE(dev_priv))
7684                 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7685         else if (IS_BROXTON(dev_priv))
7686                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7687         else if (IS_BROADWELL(dev_priv))
7688                 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7689         else if (IS_CHERRYVIEW(dev_priv))
7690                 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7691         else if (IS_HASWELL(dev_priv))
7692                 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7693         else if (IS_IVYBRIDGE(dev_priv))
7694                 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7695         else if (IS_VALLEYVIEW(dev_priv))
7696                 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7697         else if (IS_GEN6(dev_priv))
7698                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7699         else if (IS_GEN5(dev_priv))
7700                 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7701         else if (IS_G4X(dev_priv))
7702                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7703         else if (IS_CRESTLINE(dev_priv))
7704                 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7705         else if (IS_BROADWATER(dev_priv))
7706                 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7707         else if (IS_GEN3(dev_priv))
7708                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7709         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7710                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7711         else if (IS_GEN2(dev_priv))
7712                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7713         else {
7714                 MISSING_CASE(INTEL_DEVID(dev_priv));
7715                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7716         }
7717 }
7718
7719 /* Set up chip specific power management-related functions */
7720 void intel_init_pm(struct drm_device *dev)
7721 {
7722         struct drm_i915_private *dev_priv = to_i915(dev);
7723
7724         intel_fbc_init(dev_priv);
7725
7726         /* For cxsr */
7727         if (IS_PINEVIEW(dev))
7728                 i915_pineview_get_mem_freq(dev);
7729         else if (IS_GEN5(dev_priv))
7730                 i915_ironlake_get_mem_freq(dev);
7731
7732         /* For FIFO watermark updates */
7733         if (INTEL_INFO(dev)->gen >= 9) {
7734                 skl_setup_wm_latency(dev);
7735                 dev_priv->display.update_wm = skl_update_wm;
7736                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7737         } else if (HAS_PCH_SPLIT(dev_priv)) {
7738                 ilk_setup_wm_latency(dev);
7739
7740                 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
7741                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7742                     (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
7743                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7744                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7745                         dev_priv->display.compute_intermediate_wm =
7746                                 ilk_compute_intermediate_wm;
7747                         dev_priv->display.initial_watermarks =
7748                                 ilk_initial_watermarks;
7749                         dev_priv->display.optimize_watermarks =
7750                                 ilk_optimize_watermarks;
7751                 } else {
7752                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7753                                       "Disable CxSR\n");
7754                 }
7755         } else if (IS_CHERRYVIEW(dev_priv)) {
7756                 vlv_setup_wm_latency(dev);
7757                 dev_priv->display.update_wm = vlv_update_wm;
7758         } else if (IS_VALLEYVIEW(dev_priv)) {
7759                 vlv_setup_wm_latency(dev);
7760                 dev_priv->display.update_wm = vlv_update_wm;
7761         } else if (IS_PINEVIEW(dev)) {
7762                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
7763                                             dev_priv->is_ddr3,
7764                                             dev_priv->fsb_freq,
7765                                             dev_priv->mem_freq)) {
7766                         DRM_INFO("failed to find known CxSR latency "
7767                                  "(found ddr%s fsb freq %d, mem freq %d), "
7768                                  "disabling CxSR\n",
7769                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7770                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7771                         /* Disable CxSR and never update its watermark again */
7772                         intel_set_memory_cxsr(dev_priv, false);
7773                         dev_priv->display.update_wm = NULL;
7774                 } else
7775                         dev_priv->display.update_wm = pineview_update_wm;
7776         } else if (IS_G4X(dev_priv)) {
7777                 dev_priv->display.update_wm = g4x_update_wm;
7778         } else if (IS_GEN4(dev_priv)) {
7779                 dev_priv->display.update_wm = i965_update_wm;
7780         } else if (IS_GEN3(dev_priv)) {
7781                 dev_priv->display.update_wm = i9xx_update_wm;
7782                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7783         } else if (IS_GEN2(dev_priv)) {
7784                 if (INTEL_INFO(dev)->num_pipes == 1) {
7785                         dev_priv->display.update_wm = i845_update_wm;
7786                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7787                 } else {
7788                         dev_priv->display.update_wm = i9xx_update_wm;
7789                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7790                 }
7791         } else {
7792                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7793         }
7794 }
7795
7796 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7797 {
7798         uint32_t flags =
7799                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7800
7801         switch (flags) {
7802         case GEN6_PCODE_SUCCESS:
7803                 return 0;
7804         case GEN6_PCODE_UNIMPLEMENTED_CMD:
7805         case GEN6_PCODE_ILLEGAL_CMD:
7806                 return -ENXIO;
7807         case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7808         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7809                 return -EOVERFLOW;
7810         case GEN6_PCODE_TIMEOUT:
7811                 return -ETIMEDOUT;
7812         default:
7813                 MISSING_CASE(flags)
7814                 return 0;
7815         }
7816 }
7817
7818 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7819 {
7820         uint32_t flags =
7821                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7822
7823         switch (flags) {
7824         case GEN6_PCODE_SUCCESS:
7825                 return 0;
7826         case GEN6_PCODE_ILLEGAL_CMD:
7827                 return -ENXIO;
7828         case GEN7_PCODE_TIMEOUT:
7829                 return -ETIMEDOUT;
7830         case GEN7_PCODE_ILLEGAL_DATA:
7831                 return -EINVAL;
7832         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7833                 return -EOVERFLOW;
7834         default:
7835                 MISSING_CASE(flags);
7836                 return 0;
7837         }
7838 }
7839
7840 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7841 {
7842         int status;
7843
7844         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7845
7846         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7847          * use te fw I915_READ variants to reduce the amount of work
7848          * required when reading/writing.
7849          */
7850
7851         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7852                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7853                 return -EAGAIN;
7854         }
7855
7856         I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7857         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7858         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7859
7860         if (intel_wait_for_register_fw(dev_priv,
7861                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7862                                        500)) {
7863                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7864                 return -ETIMEDOUT;
7865         }
7866
7867         *val = I915_READ_FW(GEN6_PCODE_DATA);
7868         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7869
7870         if (INTEL_GEN(dev_priv) > 6)
7871                 status = gen7_check_mailbox_status(dev_priv);
7872         else
7873                 status = gen6_check_mailbox_status(dev_priv);
7874
7875         if (status) {
7876                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7877                                  status);
7878                 return status;
7879         }
7880
7881         return 0;
7882 }
7883
7884 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
7885                             u32 mbox, u32 val)
7886 {
7887         int status;
7888
7889         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7890
7891         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7892          * use te fw I915_READ variants to reduce the amount of work
7893          * required when reading/writing.
7894          */
7895
7896         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7897                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7898                 return -EAGAIN;
7899         }
7900
7901         I915_WRITE_FW(GEN6_PCODE_DATA, val);
7902         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7903
7904         if (intel_wait_for_register_fw(dev_priv,
7905                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7906                                        500)) {
7907                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7908                 return -ETIMEDOUT;
7909         }
7910
7911         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7912
7913         if (INTEL_GEN(dev_priv) > 6)
7914                 status = gen7_check_mailbox_status(dev_priv);
7915         else
7916                 status = gen6_check_mailbox_status(dev_priv);
7917
7918         if (status) {
7919                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7920                                  status);
7921                 return status;
7922         }
7923
7924         return 0;
7925 }
7926
7927 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7928 {
7929         /*
7930          * N = val - 0xb7
7931          * Slow = Fast = GPLL ref * N
7932          */
7933         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7934 }
7935
7936 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7937 {
7938         return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7939 }
7940
7941 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7942 {
7943         /*
7944          * N = val / 2
7945          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7946          */
7947         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7948 }
7949
7950 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7951 {
7952         /* CHV needs even values */
7953         return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7954 }
7955
7956 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7957 {
7958         if (IS_GEN9(dev_priv))
7959                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7960                                          GEN9_FREQ_SCALER);
7961         else if (IS_CHERRYVIEW(dev_priv))
7962                 return chv_gpu_freq(dev_priv, val);
7963         else if (IS_VALLEYVIEW(dev_priv))
7964                 return byt_gpu_freq(dev_priv, val);
7965         else
7966                 return val * GT_FREQUENCY_MULTIPLIER;
7967 }
7968
7969 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7970 {
7971         if (IS_GEN9(dev_priv))
7972                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7973                                          GT_FREQUENCY_MULTIPLIER);
7974         else if (IS_CHERRYVIEW(dev_priv))
7975                 return chv_freq_opcode(dev_priv, val);
7976         else if (IS_VALLEYVIEW(dev_priv))
7977                 return byt_freq_opcode(dev_priv, val);
7978         else
7979                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7980 }
7981
7982 struct request_boost {
7983         struct work_struct work;
7984         struct drm_i915_gem_request *req;
7985 };
7986
7987 static void __intel_rps_boost_work(struct work_struct *work)
7988 {
7989         struct request_boost *boost = container_of(work, struct request_boost, work);
7990         struct drm_i915_gem_request *req = boost->req;
7991
7992         if (!i915_gem_request_completed(req))
7993                 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
7994
7995         i915_gem_request_put(req);
7996         kfree(boost);
7997 }
7998
7999 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
8000 {
8001         struct request_boost *boost;
8002
8003         if (req == NULL || INTEL_GEN(req->i915) < 6)
8004                 return;
8005
8006         if (i915_gem_request_completed(req))
8007                 return;
8008
8009         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
8010         if (boost == NULL)
8011                 return;
8012
8013         boost->req = i915_gem_request_get(req);
8014
8015         INIT_WORK(&boost->work, __intel_rps_boost_work);
8016         queue_work(req->i915->wq, &boost->work);
8017 }
8018
8019 void intel_pm_setup(struct drm_device *dev)
8020 {
8021         struct drm_i915_private *dev_priv = to_i915(dev);
8022
8023         mutex_init(&dev_priv->rps.hw_lock);
8024         spin_lock_init(&dev_priv->rps.client_lock);
8025
8026         INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8027                           __intel_autoenable_gt_powersave);
8028         INIT_LIST_HEAD(&dev_priv->rps.clients);
8029
8030         dev_priv->pm.suspended = false;
8031         atomic_set(&dev_priv->pm.wakeref_count, 0);
8032         atomic_set(&dev_priv->pm.atomic_seq, 0);
8033 }