drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include "i915_drv.h"
  31 #include "intel_drv.h"
  32 #include "../../../platform/x86/intel_ips.h"
  33 #include <linux/module.h>
  34
  35 /**
  36  * DOC: RC6
  37  *
  38  * RC6 is a special power stage which allows the GPU to enter an very
  39  * low-voltage mode when idle, using down to 0V while at this stage.  This
  40  * stage is entered automatically when the GPU is idle when RC6 support is
  41  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  42  *
  43  * There are different RC6 modes available in Intel GPU, which differentiate
  44  * among each other with the latency required to enter and leave RC6 and
  45  * voltage consumed by the GPU in different states.
  46  *
  47  * The combination of the following flags define which states GPU is allowed
  48  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  49  * RC6pp is deepest RC6. Their support by hardware varies according to the
  50  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  51  * which brings the most power savings; deeper states save more power, but
  52  * require higher latency to switch to and wake up.
  53  */
  54 #define INTEL_RC6_ENABLE                        (1<<0)
  55 #define INTEL_RC6p_ENABLE                       (1<<1)
  56 #define INTEL_RC6pp_ENABLE                      (1<<2)
  57
  58 static void gen9_init_clock_gating(struct drm_device *dev)
  59 {
  60         struct drm_i915_private *dev_priv = dev->dev_private;
  61
  62         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
  63         I915_WRITE(CHICKEN_PAR1_1,
  64                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  65
  66         I915_WRITE(GEN8_CONFIG0,
  67                    I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
  68
  69         /* WaEnableChickenDCPR:skl,bxt,kbl */
  70         I915_WRITE(GEN8_CHICKEN_DCPR_1,
  71                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  72
  73         /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
  74         /* WaFbcWakeMemOn:skl,bxt,kbl */
  75         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
  76                    DISP_FBC_WM_DIS |
  77                    DISP_FBC_MEMORY_WAKE);
  78
  79         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
  80         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
  81                    ILK_DPFC_DISABLE_DUMMY0);
  82 }
  83
  84 static void bxt_init_clock_gating(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = to_i915(dev);
  87
  88         gen9_init_clock_gating(dev);
  89
  90         /* WaDisableSDEUnitClockGating:bxt */
  91         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  92                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  93
  94         /*
  95          * FIXME:
  96          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  97          */
  98         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  99                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 100
 101         /*
 102          * Wa: Backlight PWM may stop in the asserted state, causing backlight
 103          * to stay fully on.
 104          */
 105         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
 106                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 107                            PWM1_GATING_DIS | PWM2_GATING_DIS);
 108 }
 109
 110 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 111 {
 112         struct drm_i915_private *dev_priv = to_i915(dev);
 113         u32 tmp;
 114
 115         tmp = I915_READ(CLKCFG);
 116
 117         switch (tmp & CLKCFG_FSB_MASK) {
 118         case CLKCFG_FSB_533:
 119                 dev_priv->fsb_freq = 533; /* 133*4 */
 120                 break;
 121         case CLKCFG_FSB_800:
 122                 dev_priv->fsb_freq = 800; /* 200*4 */
 123                 break;
 124         case CLKCFG_FSB_667:
 125                 dev_priv->fsb_freq =  667; /* 167*4 */
 126                 break;
 127         case CLKCFG_FSB_400:
 128                 dev_priv->fsb_freq = 400; /* 100*4 */
 129                 break;
 130         }
 131
 132         switch (tmp & CLKCFG_MEM_MASK) {
 133         case CLKCFG_MEM_533:
 134                 dev_priv->mem_freq = 533;
 135                 break;
 136         case CLKCFG_MEM_667:
 137                 dev_priv->mem_freq = 667;
 138                 break;
 139         case CLKCFG_MEM_800:
 140                 dev_priv->mem_freq = 800;
 141                 break;
 142         }
 143
 144         /* detect pineview DDR3 setting */
 145         tmp = I915_READ(CSHRDDR3CTL);
 146         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 147 }
 148
 149 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 150 {
 151         struct drm_i915_private *dev_priv = to_i915(dev);
 152         u16 ddrpll, csipll;
 153
 154         ddrpll = I915_READ16(DDRMPLL1);
 155         csipll = I915_READ16(CSIPLL0);
 156
 157         switch (ddrpll & 0xff) {
 158         case 0xc:
 159                 dev_priv->mem_freq = 800;
 160                 break;
 161         case 0x10:
 162                 dev_priv->mem_freq = 1066;
 163                 break;
 164         case 0x14:
 165                 dev_priv->mem_freq = 1333;
 166                 break;
 167         case 0x18:
 168                 dev_priv->mem_freq = 1600;
 169                 break;
 170         default:
 171                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 172                                  ddrpll & 0xff);
 173                 dev_priv->mem_freq = 0;
 174                 break;
 175         }
 176
 177         dev_priv->ips.r_t = dev_priv->mem_freq;
 178
 179         switch (csipll & 0x3ff) {
 180         case 0x00c:
 181                 dev_priv->fsb_freq = 3200;
 182                 break;
 183         case 0x00e:
 184                 dev_priv->fsb_freq = 3733;
 185                 break;
 186         case 0x010:
 187                 dev_priv->fsb_freq = 4266;
 188                 break;
 189         case 0x012:
 190                 dev_priv->fsb_freq = 4800;
 191                 break;
 192         case 0x014:
 193                 dev_priv->fsb_freq = 5333;
 194                 break;
 195         case 0x016:
 196                 dev_priv->fsb_freq = 5866;
 197                 break;
 198         case 0x018:
 199                 dev_priv->fsb_freq = 6400;
 200                 break;
 201         default:
 202                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 203                                  csipll & 0x3ff);
 204                 dev_priv->fsb_freq = 0;
 205                 break;
 206         }
 207
 208         if (dev_priv->fsb_freq == 3200) {
 209                 dev_priv->ips.c_m = 0;
 210         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 211                 dev_priv->ips.c_m = 1;
 212         } else {
 213                 dev_priv->ips.c_m = 2;
 214         }
 215 }
 216
 217 static const struct cxsr_latency cxsr_latency_table[] = {
 218         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 219         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 220         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 221         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 222         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 223
 224         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 225         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 226         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 227         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 228         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 229
 230         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 231         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 232         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 233         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 234         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 235
 236         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 237         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 238         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 239         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 240         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 241
 242         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 243         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 244         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 245         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 246         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 247
 248         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 249         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 250         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 251         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 252         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 253 };
 254
 255 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 256                                                          int is_ddr3,
 257                                                          int fsb,
 258                                                          int mem)
 259 {
 260         const struct cxsr_latency *latency;
 261         int i;
 262
 263         if (fsb == 0 || mem == 0)
 264                 return NULL;
 265
 266         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 267                 latency = &cxsr_latency_table[i];
 268                 if (is_desktop == latency->is_desktop &&
 269                     is_ddr3 == latency->is_ddr3 &&
 270                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 271                         return latency;
 272         }
 273
 274         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 275
 276         return NULL;
 277 }
 278
 279 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 280 {
 281         u32 val;
 282
 283         mutex_lock(&dev_priv->rps.hw_lock);
 284
 285         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 286         if (enable)
 287                 val &= ~FORCE_DDR_HIGH_FREQ;
 288         else
 289                 val |= FORCE_DDR_HIGH_FREQ;
 290         val &= ~FORCE_DDR_LOW_FREQ;
 291         val |= FORCE_DDR_FREQ_REQ_ACK;
 292         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 293
 294         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 295                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 296                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 297
 298         mutex_unlock(&dev_priv->rps.hw_lock);
 299 }
 300
 301 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 302 {
 303         u32 val;
 304
 305         mutex_lock(&dev_priv->rps.hw_lock);
 306
 307         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 308         if (enable)
 309                 val |= DSP_MAXFIFO_PM5_ENABLE;
 310         else
 311                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 312         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 313
 314         mutex_unlock(&dev_priv->rps.hw_lock);
 315 }
 316
 317 #define FW_WM(value, plane) \
 318         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 319
 320 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 321 {
 322         struct drm_device *dev = &dev_priv->drm;
 323         u32 val;
 324
 325         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 326                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 327                 POSTING_READ(FW_BLC_SELF_VLV);
 328                 dev_priv->wm.vlv.cxsr = enable;
 329         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 330                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 331                 POSTING_READ(FW_BLC_SELF);
 332         } else if (IS_PINEVIEW(dev)) {
 333                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 334                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 335                 I915_WRITE(DSPFW3, val);
 336                 POSTING_READ(DSPFW3);
 337         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 338                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 339                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 340                 I915_WRITE(FW_BLC_SELF, val);
 341                 POSTING_READ(FW_BLC_SELF);
 342         } else if (IS_I915GM(dev)) {
 343                 /*
 344                  * FIXME can't find a bit like this for 915G, and
 345                  * and yet it does have the related watermark in
 346                  * FW_BLC_SELF. What's going on?
 347                  */
 348                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 349                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 350                 I915_WRITE(INSTPM, val);
 351                 POSTING_READ(INSTPM);
 352         } else {
 353                 return;
 354         }
 355
 356         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 357                       enable ? "enabled" : "disabled");
 358 }
 359
 360
 361 /*
 362  * Latency for FIFO fetches is dependent on several factors:
 363  *   - memory configuration (speed, channels)
 364  *   - chipset
 365  *   - current MCH state
 366  * It can be fairly high in some situations, so here we assume a fairly
 367  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 368  * set this value too high, the FIFO will fetch frequently to stay full)
 369  * and power consumption (set it too low to save power and we might see
 370  * FIFO underruns and display "flicker").
 371  *
 372  * A value of 5us seems to be a good balance; safe for very low end
 373  * platforms but not overly aggressive on lower latency configs.
 374  */
 375 static const int pessimal_latency_ns = 5000;
 376
 377 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 378         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 379
 380 static int vlv_get_fifo_size(struct drm_device *dev,
 381                               enum pipe pipe, int plane)
 382 {
 383         struct drm_i915_private *dev_priv = to_i915(dev);
 384         int sprite0_start, sprite1_start, size;
 385
 386         switch (pipe) {
 387                 uint32_t dsparb, dsparb2, dsparb3;
 388         case PIPE_A:
 389                 dsparb = I915_READ(DSPARB);
 390                 dsparb2 = I915_READ(DSPARB2);
 391                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 392                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 393                 break;
 394         case PIPE_B:
 395                 dsparb = I915_READ(DSPARB);
 396                 dsparb2 = I915_READ(DSPARB2);
 397                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 398                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 399                 break;
 400         case PIPE_C:
 401                 dsparb2 = I915_READ(DSPARB2);
 402                 dsparb3 = I915_READ(DSPARB3);
 403                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 404                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 405                 break;
 406         default:
 407                 return 0;
 408         }
 409
 410         switch (plane) {
 411         case 0:
 412                 size = sprite0_start;
 413                 break;
 414         case 1:
 415                 size = sprite1_start - sprite0_start;
 416                 break;
 417         case 2:
 418                 size = 512 - 1 - sprite1_start;
 419                 break;
 420         default:
 421                 return 0;
 422         }
 423
 424         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 425                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 426                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 427                       size);
 428
 429         return size;
 430 }
 431
 432 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 433 {
 434         struct drm_i915_private *dev_priv = to_i915(dev);
 435         uint32_t dsparb = I915_READ(DSPARB);
 436         int size;
 437
 438         size = dsparb & 0x7f;
 439         if (plane)
 440                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 441
 442         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 443                       plane ? "B" : "A", size);
 444
 445         return size;
 446 }
 447
 448 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 449 {
 450         struct drm_i915_private *dev_priv = to_i915(dev);
 451         uint32_t dsparb = I915_READ(DSPARB);
 452         int size;
 453
 454         size = dsparb & 0x1ff;
 455         if (plane)
 456                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 457         size >>= 1; /* Convert to cachelines */
 458
 459         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 460                       plane ? "B" : "A", size);
 461
 462         return size;
 463 }
 464
 465 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 466 {
 467         struct drm_i915_private *dev_priv = to_i915(dev);
 468         uint32_t dsparb = I915_READ(DSPARB);
 469         int size;
 470
 471         size = dsparb & 0x7f;
 472         size >>= 2; /* Convert to cachelines */
 473
 474         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 475                       plane ? "B" : "A",
 476                       size);
 477
 478         return size;
 479 }
 480
 481 /* Pineview has different values for various configs */
 482 static const struct intel_watermark_params pineview_display_wm = {
 483         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 484         .max_wm = PINEVIEW_MAX_WM,
 485         .default_wm = PINEVIEW_DFT_WM,
 486         .guard_size = PINEVIEW_GUARD_WM,
 487         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 488 };
 489 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 490         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 491         .max_wm = PINEVIEW_MAX_WM,
 492         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 493         .guard_size = PINEVIEW_GUARD_WM,
 494         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 495 };
 496 static const struct intel_watermark_params pineview_cursor_wm = {
 497         .fifo_size = PINEVIEW_CURSOR_FIFO,
 498         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 499         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 500         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 501         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 502 };
 503 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 504         .fifo_size = PINEVIEW_CURSOR_FIFO,
 505         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 506         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 507         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 508         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 509 };
 510 static const struct intel_watermark_params g4x_wm_info = {
 511         .fifo_size = G4X_FIFO_SIZE,
 512         .max_wm = G4X_MAX_WM,
 513         .default_wm = G4X_MAX_WM,
 514         .guard_size = 2,
 515         .cacheline_size = G4X_FIFO_LINE_SIZE,
 516 };
 517 static const struct intel_watermark_params g4x_cursor_wm_info = {
 518         .fifo_size = I965_CURSOR_FIFO,
 519         .max_wm = I965_CURSOR_MAX_WM,
 520         .default_wm = I965_CURSOR_DFT_WM,
 521         .guard_size = 2,
 522         .cacheline_size = G4X_FIFO_LINE_SIZE,
 523 };
 524 static const struct intel_watermark_params i965_cursor_wm_info = {
 525         .fifo_size = I965_CURSOR_FIFO,
 526         .max_wm = I965_CURSOR_MAX_WM,
 527         .default_wm = I965_CURSOR_DFT_WM,
 528         .guard_size = 2,
 529         .cacheline_size = I915_FIFO_LINE_SIZE,
 530 };
 531 static const struct intel_watermark_params i945_wm_info = {
 532         .fifo_size = I945_FIFO_SIZE,
 533         .max_wm = I915_MAX_WM,
 534         .default_wm = 1,
 535         .guard_size = 2,
 536         .cacheline_size = I915_FIFO_LINE_SIZE,
 537 };
 538 static const struct intel_watermark_params i915_wm_info = {
 539         .fifo_size = I915_FIFO_SIZE,
 540         .max_wm = I915_MAX_WM,
 541         .default_wm = 1,
 542         .guard_size = 2,
 543         .cacheline_size = I915_FIFO_LINE_SIZE,
 544 };
 545 static const struct intel_watermark_params i830_a_wm_info = {
 546         .fifo_size = I855GM_FIFO_SIZE,
 547         .max_wm = I915_MAX_WM,
 548         .default_wm = 1,
 549         .guard_size = 2,
 550         .cacheline_size = I830_FIFO_LINE_SIZE,
 551 };
 552 static const struct intel_watermark_params i830_bc_wm_info = {
 553         .fifo_size = I855GM_FIFO_SIZE,
 554         .max_wm = I915_MAX_WM/2,
 555         .default_wm = 1,
 556         .guard_size = 2,
 557         .cacheline_size = I830_FIFO_LINE_SIZE,
 558 };
 559 static const struct intel_watermark_params i845_wm_info = {
 560         .fifo_size = I830_FIFO_SIZE,
 561         .max_wm = I915_MAX_WM,
 562         .default_wm = 1,
 563         .guard_size = 2,
 564         .cacheline_size = I830_FIFO_LINE_SIZE,
 565 };
 566
 567 /**
 568  * intel_calculate_wm - calculate watermark level
 569  * @clock_in_khz: pixel clock
 570  * @wm: chip FIFO params
 571  * @cpp: bytes per pixel
 572  * @latency_ns: memory latency for the platform
 573  *
 574  * Calculate the watermark level (the level at which the display plane will
 575  * start fetching from memory again).  Each chip has a different display
 576  * FIFO size and allocation, so the caller needs to figure that out and pass
 577  * in the correct intel_watermark_params structure.
 578  *
 579  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 580  * on the pixel size.  When it reaches the watermark level, it'll start
 581  * fetching FIFO line sized based chunks from memory until the FIFO fills
 582  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 583  * will occur, and a display engine hang could result.
 584  */
 585 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 586                                         const struct intel_watermark_params *wm,
 587                                         int fifo_size, int cpp,
 588                                         unsigned long latency_ns)
 589 {
 590         long entries_required, wm_size;
 591
 592         /*
 593          * Note: we need to make sure we don't overflow for various clock &
 594          * latency values.
 595          * clocks go from a few thousand to several hundred thousand.
 596          * latency is usually a few thousand
 597          */
 598         entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
 599                 1000;
 600         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 601
 602         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 603
 604         wm_size = fifo_size - (entries_required + wm->guard_size);
 605
 606         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 607
 608         /* Don't promote wm_size to unsigned... */
 609         if (wm_size > (long)wm->max_wm)
 610                 wm_size = wm->max_wm;
 611         if (wm_size <= 0)
 612                 wm_size = wm->default_wm;
 613
 614         /*
 615          * Bspec seems to indicate that the value shouldn't be lower than
 616          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 617          * Lets go for 8 which is the burst size since certain platforms
 618          * already use a hardcoded 8 (which is what the spec says should be
 619          * done).
 620          */
 621         if (wm_size <= 8)
 622                 wm_size = 8;
 623
 624         return wm_size;
 625 }
 626
 627 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 628 {
 629         struct drm_crtc *crtc, *enabled = NULL;
 630
 631         for_each_crtc(dev, crtc) {
 632                 if (intel_crtc_active(crtc)) {
 633                         if (enabled)
 634                                 return NULL;
 635                         enabled = crtc;
 636                 }
 637         }
 638
 639         return enabled;
 640 }
 641
 642 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 643 {
 644         struct drm_device *dev = unused_crtc->dev;
 645         struct drm_i915_private *dev_priv = to_i915(dev);
 646         struct drm_crtc *crtc;
 647         const struct cxsr_latency *latency;
 648         u32 reg;
 649         unsigned long wm;
 650
 651         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 652                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 653         if (!latency) {
 654                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 655                 intel_set_memory_cxsr(dev_priv, false);
 656                 return;
 657         }
 658
 659         crtc = single_enabled_crtc(dev);
 660         if (crtc) {
 661                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 662                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 663                 int clock = adjusted_mode->crtc_clock;
 664
 665                 /* Display SR */
 666                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 667                                         pineview_display_wm.fifo_size,
 668                                         cpp, latency->display_sr);
 669                 reg = I915_READ(DSPFW1);
 670                 reg &= ~DSPFW_SR_MASK;
 671                 reg |= FW_WM(wm, SR);
 672                 I915_WRITE(DSPFW1, reg);
 673                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 674
 675                 /* cursor SR */
 676                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 677                                         pineview_display_wm.fifo_size,
 678                                         cpp, latency->cursor_sr);
 679                 reg = I915_READ(DSPFW3);
 680                 reg &= ~DSPFW_CURSOR_SR_MASK;
 681                 reg |= FW_WM(wm, CURSOR_SR);
 682                 I915_WRITE(DSPFW3, reg);
 683
 684                 /* Display HPLL off SR */
 685                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 686                                         pineview_display_hplloff_wm.fifo_size,
 687                                         cpp, latency->display_hpll_disable);
 688                 reg = I915_READ(DSPFW3);
 689                 reg &= ~DSPFW_HPLL_SR_MASK;
 690                 reg |= FW_WM(wm, HPLL_SR);
 691                 I915_WRITE(DSPFW3, reg);
 692
 693                 /* cursor HPLL off SR */
 694                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 695                                         pineview_display_hplloff_wm.fifo_size,
 696                                         cpp, latency->cursor_hpll_disable);
 697                 reg = I915_READ(DSPFW3);
 698                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 699                 reg |= FW_WM(wm, HPLL_CURSOR);
 700                 I915_WRITE(DSPFW3, reg);
 701                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 702
 703                 intel_set_memory_cxsr(dev_priv, true);
 704         } else {
 705                 intel_set_memory_cxsr(dev_priv, false);
 706         }
 707 }
 708
 709 static bool g4x_compute_wm0(struct drm_device *dev,
 710                             int plane,
 711                             const struct intel_watermark_params *display,
 712                             int display_latency_ns,
 713                             const struct intel_watermark_params *cursor,
 714                             int cursor_latency_ns,
 715                             int *plane_wm,
 716                             int *cursor_wm)
 717 {
 718         struct drm_crtc *crtc;
 719         const struct drm_display_mode *adjusted_mode;
 720         int htotal, hdisplay, clock, cpp;
 721         int line_time_us, line_count;
 722         int entries, tlb_miss;
 723
 724         crtc = intel_get_crtc_for_plane(dev, plane);
 725         if (!intel_crtc_active(crtc)) {
 726                 *cursor_wm = cursor->guard_size;
 727                 *plane_wm = display->guard_size;
 728                 return false;
 729         }
 730
 731         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 732         clock = adjusted_mode->crtc_clock;
 733         htotal = adjusted_mode->crtc_htotal;
 734         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 735         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 736
 737         /* Use the small buffer method to calculate plane watermark */
 738         entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
 739         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 740         if (tlb_miss > 0)
 741                 entries += tlb_miss;
 742         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 743         *plane_wm = entries + display->guard_size;
 744         if (*plane_wm > (int)display->max_wm)
 745                 *plane_wm = display->max_wm;
 746
 747         /* Use the large buffer method to calculate cursor watermark */
 748         line_time_us = max(htotal * 1000 / clock, 1);
 749         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 750         entries = line_count * crtc->cursor->state->crtc_w * cpp;
 751         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 752         if (tlb_miss > 0)
 753                 entries += tlb_miss;
 754         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 755         *cursor_wm = entries + cursor->guard_size;
 756         if (*cursor_wm > (int)cursor->max_wm)
 757                 *cursor_wm = (int)cursor->max_wm;
 758
 759         return true;
 760 }
 761
 762 /*
 763  * Check the wm result.
 764  *
 765  * If any calculated watermark values is larger than the maximum value that
 766  * can be programmed into the associated watermark register, that watermark
 767  * must be disabled.
 768  */
 769 static bool g4x_check_srwm(struct drm_device *dev,
 770                            int display_wm, int cursor_wm,
 771                            const struct intel_watermark_params *display,
 772                            const struct intel_watermark_params *cursor)
 773 {
 774         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 775                       display_wm, cursor_wm);
 776
 777         if (display_wm > display->max_wm) {
 778                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 779                               display_wm, display->max_wm);
 780                 return false;
 781         }
 782
 783         if (cursor_wm > cursor->max_wm) {
 784                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 785                               cursor_wm, cursor->max_wm);
 786                 return false;
 787         }
 788
 789         if (!(display_wm || cursor_wm)) {
 790                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 791                 return false;
 792         }
 793
 794         return true;
 795 }
 796
 797 static bool g4x_compute_srwm(struct drm_device *dev,
 798                              int plane,
 799                              int latency_ns,
 800                              const struct intel_watermark_params *display,
 801                              const struct intel_watermark_params *cursor,
 802                              int *display_wm, int *cursor_wm)
 803 {
 804         struct drm_crtc *crtc;
 805         const struct drm_display_mode *adjusted_mode;
 806         int hdisplay, htotal, cpp, clock;
 807         unsigned long line_time_us;
 808         int line_count, line_size;
 809         int small, large;
 810         int entries;
 811
 812         if (!latency_ns) {
 813                 *display_wm = *cursor_wm = 0;
 814                 return false;
 815         }
 816
 817         crtc = intel_get_crtc_for_plane(dev, plane);
 818         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 819         clock = adjusted_mode->crtc_clock;
 820         htotal = adjusted_mode->crtc_htotal;
 821         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 822         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 823
 824         line_time_us = max(htotal * 1000 / clock, 1);
 825         line_count = (latency_ns / line_time_us + 1000) / 1000;
 826         line_size = hdisplay * cpp;
 827
 828         /* Use the minimum of the small and large buffer method for primary */
 829         small = ((clock * cpp / 1000) * latency_ns) / 1000;
 830         large = line_count * line_size;
 831
 832         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 833         *display_wm = entries + display->guard_size;
 834
 835         /* calculate the self-refresh watermark for display cursor */
 836         entries = line_count * cpp * crtc->cursor->state->crtc_w;
 837         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 838         *cursor_wm = entries + cursor->guard_size;
 839
 840         return g4x_check_srwm(dev,
 841                               *display_wm, *cursor_wm,
 842                               display, cursor);
 843 }
 844
 845 #define FW_WM_VLV(value, plane) \
 846         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 847
 848 static void vlv_write_wm_values(struct intel_crtc *crtc,
 849                                 const struct vlv_wm_values *wm)
 850 {
 851         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 852         enum pipe pipe = crtc->pipe;
 853
 854         I915_WRITE(VLV_DDL(pipe),
 855                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 856                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 857                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 858                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 859
 860         I915_WRITE(DSPFW1,
 861                    FW_WM(wm->sr.plane, SR) |
 862                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 863                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 864                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 865         I915_WRITE(DSPFW2,
 866                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 867                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 868                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 869         I915_WRITE(DSPFW3,
 870                    FW_WM(wm->sr.cursor, CURSOR_SR));
 871
 872         if (IS_CHERRYVIEW(dev_priv)) {
 873                 I915_WRITE(DSPFW7_CHV,
 874                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 875                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 876                 I915_WRITE(DSPFW8_CHV,
 877                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 878                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 879                 I915_WRITE(DSPFW9_CHV,
 880                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 881                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 882                 I915_WRITE(DSPHOWM,
 883                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 884                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 885                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 886                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 887                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 888                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 889                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 890                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 891                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 892                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 893         } else {
 894                 I915_WRITE(DSPFW7,
 895                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 896                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 897                 I915_WRITE(DSPHOWM,
 898                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 899                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 900                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 901                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 902                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 903                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 904                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 905         }
 906
 907         /* zero (unused) WM1 watermarks */
 908         I915_WRITE(DSPFW4, 0);
 909         I915_WRITE(DSPFW5, 0);
 910         I915_WRITE(DSPFW6, 0);
 911         I915_WRITE(DSPHOWM1, 0);
 912
 913         POSTING_READ(DSPFW1);
 914 }
 915
 916 #undef FW_WM_VLV
 917
 918 enum vlv_wm_level {
 919         VLV_WM_LEVEL_PM2,
 920         VLV_WM_LEVEL_PM5,
 921         VLV_WM_LEVEL_DDR_DVFS,
 922 };
 923
 924 /* latency must be in 0.1us units. */
 925 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 926                                    unsigned int pipe_htotal,
 927                                    unsigned int horiz_pixels,
 928                                    unsigned int cpp,
 929                                    unsigned int latency)
 930 {
 931         unsigned int ret;
 932
 933         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 934         ret = (ret + 1) * horiz_pixels * cpp;
 935         ret = DIV_ROUND_UP(ret, 64);
 936
 937         return ret;
 938 }
 939
 940 static void vlv_setup_wm_latency(struct drm_device *dev)
 941 {
 942         struct drm_i915_private *dev_priv = to_i915(dev);
 943
 944         /* all latencies in usec */
 945         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 946
 947         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 948
 949         if (IS_CHERRYVIEW(dev_priv)) {
 950                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 951                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 952
 953                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 954         }
 955 }
 956
 957 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 958                                      struct intel_crtc *crtc,
 959                                      const struct intel_plane_state *state,
 960                                      int level)
 961 {
 962         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 963         int clock, htotal, cpp, width, wm;
 964
 965         if (dev_priv->wm.pri_latency[level] == 0)
 966                 return USHRT_MAX;
 967
 968         if (!state->base.visible)
 969                 return 0;
 970
 971         cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 972         clock = crtc->config->base.adjusted_mode.crtc_clock;
 973         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 974         width = crtc->config->pipe_src_w;
 975         if (WARN_ON(htotal == 0))
 976                 htotal = 1;
 977
 978         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 979                 /*
 980                  * FIXME the formula gives values that are
 981                  * too big for the cursor FIFO, and hence we
 982                  * would never be able to use cursors. For
 983                  * now just hardcode the watermark.
 984                  */
 985                 wm = 63;
 986         } else {
 987                 wm = vlv_wm_method2(clock, htotal, width, cpp,
 988                                     dev_priv->wm.pri_latency[level] * 10);
 989         }
 990
 991         return min_t(int, wm, USHRT_MAX);
 992 }
 993
 994 static void vlv_compute_fifo(struct intel_crtc *crtc)
 995 {
 996         struct drm_device *dev = crtc->base.dev;
 997         struct vlv_wm_state *wm_state = &crtc->wm_state;
 998         struct intel_plane *plane;
 999         unsigned int total_rate = 0;
1000         const int fifo_size = 512 - 1;
1001         int fifo_extra, fifo_left = fifo_size;
1002
1003         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1004                 struct intel_plane_state *state =
1005                         to_intel_plane_state(plane->base.state);
1006
1007                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1008                         continue;
1009
1010                 if (state->base.visible) {
1011                         wm_state->num_active_planes++;
1012                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1013                 }
1014         }
1015
1016         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1017                 struct intel_plane_state *state =
1018                         to_intel_plane_state(plane->base.state);
1019                 unsigned int rate;
1020
1021                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1022                         plane->wm.fifo_size = 63;
1023                         continue;
1024                 }
1025
1026                 if (!state->base.visible) {
1027                         plane->wm.fifo_size = 0;
1028                         continue;
1029                 }
1030
1031                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1032                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1033                 fifo_left -= plane->wm.fifo_size;
1034         }
1035
1036         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1037
1038         /* spread the remainder evenly */
1039         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1040                 int plane_extra;
1041
1042                 if (fifo_left == 0)
1043                         break;
1044
1045                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1046                         continue;
1047
1048                 /* give it all to the first plane if none are active */
1049                 if (plane->wm.fifo_size == 0 &&
1050                     wm_state->num_active_planes)
1051                         continue;
1052
1053                 plane_extra = min(fifo_extra, fifo_left);
1054                 plane->wm.fifo_size += plane_extra;
1055                 fifo_left -= plane_extra;
1056         }
1057
1058         WARN_ON(fifo_left != 0);
1059 }
1060
1061 static void vlv_invert_wms(struct intel_crtc *crtc)
1062 {
1063         struct vlv_wm_state *wm_state = &crtc->wm_state;
1064         int level;
1065
1066         for (level = 0; level < wm_state->num_levels; level++) {
1067                 struct drm_device *dev = crtc->base.dev;
1068                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1069                 struct intel_plane *plane;
1070
1071                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1072                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1073
1074                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1075                         switch (plane->base.type) {
1076                                 int sprite;
1077                         case DRM_PLANE_TYPE_CURSOR:
1078                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1079                                         wm_state->wm[level].cursor;
1080                                 break;
1081                         case DRM_PLANE_TYPE_PRIMARY:
1082                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1083                                         wm_state->wm[level].primary;
1084                                 break;
1085                         case DRM_PLANE_TYPE_OVERLAY:
1086                                 sprite = plane->plane;
1087                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1088                                         wm_state->wm[level].sprite[sprite];
1089                                 break;
1090                         }
1091                 }
1092         }
1093 }
1094
1095 static void vlv_compute_wm(struct intel_crtc *crtc)
1096 {
1097         struct drm_device *dev = crtc->base.dev;
1098         struct vlv_wm_state *wm_state = &crtc->wm_state;
1099         struct intel_plane *plane;
1100         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1101         int level;
1102
1103         memset(wm_state, 0, sizeof(*wm_state));
1104
1105         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1106         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1107
1108         wm_state->num_active_planes = 0;
1109
1110         vlv_compute_fifo(crtc);
1111
1112         if (wm_state->num_active_planes != 1)
1113                 wm_state->cxsr = false;
1114
1115         if (wm_state->cxsr) {
1116                 for (level = 0; level < wm_state->num_levels; level++) {
1117                         wm_state->sr[level].plane = sr_fifo_size;
1118                         wm_state->sr[level].cursor = 63;
1119                 }
1120         }
1121
1122         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1123                 struct intel_plane_state *state =
1124                         to_intel_plane_state(plane->base.state);
1125
1126                 if (!state->base.visible)
1127                         continue;
1128
1129                 /* normal watermarks */
1130                 for (level = 0; level < wm_state->num_levels; level++) {
1131                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1132                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1133
1134                         /* hack */
1135                         if (WARN_ON(level == 0 && wm > max_wm))
1136                                 wm = max_wm;
1137
1138                         if (wm > plane->wm.fifo_size)
1139                                 break;
1140
1141                         switch (plane->base.type) {
1142                                 int sprite;
1143                         case DRM_PLANE_TYPE_CURSOR:
1144                                 wm_state->wm[level].cursor = wm;
1145                                 break;
1146                         case DRM_PLANE_TYPE_PRIMARY:
1147                                 wm_state->wm[level].primary = wm;
1148                                 break;
1149                         case DRM_PLANE_TYPE_OVERLAY:
1150                                 sprite = plane->plane;
1151                                 wm_state->wm[level].sprite[sprite] = wm;
1152                                 break;
1153                         }
1154                 }
1155
1156                 wm_state->num_levels = level;
1157
1158                 if (!wm_state->cxsr)
1159                         continue;
1160
1161                 /* maxfifo watermarks */
1162                 switch (plane->base.type) {
1163                         int sprite, level;
1164                 case DRM_PLANE_TYPE_CURSOR:
1165                         for (level = 0; level < wm_state->num_levels; level++)
1166                                 wm_state->sr[level].cursor =
1167                                         wm_state->wm[level].cursor;
1168                         break;
1169                 case DRM_PLANE_TYPE_PRIMARY:
1170                         for (level = 0; level < wm_state->num_levels; level++)
1171                                 wm_state->sr[level].plane =
1172                                         min(wm_state->sr[level].plane,
1173                                             wm_state->wm[level].primary);
1174                         break;
1175                 case DRM_PLANE_TYPE_OVERLAY:
1176                         sprite = plane->plane;
1177                         for (level = 0; level < wm_state->num_levels; level++)
1178                                 wm_state->sr[level].plane =
1179                                         min(wm_state->sr[level].plane,
1180                                             wm_state->wm[level].sprite[sprite]);
1181                         break;
1182                 }
1183         }
1184
1185         /* clear any (partially) filled invalid levels */
1186         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1187                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1188                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1189         }
1190
1191         vlv_invert_wms(crtc);
1192 }
1193
1194 #define VLV_FIFO(plane, value) \
1195         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1196
1197 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1198 {
1199         struct drm_device *dev = crtc->base.dev;
1200         struct drm_i915_private *dev_priv = to_i915(dev);
1201         struct intel_plane *plane;
1202         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1203
1204         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1205                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1206                         WARN_ON(plane->wm.fifo_size != 63);
1207                         continue;
1208                 }
1209
1210                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1211                         sprite0_start = plane->wm.fifo_size;
1212                 else if (plane->plane == 0)
1213                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1214                 else
1215                         fifo_size = sprite1_start + plane->wm.fifo_size;
1216         }
1217
1218         WARN_ON(fifo_size != 512 - 1);
1219
1220         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1221                       pipe_name(crtc->pipe), sprite0_start,
1222                       sprite1_start, fifo_size);
1223
1224         switch (crtc->pipe) {
1225                 uint32_t dsparb, dsparb2, dsparb3;
1226         case PIPE_A:
1227                 dsparb = I915_READ(DSPARB);
1228                 dsparb2 = I915_READ(DSPARB2);
1229
1230                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1231                             VLV_FIFO(SPRITEB, 0xff));
1232                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1233                            VLV_FIFO(SPRITEB, sprite1_start));
1234
1235                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1236                              VLV_FIFO(SPRITEB_HI, 0x1));
1237                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1238                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1239
1240                 I915_WRITE(DSPARB, dsparb);
1241                 I915_WRITE(DSPARB2, dsparb2);
1242                 break;
1243         case PIPE_B:
1244                 dsparb = I915_READ(DSPARB);
1245                 dsparb2 = I915_READ(DSPARB2);
1246
1247                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1248                             VLV_FIFO(SPRITED, 0xff));
1249                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1250                            VLV_FIFO(SPRITED, sprite1_start));
1251
1252                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1253                              VLV_FIFO(SPRITED_HI, 0xff));
1254                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1255                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1256
1257                 I915_WRITE(DSPARB, dsparb);
1258                 I915_WRITE(DSPARB2, dsparb2);
1259                 break;
1260         case PIPE_C:
1261                 dsparb3 = I915_READ(DSPARB3);
1262                 dsparb2 = I915_READ(DSPARB2);
1263
1264                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1265                              VLV_FIFO(SPRITEF, 0xff));
1266                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1267                             VLV_FIFO(SPRITEF, sprite1_start));
1268
1269                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1270                              VLV_FIFO(SPRITEF_HI, 0xff));
1271                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1272                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1273
1274                 I915_WRITE(DSPARB3, dsparb3);
1275                 I915_WRITE(DSPARB2, dsparb2);
1276                 break;
1277         default:
1278                 break;
1279         }
1280 }
1281
1282 #undef VLV_FIFO
1283
1284 static void vlv_merge_wm(struct drm_device *dev,
1285                          struct vlv_wm_values *wm)
1286 {
1287         struct intel_crtc *crtc;
1288         int num_active_crtcs = 0;
1289
1290         wm->level = to_i915(dev)->wm.max_level;
1291         wm->cxsr = true;
1292
1293         for_each_intel_crtc(dev, crtc) {
1294                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1295
1296                 if (!crtc->active)
1297                         continue;
1298
1299                 if (!wm_state->cxsr)
1300                         wm->cxsr = false;
1301
1302                 num_active_crtcs++;
1303                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1304         }
1305
1306         if (num_active_crtcs != 1)
1307                 wm->cxsr = false;
1308
1309         if (num_active_crtcs > 1)
1310                 wm->level = VLV_WM_LEVEL_PM2;
1311
1312         for_each_intel_crtc(dev, crtc) {
1313                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1314                 enum pipe pipe = crtc->pipe;
1315
1316                 if (!crtc->active)
1317                         continue;
1318
1319                 wm->pipe[pipe] = wm_state->wm[wm->level];
1320                 if (wm->cxsr)
1321                         wm->sr = wm_state->sr[wm->level];
1322
1323                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1324                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1325                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1326                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1327         }
1328 }
1329
1330 static void vlv_update_wm(struct drm_crtc *crtc)
1331 {
1332         struct drm_device *dev = crtc->dev;
1333         struct drm_i915_private *dev_priv = to_i915(dev);
1334         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1335         enum pipe pipe = intel_crtc->pipe;
1336         struct vlv_wm_values wm = {};
1337
1338         vlv_compute_wm(intel_crtc);
1339         vlv_merge_wm(dev, &wm);
1340
1341         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1342                 /* FIXME should be part of crtc atomic commit */
1343                 vlv_pipe_set_fifo_size(intel_crtc);
1344                 return;
1345         }
1346
1347         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1348             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1349                 chv_set_memory_dvfs(dev_priv, false);
1350
1351         if (wm.level < VLV_WM_LEVEL_PM5 &&
1352             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1353                 chv_set_memory_pm5(dev_priv, false);
1354
1355         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1356                 intel_set_memory_cxsr(dev_priv, false);
1357
1358         /* FIXME should be part of crtc atomic commit */
1359         vlv_pipe_set_fifo_size(intel_crtc);
1360
1361         vlv_write_wm_values(intel_crtc, &wm);
1362
1363         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1364                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1365                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1366                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1367                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1368
1369         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1370                 intel_set_memory_cxsr(dev_priv, true);
1371
1372         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1373             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1374                 chv_set_memory_pm5(dev_priv, true);
1375
1376         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1377             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1378                 chv_set_memory_dvfs(dev_priv, true);
1379
1380         dev_priv->wm.vlv = wm;
1381 }
1382
1383 #define single_plane_enabled(mask) is_power_of_2(mask)
1384
1385 static void g4x_update_wm(struct drm_crtc *crtc)
1386 {
1387         struct drm_device *dev = crtc->dev;
1388         static const int sr_latency_ns = 12000;
1389         struct drm_i915_private *dev_priv = to_i915(dev);
1390         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1391         int plane_sr, cursor_sr;
1392         unsigned int enabled = 0;
1393         bool cxsr_enabled;
1394
1395         if (g4x_compute_wm0(dev, PIPE_A,
1396                             &g4x_wm_info, pessimal_latency_ns,
1397                             &g4x_cursor_wm_info, pessimal_latency_ns,
1398                             &planea_wm, &cursora_wm))
1399                 enabled |= 1 << PIPE_A;
1400
1401         if (g4x_compute_wm0(dev, PIPE_B,
1402                             &g4x_wm_info, pessimal_latency_ns,
1403                             &g4x_cursor_wm_info, pessimal_latency_ns,
1404                             &planeb_wm, &cursorb_wm))
1405                 enabled |= 1 << PIPE_B;
1406
1407         if (single_plane_enabled(enabled) &&
1408             g4x_compute_srwm(dev, ffs(enabled) - 1,
1409                              sr_latency_ns,
1410                              &g4x_wm_info,
1411                              &g4x_cursor_wm_info,
1412                              &plane_sr, &cursor_sr)) {
1413                 cxsr_enabled = true;
1414         } else {
1415                 cxsr_enabled = false;
1416                 intel_set_memory_cxsr(dev_priv, false);
1417                 plane_sr = cursor_sr = 0;
1418         }
1419
1420         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1421                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1422                       planea_wm, cursora_wm,
1423                       planeb_wm, cursorb_wm,
1424                       plane_sr, cursor_sr);
1425
1426         I915_WRITE(DSPFW1,
1427                    FW_WM(plane_sr, SR) |
1428                    FW_WM(cursorb_wm, CURSORB) |
1429                    FW_WM(planeb_wm, PLANEB) |
1430                    FW_WM(planea_wm, PLANEA));
1431         I915_WRITE(DSPFW2,
1432                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1433                    FW_WM(cursora_wm, CURSORA));
1434         /* HPLL off in SR has some issues on G4x... disable it */
1435         I915_WRITE(DSPFW3,
1436                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1437                    FW_WM(cursor_sr, CURSOR_SR));
1438
1439         if (cxsr_enabled)
1440                 intel_set_memory_cxsr(dev_priv, true);
1441 }
1442
1443 static void i965_update_wm(struct drm_crtc *unused_crtc)
1444 {
1445         struct drm_device *dev = unused_crtc->dev;
1446         struct drm_i915_private *dev_priv = to_i915(dev);
1447         struct drm_crtc *crtc;
1448         int srwm = 1;
1449         int cursor_sr = 16;
1450         bool cxsr_enabled;
1451
1452         /* Calc sr entries for one plane configs */
1453         crtc = single_enabled_crtc(dev);
1454         if (crtc) {
1455                 /* self-refresh has much higher latency */
1456                 static const int sr_latency_ns = 12000;
1457                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1458                 int clock = adjusted_mode->crtc_clock;
1459                 int htotal = adjusted_mode->crtc_htotal;
1460                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1461                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1462                 unsigned long line_time_us;
1463                 int entries;
1464
1465                 line_time_us = max(htotal * 1000 / clock, 1);
1466
1467                 /* Use ns/us then divide to preserve precision */
1468                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1469                         cpp * hdisplay;
1470                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1471                 srwm = I965_FIFO_SIZE - entries;
1472                 if (srwm < 0)
1473                         srwm = 1;
1474                 srwm &= 0x1ff;
1475                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1476                               entries, srwm);
1477
1478                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1479                         cpp * crtc->cursor->state->crtc_w;
1480                 entries = DIV_ROUND_UP(entries,
1481                                           i965_cursor_wm_info.cacheline_size);
1482                 cursor_sr = i965_cursor_wm_info.fifo_size -
1483                         (entries + i965_cursor_wm_info.guard_size);
1484
1485                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1486                         cursor_sr = i965_cursor_wm_info.max_wm;
1487
1488                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1489                               "cursor %d\n", srwm, cursor_sr);
1490
1491                 cxsr_enabled = true;
1492         } else {
1493                 cxsr_enabled = false;
1494                 /* Turn off self refresh if both pipes are enabled */
1495                 intel_set_memory_cxsr(dev_priv, false);
1496         }
1497
1498         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1499                       srwm);
1500
1501         /* 965 has limitations... */
1502         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1503                    FW_WM(8, CURSORB) |
1504                    FW_WM(8, PLANEB) |
1505                    FW_WM(8, PLANEA));
1506         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1507                    FW_WM(8, PLANEC_OLD));
1508         /* update cursor SR watermark */
1509         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1510
1511         if (cxsr_enabled)
1512                 intel_set_memory_cxsr(dev_priv, true);
1513 }
1514
1515 #undef FW_WM
1516
1517 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1518 {
1519         struct drm_device *dev = unused_crtc->dev;
1520         struct drm_i915_private *dev_priv = to_i915(dev);
1521         const struct intel_watermark_params *wm_info;
1522         uint32_t fwater_lo;
1523         uint32_t fwater_hi;
1524         int cwm, srwm = 1;
1525         int fifo_size;
1526         int planea_wm, planeb_wm;
1527         struct drm_crtc *crtc, *enabled = NULL;
1528
1529         if (IS_I945GM(dev))
1530                 wm_info = &i945_wm_info;
1531         else if (!IS_GEN2(dev))
1532                 wm_info = &i915_wm_info;
1533         else
1534                 wm_info = &i830_a_wm_info;
1535
1536         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1537         crtc = intel_get_crtc_for_plane(dev, 0);
1538         if (intel_crtc_active(crtc)) {
1539                 const struct drm_display_mode *adjusted_mode;
1540                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1541                 if (IS_GEN2(dev))
1542                         cpp = 4;
1543
1544                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1545                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1546                                                wm_info, fifo_size, cpp,
1547                                                pessimal_latency_ns);
1548                 enabled = crtc;
1549         } else {
1550                 planea_wm = fifo_size - wm_info->guard_size;
1551                 if (planea_wm > (long)wm_info->max_wm)
1552                         planea_wm = wm_info->max_wm;
1553         }
1554
1555         if (IS_GEN2(dev))
1556                 wm_info = &i830_bc_wm_info;
1557
1558         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1559         crtc = intel_get_crtc_for_plane(dev, 1);
1560         if (intel_crtc_active(crtc)) {
1561                 const struct drm_display_mode *adjusted_mode;
1562                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1563                 if (IS_GEN2(dev))
1564                         cpp = 4;
1565
1566                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1567                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1568                                                wm_info, fifo_size, cpp,
1569                                                pessimal_latency_ns);
1570                 if (enabled == NULL)
1571                         enabled = crtc;
1572                 else
1573                         enabled = NULL;
1574         } else {
1575                 planeb_wm = fifo_size - wm_info->guard_size;
1576                 if (planeb_wm > (long)wm_info->max_wm)
1577                         planeb_wm = wm_info->max_wm;
1578         }
1579
1580         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1581
1582         if (IS_I915GM(dev) && enabled) {
1583                 struct drm_i915_gem_object *obj;
1584
1585                 obj = intel_fb_obj(enabled->primary->state->fb);
1586
1587                 /* self-refresh seems busted with untiled */
1588                 if (!i915_gem_object_is_tiled(obj))
1589                         enabled = NULL;
1590         }
1591
1592         /*
1593          * Overlay gets an aggressive default since video jitter is bad.
1594          */
1595         cwm = 2;
1596
1597         /* Play safe and disable self-refresh before adjusting watermarks. */
1598         intel_set_memory_cxsr(dev_priv, false);
1599
1600         /* Calc sr entries for one plane configs */
1601         if (HAS_FW_BLC(dev) && enabled) {
1602                 /* self-refresh has much higher latency */
1603                 static const int sr_latency_ns = 6000;
1604                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1605                 int clock = adjusted_mode->crtc_clock;
1606                 int htotal = adjusted_mode->crtc_htotal;
1607                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1608                 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1609                 unsigned long line_time_us;
1610                 int entries;
1611
1612                 if (IS_I915GM(dev) || IS_I945GM(dev))
1613                         cpp = 4;
1614
1615                 line_time_us = max(htotal * 1000 / clock, 1);
1616
1617                 /* Use ns/us then divide to preserve precision */
1618                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1619                         cpp * hdisplay;
1620                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1621                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1622                 srwm = wm_info->fifo_size - entries;
1623                 if (srwm < 0)
1624                         srwm = 1;
1625
1626                 if (IS_I945G(dev) || IS_I945GM(dev))
1627                         I915_WRITE(FW_BLC_SELF,
1628                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1629                 else
1630                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1631         }
1632
1633         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1634                       planea_wm, planeb_wm, cwm, srwm);
1635
1636         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1637         fwater_hi = (cwm & 0x1f);
1638
1639         /* Set request length to 8 cachelines per fetch */
1640         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1641         fwater_hi = fwater_hi | (1 << 8);
1642
1643         I915_WRITE(FW_BLC, fwater_lo);
1644         I915_WRITE(FW_BLC2, fwater_hi);
1645
1646         if (enabled)
1647                 intel_set_memory_cxsr(dev_priv, true);
1648 }
1649
1650 static void i845_update_wm(struct drm_crtc *unused_crtc)
1651 {
1652         struct drm_device *dev = unused_crtc->dev;
1653         struct drm_i915_private *dev_priv = to_i915(dev);
1654         struct drm_crtc *crtc;
1655         const struct drm_display_mode *adjusted_mode;
1656         uint32_t fwater_lo;
1657         int planea_wm;
1658
1659         crtc = single_enabled_crtc(dev);
1660         if (crtc == NULL)
1661                 return;
1662
1663         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1664         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1665                                        &i845_wm_info,
1666                                        dev_priv->display.get_fifo_size(dev, 0),
1667                                        4, pessimal_latency_ns);
1668         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1669         fwater_lo |= (3<<8) | planea_wm;
1670
1671         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1672
1673         I915_WRITE(FW_BLC, fwater_lo);
1674 }
1675
1676 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1677 {
1678         uint32_t pixel_rate;
1679
1680         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1681
1682         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1683          * adjust the pixel_rate here. */
1684
1685         if (pipe_config->pch_pfit.enabled) {
1686                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1687                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1688
1689                 pipe_w = pipe_config->pipe_src_w;
1690                 pipe_h = pipe_config->pipe_src_h;
1691
1692                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1693                 pfit_h = pfit_size & 0xFFFF;
1694                 if (pipe_w < pfit_w)
1695                         pipe_w = pfit_w;
1696                 if (pipe_h < pfit_h)
1697                         pipe_h = pfit_h;
1698
1699                 if (WARN_ON(!pfit_w || !pfit_h))
1700                         return pixel_rate;
1701
1702                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1703                                      pfit_w * pfit_h);
1704         }
1705
1706         return pixel_rate;
1707 }
1708
1709 /* latency must be in 0.1us units. */
1710 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1711 {
1712         uint64_t ret;
1713
1714         if (WARN(latency == 0, "Latency value missing\n"))
1715                 return UINT_MAX;
1716
1717         ret = (uint64_t) pixel_rate * cpp * latency;
1718         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1719
1720         return ret;
1721 }
1722
1723 /* latency must be in 0.1us units. */
1724 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1725                                uint32_t horiz_pixels, uint8_t cpp,
1726                                uint32_t latency)
1727 {
1728         uint32_t ret;
1729
1730         if (WARN(latency == 0, "Latency value missing\n"))
1731                 return UINT_MAX;
1732         if (WARN_ON(!pipe_htotal))
1733                 return UINT_MAX;
1734
1735         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1736         ret = (ret + 1) * horiz_pixels * cpp;
1737         ret = DIV_ROUND_UP(ret, 64) + 2;
1738         return ret;
1739 }
1740
1741 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1742                            uint8_t cpp)
1743 {
1744         /*
1745          * Neither of these should be possible since this function shouldn't be
1746          * called if the CRTC is off or the plane is invisible.  But let's be
1747          * extra paranoid to avoid a potential divide-by-zero if we screw up
1748          * elsewhere in the driver.
1749          */
1750         if (WARN_ON(!cpp))
1751                 return 0;
1752         if (WARN_ON(!horiz_pixels))
1753                 return 0;
1754
1755         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1756 }
1757
1758 struct ilk_wm_maximums {
1759         uint16_t pri;
1760         uint16_t spr;
1761         uint16_t cur;
1762         uint16_t fbc;
1763 };
1764
1765 /*
1766  * For both WM_PIPE and WM_LP.
1767  * mem_value must be in 0.1us units.
1768  */
1769 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1770                                    const struct intel_plane_state *pstate,
1771                                    uint32_t mem_value,
1772                                    bool is_lp)
1773 {
1774         int cpp = pstate->base.fb ?
1775                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1776         uint32_t method1, method2;
1777
1778         if (!cstate->base.active || !pstate->base.visible)
1779                 return 0;
1780
1781         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1782
1783         if (!is_lp)
1784                 return method1;
1785
1786         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1787                                  cstate->base.adjusted_mode.crtc_htotal,
1788                                  drm_rect_width(&pstate->base.dst),
1789                                  cpp, mem_value);
1790
1791         return min(method1, method2);
1792 }
1793
1794 /*
1795  * For both WM_PIPE and WM_LP.
1796  * mem_value must be in 0.1us units.
1797  */
1798 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1799                                    const struct intel_plane_state *pstate,
1800                                    uint32_t mem_value)
1801 {
1802         int cpp = pstate->base.fb ?
1803                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1804         uint32_t method1, method2;
1805
1806         if (!cstate->base.active || !pstate->base.visible)
1807                 return 0;
1808
1809         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1810         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1811                                  cstate->base.adjusted_mode.crtc_htotal,
1812                                  drm_rect_width(&pstate->base.dst),
1813                                  cpp, mem_value);
1814         return min(method1, method2);
1815 }
1816
1817 /*
1818  * For both WM_PIPE and WM_LP.
1819  * mem_value must be in 0.1us units.
1820  */
1821 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1822                                    const struct intel_plane_state *pstate,
1823                                    uint32_t mem_value)
1824 {
1825         /*
1826          * We treat the cursor plane as always-on for the purposes of watermark
1827          * calculation.  Until we have two-stage watermark programming merged,
1828          * this is necessary to avoid flickering.
1829          */
1830         int cpp = 4;
1831         int width = pstate->base.visible ? pstate->base.crtc_w : 64;
1832
1833         if (!cstate->base.active)
1834                 return 0;
1835
1836         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1837                               cstate->base.adjusted_mode.crtc_htotal,
1838                               width, cpp, mem_value);
1839 }
1840
1841 /* Only for WM_LP. */
1842 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1843                                    const struct intel_plane_state *pstate,
1844                                    uint32_t pri_val)
1845 {
1846         int cpp = pstate->base.fb ?
1847                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1848
1849         if (!cstate->base.active || !pstate->base.visible)
1850                 return 0;
1851
1852         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
1853 }
1854
1855 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1856 {
1857         if (INTEL_INFO(dev)->gen >= 8)
1858                 return 3072;
1859         else if (INTEL_INFO(dev)->gen >= 7)
1860                 return 768;
1861         else
1862                 return 512;
1863 }
1864
1865 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1866                                          int level, bool is_sprite)
1867 {
1868         if (INTEL_INFO(dev)->gen >= 8)
1869                 /* BDW primary/sprite plane watermarks */
1870                 return level == 0 ? 255 : 2047;
1871         else if (INTEL_INFO(dev)->gen >= 7)
1872                 /* IVB/HSW primary/sprite plane watermarks */
1873                 return level == 0 ? 127 : 1023;
1874         else if (!is_sprite)
1875                 /* ILK/SNB primary plane watermarks */
1876                 return level == 0 ? 127 : 511;
1877         else
1878                 /* ILK/SNB sprite plane watermarks */
1879                 return level == 0 ? 63 : 255;
1880 }
1881
1882 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1883                                           int level)
1884 {
1885         if (INTEL_INFO(dev)->gen >= 7)
1886                 return level == 0 ? 63 : 255;
1887         else
1888                 return level == 0 ? 31 : 63;
1889 }
1890
1891 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1892 {
1893         if (INTEL_INFO(dev)->gen >= 8)
1894                 return 31;
1895         else
1896                 return 15;
1897 }
1898
1899 /* Calculate the maximum primary/sprite plane watermark */
1900 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1901                                      int level,
1902                                      const struct intel_wm_config *config,
1903                                      enum intel_ddb_partitioning ddb_partitioning,
1904                                      bool is_sprite)
1905 {
1906         unsigned int fifo_size = ilk_display_fifo_size(dev);
1907
1908         /* if sprites aren't enabled, sprites get nothing */
1909         if (is_sprite && !config->sprites_enabled)
1910                 return 0;
1911
1912         /* HSW allows LP1+ watermarks even with multiple pipes */
1913         if (level == 0 || config->num_pipes_active > 1) {
1914                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1915
1916                 /*
1917                  * For some reason the non self refresh
1918                  * FIFO size is only half of the self
1919                  * refresh FIFO size on ILK/SNB.
1920                  */
1921                 if (INTEL_INFO(dev)->gen <= 6)
1922                         fifo_size /= 2;
1923         }
1924
1925         if (config->sprites_enabled) {
1926                 /* level 0 is always calculated with 1:1 split */
1927                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1928                         if (is_sprite)
1929                                 fifo_size *= 5;
1930                         fifo_size /= 6;
1931                 } else {
1932                         fifo_size /= 2;
1933                 }
1934         }
1935
1936         /* clamp to max that the registers can hold */
1937         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1938 }
1939
1940 /* Calculate the maximum cursor plane watermark */
1941 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1942                                       int level,
1943                                       const struct intel_wm_config *config)
1944 {
1945         /* HSW LP1+ watermarks w/ multiple pipes */
1946         if (level > 0 && config->num_pipes_active > 1)
1947                 return 64;
1948
1949         /* otherwise just report max that registers can hold */
1950         return ilk_cursor_wm_reg_max(dev, level);
1951 }
1952
1953 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1954                                     int level,
1955                                     const struct intel_wm_config *config,
1956                                     enum intel_ddb_partitioning ddb_partitioning,
1957                                     struct ilk_wm_maximums *max)
1958 {
1959         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1960         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1961         max->cur = ilk_cursor_wm_max(dev, level, config);
1962         max->fbc = ilk_fbc_wm_reg_max(dev);
1963 }
1964
1965 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1966                                         int level,
1967                                         struct ilk_wm_maximums *max)
1968 {
1969         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1970         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1971         max->cur = ilk_cursor_wm_reg_max(dev, level);
1972         max->fbc = ilk_fbc_wm_reg_max(dev);
1973 }
1974
1975 static bool ilk_validate_wm_level(int level,
1976                                   const struct ilk_wm_maximums *max,
1977                                   struct intel_wm_level *result)
1978 {
1979         bool ret;
1980
1981         /* already determined to be invalid? */
1982         if (!result->enable)
1983                 return false;
1984
1985         result->enable = result->pri_val <= max->pri &&
1986                          result->spr_val <= max->spr &&
1987                          result->cur_val <= max->cur;
1988
1989         ret = result->enable;
1990
1991         /*
1992          * HACK until we can pre-compute everything,
1993          * and thus fail gracefully if LP0 watermarks
1994          * are exceeded...
1995          */
1996         if (level == 0 && !result->enable) {
1997                 if (result->pri_val > max->pri)
1998                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1999                                       level, result->pri_val, max->pri);
2000                 if (result->spr_val > max->spr)
2001                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2002                                       level, result->spr_val, max->spr);
2003                 if (result->cur_val > max->cur)
2004                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2005                                       level, result->cur_val, max->cur);
2006
2007                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2008                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2009                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2010                 result->enable = true;
2011         }
2012
2013         return ret;
2014 }
2015
2016 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2017                                  const struct intel_crtc *intel_crtc,
2018                                  int level,
2019                                  struct intel_crtc_state *cstate,
2020                                  struct intel_plane_state *pristate,
2021                                  struct intel_plane_state *sprstate,
2022                                  struct intel_plane_state *curstate,
2023                                  struct intel_wm_level *result)
2024 {
2025         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2026         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2027         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2028
2029         /* WM1+ latency values stored in 0.5us units */
2030         if (level > 0) {
2031                 pri_latency *= 5;
2032                 spr_latency *= 5;
2033                 cur_latency *= 5;
2034         }
2035
2036         if (pristate) {
2037                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2038                                                      pri_latency, level);
2039                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2040         }
2041
2042         if (sprstate)
2043                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2044
2045         if (curstate)
2046                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2047
2048         result->enable = true;
2049 }
2050
2051 static uint32_t
2052 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2053 {
2054         const struct intel_atomic_state *intel_state =
2055                 to_intel_atomic_state(cstate->base.state);
2056         const struct drm_display_mode *adjusted_mode =
2057                 &cstate->base.adjusted_mode;
2058         u32 linetime, ips_linetime;
2059
2060         if (!cstate->base.active)
2061                 return 0;
2062         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2063                 return 0;
2064         if (WARN_ON(intel_state->cdclk == 0))
2065                 return 0;
2066
2067         /* The WM are computed with base on how long it takes to fill a single
2068          * row at the given clock rate, multiplied by 8.
2069          * */
2070         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2071                                      adjusted_mode->crtc_clock);
2072         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2073                                          intel_state->cdclk);
2074
2075         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2076                PIPE_WM_LINETIME_TIME(linetime);
2077 }
2078
2079 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2080 {
2081         struct drm_i915_private *dev_priv = to_i915(dev);
2082
2083         if (IS_GEN9(dev)) {
2084                 uint32_t val;
2085                 int ret, i;
2086                 int level, max_level = ilk_wm_max_level(dev);
2087
2088                 /* read the first set of memory latencies[0:3] */
2089                 val = 0; /* data0 to be programmed to 0 for first set */
2090                 mutex_lock(&dev_priv->rps.hw_lock);
2091                 ret = sandybridge_pcode_read(dev_priv,
2092                                              GEN9_PCODE_READ_MEM_LATENCY,
2093                                              &val);
2094                 mutex_unlock(&dev_priv->rps.hw_lock);
2095
2096                 if (ret) {
2097                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2098                         return;
2099                 }
2100
2101                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2102                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2103                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2104                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2105                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2106                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2107                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2108
2109                 /* read the second set of memory latencies[4:7] */
2110                 val = 1; /* data0 to be programmed to 1 for second set */
2111                 mutex_lock(&dev_priv->rps.hw_lock);
2112                 ret = sandybridge_pcode_read(dev_priv,
2113                                              GEN9_PCODE_READ_MEM_LATENCY,
2114                                              &val);
2115                 mutex_unlock(&dev_priv->rps.hw_lock);
2116                 if (ret) {
2117                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2118                         return;
2119                 }
2120
2121                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2122                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2123                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2124                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2125                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2126                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2127                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2128
2129                 /*
2130                  * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2131                  * need to be disabled. We make sure to sanitize the values out
2132                  * of the punit to satisfy this requirement.
2133                  */
2134                 for (level = 1; level <= max_level; level++) {
2135                         if (wm[level] == 0) {
2136                                 for (i = level + 1; i <= max_level; i++)
2137                                         wm[i] = 0;
2138                                 break;
2139                         }
2140                 }
2141
2142                 /*
2143                  * WaWmMemoryReadLatency:skl
2144                  *
2145                  * punit doesn't take into account the read latency so we need
2146                  * to add 2us to the various latency levels we retrieve from the
2147                  * punit when level 0 response data us 0us.
2148                  */
2149                 if (wm[0] == 0) {
2150                         wm[0] += 2;
2151                         for (level = 1; level <= max_level; level++) {
2152                                 if (wm[level] == 0)
2153                                         break;
2154                                 wm[level] += 2;
2155                         }
2156                 }
2157
2158         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2159                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2160
2161                 wm[0] = (sskpd >> 56) & 0xFF;
2162                 if (wm[0] == 0)
2163                         wm[0] = sskpd & 0xF;
2164                 wm[1] = (sskpd >> 4) & 0xFF;
2165                 wm[2] = (sskpd >> 12) & 0xFF;
2166                 wm[3] = (sskpd >> 20) & 0x1FF;
2167                 wm[4] = (sskpd >> 32) & 0x1FF;
2168         } else if (INTEL_INFO(dev)->gen >= 6) {
2169                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2170
2171                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2172                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2173                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2174                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2175         } else if (INTEL_INFO(dev)->gen >= 5) {
2176                 uint32_t mltr = I915_READ(MLTR_ILK);
2177
2178                 /* ILK primary LP0 latency is 700 ns */
2179                 wm[0] = 7;
2180                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2181                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2182         }
2183 }
2184
2185 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2186 {
2187         /* ILK sprite LP0 latency is 1300 ns */
2188         if (IS_GEN5(dev))
2189                 wm[0] = 13;
2190 }
2191
2192 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2193 {
2194         /* ILK cursor LP0 latency is 1300 ns */
2195         if (IS_GEN5(dev))
2196                 wm[0] = 13;
2197
2198         /* WaDoubleCursorLP3Latency:ivb */
2199         if (IS_IVYBRIDGE(dev))
2200                 wm[3] *= 2;
2201 }
2202
2203 int ilk_wm_max_level(const struct drm_device *dev)
2204 {
2205         /* how many WM levels are we expecting */
2206         if (INTEL_INFO(dev)->gen >= 9)
2207                 return 7;
2208         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2209                 return 4;
2210         else if (INTEL_INFO(dev)->gen >= 6)
2211                 return 3;
2212         else
2213                 return 2;
2214 }
2215
2216 static void intel_print_wm_latency(struct drm_device *dev,
2217                                    const char *name,
2218                                    const uint16_t wm[8])
2219 {
2220         int level, max_level = ilk_wm_max_level(dev);
2221
2222         for (level = 0; level <= max_level; level++) {
2223                 unsigned int latency = wm[level];
2224
2225                 if (latency == 0) {
2226                         DRM_ERROR("%s WM%d latency not provided\n",
2227                                   name, level);
2228                         continue;
2229                 }
2230
2231                 /*
2232                  * - latencies are in us on gen9.
2233                  * - before then, WM1+ latency values are in 0.5us units
2234                  */
2235                 if (IS_GEN9(dev))
2236                         latency *= 10;
2237                 else if (level > 0)
2238                         latency *= 5;
2239
2240                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2241                               name, level, wm[level],
2242                               latency / 10, latency % 10);
2243         }
2244 }
2245
2246 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2247                                     uint16_t wm[5], uint16_t min)
2248 {
2249         int level, max_level = ilk_wm_max_level(&dev_priv->drm);
2250
2251         if (wm[0] >= min)
2252                 return false;
2253
2254         wm[0] = max(wm[0], min);
2255         for (level = 1; level <= max_level; level++)
2256                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2257
2258         return true;
2259 }
2260
2261 static void snb_wm_latency_quirk(struct drm_device *dev)
2262 {
2263         struct drm_i915_private *dev_priv = to_i915(dev);
2264         bool changed;
2265
2266         /*
2267          * The BIOS provided WM memory latency values are often
2268          * inadequate for high resolution displays. Adjust them.
2269          */
2270         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2271                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2272                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2273
2274         if (!changed)
2275                 return;
2276
2277         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2278         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2279         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2280         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2281 }
2282
2283 static void ilk_setup_wm_latency(struct drm_device *dev)
2284 {
2285         struct drm_i915_private *dev_priv = to_i915(dev);
2286
2287         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2288
2289         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2290                sizeof(dev_priv->wm.pri_latency));
2291         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2292                sizeof(dev_priv->wm.pri_latency));
2293
2294         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2295         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2296
2297         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2298         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2299         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2300
2301         if (IS_GEN6(dev))
2302                 snb_wm_latency_quirk(dev);
2303 }
2304
2305 static void skl_setup_wm_latency(struct drm_device *dev)
2306 {
2307         struct drm_i915_private *dev_priv = to_i915(dev);
2308
2309         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2310         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2311 }
2312
2313 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2314                                  struct intel_pipe_wm *pipe_wm)
2315 {
2316         /* LP0 watermark maximums depend on this pipe alone */
2317         const struct intel_wm_config config = {
2318                 .num_pipes_active = 1,
2319                 .sprites_enabled = pipe_wm->sprites_enabled,
2320                 .sprites_scaled = pipe_wm->sprites_scaled,
2321         };
2322         struct ilk_wm_maximums max;
2323
2324         /* LP0 watermarks always use 1/2 DDB partitioning */
2325         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2326
2327         /* At least LP0 must be valid */
2328         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2329                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2330                 return false;
2331         }
2332
2333         return true;
2334 }
2335
2336 /* Compute new watermarks for the pipe */
2337 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2338 {
2339         struct drm_atomic_state *state = cstate->base.state;
2340         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2341         struct intel_pipe_wm *pipe_wm;
2342         struct drm_device *dev = state->dev;
2343         const struct drm_i915_private *dev_priv = to_i915(dev);
2344         struct intel_plane *intel_plane;
2345         struct intel_plane_state *pristate = NULL;
2346         struct intel_plane_state *sprstate = NULL;
2347         struct intel_plane_state *curstate = NULL;
2348         int level, max_level = ilk_wm_max_level(dev), usable_level;
2349         struct ilk_wm_maximums max;
2350
2351         pipe_wm = &cstate->wm.ilk.optimal;
2352
2353         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2354                 struct intel_plane_state *ps;
2355
2356                 ps = intel_atomic_get_existing_plane_state(state,
2357                                                            intel_plane);
2358                 if (!ps)
2359                         continue;
2360
2361                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2362                         pristate = ps;
2363                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2364                         sprstate = ps;
2365                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2366                         curstate = ps;
2367         }
2368
2369         pipe_wm->pipe_enabled = cstate->base.active;
2370         if (sprstate) {
2371                 pipe_wm->sprites_enabled = sprstate->base.visible;
2372                 pipe_wm->sprites_scaled = sprstate->base.visible &&
2373                         (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2374                          drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
2375         }
2376
2377         usable_level = max_level;
2378
2379         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2380         if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
2381                 usable_level = 1;
2382
2383         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2384         if (pipe_wm->sprites_scaled)
2385                 usable_level = 0;
2386
2387         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2388                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2389
2390         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2391         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2392
2393         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2394                 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2395
2396         if (!ilk_validate_pipe_wm(dev, pipe_wm))
2397                 return -EINVAL;
2398
2399         ilk_compute_wm_reg_maximums(dev, 1, &max);
2400
2401         for (level = 1; level <= max_level; level++) {
2402                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2403
2404                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2405                                      pristate, sprstate, curstate, wm);
2406
2407                 /*
2408                  * Disable any watermark level that exceeds the
2409                  * register maximums since such watermarks are
2410                  * always invalid.
2411                  */
2412                 if (level > usable_level)
2413                         continue;
2414
2415                 if (ilk_validate_wm_level(level, &max, wm))
2416                         pipe_wm->wm[level] = *wm;
2417                 else
2418                         usable_level = level;
2419         }
2420
2421         return 0;
2422 }
2423
2424 /*
2425  * Build a set of 'intermediate' watermark values that satisfy both the old
2426  * state and the new state.  These can be programmed to the hardware
2427  * immediately.
2428  */
2429 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2430                                        struct intel_crtc *intel_crtc,
2431                                        struct intel_crtc_state *newstate)
2432 {
2433         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2434         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2435         int level, max_level = ilk_wm_max_level(dev);
2436
2437         /*
2438          * Start with the final, target watermarks, then combine with the
2439          * currently active watermarks to get values that are safe both before
2440          * and after the vblank.
2441          */
2442         *a = newstate->wm.ilk.optimal;
2443         a->pipe_enabled |= b->pipe_enabled;
2444         a->sprites_enabled |= b->sprites_enabled;
2445         a->sprites_scaled |= b->sprites_scaled;
2446
2447         for (level = 0; level <= max_level; level++) {
2448                 struct intel_wm_level *a_wm = &a->wm[level];
2449                 const struct intel_wm_level *b_wm = &b->wm[level];
2450
2451                 a_wm->enable &= b_wm->enable;
2452                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2453                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2454                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2455                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2456         }
2457
2458         /*
2459          * We need to make sure that these merged watermark values are
2460          * actually a valid configuration themselves.  If they're not,
2461          * there's no safe way to transition from the old state to
2462          * the new state, so we need to fail the atomic transaction.
2463          */
2464         if (!ilk_validate_pipe_wm(dev, a))
2465                 return -EINVAL;
2466
2467         /*
2468          * If our intermediate WM are identical to the final WM, then we can
2469          * omit the post-vblank programming; only update if it's different.
2470          */
2471         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2472                 newstate->wm.need_postvbl_update = false;
2473
2474         return 0;
2475 }
2476
2477 /*
2478  * Merge the watermarks from all active pipes for a specific level.
2479  */
2480 static void ilk_merge_wm_level(struct drm_device *dev,
2481                                int level,
2482                                struct intel_wm_level *ret_wm)
2483 {
2484         const struct intel_crtc *intel_crtc;
2485
2486         ret_wm->enable = true;
2487
2488         for_each_intel_crtc(dev, intel_crtc) {
2489                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2490                 const struct intel_wm_level *wm = &active->wm[level];
2491
2492                 if (!active->pipe_enabled)
2493                         continue;
2494
2495                 /*
2496                  * The watermark values may have been used in the past,
2497                  * so we must maintain them in the registers for some
2498                  * time even if the level is now disabled.
2499                  */
2500                 if (!wm->enable)
2501                         ret_wm->enable = false;
2502
2503                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2504                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2505                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2506                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2507         }
2508 }
2509
2510 /*
2511  * Merge all low power watermarks for all active pipes.
2512  */
2513 static void ilk_wm_merge(struct drm_device *dev,
2514                          const struct intel_wm_config *config,
2515                          const struct ilk_wm_maximums *max,
2516                          struct intel_pipe_wm *merged)
2517 {
2518         struct drm_i915_private *dev_priv = to_i915(dev);
2519         int level, max_level = ilk_wm_max_level(dev);
2520         int last_enabled_level = max_level;
2521
2522         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2523         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2524             config->num_pipes_active > 1)
2525                 last_enabled_level = 0;
2526
2527         /* ILK: FBC WM must be disabled always */
2528         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2529
2530         /* merge each WM1+ level */
2531         for (level = 1; level <= max_level; level++) {
2532                 struct intel_wm_level *wm = &merged->wm[level];
2533
2534                 ilk_merge_wm_level(dev, level, wm);
2535
2536                 if (level > last_enabled_level)
2537                         wm->enable = false;
2538                 else if (!ilk_validate_wm_level(level, max, wm))
2539                         /* make sure all following levels get disabled */
2540                         last_enabled_level = level - 1;
2541
2542                 /*
2543                  * The spec says it is preferred to disable
2544                  * FBC WMs instead of disabling a WM level.
2545                  */
2546                 if (wm->fbc_val > max->fbc) {
2547                         if (wm->enable)
2548                                 merged->fbc_wm_enabled = false;
2549                         wm->fbc_val = 0;
2550                 }
2551         }
2552
2553         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2554         /*
2555          * FIXME this is racy. FBC might get enabled later.
2556          * What we should check here is whether FBC can be
2557          * enabled sometime later.
2558          */
2559         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2560             intel_fbc_is_active(dev_priv)) {
2561                 for (level = 2; level <= max_level; level++) {
2562                         struct intel_wm_level *wm = &merged->wm[level];
2563
2564                         wm->enable = false;
2565                 }
2566         }
2567 }
2568
2569 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2570 {
2571         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2572         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2573 }
2574
2575 /* The value we need to program into the WM_LPx latency field */
2576 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2577 {
2578         struct drm_i915_private *dev_priv = to_i915(dev);
2579
2580         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2581                 return 2 * level;
2582         else
2583                 return dev_priv->wm.pri_latency[level];
2584 }
2585
2586 static void ilk_compute_wm_results(struct drm_device *dev,
2587                                    const struct intel_pipe_wm *merged,
2588                                    enum intel_ddb_partitioning partitioning,
2589                                    struct ilk_wm_values *results)
2590 {
2591         struct intel_crtc *intel_crtc;
2592         int level, wm_lp;
2593
2594         results->enable_fbc_wm = merged->fbc_wm_enabled;
2595         results->partitioning = partitioning;
2596
2597         /* LP1+ register values */
2598         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2599                 const struct intel_wm_level *r;
2600
2601                 level = ilk_wm_lp_to_level(wm_lp, merged);
2602
2603                 r = &merged->wm[level];
2604
2605                 /*
2606                  * Maintain the watermark values even if the level is
2607                  * disabled. Doing otherwise could cause underruns.
2608                  */
2609                 results->wm_lp[wm_lp - 1] =
2610                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2611                         (r->pri_val << WM1_LP_SR_SHIFT) |
2612                         r->cur_val;
2613
2614                 if (r->enable)
2615                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2616
2617                 if (INTEL_INFO(dev)->gen >= 8)
2618                         results->wm_lp[wm_lp - 1] |=
2619                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2620                 else
2621                         results->wm_lp[wm_lp - 1] |=
2622                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2623
2624                 /*
2625                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2626                  * level is disabled. Doing otherwise could cause underruns.
2627                  */
2628                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2629                         WARN_ON(wm_lp != 1);
2630                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2631                 } else
2632                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2633         }
2634
2635         /* LP0 register values */
2636         for_each_intel_crtc(dev, intel_crtc) {
2637                 enum pipe pipe = intel_crtc->pipe;
2638                 const struct intel_wm_level *r =
2639                         &intel_crtc->wm.active.ilk.wm[0];
2640
2641                 if (WARN_ON(!r->enable))
2642                         continue;
2643
2644                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2645
2646                 results->wm_pipe[pipe] =
2647                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2648                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2649                         r->cur_val;
2650         }
2651 }
2652
2653 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2654  * case both are at the same level. Prefer r1 in case they're the same. */
2655 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2656                                                   struct intel_pipe_wm *r1,
2657                                                   struct intel_pipe_wm *r2)
2658 {
2659         int level, max_level = ilk_wm_max_level(dev);
2660         int level1 = 0, level2 = 0;
2661
2662         for (level = 1; level <= max_level; level++) {
2663                 if (r1->wm[level].enable)
2664                         level1 = level;
2665                 if (r2->wm[level].enable)
2666                         level2 = level;
2667         }
2668
2669         if (level1 == level2) {
2670                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2671                         return r2;
2672                 else
2673                         return r1;
2674         } else if (level1 > level2) {
2675                 return r1;
2676         } else {
2677                 return r2;
2678         }
2679 }
2680
2681 /* dirty bits used to track which watermarks need changes */
2682 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2683 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2684 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2685 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2686 #define WM_DIRTY_FBC (1 << 24)
2687 #define WM_DIRTY_DDB (1 << 25)
2688
2689 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2690                                          const struct ilk_wm_values *old,
2691                                          const struct ilk_wm_values *new)
2692 {
2693         unsigned int dirty = 0;
2694         enum pipe pipe;
2695         int wm_lp;
2696
2697         for_each_pipe(dev_priv, pipe) {
2698                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2699                         dirty |= WM_DIRTY_LINETIME(pipe);
2700                         /* Must disable LP1+ watermarks too */
2701                         dirty |= WM_DIRTY_LP_ALL;
2702                 }
2703
2704                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2705                         dirty |= WM_DIRTY_PIPE(pipe);
2706                         /* Must disable LP1+ watermarks too */
2707                         dirty |= WM_DIRTY_LP_ALL;
2708                 }
2709         }
2710
2711         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2712                 dirty |= WM_DIRTY_FBC;
2713                 /* Must disable LP1+ watermarks too */
2714                 dirty |= WM_DIRTY_LP_ALL;
2715         }
2716
2717         if (old->partitioning != new->partitioning) {
2718                 dirty |= WM_DIRTY_DDB;
2719                 /* Must disable LP1+ watermarks too */
2720                 dirty |= WM_DIRTY_LP_ALL;
2721         }
2722
2723         /* LP1+ watermarks already deemed dirty, no need to continue */
2724         if (dirty & WM_DIRTY_LP_ALL)
2725                 return dirty;
2726
2727         /* Find the lowest numbered LP1+ watermark in need of an update... */
2728         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2729                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2730                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2731                         break;
2732         }
2733
2734         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2735         for (; wm_lp <= 3; wm_lp++)
2736                 dirty |= WM_DIRTY_LP(wm_lp);
2737
2738         return dirty;
2739 }
2740
2741 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2742                                unsigned int dirty)
2743 {
2744         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2745         bool changed = false;
2746
2747         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2748                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2749                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2750                 changed = true;
2751         }
2752         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2753                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2754                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2755                 changed = true;
2756         }
2757         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2758                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2759                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2760                 changed = true;
2761         }
2762
2763         /*
2764          * Don't touch WM1S_LP_EN here.
2765          * Doing so could cause underruns.
2766          */
2767
2768         return changed;
2769 }
2770
2771 /*
2772  * The spec says we shouldn't write when we don't need, because every write
2773  * causes WMs to be re-evaluated, expending some power.
2774  */
2775 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2776                                 struct ilk_wm_values *results)
2777 {
2778         struct drm_device *dev = &dev_priv->drm;
2779         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2780         unsigned int dirty;
2781         uint32_t val;
2782
2783         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2784         if (!dirty)
2785                 return;
2786
2787         _ilk_disable_lp_wm(dev_priv, dirty);
2788
2789         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2790                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2791         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2792                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2793         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2794                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2795
2796         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2797                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2798         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2799                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2800         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2801                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2802
2803         if (dirty & WM_DIRTY_DDB) {
2804                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2805                         val = I915_READ(WM_MISC);
2806                         if (results->partitioning == INTEL_DDB_PART_1_2)
2807                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2808                         else
2809                                 val |= WM_MISC_DATA_PARTITION_5_6;
2810                         I915_WRITE(WM_MISC, val);
2811                 } else {
2812                         val = I915_READ(DISP_ARB_CTL2);
2813                         if (results->partitioning == INTEL_DDB_PART_1_2)
2814                                 val &= ~DISP_DATA_PARTITION_5_6;
2815                         else
2816                                 val |= DISP_DATA_PARTITION_5_6;
2817                         I915_WRITE(DISP_ARB_CTL2, val);
2818                 }
2819         }
2820
2821         if (dirty & WM_DIRTY_FBC) {
2822                 val = I915_READ(DISP_ARB_CTL);
2823                 if (results->enable_fbc_wm)
2824                         val &= ~DISP_FBC_WM_DIS;
2825                 else
2826                         val |= DISP_FBC_WM_DIS;
2827                 I915_WRITE(DISP_ARB_CTL, val);
2828         }
2829
2830         if (dirty & WM_DIRTY_LP(1) &&
2831             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2832                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2833
2834         if (INTEL_INFO(dev)->gen >= 7) {
2835                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2836                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2837                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2838                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2839         }
2840
2841         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2842                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2843         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2844                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2845         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2846                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2847
2848         dev_priv->wm.hw = *results;
2849 }
2850
2851 bool ilk_disable_lp_wm(struct drm_device *dev)
2852 {
2853         struct drm_i915_private *dev_priv = to_i915(dev);
2854
2855         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2856 }
2857
2858 #define SKL_SAGV_BLOCK_TIME     30 /* µs */
2859
2860 /*
2861  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2862  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2863  * other universal planes are in indices 1..n.  Note that this may leave unused
2864  * indices between the top "sprite" plane and the cursor.
2865  */
2866 static int
2867 skl_wm_plane_id(const struct intel_plane *plane)
2868 {
2869         switch (plane->base.type) {
2870         case DRM_PLANE_TYPE_PRIMARY:
2871                 return 0;
2872         case DRM_PLANE_TYPE_CURSOR:
2873                 return PLANE_CURSOR;
2874         case DRM_PLANE_TYPE_OVERLAY:
2875                 return plane->plane + 1;
2876         default:
2877                 MISSING_CASE(plane->base.type);
2878                 return plane->plane;
2879         }
2880 }
2881
2882 static bool
2883 intel_has_sagv(struct drm_i915_private *dev_priv)
2884 {
2885         if (IS_KABYLAKE(dev_priv))
2886                 return true;
2887
2888         if (IS_SKYLAKE(dev_priv) &&
2889             dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2890                 return true;
2891
2892         return false;
2893 }
2894
2895 /*
2896  * SAGV dynamically adjusts the system agent voltage and clock frequencies
2897  * depending on power and performance requirements. The display engine access
2898  * to system memory is blocked during the adjustment time. Because of the
2899  * blocking time, having this enabled can cause full system hangs and/or pipe
2900  * underruns if we don't meet all of the following requirements:
2901  *
2902  *  - <= 1 pipe enabled
2903  *  - All planes can enable watermarks for latencies >= SAGV engine block time
2904  *  - We're not using an interlaced display configuration
2905  */
2906 int
2907 intel_enable_sagv(struct drm_i915_private *dev_priv)
2908 {
2909         int ret;
2910
2911         if (!intel_has_sagv(dev_priv))
2912                 return 0;
2913
2914         if (dev_priv->sagv_status == I915_SAGV_ENABLED)
2915                 return 0;
2916
2917         DRM_DEBUG_KMS("Enabling the SAGV\n");
2918         mutex_lock(&dev_priv->rps.hw_lock);
2919
2920         ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2921                                       GEN9_SAGV_ENABLE);
2922
2923         /* We don't need to wait for the SAGV when enabling */
2924         mutex_unlock(&dev_priv->rps.hw_lock);
2925
2926         /*
2927          * Some skl systems, pre-release machines in particular,
2928          * don't actually have an SAGV.
2929          */
2930         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2931                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2932                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2933                 return 0;
2934         } else if (ret < 0) {
2935                 DRM_ERROR("Failed to enable the SAGV\n");
2936                 return ret;
2937         }
2938
2939         dev_priv->sagv_status = I915_SAGV_ENABLED;
2940         return 0;
2941 }
2942
2943 static int
2944 intel_do_sagv_disable(struct drm_i915_private *dev_priv)
2945 {
2946         int ret;
2947         uint32_t temp = GEN9_SAGV_DISABLE;
2948
2949         ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2950                                      &temp);
2951         if (ret)
2952                 return ret;
2953         else
2954                 return temp & GEN9_SAGV_IS_DISABLED;
2955 }
2956
2957 int
2958 intel_disable_sagv(struct drm_i915_private *dev_priv)
2959 {
2960         int ret, result;
2961
2962         if (!intel_has_sagv(dev_priv))
2963                 return 0;
2964
2965         if (dev_priv->sagv_status == I915_SAGV_DISABLED)
2966                 return 0;
2967
2968         DRM_DEBUG_KMS("Disabling the SAGV\n");
2969         mutex_lock(&dev_priv->rps.hw_lock);
2970
2971         /* bspec says to keep retrying for at least 1 ms */
2972         ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
2973         mutex_unlock(&dev_priv->rps.hw_lock);
2974
2975         if (ret == -ETIMEDOUT) {
2976                 DRM_ERROR("Request to disable SAGV timed out\n");
2977                 return -ETIMEDOUT;
2978         }
2979
2980         /*
2981          * Some skl systems, pre-release machines in particular,
2982          * don't actually have an SAGV.
2983          */
2984         if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
2985                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2986                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2987                 return 0;
2988         } else if (result < 0) {
2989                 DRM_ERROR("Failed to disable the SAGV\n");
2990                 return result;
2991         }
2992
2993         dev_priv->sagv_status = I915_SAGV_DISABLED;
2994         return 0;
2995 }
2996
2997 bool intel_can_enable_sagv(struct drm_atomic_state *state)
2998 {
2999         struct drm_device *dev = state->dev;
3000         struct drm_i915_private *dev_priv = to_i915(dev);
3001         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3002         struct drm_crtc *crtc;
3003         enum pipe pipe;
3004         int level, plane;
3005
3006         if (!intel_has_sagv(dev_priv))
3007                 return false;
3008
3009         /*
3010          * SKL workaround: bspec recommends we disable the SAGV when we have
3011          * more then one pipe enabled
3012          *
3013          * If there are no active CRTCs, no additional checks need be performed
3014          */
3015         if (hweight32(intel_state->active_crtcs) == 0)
3016                 return true;
3017         else if (hweight32(intel_state->active_crtcs) > 1)
3018                 return false;
3019
3020         /* Since we're now guaranteed to only have one active CRTC... */
3021         pipe = ffs(intel_state->active_crtcs) - 1;
3022         crtc = dev_priv->pipe_to_crtc_mapping[pipe];
3023
3024         if (crtc->state->mode.flags & DRM_MODE_FLAG_INTERLACE)
3025                 return false;
3026
3027         for_each_plane(dev_priv, pipe, plane) {
3028                 /* Skip this plane if it's not enabled */
3029                 if (intel_state->wm_results.plane[pipe][plane][0] == 0)
3030                         continue;
3031
3032                 /* Find the highest enabled wm level for this plane */
3033                 for (level = ilk_wm_max_level(dev);
3034                      intel_state->wm_results.plane[pipe][plane][level] == 0; --level)
3035                      { }
3036
3037                 /*
3038                  * If any of the planes on this pipe don't enable wm levels
3039                  * that incur memory latencies higher then 30µs we can't enable
3040                  * the SAGV
3041                  */
3042                 if (dev_priv->wm.skl_latency[level] < SKL_SAGV_BLOCK_TIME)
3043                         return false;
3044         }
3045
3046         return true;
3047 }
3048
3049 static void
3050 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3051                                    const struct intel_crtc_state *cstate,
3052                                    struct skl_ddb_entry *alloc, /* out */
3053                                    int *num_active /* out */)
3054 {
3055         struct drm_atomic_state *state = cstate->base.state;
3056         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3057         struct drm_i915_private *dev_priv = to_i915(dev);
3058         struct drm_crtc *for_crtc = cstate->base.crtc;
3059         unsigned int pipe_size, ddb_size;
3060         int nth_active_pipe;
3061         int pipe = to_intel_crtc(for_crtc)->pipe;
3062
3063         if (WARN_ON(!state) || !cstate->base.active) {
3064                 alloc->start = 0;
3065                 alloc->end = 0;
3066                 *num_active = hweight32(dev_priv->active_crtcs);
3067                 return;
3068         }
3069
3070         if (intel_state->active_pipe_changes)
3071                 *num_active = hweight32(intel_state->active_crtcs);
3072         else
3073                 *num_active = hweight32(dev_priv->active_crtcs);
3074
3075         ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3076         WARN_ON(ddb_size == 0);
3077
3078         ddb_size -= 4; /* 4 blocks for bypass path allocation */
3079
3080         /*
3081          * If the state doesn't change the active CRTC's, then there's
3082          * no need to recalculate; the existing pipe allocation limits
3083          * should remain unchanged.  Note that we're safe from racing
3084          * commits since any racing commit that changes the active CRTC
3085          * list would need to grab _all_ crtc locks, including the one
3086          * we currently hold.
3087          */
3088         if (!intel_state->active_pipe_changes) {
3089                 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
3090                 return;
3091         }
3092
3093         nth_active_pipe = hweight32(intel_state->active_crtcs &
3094                                     (drm_crtc_mask(for_crtc) - 1));
3095         pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3096         alloc->start = nth_active_pipe * ddb_size / *num_active;
3097         alloc->end = alloc->start + pipe_size;
3098 }
3099
3100 static unsigned int skl_cursor_allocation(int num_active)
3101 {
3102         if (num_active == 1)
3103                 return 32;
3104
3105         return 8;
3106 }
3107
3108 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3109 {
3110         entry->start = reg & 0x3ff;
3111         entry->end = (reg >> 16) & 0x3ff;
3112         if (entry->end)
3113                 entry->end += 1;
3114 }
3115
3116 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3117                           struct skl_ddb_allocation *ddb /* out */)
3118 {
3119         enum pipe pipe;
3120         int plane;
3121         u32 val;
3122
3123         memset(ddb, 0, sizeof(*ddb));
3124
3125         for_each_pipe(dev_priv, pipe) {
3126                 enum intel_display_power_domain power_domain;
3127
3128                 power_domain = POWER_DOMAIN_PIPE(pipe);
3129                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3130                         continue;
3131
3132                 for_each_plane(dev_priv, pipe, plane) {
3133                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3134                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3135                                                    val);
3136                 }
3137
3138                 val = I915_READ(CUR_BUF_CFG(pipe));
3139                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3140                                            val);
3141
3142                 intel_display_power_put(dev_priv, power_domain);
3143         }
3144 }
3145
3146 /*
3147  * Determines the downscale amount of a plane for the purposes of watermark calculations.
3148  * The bspec defines downscale amount as:
3149  *
3150  * """
3151  * Horizontal down scale amount = maximum[1, Horizontal source size /
3152  *                                           Horizontal destination size]
3153  * Vertical down scale amount = maximum[1, Vertical source size /
3154  *                                         Vertical destination size]
3155  * Total down scale amount = Horizontal down scale amount *
3156  *                           Vertical down scale amount
3157  * """
3158  *
3159  * Return value is provided in 16.16 fixed point form to retain fractional part.
3160  * Caller should take care of dividing & rounding off the value.
3161  */
3162 static uint32_t
3163 skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3164 {
3165         uint32_t downscale_h, downscale_w;
3166         uint32_t src_w, src_h, dst_w, dst_h;
3167
3168         if (WARN_ON(!pstate->base.visible))
3169                 return DRM_PLANE_HELPER_NO_SCALING;
3170
3171         /* n.b., src is 16.16 fixed point, dst is whole integer */
3172         src_w = drm_rect_width(&pstate->base.src);
3173         src_h = drm_rect_height(&pstate->base.src);
3174         dst_w = drm_rect_width(&pstate->base.dst);
3175         dst_h = drm_rect_height(&pstate->base.dst);
3176         if (intel_rotation_90_or_270(pstate->base.rotation))
3177                 swap(dst_w, dst_h);
3178
3179         downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3180         downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3181
3182         /* Provide result in 16.16 fixed point */
3183         return (uint64_t)downscale_w * downscale_h >> 16;
3184 }
3185
3186 static unsigned int
3187 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3188                              const struct drm_plane_state *pstate,
3189                              int y)
3190 {
3191         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3192         struct drm_framebuffer *fb = pstate->fb;
3193         uint32_t down_scale_amount, data_rate;
3194         uint32_t width = 0, height = 0;
3195         unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3196
3197         if (!intel_pstate->base.visible)
3198                 return 0;
3199         if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3200                 return 0;
3201         if (y && format != DRM_FORMAT_NV12)
3202                 return 0;
3203
3204         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3205         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3206
3207         if (intel_rotation_90_or_270(pstate->rotation))
3208                 swap(width, height);
3209
3210         /* for planar format */
3211         if (format == DRM_FORMAT_NV12) {
3212                 if (y)  /* y-plane data rate */
3213                         data_rate = width * height *
3214                                 drm_format_plane_cpp(format, 0);
3215                 else    /* uv-plane data rate */
3216                         data_rate = (width / 2) * (height / 2) *
3217                                 drm_format_plane_cpp(format, 1);
3218         } else {
3219                 /* for packed formats */
3220                 data_rate = width * height * drm_format_plane_cpp(format, 0);
3221         }
3222
3223         down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3224
3225         return (uint64_t)data_rate * down_scale_amount >> 16;
3226 }
3227
3228 /*
3229  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3230  * a 8192x4096@32bpp framebuffer:
3231  *   3 * 4096 * 8192  * 4 < 2^32
3232  */
3233 static unsigned int
3234 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
3235 {
3236         struct drm_crtc_state *cstate = &intel_cstate->base;
3237         struct drm_atomic_state *state = cstate->state;
3238         struct drm_crtc *crtc = cstate->crtc;
3239         struct drm_device *dev = crtc->dev;
3240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3241         const struct drm_plane *plane;
3242         const struct intel_plane *intel_plane;
3243         struct drm_plane_state *pstate;
3244         unsigned int rate, total_data_rate = 0;
3245         int id;
3246         int i;
3247
3248         if (WARN_ON(!state))
3249                 return 0;
3250
3251         /* Calculate and cache data rate for each plane */
3252         for_each_plane_in_state(state, plane, pstate, i) {
3253                 id = skl_wm_plane_id(to_intel_plane(plane));
3254                 intel_plane = to_intel_plane(plane);
3255
3256                 if (intel_plane->pipe != intel_crtc->pipe)
3257                         continue;
3258
3259                 /* packed/uv */
3260                 rate = skl_plane_relative_data_rate(intel_cstate,
3261                                                     pstate, 0);
3262                 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3263
3264                 /* y-plane */
3265                 rate = skl_plane_relative_data_rate(intel_cstate,
3266                                                     pstate, 1);
3267                 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
3268         }
3269
3270         /* Calculate CRTC's total data rate from cached values */
3271         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3272                 int id = skl_wm_plane_id(intel_plane);
3273
3274                 /* packed/uv */
3275                 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3276                 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
3277         }
3278
3279         return total_data_rate;
3280 }
3281
3282 static uint16_t
3283 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3284                   const int y)
3285 {
3286         struct drm_framebuffer *fb = pstate->fb;
3287         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3288         uint32_t src_w, src_h;
3289         uint32_t min_scanlines = 8;
3290         uint8_t plane_bpp;
3291
3292         if (WARN_ON(!fb))
3293                 return 0;
3294
3295         /* For packed formats, no y-plane, return 0 */
3296         if (y && fb->pixel_format != DRM_FORMAT_NV12)
3297                 return 0;
3298
3299         /* For Non Y-tile return 8-blocks */
3300         if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3301             fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3302                 return 8;
3303
3304         src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3305         src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
3306
3307         if (intel_rotation_90_or_270(pstate->rotation))
3308                 swap(src_w, src_h);
3309
3310         /* Halve UV plane width and height for NV12 */
3311         if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3312                 src_w /= 2;
3313                 src_h /= 2;
3314         }
3315
3316         if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3317                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3318         else
3319                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3320
3321         if (intel_rotation_90_or_270(pstate->rotation)) {
3322                 switch (plane_bpp) {
3323                 case 1:
3324                         min_scanlines = 32;
3325                         break;
3326                 case 2:
3327                         min_scanlines = 16;
3328                         break;
3329                 case 4:
3330                         min_scanlines = 8;
3331                         break;
3332                 case 8:
3333                         min_scanlines = 4;
3334                         break;
3335                 default:
3336                         WARN(1, "Unsupported pixel depth %u for rotation",
3337                              plane_bpp);
3338                         min_scanlines = 32;
3339                 }
3340         }
3341
3342         return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3343 }
3344
3345 static int
3346 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3347                       struct skl_ddb_allocation *ddb /* out */)
3348 {
3349         struct drm_atomic_state *state = cstate->base.state;
3350         struct drm_crtc *crtc = cstate->base.crtc;
3351         struct drm_device *dev = crtc->dev;
3352         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3353         struct intel_plane *intel_plane;
3354         struct drm_plane *plane;
3355         struct drm_plane_state *pstate;
3356         enum pipe pipe = intel_crtc->pipe;
3357         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
3358         uint16_t alloc_size, start, cursor_blocks;
3359         uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3360         uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
3361         unsigned int total_data_rate;
3362         int num_active;
3363         int id, i;
3364
3365         if (WARN_ON(!state))
3366                 return 0;
3367
3368         if (!cstate->base.active) {
3369                 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3370                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3371                 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3372                 return 0;
3373         }
3374
3375         skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3376         alloc_size = skl_ddb_entry_size(alloc);
3377         if (alloc_size == 0) {
3378                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3379                 return 0;
3380         }
3381
3382         cursor_blocks = skl_cursor_allocation(num_active);
3383         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3384         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3385
3386         alloc_size -= cursor_blocks;
3387
3388         /* 1. Allocate the mininum required blocks for each active plane */
3389         for_each_plane_in_state(state, plane, pstate, i) {
3390                 intel_plane = to_intel_plane(plane);
3391                 id = skl_wm_plane_id(intel_plane);
3392
3393                 if (intel_plane->pipe != pipe)
3394                         continue;
3395
3396                 if (!to_intel_plane_state(pstate)->base.visible) {
3397                         minimum[id] = 0;
3398                         y_minimum[id] = 0;
3399                         continue;
3400                 }
3401                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3402                         minimum[id] = 0;
3403                         y_minimum[id] = 0;
3404                         continue;
3405                 }
3406
3407                 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3408                 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3409         }
3410
3411         for (i = 0; i < PLANE_CURSOR; i++) {
3412                 alloc_size -= minimum[i];
3413                 alloc_size -= y_minimum[i];
3414         }
3415
3416         /*
3417          * 2. Distribute the remaining space in proportion to the amount of
3418          * data each plane needs to fetch from memory.
3419          *
3420          * FIXME: we may not allocate every single block here.
3421          */
3422         total_data_rate = skl_get_total_relative_data_rate(cstate);
3423         if (total_data_rate == 0)
3424                 return 0;
3425
3426         start = alloc->start;
3427         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3428                 unsigned int data_rate, y_data_rate;
3429                 uint16_t plane_blocks, y_plane_blocks = 0;
3430                 int id = skl_wm_plane_id(intel_plane);
3431
3432                 data_rate = cstate->wm.skl.plane_data_rate[id];
3433
3434                 /*
3435                  * allocation for (packed formats) or (uv-plane part of planar format):
3436                  * promote the expression to 64 bits to avoid overflowing, the
3437                  * result is < available as data_rate / total_data_rate < 1
3438                  */
3439                 plane_blocks = minimum[id];
3440                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3441                                         total_data_rate);
3442
3443                 /* Leave disabled planes at (0,0) */
3444                 if (data_rate) {
3445                         ddb->plane[pipe][id].start = start;
3446                         ddb->plane[pipe][id].end = start + plane_blocks;
3447                 }
3448
3449                 start += plane_blocks;
3450
3451                 /*
3452                  * allocation for y_plane part of planar format:
3453                  */
3454                 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3455
3456                 y_plane_blocks = y_minimum[id];
3457                 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3458                                         total_data_rate);
3459
3460                 if (y_data_rate) {
3461                         ddb->y_plane[pipe][id].start = start;
3462                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3463                 }
3464
3465                 start += y_plane_blocks;
3466         }
3467
3468         return 0;
3469 }
3470
3471 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3472 {
3473         /* TODO: Take into account the scalers once we support them */
3474         return config->base.adjusted_mode.crtc_clock;
3475 }
3476
3477 /*
3478  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3479  * for the read latency) and cpp should always be <= 8, so that
3480  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3481  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3482 */
3483 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3484 {
3485         uint32_t wm_intermediate_val, ret;
3486
3487         if (latency == 0)
3488                 return UINT_MAX;
3489
3490         wm_intermediate_val = latency * pixel_rate * cpp / 512;
3491         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3492
3493         return ret;
3494 }
3495
3496 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3497                                uint32_t latency, uint32_t plane_blocks_per_line)
3498 {
3499         uint32_t ret;
3500         uint32_t wm_intermediate_val;
3501
3502         if (latency == 0)
3503                 return UINT_MAX;
3504
3505         wm_intermediate_val = latency * pixel_rate;
3506         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3507                                 plane_blocks_per_line;
3508
3509         return ret;
3510 }
3511
3512 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3513                                               struct intel_plane_state *pstate)
3514 {
3515         uint64_t adjusted_pixel_rate;
3516         uint64_t downscale_amount;
3517         uint64_t pixel_rate;
3518
3519         /* Shouldn't reach here on disabled planes... */
3520         if (WARN_ON(!pstate->base.visible))
3521                 return 0;
3522
3523         /*
3524          * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3525          * with additional adjustments for plane-specific scaling.
3526          */
3527         adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
3528         downscale_amount = skl_plane_downscale_amount(pstate);
3529
3530         pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3531         WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3532
3533         return pixel_rate;
3534 }
3535
3536 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3537                                 struct intel_crtc_state *cstate,
3538                                 struct intel_plane_state *intel_pstate,
3539                                 uint16_t ddb_allocation,
3540                                 int level,
3541                                 uint16_t *out_blocks, /* out */
3542                                 uint8_t *out_lines, /* out */
3543                                 bool *enabled /* out */)
3544 {
3545         struct drm_plane_state *pstate = &intel_pstate->base;
3546         struct drm_framebuffer *fb = pstate->fb;
3547         uint32_t latency = dev_priv->wm.skl_latency[level];
3548         uint32_t method1, method2;
3549         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3550         uint32_t res_blocks, res_lines;
3551         uint32_t selected_result;
3552         uint8_t cpp;
3553         uint32_t width = 0, height = 0;
3554         uint32_t plane_pixel_rate;
3555         uint32_t y_tile_minimum, y_min_scanlines;
3556
3557         if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
3558                 *enabled = false;
3559                 return 0;
3560         }
3561
3562         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3563         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3564
3565         if (intel_rotation_90_or_270(pstate->rotation))
3566                 swap(width, height);
3567
3568         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3569         plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3570
3571         if (intel_rotation_90_or_270(pstate->rotation)) {
3572                 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3573                         drm_format_plane_cpp(fb->pixel_format, 1) :
3574                         drm_format_plane_cpp(fb->pixel_format, 0);
3575
3576                 switch (cpp) {
3577                 case 1:
3578                         y_min_scanlines = 16;
3579                         break;
3580                 case 2:
3581                         y_min_scanlines = 8;
3582                         break;
3583                 default:
3584                         WARN(1, "Unsupported pixel depth for rotation");
3585                 case 4:
3586                         y_min_scanlines = 4;
3587                         break;
3588                 }
3589         } else {
3590                 y_min_scanlines = 4;
3591         }
3592
3593         plane_bytes_per_line = width * cpp;
3594         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3595             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3596                 plane_blocks_per_line =
3597                       DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3598                 plane_blocks_per_line /= y_min_scanlines;
3599         } else if (fb->modifier[0] == DRM_FORMAT_MOD_NONE) {
3600                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3601                                         + 1;
3602         } else {
3603                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3604         }
3605
3606         method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3607         method2 = skl_wm_method2(plane_pixel_rate,
3608                                  cstate->base.adjusted_mode.crtc_htotal,
3609                                  latency,
3610                                  plane_blocks_per_line);
3611
3612         y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
3613
3614         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3615             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3616                 selected_result = max(method2, y_tile_minimum);
3617         } else {
3618                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3619                         selected_result = min(method1, method2);
3620                 else
3621                         selected_result = method1;
3622         }
3623
3624         res_blocks = selected_result + 1;
3625         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3626
3627         if (level >= 1 && level <= 7) {
3628                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3629                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3630                         res_blocks += y_tile_minimum;
3631                         res_lines += y_min_scanlines;
3632                 } else {
3633                         res_blocks++;
3634                 }
3635         }
3636
3637         if (res_blocks >= ddb_allocation || res_lines > 31) {
3638                 *enabled = false;
3639
3640                 /*
3641                  * If there are no valid level 0 watermarks, then we can't
3642                  * support this display configuration.
3643                  */
3644                 if (level) {
3645                         return 0;
3646                 } else {
3647                         DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3648                         DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3649                                       to_intel_crtc(cstate->base.crtc)->pipe,
3650                                       skl_wm_plane_id(to_intel_plane(pstate->plane)),
3651                                       res_blocks, ddb_allocation, res_lines);
3652
3653                         return -EINVAL;
3654                 }
3655         }
3656
3657         *out_blocks = res_blocks;
3658         *out_lines = res_lines;
3659         *enabled = true;
3660
3661         return 0;
3662 }
3663
3664 static int
3665 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3666                      struct skl_ddb_allocation *ddb,
3667                      struct intel_crtc_state *cstate,
3668                      int level,
3669                      struct skl_wm_level *result)
3670 {
3671         struct drm_atomic_state *state = cstate->base.state;
3672         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3673         struct drm_plane *plane;
3674         struct intel_plane *intel_plane;
3675         struct intel_plane_state *intel_pstate;
3676         uint16_t ddb_blocks;
3677         enum pipe pipe = intel_crtc->pipe;
3678         int ret;
3679
3680         /*
3681          * We'll only calculate watermarks for planes that are actually
3682          * enabled, so make sure all other planes are set as disabled.
3683          */
3684         memset(result, 0, sizeof(*result));
3685
3686         for_each_intel_plane_mask(&dev_priv->drm,
3687                                   intel_plane,
3688                                   cstate->base.plane_mask) {
3689                 int i = skl_wm_plane_id(intel_plane);
3690
3691                 plane = &intel_plane->base;
3692                 intel_pstate = NULL;
3693                 if (state)
3694                         intel_pstate =
3695                                 intel_atomic_get_existing_plane_state(state,
3696                                                                       intel_plane);
3697
3698                 /*
3699                  * Note: If we start supporting multiple pending atomic commits
3700                  * against the same planes/CRTC's in the future, plane->state
3701                  * will no longer be the correct pre-state to use for the
3702                  * calculations here and we'll need to change where we get the
3703                  * 'unchanged' plane data from.
3704                  *
3705                  * For now this is fine because we only allow one queued commit
3706                  * against a CRTC.  Even if the plane isn't modified by this
3707                  * transaction and we don't have a plane lock, we still have
3708                  * the CRTC's lock, so we know that no other transactions are
3709                  * racing with us to update it.
3710                  */
3711                 if (!intel_pstate)
3712                         intel_pstate = to_intel_plane_state(plane->state);
3713
3714                 WARN_ON(!intel_pstate->base.fb);
3715
3716                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3717
3718                 ret = skl_compute_plane_wm(dev_priv,
3719                                            cstate,
3720                                            intel_pstate,
3721                                            ddb_blocks,
3722                                            level,
3723                                            &result->plane_res_b[i],
3724                                            &result->plane_res_l[i],
3725                                            &result->plane_en[i]);
3726                 if (ret)
3727                         return ret;
3728         }
3729
3730         return 0;
3731 }
3732
3733 static uint32_t
3734 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3735 {
3736         if (!cstate->base.active)
3737                 return 0;
3738
3739         if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3740                 return 0;
3741
3742         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3743                             skl_pipe_pixel_rate(cstate));
3744 }
3745
3746 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3747                                       struct skl_wm_level *trans_wm /* out */)
3748 {
3749         struct drm_crtc *crtc = cstate->base.crtc;
3750         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3751         struct intel_plane *intel_plane;
3752
3753         if (!cstate->base.active)
3754                 return;
3755
3756         /* Until we know more, just disable transition WMs */
3757         for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3758                 int i = skl_wm_plane_id(intel_plane);
3759
3760                 trans_wm->plane_en[i] = false;
3761         }
3762 }
3763
3764 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3765                              struct skl_ddb_allocation *ddb,
3766                              struct skl_pipe_wm *pipe_wm)
3767 {
3768         struct drm_device *dev = cstate->base.crtc->dev;
3769         const struct drm_i915_private *dev_priv = to_i915(dev);
3770         int level, max_level = ilk_wm_max_level(dev);
3771         int ret;
3772
3773         for (level = 0; level <= max_level; level++) {
3774                 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3775                                            level, &pipe_wm->wm[level]);
3776                 if (ret)
3777                         return ret;
3778         }
3779         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3780
3781         skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3782
3783         return 0;
3784 }
3785
3786 static void skl_compute_wm_results(struct drm_device *dev,
3787                                    struct skl_pipe_wm *p_wm,
3788                                    struct skl_wm_values *r,
3789                                    struct intel_crtc *intel_crtc)
3790 {
3791         int level, max_level = ilk_wm_max_level(dev);
3792         enum pipe pipe = intel_crtc->pipe;
3793         uint32_t temp;
3794         int i;
3795
3796         for (level = 0; level <= max_level; level++) {
3797                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3798                         temp = 0;
3799
3800                         temp |= p_wm->wm[level].plane_res_l[i] <<
3801                                         PLANE_WM_LINES_SHIFT;
3802                         temp |= p_wm->wm[level].plane_res_b[i];
3803                         if (p_wm->wm[level].plane_en[i])
3804                                 temp |= PLANE_WM_EN;
3805
3806                         r->plane[pipe][i][level] = temp;
3807                 }
3808
3809                 temp = 0;
3810
3811                 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3812                 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3813
3814                 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3815                         temp |= PLANE_WM_EN;
3816
3817                 r->plane[pipe][PLANE_CURSOR][level] = temp;
3818
3819         }
3820
3821         /* transition WMs */
3822         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3823                 temp = 0;
3824                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3825                 temp |= p_wm->trans_wm.plane_res_b[i];
3826                 if (p_wm->trans_wm.plane_en[i])
3827                         temp |= PLANE_WM_EN;
3828
3829                 r->plane_trans[pipe][i] = temp;
3830         }
3831
3832         temp = 0;
3833         temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3834         temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3835         if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3836                 temp |= PLANE_WM_EN;
3837
3838         r->plane_trans[pipe][PLANE_CURSOR] = temp;
3839
3840         r->wm_linetime[pipe] = p_wm->linetime;
3841 }
3842
3843 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3844                                 i915_reg_t reg,
3845                                 const struct skl_ddb_entry *entry)
3846 {
3847         if (entry->end)
3848                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3849         else
3850                 I915_WRITE(reg, 0);
3851 }
3852
3853 void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3854                         const struct skl_wm_values *wm,
3855                         int plane)
3856 {
3857         struct drm_crtc *crtc = &intel_crtc->base;
3858         struct drm_device *dev = crtc->dev;
3859         struct drm_i915_private *dev_priv = to_i915(dev);
3860         int level, max_level = ilk_wm_max_level(dev);
3861         enum pipe pipe = intel_crtc->pipe;
3862
3863         for (level = 0; level <= max_level; level++) {
3864                 I915_WRITE(PLANE_WM(pipe, plane, level),
3865                            wm->plane[pipe][plane][level]);
3866         }
3867         I915_WRITE(PLANE_WM_TRANS(pipe, plane), wm->plane_trans[pipe][plane]);
3868
3869         skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
3870                             &wm->ddb.plane[pipe][plane]);
3871         skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
3872                             &wm->ddb.y_plane[pipe][plane]);
3873 }
3874
3875 void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3876                          const struct skl_wm_values *wm)
3877 {
3878         struct drm_crtc *crtc = &intel_crtc->base;
3879         struct drm_device *dev = crtc->dev;
3880         struct drm_i915_private *dev_priv = to_i915(dev);
3881         int level, max_level = ilk_wm_max_level(dev);
3882         enum pipe pipe = intel_crtc->pipe;
3883
3884         for (level = 0; level <= max_level; level++) {
3885                 I915_WRITE(CUR_WM(pipe, level),
3886                            wm->plane[pipe][PLANE_CURSOR][level]);
3887         }
3888         I915_WRITE(CUR_WM_TRANS(pipe), wm->plane_trans[pipe][PLANE_CURSOR]);
3889
3890         skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3891                             &wm->ddb.plane[pipe][PLANE_CURSOR]);
3892 }
3893
3894 bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,
3895                                const struct skl_ddb_allocation *new,
3896                                enum pipe pipe)
3897 {
3898         return new->pipe[pipe].start == old->pipe[pipe].start &&
3899                new->pipe[pipe].end == old->pipe[pipe].end;
3900 }
3901
3902 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3903                                            const struct skl_ddb_entry *b)
3904 {
3905         return a->start < b->end && b->start < a->end;
3906 }
3907
3908 bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
3909                                  const struct skl_ddb_allocation *old,
3910                                  const struct skl_ddb_allocation *new,
3911                                  enum pipe pipe)
3912 {
3913         struct drm_device *dev = state->dev;
3914         struct intel_crtc *intel_crtc;
3915         enum pipe otherp;
3916
3917         for_each_intel_crtc(dev, intel_crtc) {
3918                 otherp = intel_crtc->pipe;
3919
3920                 if (otherp == pipe)
3921                         continue;
3922
3923                 if (skl_ddb_entries_overlap(&new->pipe[pipe],
3924                                             &old->pipe[otherp]))
3925                         return true;
3926         }
3927
3928         return false;
3929 }
3930
3931 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3932                               struct skl_ddb_allocation *ddb, /* out */
3933                               struct skl_pipe_wm *pipe_wm, /* out */
3934                               bool *changed /* out */)
3935 {
3936         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3937         struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3938         int ret;
3939
3940         ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3941         if (ret)
3942                 return ret;
3943
3944         if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3945                 *changed = false;
3946         else
3947                 *changed = true;
3948
3949         return 0;
3950 }
3951
3952 static uint32_t
3953 pipes_modified(struct drm_atomic_state *state)
3954 {
3955         struct drm_crtc *crtc;
3956         struct drm_crtc_state *cstate;
3957         uint32_t i, ret = 0;
3958
3959         for_each_crtc_in_state(state, crtc, cstate, i)
3960                 ret |= drm_crtc_mask(crtc);
3961
3962         return ret;
3963 }
3964
3965 int
3966 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3967 {
3968         struct drm_atomic_state *state = cstate->base.state;
3969         struct drm_device *dev = state->dev;
3970         struct drm_crtc *crtc = cstate->base.crtc;
3971         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3972         struct drm_i915_private *dev_priv = to_i915(dev);
3973         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3974         struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3975         struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3976         struct drm_plane_state *plane_state;
3977         struct drm_plane *plane;
3978         enum pipe pipe = intel_crtc->pipe;
3979         int id;
3980
3981         WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3982
3983         drm_for_each_plane_mask(plane, dev, crtc->state->plane_mask) {
3984                 id = skl_wm_plane_id(to_intel_plane(plane));
3985
3986                 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
3987                                         &new_ddb->plane[pipe][id]) &&
3988                     skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
3989                                         &new_ddb->y_plane[pipe][id]))
3990                         continue;
3991
3992                 plane_state = drm_atomic_get_plane_state(state, plane);
3993                 if (IS_ERR(plane_state))
3994                         return PTR_ERR(plane_state);
3995         }
3996
3997         return 0;
3998 }
3999
4000 static int
4001 skl_compute_ddb(struct drm_atomic_state *state)
4002 {
4003         struct drm_device *dev = state->dev;
4004         struct drm_i915_private *dev_priv = to_i915(dev);
4005         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4006         struct intel_crtc *intel_crtc;
4007         struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
4008         uint32_t realloc_pipes = pipes_modified(state);
4009         int ret;
4010
4011         /*
4012          * If this is our first atomic update following hardware readout,
4013          * we can't trust the DDB that the BIOS programmed for us.  Let's
4014          * pretend that all pipes switched active status so that we'll
4015          * ensure a full DDB recompute.
4016          */
4017         if (dev_priv->wm.distrust_bios_wm) {
4018                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4019                                        state->acquire_ctx);
4020                 if (ret)
4021                         return ret;
4022
4023                 intel_state->active_pipe_changes = ~0;
4024
4025                 /*
4026                  * We usually only initialize intel_state->active_crtcs if we
4027                  * we're doing a modeset; make sure this field is always
4028                  * initialized during the sanitization process that happens
4029                  * on the first commit too.
4030                  */
4031                 if (!intel_state->modeset)
4032                         intel_state->active_crtcs = dev_priv->active_crtcs;
4033         }
4034
4035         /*
4036          * If the modeset changes which CRTC's are active, we need to
4037          * recompute the DDB allocation for *all* active pipes, even
4038          * those that weren't otherwise being modified in any way by this
4039          * atomic commit.  Due to the shrinking of the per-pipe allocations
4040          * when new active CRTC's are added, it's possible for a pipe that
4041          * we were already using and aren't changing at all here to suddenly
4042          * become invalid if its DDB needs exceeds its new allocation.
4043          *
4044          * Note that if we wind up doing a full DDB recompute, we can't let
4045          * any other display updates race with this transaction, so we need
4046          * to grab the lock on *all* CRTC's.
4047          */
4048         if (intel_state->active_pipe_changes) {
4049                 realloc_pipes = ~0;
4050                 intel_state->wm_results.dirty_pipes = ~0;
4051         }
4052
4053         for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4054                 struct intel_crtc_state *cstate;
4055
4056                 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4057                 if (IS_ERR(cstate))
4058                         return PTR_ERR(cstate);
4059
4060                 ret = skl_allocate_pipe_ddb(cstate, ddb);
4061                 if (ret)
4062                         return ret;
4063
4064                 ret = skl_ddb_add_affected_planes(cstate);
4065                 if (ret)
4066                         return ret;
4067         }
4068
4069         return 0;
4070 }
4071
4072 static void
4073 skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4074                      struct skl_wm_values *src,
4075                      enum pipe pipe)
4076 {
4077         dst->wm_linetime[pipe] = src->wm_linetime[pipe];
4078         memcpy(dst->plane[pipe], src->plane[pipe],
4079                sizeof(dst->plane[pipe]));
4080         memcpy(dst->plane_trans[pipe], src->plane_trans[pipe],
4081                sizeof(dst->plane_trans[pipe]));
4082
4083         dst->ddb.pipe[pipe] = src->ddb.pipe[pipe];
4084         memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4085                sizeof(dst->ddb.y_plane[pipe]));
4086         memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4087                sizeof(dst->ddb.plane[pipe]));
4088 }
4089
4090 static int
4091 skl_compute_wm(struct drm_atomic_state *state)
4092 {
4093         struct drm_crtc *crtc;
4094         struct drm_crtc_state *cstate;
4095         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4096         struct skl_wm_values *results = &intel_state->wm_results;
4097         struct skl_pipe_wm *pipe_wm;
4098         bool changed = false;
4099         int ret, i;
4100
4101         /*
4102          * If this transaction isn't actually touching any CRTC's, don't
4103          * bother with watermark calculation.  Note that if we pass this
4104          * test, we're guaranteed to hold at least one CRTC state mutex,
4105          * which means we can safely use values like dev_priv->active_crtcs
4106          * since any racing commits that want to update them would need to
4107          * hold _all_ CRTC state mutexes.
4108          */
4109         for_each_crtc_in_state(state, crtc, cstate, i)
4110                 changed = true;
4111         if (!changed)
4112                 return 0;
4113
4114         /* Clear all dirty flags */
4115         results->dirty_pipes = 0;
4116
4117         ret = skl_compute_ddb(state);
4118         if (ret)
4119                 return ret;
4120
4121         /*
4122          * Calculate WM's for all pipes that are part of this transaction.
4123          * Note that the DDB allocation above may have added more CRTC's that
4124          * weren't otherwise being modified (and set bits in dirty_pipes) if
4125          * pipe allocations had to change.
4126          *
4127          * FIXME:  Now that we're doing this in the atomic check phase, we
4128          * should allow skl_update_pipe_wm() to return failure in cases where
4129          * no suitable watermark values can be found.
4130          */
4131         for_each_crtc_in_state(state, crtc, cstate, i) {
4132                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4133                 struct intel_crtc_state *intel_cstate =
4134                         to_intel_crtc_state(cstate);
4135
4136                 pipe_wm = &intel_cstate->wm.skl.optimal;
4137                 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
4138                                          &changed);
4139                 if (ret)
4140                         return ret;
4141
4142                 if (changed)
4143                         results->dirty_pipes |= drm_crtc_mask(crtc);
4144
4145                 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4146                         /* This pipe's WM's did not change */
4147                         continue;
4148
4149                 intel_cstate->update_wm_pre = true;
4150                 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
4151         }
4152
4153         return 0;
4154 }
4155
4156 static void skl_update_wm(struct drm_crtc *crtc)
4157 {
4158         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4159         struct drm_device *dev = crtc->dev;
4160         struct drm_i915_private *dev_priv = to_i915(dev);
4161         struct skl_wm_values *results = &dev_priv->wm.skl_results;
4162         struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4163         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4164         struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
4165         enum pipe pipe = intel_crtc->pipe;
4166
4167         if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4168                 return;
4169
4170         intel_crtc->wm.active.skl = *pipe_wm;
4171
4172         mutex_lock(&dev_priv->wm.wm_mutex);
4173
4174         /*
4175          * If this pipe isn't active already, we're going to be enabling it
4176          * very soon. Since it's safe to update a pipe's ddb allocation while
4177          * the pipe's shut off, just do so here. Already active pipes will have
4178          * their watermarks updated once we update their planes.
4179          */
4180         if (crtc->state->active_changed) {
4181                 int plane;
4182
4183                 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++)
4184                         skl_write_plane_wm(intel_crtc, results, plane);
4185
4186                 skl_write_cursor_wm(intel_crtc, results);
4187         }
4188
4189         skl_copy_wm_for_pipe(hw_vals, results, pipe);
4190
4191         mutex_unlock(&dev_priv->wm.wm_mutex);
4192 }
4193
4194 static void ilk_compute_wm_config(struct drm_device *dev,
4195                                   struct intel_wm_config *config)
4196 {
4197         struct intel_crtc *crtc;
4198
4199         /* Compute the currently _active_ config */
4200         for_each_intel_crtc(dev, crtc) {
4201                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4202
4203                 if (!wm->pipe_enabled)
4204                         continue;
4205
4206                 config->sprites_enabled |= wm->sprites_enabled;
4207                 config->sprites_scaled |= wm->sprites_scaled;
4208                 config->num_pipes_active++;
4209         }
4210 }
4211
4212 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4213 {
4214         struct drm_device *dev = &dev_priv->drm;
4215         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4216         struct ilk_wm_maximums max;
4217         struct intel_wm_config config = {};
4218         struct ilk_wm_values results = {};
4219         enum intel_ddb_partitioning partitioning;
4220
4221         ilk_compute_wm_config(dev, &config);
4222
4223         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4224         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4225
4226         /* 5/6 split only in single pipe config on IVB+ */
4227         if (INTEL_INFO(dev)->gen >= 7 &&
4228             config.num_pipes_active == 1 && config.sprites_enabled) {
4229                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4230                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4231
4232                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4233         } else {
4234                 best_lp_wm = &lp_wm_1_2;
4235         }
4236
4237         partitioning = (best_lp_wm == &lp_wm_1_2) ?
4238                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4239
4240         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4241
4242         ilk_write_wm_values(dev_priv, &results);
4243 }
4244
4245 static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
4246 {
4247         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4248         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4249
4250         mutex_lock(&dev_priv->wm.wm_mutex);
4251         intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4252         ilk_program_watermarks(dev_priv);
4253         mutex_unlock(&dev_priv->wm.wm_mutex);
4254 }
4255
4256 static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4257 {
4258         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4259         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4260
4261         mutex_lock(&dev_priv->wm.wm_mutex);
4262         if (cstate->wm.need_postvbl_update) {
4263                 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4264                 ilk_program_watermarks(dev_priv);
4265         }
4266         mutex_unlock(&dev_priv->wm.wm_mutex);
4267 }
4268
4269 static void skl_pipe_wm_active_state(uint32_t val,
4270                                      struct skl_pipe_wm *active,
4271                                      bool is_transwm,
4272                                      bool is_cursor,
4273                                      int i,
4274                                      int level)
4275 {
4276         bool is_enabled = (val & PLANE_WM_EN) != 0;
4277
4278         if (!is_transwm) {
4279                 if (!is_cursor) {
4280                         active->wm[level].plane_en[i] = is_enabled;
4281                         active->wm[level].plane_res_b[i] =
4282                                         val & PLANE_WM_BLOCKS_MASK;
4283                         active->wm[level].plane_res_l[i] =
4284                                         (val >> PLANE_WM_LINES_SHIFT) &
4285                                                 PLANE_WM_LINES_MASK;
4286                 } else {
4287                         active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
4288                         active->wm[level].plane_res_b[PLANE_CURSOR] =
4289                                         val & PLANE_WM_BLOCKS_MASK;
4290                         active->wm[level].plane_res_l[PLANE_CURSOR] =
4291                                         (val >> PLANE_WM_LINES_SHIFT) &
4292                                                 PLANE_WM_LINES_MASK;
4293                 }
4294         } else {
4295                 if (!is_cursor) {
4296                         active->trans_wm.plane_en[i] = is_enabled;
4297                         active->trans_wm.plane_res_b[i] =
4298                                         val & PLANE_WM_BLOCKS_MASK;
4299                         active->trans_wm.plane_res_l[i] =
4300                                         (val >> PLANE_WM_LINES_SHIFT) &
4301                                                 PLANE_WM_LINES_MASK;
4302                 } else {
4303                         active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
4304                         active->trans_wm.plane_res_b[PLANE_CURSOR] =
4305                                         val & PLANE_WM_BLOCKS_MASK;
4306                         active->trans_wm.plane_res_l[PLANE_CURSOR] =
4307                                         (val >> PLANE_WM_LINES_SHIFT) &
4308                                                 PLANE_WM_LINES_MASK;
4309                 }
4310         }
4311 }
4312
4313 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4314 {
4315         struct drm_device *dev = crtc->dev;
4316         struct drm_i915_private *dev_priv = to_i915(dev);
4317         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4318         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4319         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4320         struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
4321         enum pipe pipe = intel_crtc->pipe;
4322         int level, i, max_level;
4323         uint32_t temp;
4324
4325         max_level = ilk_wm_max_level(dev);
4326
4327         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4328
4329         for (level = 0; level <= max_level; level++) {
4330                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4331                         hw->plane[pipe][i][level] =
4332                                         I915_READ(PLANE_WM(pipe, i, level));
4333                 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
4334         }
4335
4336         for (i = 0; i < intel_num_planes(intel_crtc); i++)
4337                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4338         hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
4339
4340         if (!intel_crtc->active)
4341                 return;
4342
4343         hw->dirty_pipes |= drm_crtc_mask(crtc);
4344
4345         active->linetime = hw->wm_linetime[pipe];
4346
4347         for (level = 0; level <= max_level; level++) {
4348                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4349                         temp = hw->plane[pipe][i][level];
4350                         skl_pipe_wm_active_state(temp, active, false,
4351                                                 false, i, level);
4352                 }
4353                 temp = hw->plane[pipe][PLANE_CURSOR][level];
4354                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4355         }
4356
4357         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4358                 temp = hw->plane_trans[pipe][i];
4359                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4360         }
4361
4362         temp = hw->plane_trans[pipe][PLANE_CURSOR];
4363         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4364
4365         intel_crtc->wm.active.skl = *active;
4366 }
4367
4368 void skl_wm_get_hw_state(struct drm_device *dev)
4369 {
4370         struct drm_i915_private *dev_priv = to_i915(dev);
4371         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4372         struct drm_crtc *crtc;
4373
4374         skl_ddb_get_hw_state(dev_priv, ddb);
4375         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4376                 skl_pipe_wm_get_hw_state(crtc);
4377
4378         if (dev_priv->active_crtcs) {
4379                 /* Fully recompute DDB on first atomic commit */
4380                 dev_priv->wm.distrust_bios_wm = true;
4381         } else {
4382                 /* Easy/common case; just sanitize DDB now if everything off */
4383                 memset(ddb, 0, sizeof(*ddb));
4384         }
4385 }
4386
4387 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4388 {
4389         struct drm_device *dev = crtc->dev;
4390         struct drm_i915_private *dev_priv = to_i915(dev);
4391         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4392         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4393         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4394         struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4395         enum pipe pipe = intel_crtc->pipe;
4396         static const i915_reg_t wm0_pipe_reg[] = {
4397                 [PIPE_A] = WM0_PIPEA_ILK,
4398                 [PIPE_B] = WM0_PIPEB_ILK,
4399                 [PIPE_C] = WM0_PIPEC_IVB,
4400         };
4401
4402         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4403         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4404                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4405
4406         memset(active, 0, sizeof(*active));
4407
4408         active->pipe_enabled = intel_crtc->active;
4409
4410         if (active->pipe_enabled) {
4411                 u32 tmp = hw->wm_pipe[pipe];
4412
4413                 /*
4414                  * For active pipes LP0 watermark is marked as
4415                  * enabled, and LP1+ watermaks as disabled since
4416                  * we can't really reverse compute them in case
4417                  * multiple pipes are active.
4418                  */
4419                 active->wm[0].enable = true;
4420                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4421                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4422                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4423                 active->linetime = hw->wm_linetime[pipe];
4424         } else {
4425                 int level, max_level = ilk_wm_max_level(dev);
4426
4427                 /*
4428                  * For inactive pipes, all watermark levels
4429                  * should be marked as enabled but zeroed,
4430                  * which is what we'd compute them to.
4431                  */
4432                 for (level = 0; level <= max_level; level++)
4433                         active->wm[level].enable = true;
4434         }
4435
4436         intel_crtc->wm.active.ilk = *active;
4437 }
4438
4439 #define _FW_WM(value, plane) \
4440         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4441 #define _FW_WM_VLV(value, plane) \
4442         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4443
4444 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4445                                struct vlv_wm_values *wm)
4446 {
4447         enum pipe pipe;
4448         uint32_t tmp;
4449
4450         for_each_pipe(dev_priv, pipe) {
4451                 tmp = I915_READ(VLV_DDL(pipe));
4452
4453                 wm->ddl[pipe].primary =
4454                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4455                 wm->ddl[pipe].cursor =
4456                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4457                 wm->ddl[pipe].sprite[0] =
4458                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4459                 wm->ddl[pipe].sprite[1] =
4460                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4461         }
4462
4463         tmp = I915_READ(DSPFW1);
4464         wm->sr.plane = _FW_WM(tmp, SR);
4465         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4466         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4467         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4468
4469         tmp = I915_READ(DSPFW2);
4470         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4471         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4472         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4473
4474         tmp = I915_READ(DSPFW3);
4475         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4476
4477         if (IS_CHERRYVIEW(dev_priv)) {
4478                 tmp = I915_READ(DSPFW7_CHV);
4479                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4480                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4481
4482                 tmp = I915_READ(DSPFW8_CHV);
4483                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4484                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4485
4486                 tmp = I915_READ(DSPFW9_CHV);
4487                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4488                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4489
4490                 tmp = I915_READ(DSPHOWM);
4491                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4492                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4493                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4494                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4495                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4496                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4497                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4498                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4499                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4500                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4501         } else {
4502                 tmp = I915_READ(DSPFW7);
4503                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4504                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4505
4506                 tmp = I915_READ(DSPHOWM);
4507                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4508                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4509                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4510                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4511                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4512                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4513                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4514         }
4515 }
4516
4517 #undef _FW_WM
4518 #undef _FW_WM_VLV
4519
4520 void vlv_wm_get_hw_state(struct drm_device *dev)
4521 {
4522         struct drm_i915_private *dev_priv = to_i915(dev);
4523         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4524         struct intel_plane *plane;
4525         enum pipe pipe;
4526         u32 val;
4527
4528         vlv_read_wm_values(dev_priv, wm);
4529
4530         for_each_intel_plane(dev, plane) {
4531                 switch (plane->base.type) {
4532                         int sprite;
4533                 case DRM_PLANE_TYPE_CURSOR:
4534                         plane->wm.fifo_size = 63;
4535                         break;
4536                 case DRM_PLANE_TYPE_PRIMARY:
4537                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4538                         break;
4539                 case DRM_PLANE_TYPE_OVERLAY:
4540                         sprite = plane->plane;
4541                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4542                         break;
4543                 }
4544         }
4545
4546         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4547         wm->level = VLV_WM_LEVEL_PM2;
4548
4549         if (IS_CHERRYVIEW(dev_priv)) {
4550                 mutex_lock(&dev_priv->rps.hw_lock);
4551
4552                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4553                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4554                         wm->level = VLV_WM_LEVEL_PM5;
4555
4556                 /*
4557                  * If DDR DVFS is disabled in the BIOS, Punit
4558                  * will never ack the request. So if that happens
4559                  * assume we don't have to enable/disable DDR DVFS
4560                  * dynamically. To test that just set the REQ_ACK
4561                  * bit to poke the Punit, but don't change the
4562                  * HIGH/LOW bits so that we don't actually change
4563                  * the current state.
4564                  */
4565                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4566                 val |= FORCE_DDR_FREQ_REQ_ACK;
4567                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4568
4569                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4570                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4571                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4572                                       "assuming DDR DVFS is disabled\n");
4573                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4574                 } else {
4575                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4576                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4577                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4578                 }
4579
4580                 mutex_unlock(&dev_priv->rps.hw_lock);
4581         }
4582
4583         for_each_pipe(dev_priv, pipe)
4584                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4585                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4586                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4587
4588         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4589                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4590 }
4591
4592 void ilk_wm_get_hw_state(struct drm_device *dev)
4593 {
4594         struct drm_i915_private *dev_priv = to_i915(dev);
4595         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4596         struct drm_crtc *crtc;
4597
4598         for_each_crtc(dev, crtc)
4599                 ilk_pipe_wm_get_hw_state(crtc);
4600
4601         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4602         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4603         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4604
4605         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4606         if (INTEL_INFO(dev)->gen >= 7) {
4607                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4608                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4609         }
4610
4611         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4612                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4613                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4614         else if (IS_IVYBRIDGE(dev))
4615                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4616                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4617
4618         hw->enable_fbc_wm =
4619                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4620 }
4621
4622 /**
4623  * intel_update_watermarks - update FIFO watermark values based on current modes
4624  *
4625  * Calculate watermark values for the various WM regs based on current mode
4626  * and plane configuration.
4627  *
4628  * There are several cases to deal with here:
4629  *   - normal (i.e. non-self-refresh)
4630  *   - self-refresh (SR) mode
4631  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4632  *   - lines are small relative to FIFO size (buffer can hold more than 2
4633  *     lines), so need to account for TLB latency
4634  *
4635  *   The normal calculation is:
4636  *     watermark = dotclock * bytes per pixel * latency
4637  *   where latency is platform & configuration dependent (we assume pessimal
4638  *   values here).
4639  *
4640  *   The SR calculation is:
4641  *     watermark = (trunc(latency/line time)+1) * surface width *
4642  *       bytes per pixel
4643  *   where
4644  *     line time = htotal / dotclock
4645  *     surface width = hdisplay for normal plane and 64 for cursor
4646  *   and latency is assumed to be high, as above.
4647  *
4648  * The final value programmed to the register should always be rounded up,
4649  * and include an extra 2 entries to account for clock crossings.
4650  *
4651  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4652  * to set the non-SR watermarks to 8.
4653  */
4654 void intel_update_watermarks(struct drm_crtc *crtc)
4655 {
4656         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4657
4658         if (dev_priv->display.update_wm)
4659                 dev_priv->display.update_wm(crtc);
4660 }
4661
4662 /*
4663  * Lock protecting IPS related data structures
4664  */
4665 DEFINE_SPINLOCK(mchdev_lock);
4666
4667 /* Global for IPS driver to get at the current i915 device. Protected by
4668  * mchdev_lock. */
4669 static struct drm_i915_private *i915_mch_dev;
4670
4671 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4672 {
4673         u16 rgvswctl;
4674
4675         assert_spin_locked(&mchdev_lock);
4676
4677         rgvswctl = I915_READ16(MEMSWCTL);
4678         if (rgvswctl & MEMCTL_CMD_STS) {
4679                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4680                 return false; /* still busy with another command */
4681         }
4682
4683         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4684                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4685         I915_WRITE16(MEMSWCTL, rgvswctl);
4686         POSTING_READ16(MEMSWCTL);
4687
4688         rgvswctl |= MEMCTL_CMD_STS;
4689         I915_WRITE16(MEMSWCTL, rgvswctl);
4690
4691         return true;
4692 }
4693
4694 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4695 {
4696         u32 rgvmodectl;
4697         u8 fmax, fmin, fstart, vstart;
4698
4699         spin_lock_irq(&mchdev_lock);
4700
4701         rgvmodectl = I915_READ(MEMMODECTL);
4702
4703         /* Enable temp reporting */
4704         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4705         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4706
4707         /* 100ms RC evaluation intervals */
4708         I915_WRITE(RCUPEI, 100000);
4709         I915_WRITE(RCDNEI, 100000);
4710
4711         /* Set max/min thresholds to 90ms and 80ms respectively */
4712         I915_WRITE(RCBMAXAVG, 90000);
4713         I915_WRITE(RCBMINAVG, 80000);
4714
4715         I915_WRITE(MEMIHYST, 1);
4716
4717         /* Set up min, max, and cur for interrupt handling */
4718         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4719         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4720         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4721                 MEMMODE_FSTART_SHIFT;
4722
4723         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4724                 PXVFREQ_PX_SHIFT;
4725
4726         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4727         dev_priv->ips.fstart = fstart;
4728
4729         dev_priv->ips.max_delay = fstart;
4730         dev_priv->ips.min_delay = fmin;
4731         dev_priv->ips.cur_delay = fstart;
4732
4733         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4734                          fmax, fmin, fstart);
4735
4736         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4737
4738         /*
4739          * Interrupts will be enabled in ironlake_irq_postinstall
4740          */
4741
4742         I915_WRITE(VIDSTART, vstart);
4743         POSTING_READ(VIDSTART);
4744
4745         rgvmodectl |= MEMMODE_SWMODE_EN;
4746         I915_WRITE(MEMMODECTL, rgvmodectl);
4747
4748         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4749                 DRM_ERROR("stuck trying to change perf mode\n");
4750         mdelay(1);
4751
4752         ironlake_set_drps(dev_priv, fstart);
4753
4754         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4755                 I915_READ(DDREC) + I915_READ(CSIEC);
4756         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4757         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4758         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4759
4760         spin_unlock_irq(&mchdev_lock);
4761 }
4762
4763 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4764 {
4765         u16 rgvswctl;
4766
4767         spin_lock_irq(&mchdev_lock);
4768
4769         rgvswctl = I915_READ16(MEMSWCTL);
4770
4771         /* Ack interrupts, disable EFC interrupt */
4772         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4773         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4774         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4775         I915_WRITE(DEIIR, DE_PCU_EVENT);
4776         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4777
4778         /* Go back to the starting frequency */
4779         ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4780         mdelay(1);
4781         rgvswctl |= MEMCTL_CMD_STS;
4782         I915_WRITE(MEMSWCTL, rgvswctl);
4783         mdelay(1);
4784
4785         spin_unlock_irq(&mchdev_lock);
4786 }
4787
4788 /* There's a funny hw issue where the hw returns all 0 when reading from
4789  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4790  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4791  * all limits and the gpu stuck at whatever frequency it is at atm).
4792  */
4793 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4794 {
4795         u32 limits;
4796
4797         /* Only set the down limit when we've reached the lowest level to avoid
4798          * getting more interrupts, otherwise leave this clear. This prevents a
4799          * race in the hw when coming out of rc6: There's a tiny window where
4800          * the hw runs at the minimal clock before selecting the desired
4801          * frequency, if the down threshold expires in that window we will not
4802          * receive a down interrupt. */
4803         if (IS_GEN9(dev_priv)) {
4804                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4805                 if (val <= dev_priv->rps.min_freq_softlimit)
4806                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4807         } else {
4808                 limits = dev_priv->rps.max_freq_softlimit << 24;
4809                 if (val <= dev_priv->rps.min_freq_softlimit)
4810                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4811         }
4812
4813         return limits;
4814 }
4815
4816 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4817 {
4818         int new_power;
4819         u32 threshold_up = 0, threshold_down = 0; /* in % */
4820         u32 ei_up = 0, ei_down = 0;
4821
4822         new_power = dev_priv->rps.power;
4823         switch (dev_priv->rps.power) {
4824         case LOW_POWER:
4825                 if (val > dev_priv->rps.efficient_freq + 1 &&
4826                     val > dev_priv->rps.cur_freq)
4827                         new_power = BETWEEN;
4828                 break;
4829
4830         case BETWEEN:
4831                 if (val <= dev_priv->rps.efficient_freq &&
4832                     val < dev_priv->rps.cur_freq)
4833                         new_power = LOW_POWER;
4834                 else if (val >= dev_priv->rps.rp0_freq &&
4835                          val > dev_priv->rps.cur_freq)
4836                         new_power = HIGH_POWER;
4837                 break;
4838
4839         case HIGH_POWER:
4840                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4841                     val < dev_priv->rps.cur_freq)
4842                         new_power = BETWEEN;
4843                 break;
4844         }
4845         /* Max/min bins are special */
4846         if (val <= dev_priv->rps.min_freq_softlimit)
4847                 new_power = LOW_POWER;
4848         if (val >= dev_priv->rps.max_freq_softlimit)
4849                 new_power = HIGH_POWER;
4850         if (new_power == dev_priv->rps.power)
4851                 return;
4852
4853         /* Note the units here are not exactly 1us, but 1280ns. */
4854         switch (new_power) {
4855         case LOW_POWER:
4856                 /* Upclock if more than 95% busy over 16ms */
4857                 ei_up = 16000;
4858                 threshold_up = 95;
4859
4860                 /* Downclock if less than 85% busy over 32ms */
4861                 ei_down = 32000;
4862                 threshold_down = 85;
4863                 break;
4864
4865         case BETWEEN:
4866                 /* Upclock if more than 90% busy over 13ms */
4867                 ei_up = 13000;
4868                 threshold_up = 90;
4869
4870                 /* Downclock if less than 75% busy over 32ms */
4871                 ei_down = 32000;
4872                 threshold_down = 75;
4873                 break;
4874
4875         case HIGH_POWER:
4876                 /* Upclock if more than 85% busy over 10ms */
4877                 ei_up = 10000;
4878                 threshold_up = 85;
4879
4880                 /* Downclock if less than 60% busy over 32ms */
4881                 ei_down = 32000;
4882                 threshold_down = 60;
4883                 break;
4884         }
4885
4886         I915_WRITE(GEN6_RP_UP_EI,
4887                    GT_INTERVAL_FROM_US(dev_priv, ei_up));
4888         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4889                    GT_INTERVAL_FROM_US(dev_priv,
4890                                        ei_up * threshold_up / 100));
4891
4892         I915_WRITE(GEN6_RP_DOWN_EI,
4893                    GT_INTERVAL_FROM_US(dev_priv, ei_down));
4894         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4895                    GT_INTERVAL_FROM_US(dev_priv,
4896                                        ei_down * threshold_down / 100));
4897
4898         I915_WRITE(GEN6_RP_CONTROL,
4899                    GEN6_RP_MEDIA_TURBO |
4900                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4901                    GEN6_RP_MEDIA_IS_GFX |
4902                    GEN6_RP_ENABLE |
4903                    GEN6_RP_UP_BUSY_AVG |
4904                    GEN6_RP_DOWN_IDLE_AVG);
4905
4906         dev_priv->rps.power = new_power;
4907         dev_priv->rps.up_threshold = threshold_up;
4908         dev_priv->rps.down_threshold = threshold_down;
4909         dev_priv->rps.last_adj = 0;
4910 }
4911
4912 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4913 {
4914         u32 mask = 0;
4915
4916         if (val > dev_priv->rps.min_freq_softlimit)
4917                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4918         if (val < dev_priv->rps.max_freq_softlimit)
4919                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4920
4921         mask &= dev_priv->pm_rps_events;
4922
4923         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4924 }
4925
4926 /* gen6_set_rps is called to update the frequency request, but should also be
4927  * called when the range (min_delay and max_delay) is modified so that we can
4928  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4929 static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4930 {
4931         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4932         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4933                 return;
4934
4935         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4936         WARN_ON(val > dev_priv->rps.max_freq);
4937         WARN_ON(val < dev_priv->rps.min_freq);
4938
4939         /* min/max delay may still have been modified so be sure to
4940          * write the limits value.
4941          */
4942         if (val != dev_priv->rps.cur_freq) {
4943                 gen6_set_rps_thresholds(dev_priv, val);
4944
4945                 if (IS_GEN9(dev_priv))
4946                         I915_WRITE(GEN6_RPNSWREQ,
4947                                    GEN9_FREQUENCY(val));
4948                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4949                         I915_WRITE(GEN6_RPNSWREQ,
4950                                    HSW_FREQUENCY(val));
4951                 else
4952                         I915_WRITE(GEN6_RPNSWREQ,
4953                                    GEN6_FREQUENCY(val) |
4954                                    GEN6_OFFSET(0) |
4955                                    GEN6_AGGRESSIVE_TURBO);
4956         }
4957
4958         /* Make sure we continue to get interrupts
4959          * until we hit the minimum or maximum frequencies.
4960          */
4961         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4962         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4963
4964         POSTING_READ(GEN6_RPNSWREQ);
4965
4966         dev_priv->rps.cur_freq = val;
4967         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4968 }
4969
4970 static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4971 {
4972         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4973         WARN_ON(val > dev_priv->rps.max_freq);
4974         WARN_ON(val < dev_priv->rps.min_freq);
4975
4976         if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4977                       "Odd GPU freq value\n"))
4978                 val &= ~1;
4979
4980         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4981
4982         if (val != dev_priv->rps.cur_freq) {
4983                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4984                 if (!IS_CHERRYVIEW(dev_priv))
4985                         gen6_set_rps_thresholds(dev_priv, val);
4986         }
4987
4988         dev_priv->rps.cur_freq = val;
4989         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4990 }
4991
4992 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4993  *
4994  * * If Gfx is Idle, then
4995  * 1. Forcewake Media well.
4996  * 2. Request idle freq.
4997  * 3. Release Forcewake of Media well.
4998 */
4999 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5000 {
5001         u32 val = dev_priv->rps.idle_freq;
5002
5003         if (dev_priv->rps.cur_freq <= val)
5004                 return;
5005
5006         /* Wake up the media well, as that takes a lot less
5007          * power than the Render well. */
5008         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
5009         valleyview_set_rps(dev_priv, val);
5010         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
5011 }
5012
5013 void gen6_rps_busy(struct drm_i915_private *dev_priv)
5014 {
5015         mutex_lock(&dev_priv->rps.hw_lock);
5016         if (dev_priv->rps.enabled) {
5017                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5018                         gen6_rps_reset_ei(dev_priv);
5019                 I915_WRITE(GEN6_PMINTRMSK,
5020                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
5021
5022                 gen6_enable_rps_interrupts(dev_priv);
5023
5024                 /* Ensure we start at the user's desired frequency */
5025                 intel_set_rps(dev_priv,
5026                               clamp(dev_priv->rps.cur_freq,
5027                                     dev_priv->rps.min_freq_softlimit,
5028                                     dev_priv->rps.max_freq_softlimit));
5029         }
5030         mutex_unlock(&dev_priv->rps.hw_lock);
5031 }
5032
5033 void gen6_rps_idle(struct drm_i915_private *dev_priv)
5034 {
5035         /* Flush our bottom-half so that it does not race with us
5036          * setting the idle frequency and so that it is bounded by
5037          * our rpm wakeref. And then disable the interrupts to stop any
5038          * futher RPS reclocking whilst we are asleep.
5039          */
5040         gen6_disable_rps_interrupts(dev_priv);
5041
5042         mutex_lock(&dev_priv->rps.hw_lock);
5043         if (dev_priv->rps.enabled) {
5044                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5045                         vlv_set_rps_idle(dev_priv);
5046                 else
5047                         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5048                 dev_priv->rps.last_adj = 0;
5049                 I915_WRITE(GEN6_PMINTRMSK,
5050                            gen6_sanitize_rps_pm_mask(dev_priv, ~0));
5051         }
5052         mutex_unlock(&dev_priv->rps.hw_lock);
5053
5054         spin_lock(&dev_priv->rps.client_lock);
5055         while (!list_empty(&dev_priv->rps.clients))
5056                 list_del_init(dev_priv->rps.clients.next);
5057         spin_unlock(&dev_priv->rps.client_lock);
5058 }
5059
5060 void gen6_rps_boost(struct drm_i915_private *dev_priv,
5061                     struct intel_rps_client *rps,
5062                     unsigned long submitted)
5063 {
5064         /* This is intentionally racy! We peek at the state here, then
5065          * validate inside the RPS worker.
5066          */
5067         if (!(dev_priv->gt.awake &&
5068               dev_priv->rps.enabled &&
5069               dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
5070                 return;
5071
5072         /* Force a RPS boost (and don't count it against the client) if
5073          * the GPU is severely congested.
5074          */
5075         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
5076                 rps = NULL;
5077
5078         spin_lock(&dev_priv->rps.client_lock);
5079         if (rps == NULL || list_empty(&rps->link)) {
5080                 spin_lock_irq(&dev_priv->irq_lock);
5081                 if (dev_priv->rps.interrupts_enabled) {
5082                         dev_priv->rps.client_boost = true;
5083                         schedule_work(&dev_priv->rps.work);
5084                 }
5085                 spin_unlock_irq(&dev_priv->irq_lock);
5086
5087                 if (rps != NULL) {
5088                         list_add(&rps->link, &dev_priv->rps.clients);
5089                         rps->boosts++;
5090                 } else
5091                         dev_priv->rps.boosts++;
5092         }
5093         spin_unlock(&dev_priv->rps.client_lock);
5094 }
5095
5096 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
5097 {
5098         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5099                 valleyview_set_rps(dev_priv, val);
5100         else
5101                 gen6_set_rps(dev_priv, val);
5102 }
5103
5104 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
5105 {
5106         I915_WRITE(GEN6_RC_CONTROL, 0);
5107         I915_WRITE(GEN9_PG_ENABLE, 0);
5108 }
5109
5110 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
5111 {
5112         I915_WRITE(GEN6_RP_CONTROL, 0);
5113 }
5114
5115 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
5116 {
5117         I915_WRITE(GEN6_RC_CONTROL, 0);
5118         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
5119         I915_WRITE(GEN6_RP_CONTROL, 0);
5120 }
5121
5122 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
5123 {
5124         I915_WRITE(GEN6_RC_CONTROL, 0);
5125 }
5126
5127 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
5128 {
5129         /* we're doing forcewake before Disabling RC6,
5130          * This what the BIOS expects when going into suspend */
5131         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5132
5133         I915_WRITE(GEN6_RC_CONTROL, 0);
5134
5135         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5136 }
5137
5138 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
5139 {
5140         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5141                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5142                         mode = GEN6_RC_CTL_RC6_ENABLE;
5143                 else
5144                         mode = 0;
5145         }
5146         if (HAS_RC6p(dev_priv))
5147                 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5148                                  "RC6 %s RC6p %s RC6pp %s\n",
5149                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5150                                  onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5151                                  onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
5152
5153         else
5154                 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5155                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
5156 }
5157
5158 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
5159 {
5160         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5161         bool enable_rc6 = true;
5162         unsigned long rc6_ctx_base;
5163         u32 rc_ctl;
5164         int rc_sw_target;
5165
5166         rc_ctl = I915_READ(GEN6_RC_CONTROL);
5167         rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5168                        RC_SW_TARGET_STATE_SHIFT;
5169         DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5170                          "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5171                          onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5172                          onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5173                          rc_sw_target);
5174
5175         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
5176                 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5177                 enable_rc6 = false;
5178         }
5179
5180         /*
5181          * The exact context size is not known for BXT, so assume a page size
5182          * for this check.
5183          */
5184         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
5185         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5186               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5187                                         ggtt->stolen_reserved_size))) {
5188                 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5189                 enable_rc6 = false;
5190         }
5191
5192         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5193               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5194               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5195               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
5196                 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5197                 enable_rc6 = false;
5198         }
5199
5200         if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5201             !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5202             !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5203                 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5204                 enable_rc6 = false;
5205         }
5206
5207         if (!I915_READ(GEN6_GFXPAUSE)) {
5208                 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5209                 enable_rc6 = false;
5210         }
5211
5212         if (!I915_READ(GEN8_MISC_CTRL0)) {
5213                 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5214                 enable_rc6 = false;
5215         }
5216
5217         return enable_rc6;
5218 }
5219
5220 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
5221 {
5222         /* No RC6 before Ironlake and code is gone for ilk. */
5223         if (INTEL_INFO(dev_priv)->gen < 6)
5224                 return 0;
5225
5226         if (!enable_rc6)
5227                 return 0;
5228
5229         if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
5230                 DRM_INFO("RC6 disabled by BIOS\n");
5231                 return 0;
5232         }
5233
5234         /* Respect the kernel parameter if it is set */
5235         if (enable_rc6 >= 0) {
5236                 int mask;
5237
5238                 if (HAS_RC6p(dev_priv))
5239                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5240                                INTEL_RC6pp_ENABLE;
5241                 else
5242                         mask = INTEL_RC6_ENABLE;
5243
5244                 if ((enable_rc6 & mask) != enable_rc6)
5245                         DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5246                                          "(requested %d, valid %d)\n",
5247                                          enable_rc6 & mask, enable_rc6, mask);
5248
5249                 return enable_rc6 & mask;
5250         }
5251
5252         if (IS_IVYBRIDGE(dev_priv))
5253                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5254
5255         return INTEL_RC6_ENABLE;
5256 }
5257
5258 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5259 {
5260         /* All of these values are in units of 50MHz */
5261
5262         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5263         if (IS_BROXTON(dev_priv)) {
5264                 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5265                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5266                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5267                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
5268         } else {
5269                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5270                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
5271                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5272                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5273         }
5274         /* hw_max = RP0 until we check for overclocking */
5275         dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5276
5277         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5278         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5279             IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5280                 u32 ddcc_status = 0;
5281
5282                 if (sandybridge_pcode_read(dev_priv,
5283                                            HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5284                                            &ddcc_status) == 0)
5285                         dev_priv->rps.efficient_freq =
5286                                 clamp_t(u8,
5287                                         ((ddcc_status >> 8) & 0xff),
5288                                         dev_priv->rps.min_freq,
5289                                         dev_priv->rps.max_freq);
5290         }
5291
5292         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5293                 /* Store the frequency values in 16.66 MHZ units, which is
5294                  * the natural hardware unit for SKL
5295                  */
5296                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5297                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5298                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5299                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5300                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5301         }
5302 }
5303
5304 static void reset_rps(struct drm_i915_private *dev_priv,
5305                       void (*set)(struct drm_i915_private *, u8))
5306 {
5307         u8 freq = dev_priv->rps.cur_freq;
5308
5309         /* force a reset */
5310         dev_priv->rps.power = -1;
5311         dev_priv->rps.cur_freq = -1;
5312
5313         set(dev_priv, freq);
5314 }
5315
5316 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5317 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5318 {
5319         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5320
5321         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5322         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5323                 /*
5324                  * BIOS could leave the Hw Turbo enabled, so need to explicitly
5325                  * clear out the Control register just to avoid inconsitency
5326                  * with debugfs interface, which will show  Turbo as enabled
5327                  * only and that is not expected by the User after adding the
5328                  * WaGsvDisableTurbo. Apart from this there is no problem even
5329                  * if the Turbo is left enabled in the Control register, as the
5330                  * Up/Down interrupts would remain masked.
5331                  */
5332                 gen9_disable_rps(dev_priv);
5333                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5334                 return;
5335         }
5336
5337         /* Program defaults and thresholds for RPS*/
5338         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5339                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5340
5341         /* 1 second timeout*/
5342         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5343                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5344
5345         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5346
5347         /* Leaning on the below call to gen6_set_rps to program/setup the
5348          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5349          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5350         reset_rps(dev_priv, gen6_set_rps);
5351
5352         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5353 }
5354
5355 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5356 {
5357         struct intel_engine_cs *engine;
5358         uint32_t rc6_mask = 0;
5359
5360         /* 1a: Software RC state - RC0 */
5361         I915_WRITE(GEN6_RC_STATE, 0);
5362
5363         /* 1b: Get forcewake during program sequence. Although the driver
5364          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5365         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5366
5367         /* 2a: Disable RC states. */
5368         I915_WRITE(GEN6_RC_CONTROL, 0);
5369
5370         /* 2b: Program RC6 thresholds.*/
5371
5372         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5373         if (IS_SKYLAKE(dev_priv))
5374                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5375         else
5376                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5377         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5378         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5379         for_each_engine(engine, dev_priv)
5380                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5381
5382         if (HAS_GUC(dev_priv))
5383                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5384
5385         I915_WRITE(GEN6_RC_SLEEP, 0);
5386
5387         /* 2c: Program Coarse Power Gating Policies. */
5388         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5389         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5390
5391         /* 3a: Enable RC6 */
5392         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5393                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5394         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5395         /* WaRsUseTimeoutMode */
5396         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
5397             IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5398                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
5399                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5400                            GEN7_RC_CTL_TO_MODE |
5401                            rc6_mask);
5402         } else {
5403                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5404                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5405                            GEN6_RC_CTL_EI_MODE(1) |
5406                            rc6_mask);
5407         }
5408
5409         /*
5410          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5411          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5412          */
5413         if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5414                 I915_WRITE(GEN9_PG_ENABLE, 0);
5415         else
5416                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5417                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5418
5419         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5420 }
5421
5422 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5423 {
5424         struct intel_engine_cs *engine;
5425         uint32_t rc6_mask = 0;
5426
5427         /* 1a: Software RC state - RC0 */
5428         I915_WRITE(GEN6_RC_STATE, 0);
5429
5430         /* 1c & 1d: Get forcewake during program sequence. Although the driver
5431          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5432         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5433
5434         /* 2a: Disable RC states. */
5435         I915_WRITE(GEN6_RC_CONTROL, 0);
5436
5437         /* 2b: Program RC6 thresholds.*/
5438         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5439         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5440         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5441         for_each_engine(engine, dev_priv)
5442                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5443         I915_WRITE(GEN6_RC_SLEEP, 0);
5444         if (IS_BROADWELL(dev_priv))
5445                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5446         else
5447                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5448
5449         /* 3: Enable RC6 */
5450         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5451                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5452         intel_print_rc6_info(dev_priv, rc6_mask);
5453         if (IS_BROADWELL(dev_priv))
5454                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5455                                 GEN7_RC_CTL_TO_MODE |
5456                                 rc6_mask);
5457         else
5458                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5459                                 GEN6_RC_CTL_EI_MODE(1) |
5460                                 rc6_mask);
5461
5462         /* 4 Program defaults and thresholds for RPS*/
5463         I915_WRITE(GEN6_RPNSWREQ,
5464                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5465         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5466                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5467         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5468         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5469
5470         /* Docs recommend 900MHz, and 300 MHz respectively */
5471         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5472                    dev_priv->rps.max_freq_softlimit << 24 |
5473                    dev_priv->rps.min_freq_softlimit << 16);
5474
5475         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5476         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5477         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5478         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5479
5480         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5481
5482         /* 5: Enable RPS */
5483         I915_WRITE(GEN6_RP_CONTROL,
5484                    GEN6_RP_MEDIA_TURBO |
5485                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5486                    GEN6_RP_MEDIA_IS_GFX |
5487                    GEN6_RP_ENABLE |
5488                    GEN6_RP_UP_BUSY_AVG |
5489                    GEN6_RP_DOWN_IDLE_AVG);
5490
5491         /* 6: Ring frequency + overclocking (our driver does this later */
5492
5493         reset_rps(dev_priv, gen6_set_rps);
5494
5495         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5496 }
5497
5498 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5499 {
5500         struct intel_engine_cs *engine;
5501         u32 rc6vids, rc6_mask = 0;
5502         u32 gtfifodbg;
5503         int rc6_mode;
5504         int ret;
5505
5506         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5507
5508         /* Here begins a magic sequence of register writes to enable
5509          * auto-downclocking.
5510          *
5511          * Perhaps there might be some value in exposing these to
5512          * userspace...
5513          */
5514         I915_WRITE(GEN6_RC_STATE, 0);
5515
5516         /* Clear the DBG now so we don't confuse earlier errors */
5517         gtfifodbg = I915_READ(GTFIFODBG);
5518         if (gtfifodbg) {
5519                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5520                 I915_WRITE(GTFIFODBG, gtfifodbg);
5521         }
5522
5523         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5524
5525         /* disable the counters and set deterministic thresholds */
5526         I915_WRITE(GEN6_RC_CONTROL, 0);
5527
5528         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5529         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5530         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5531         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5532         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5533
5534         for_each_engine(engine, dev_priv)
5535                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5536
5537         I915_WRITE(GEN6_RC_SLEEP, 0);
5538         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5539         if (IS_IVYBRIDGE(dev_priv))
5540                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5541         else
5542                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5543         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5544         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5545
5546         /* Check if we are enabling RC6 */
5547         rc6_mode = intel_enable_rc6();
5548         if (rc6_mode & INTEL_RC6_ENABLE)
5549                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5550
5551         /* We don't use those on Haswell */
5552         if (!IS_HASWELL(dev_priv)) {
5553                 if (rc6_mode & INTEL_RC6p_ENABLE)
5554                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5555
5556                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5557                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5558         }
5559
5560         intel_print_rc6_info(dev_priv, rc6_mask);
5561
5562         I915_WRITE(GEN6_RC_CONTROL,
5563                    rc6_mask |
5564                    GEN6_RC_CTL_EI_MODE(1) |
5565                    GEN6_RC_CTL_HW_ENABLE);
5566
5567         /* Power down if completely idle for over 50ms */
5568         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5569         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5570
5571         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5572         if (ret)
5573                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5574
5575         reset_rps(dev_priv, gen6_set_rps);
5576
5577         rc6vids = 0;
5578         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5579         if (IS_GEN6(dev_priv) && ret) {
5580                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5581         } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5582                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5583                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5584                 rc6vids &= 0xffff00;
5585                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5586                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5587                 if (ret)
5588                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5589         }
5590
5591         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5592 }
5593
5594 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5595 {
5596         int min_freq = 15;
5597         unsigned int gpu_freq;
5598         unsigned int max_ia_freq, min_ring_freq;
5599         unsigned int max_gpu_freq, min_gpu_freq;
5600         int scaling_factor = 180;
5601         struct cpufreq_policy *policy;
5602
5603         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5604
5605         policy = cpufreq_cpu_get(0);
5606         if (policy) {
5607                 max_ia_freq = policy->cpuinfo.max_freq;
5608                 cpufreq_cpu_put(policy);
5609         } else {
5610                 /*
5611                  * Default to measured freq if none found, PCU will ensure we
5612                  * don't go over
5613                  */
5614                 max_ia_freq = tsc_khz;
5615         }
5616
5617         /* Convert from kHz to MHz */
5618         max_ia_freq /= 1000;
5619
5620         min_ring_freq = I915_READ(DCLK) & 0xf;
5621         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5622         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5623
5624         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5625                 /* Convert GT frequency to 50 HZ units */
5626                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5627                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5628         } else {
5629                 min_gpu_freq = dev_priv->rps.min_freq;
5630                 max_gpu_freq = dev_priv->rps.max_freq;
5631         }
5632
5633         /*
5634          * For each potential GPU frequency, load a ring frequency we'd like
5635          * to use for memory access.  We do this by specifying the IA frequency
5636          * the PCU should use as a reference to determine the ring frequency.
5637          */
5638         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5639                 int diff = max_gpu_freq - gpu_freq;
5640                 unsigned int ia_freq = 0, ring_freq = 0;
5641
5642                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5643                         /*
5644                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5645                          * No floor required for ring frequency on SKL.
5646                          */
5647                         ring_freq = gpu_freq;
5648                 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5649                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5650                         ring_freq = max(min_ring_freq, gpu_freq);
5651                 } else if (IS_HASWELL(dev_priv)) {
5652                         ring_freq = mult_frac(gpu_freq, 5, 4);
5653                         ring_freq = max(min_ring_freq, ring_freq);
5654                         /* leave ia_freq as the default, chosen by cpufreq */
5655                 } else {
5656                         /* On older processors, there is no separate ring
5657                          * clock domain, so in order to boost the bandwidth
5658                          * of the ring, we need to upclock the CPU (ia_freq).
5659                          *
5660                          * For GPU frequencies less than 750MHz,
5661                          * just use the lowest ring freq.
5662                          */
5663                         if (gpu_freq < min_freq)
5664                                 ia_freq = 800;
5665                         else
5666                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5667                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5668                 }
5669
5670                 sandybridge_pcode_write(dev_priv,
5671                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5672                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5673                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5674                                         gpu_freq);
5675         }
5676 }
5677
5678 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5679 {
5680         u32 val, rp0;
5681
5682         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5683
5684         switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5685         case 8:
5686                 /* (2 * 4) config */
5687                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5688                 break;
5689         case 12:
5690                 /* (2 * 6) config */
5691                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5692                 break;
5693         case 16:
5694                 /* (2 * 8) config */
5695         default:
5696                 /* Setting (2 * 8) Min RP0 for any other combination */
5697                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5698                 break;
5699         }
5700
5701         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5702
5703         return rp0;
5704 }
5705
5706 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5707 {
5708         u32 val, rpe;
5709
5710         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5711         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5712
5713         return rpe;
5714 }
5715
5716 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5717 {
5718         u32 val, rp1;
5719
5720         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5721         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5722
5723         return rp1;
5724 }
5725
5726 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5727 {
5728         u32 val, rp1;
5729
5730         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5731
5732         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5733
5734         return rp1;
5735 }
5736
5737 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5738 {
5739         u32 val, rp0;
5740
5741         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5742
5743         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5744         /* Clamp to max */
5745         rp0 = min_t(u32, rp0, 0xea);
5746
5747         return rp0;
5748 }
5749
5750 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5751 {
5752         u32 val, rpe;
5753
5754         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5755         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5756         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5757         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5758
5759         return rpe;
5760 }
5761
5762 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5763 {
5764         u32 val;
5765
5766         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5767         /*
5768          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5769          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5770          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5771          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5772          * to make sure it matches what Punit accepts.
5773          */
5774         return max_t(u32, val, 0xc0);
5775 }
5776
5777 /* Check that the pctx buffer wasn't move under us. */
5778 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5779 {
5780         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5781
5782         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5783                              dev_priv->vlv_pctx->stolen->start);
5784 }
5785
5786
5787 /* Check that the pcbr address is not empty. */
5788 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5789 {
5790         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5791
5792         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5793 }
5794
5795 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5796 {
5797         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5798         unsigned long pctx_paddr, paddr;
5799         u32 pcbr;
5800         int pctx_size = 32*1024;
5801
5802         pcbr = I915_READ(VLV_PCBR);
5803         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5804                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5805                 paddr = (dev_priv->mm.stolen_base +
5806                          (ggtt->stolen_size - pctx_size));
5807
5808                 pctx_paddr = (paddr & (~4095));
5809                 I915_WRITE(VLV_PCBR, pctx_paddr);
5810         }
5811
5812         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5813 }
5814
5815 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5816 {
5817         struct drm_i915_gem_object *pctx;
5818         unsigned long pctx_paddr;
5819         u32 pcbr;
5820         int pctx_size = 24*1024;
5821
5822         pcbr = I915_READ(VLV_PCBR);
5823         if (pcbr) {
5824                 /* BIOS set it up already, grab the pre-alloc'd space */
5825                 int pcbr_offset;
5826
5827                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5828                 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
5829                                                                       pcbr_offset,
5830                                                                       I915_GTT_OFFSET_NONE,
5831                                                                       pctx_size);
5832                 goto out;
5833         }
5834
5835         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5836
5837         /*
5838          * From the Gunit register HAS:
5839          * The Gfx driver is expected to program this register and ensure
5840          * proper allocation within Gfx stolen memory.  For example, this
5841          * register should be programmed such than the PCBR range does not
5842          * overlap with other ranges, such as the frame buffer, protected
5843          * memory, or any other relevant ranges.
5844          */
5845         pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
5846         if (!pctx) {
5847                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5848                 goto out;
5849         }
5850
5851         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5852         I915_WRITE(VLV_PCBR, pctx_paddr);
5853
5854 out:
5855         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5856         dev_priv->vlv_pctx = pctx;
5857 }
5858
5859 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5860 {
5861         if (WARN_ON(!dev_priv->vlv_pctx))
5862                 return;
5863
5864         i915_gem_object_put_unlocked(dev_priv->vlv_pctx);
5865         dev_priv->vlv_pctx = NULL;
5866 }
5867
5868 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5869 {
5870         dev_priv->rps.gpll_ref_freq =
5871                 vlv_get_cck_clock(dev_priv, "GPLL ref",
5872                                   CCK_GPLL_CLOCK_CONTROL,
5873                                   dev_priv->czclk_freq);
5874
5875         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5876                          dev_priv->rps.gpll_ref_freq);
5877 }
5878
5879 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5880 {
5881         u32 val;
5882
5883         valleyview_setup_pctx(dev_priv);
5884
5885         vlv_init_gpll_ref_freq(dev_priv);
5886
5887         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5888         switch ((val >> 6) & 3) {
5889         case 0:
5890         case 1:
5891                 dev_priv->mem_freq = 800;
5892                 break;
5893         case 2:
5894                 dev_priv->mem_freq = 1066;
5895                 break;
5896         case 3:
5897                 dev_priv->mem_freq = 1333;
5898                 break;
5899         }
5900         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5901
5902         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5903         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5904         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5905                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5906                          dev_priv->rps.max_freq);
5907
5908         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5909         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5910                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5911                          dev_priv->rps.efficient_freq);
5912
5913         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5914         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5915                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5916                          dev_priv->rps.rp1_freq);
5917
5918         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5919         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5920                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5921                          dev_priv->rps.min_freq);
5922 }
5923
5924 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5925 {
5926         u32 val;
5927
5928         cherryview_setup_pctx(dev_priv);
5929
5930         vlv_init_gpll_ref_freq(dev_priv);
5931
5932         mutex_lock(&dev_priv->sb_lock);
5933         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5934         mutex_unlock(&dev_priv->sb_lock);
5935
5936         switch ((val >> 2) & 0x7) {
5937         case 3:
5938                 dev_priv->mem_freq = 2000;
5939                 break;
5940         default:
5941                 dev_priv->mem_freq = 1600;
5942                 break;
5943         }
5944         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5945
5946         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5947         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5948         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5949                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5950                          dev_priv->rps.max_freq);
5951
5952         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5953         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5954                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5955                          dev_priv->rps.efficient_freq);
5956
5957         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5958         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5959                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5960                          dev_priv->rps.rp1_freq);
5961
5962         /* PUnit validated range is only [RPe, RP0] */
5963         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5964         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5965                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5966                          dev_priv->rps.min_freq);
5967
5968         WARN_ONCE((dev_priv->rps.max_freq |
5969                    dev_priv->rps.efficient_freq |
5970                    dev_priv->rps.rp1_freq |
5971                    dev_priv->rps.min_freq) & 1,
5972                   "Odd GPU freq values\n");
5973 }
5974
5975 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5976 {
5977         valleyview_cleanup_pctx(dev_priv);
5978 }
5979
5980 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5981 {
5982         struct intel_engine_cs *engine;
5983         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5984
5985         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5986
5987         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5988                                              GT_FIFO_FREE_ENTRIES_CHV);
5989         if (gtfifodbg) {
5990                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5991                                  gtfifodbg);
5992                 I915_WRITE(GTFIFODBG, gtfifodbg);
5993         }
5994
5995         cherryview_check_pctx(dev_priv);
5996
5997         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5998          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5999         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6000
6001         /*  Disable RC states. */
6002         I915_WRITE(GEN6_RC_CONTROL, 0);
6003
6004         /* 2a: Program RC6 thresholds.*/
6005         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6006         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6007         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6008
6009         for_each_engine(engine, dev_priv)
6010                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6011         I915_WRITE(GEN6_RC_SLEEP, 0);
6012
6013         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6014         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
6015
6016         /* allows RC6 residency counter to work */
6017         I915_WRITE(VLV_COUNTER_CONTROL,
6018                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6019                                       VLV_MEDIA_RC6_COUNT_EN |
6020                                       VLV_RENDER_RC6_COUNT_EN));
6021
6022         /* For now we assume BIOS is allocating and populating the PCBR  */
6023         pcbr = I915_READ(VLV_PCBR);
6024
6025         /* 3: Enable RC6 */
6026         if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6027             (pcbr >> VLV_PCBR_ADDR_SHIFT))
6028                 rc6_mode = GEN7_RC_CTL_TO_MODE;
6029
6030         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6031
6032         /* 4 Program defaults and thresholds for RPS*/
6033         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6034         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6035         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6036         I915_WRITE(GEN6_RP_UP_EI, 66000);
6037         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6038
6039         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6040
6041         /* 5: Enable RPS */
6042         I915_WRITE(GEN6_RP_CONTROL,
6043                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6044                    GEN6_RP_MEDIA_IS_GFX |
6045                    GEN6_RP_ENABLE |
6046                    GEN6_RP_UP_BUSY_AVG |
6047                    GEN6_RP_DOWN_IDLE_AVG);
6048
6049         /* Setting Fixed Bias */
6050         val = VLV_OVERRIDE_EN |
6051                   VLV_SOC_TDP_EN |
6052                   CHV_BIAS_CPU_50_SOC_50;
6053         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6054
6055         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6056
6057         /* RPS code assumes GPLL is used */
6058         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6059
6060         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6061         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6062
6063         reset_rps(dev_priv, valleyview_set_rps);
6064
6065         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6066 }
6067
6068 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
6069 {
6070         struct intel_engine_cs *engine;
6071         u32 gtfifodbg, val, rc6_mode = 0;
6072
6073         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6074
6075         valleyview_check_pctx(dev_priv);
6076
6077         gtfifodbg = I915_READ(GTFIFODBG);
6078         if (gtfifodbg) {
6079                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6080                                  gtfifodbg);
6081                 I915_WRITE(GTFIFODBG, gtfifodbg);
6082         }
6083
6084         /* If VLV, Forcewake all wells, else re-direct to regular path */
6085         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6086
6087         /*  Disable RC states. */
6088         I915_WRITE(GEN6_RC_CONTROL, 0);
6089
6090         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6091         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6092         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6093         I915_WRITE(GEN6_RP_UP_EI, 66000);
6094         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6095
6096         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6097
6098         I915_WRITE(GEN6_RP_CONTROL,
6099                    GEN6_RP_MEDIA_TURBO |
6100                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6101                    GEN6_RP_MEDIA_IS_GFX |
6102                    GEN6_RP_ENABLE |
6103                    GEN6_RP_UP_BUSY_AVG |
6104                    GEN6_RP_DOWN_IDLE_CONT);
6105
6106         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6107         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6108         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6109
6110         for_each_engine(engine, dev_priv)
6111                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6112
6113         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
6114
6115         /* allows RC6 residency counter to work */
6116         I915_WRITE(VLV_COUNTER_CONTROL,
6117                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6118                                       VLV_RENDER_RC0_COUNT_EN |
6119                                       VLV_MEDIA_RC6_COUNT_EN |
6120                                       VLV_RENDER_RC6_COUNT_EN));
6121
6122         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6123                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
6124
6125         intel_print_rc6_info(dev_priv, rc6_mode);
6126
6127         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6128
6129         /* Setting Fixed Bias */
6130         val = VLV_OVERRIDE_EN |
6131                   VLV_SOC_TDP_EN |
6132                   VLV_BIAS_CPU_125_SOC_875;
6133         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6134
6135         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6136
6137         /* RPS code assumes GPLL is used */
6138         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6139
6140         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6141         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6142
6143         reset_rps(dev_priv, valleyview_set_rps);
6144
6145         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6146 }
6147
6148 static unsigned long intel_pxfreq(u32 vidfreq)
6149 {
6150         unsigned long freq;
6151         int div = (vidfreq & 0x3f0000) >> 16;
6152         int post = (vidfreq & 0x3000) >> 12;
6153         int pre = (vidfreq & 0x7);
6154
6155         if (!pre)
6156                 return 0;
6157
6158         freq = ((div * 133333) / ((1<<post) * pre));
6159
6160         return freq;
6161 }
6162
6163 static const struct cparams {
6164         u16 i;
6165         u16 t;
6166         u16 m;
6167         u16 c;
6168 } cparams[] = {
6169         { 1, 1333, 301, 28664 },
6170         { 1, 1066, 294, 24460 },
6171         { 1, 800, 294, 25192 },
6172         { 0, 1333, 276, 27605 },
6173         { 0, 1066, 276, 27605 },
6174         { 0, 800, 231, 23784 },
6175 };
6176
6177 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6178 {
6179         u64 total_count, diff, ret;
6180         u32 count1, count2, count3, m = 0, c = 0;
6181         unsigned long now = jiffies_to_msecs(jiffies), diff1;
6182         int i;
6183
6184         assert_spin_locked(&mchdev_lock);
6185
6186         diff1 = now - dev_priv->ips.last_time1;
6187
6188         /* Prevent division-by-zero if we are asking too fast.
6189          * Also, we don't get interesting results if we are polling
6190          * faster than once in 10ms, so just return the saved value
6191          * in such cases.
6192          */
6193         if (diff1 <= 10)
6194                 return dev_priv->ips.chipset_power;
6195
6196         count1 = I915_READ(DMIEC);
6197         count2 = I915_READ(DDREC);
6198         count3 = I915_READ(CSIEC);
6199
6200         total_count = count1 + count2 + count3;
6201
6202         /* FIXME: handle per-counter overflow */
6203         if (total_count < dev_priv->ips.last_count1) {
6204                 diff = ~0UL - dev_priv->ips.last_count1;
6205                 diff += total_count;
6206         } else {
6207                 diff = total_count - dev_priv->ips.last_count1;
6208         }
6209
6210         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6211                 if (cparams[i].i == dev_priv->ips.c_m &&
6212                     cparams[i].t == dev_priv->ips.r_t) {
6213                         m = cparams[i].m;
6214                         c = cparams[i].c;
6215                         break;
6216                 }
6217         }
6218
6219         diff = div_u64(diff, diff1);
6220         ret = ((m * diff) + c);
6221         ret = div_u64(ret, 10);
6222
6223         dev_priv->ips.last_count1 = total_count;
6224         dev_priv->ips.last_time1 = now;
6225
6226         dev_priv->ips.chipset_power = ret;
6227
6228         return ret;
6229 }
6230
6231 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6232 {
6233         unsigned long val;
6234
6235         if (INTEL_INFO(dev_priv)->gen != 5)
6236                 return 0;
6237
6238         spin_lock_irq(&mchdev_lock);
6239
6240         val = __i915_chipset_val(dev_priv);
6241
6242         spin_unlock_irq(&mchdev_lock);
6243
6244         return val;
6245 }
6246
6247 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6248 {
6249         unsigned long m, x, b;
6250         u32 tsfs;
6251
6252         tsfs = I915_READ(TSFS);
6253
6254         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6255         x = I915_READ8(TR1);
6256
6257         b = tsfs & TSFS_INTR_MASK;
6258
6259         return ((m * x) / 127) - b;
6260 }
6261
6262 static int _pxvid_to_vd(u8 pxvid)
6263 {
6264         if (pxvid == 0)
6265                 return 0;
6266
6267         if (pxvid >= 8 && pxvid < 31)
6268                 pxvid = 31;
6269
6270         return (pxvid + 2) * 125;
6271 }
6272
6273 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6274 {
6275         const int vd = _pxvid_to_vd(pxvid);
6276         const int vm = vd - 1125;
6277
6278         if (INTEL_INFO(dev_priv)->is_mobile)
6279                 return vm > 0 ? vm : 0;
6280
6281         return vd;
6282 }
6283
6284 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6285 {
6286         u64 now, diff, diffms;
6287         u32 count;
6288
6289         assert_spin_locked(&mchdev_lock);
6290
6291         now = ktime_get_raw_ns();
6292         diffms = now - dev_priv->ips.last_time2;
6293         do_div(diffms, NSEC_PER_MSEC);
6294
6295         /* Don't divide by 0 */
6296         if (!diffms)
6297                 return;
6298
6299         count = I915_READ(GFXEC);
6300
6301         if (count < dev_priv->ips.last_count2) {
6302                 diff = ~0UL - dev_priv->ips.last_count2;
6303                 diff += count;
6304         } else {
6305                 diff = count - dev_priv->ips.last_count2;
6306         }
6307
6308         dev_priv->ips.last_count2 = count;
6309         dev_priv->ips.last_time2 = now;
6310
6311         /* More magic constants... */
6312         diff = diff * 1181;
6313         diff = div_u64(diff, diffms * 10);
6314         dev_priv->ips.gfx_power = diff;
6315 }
6316
6317 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6318 {
6319         if (INTEL_INFO(dev_priv)->gen != 5)
6320                 return;
6321
6322         spin_lock_irq(&mchdev_lock);
6323
6324         __i915_update_gfx_val(dev_priv);
6325
6326         spin_unlock_irq(&mchdev_lock);
6327 }
6328
6329 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6330 {
6331         unsigned long t, corr, state1, corr2, state2;
6332         u32 pxvid, ext_v;
6333
6334         assert_spin_locked(&mchdev_lock);
6335
6336         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6337         pxvid = (pxvid >> 24) & 0x7f;
6338         ext_v = pvid_to_extvid(dev_priv, pxvid);
6339
6340         state1 = ext_v;
6341
6342         t = i915_mch_val(dev_priv);
6343
6344         /* Revel in the empirically derived constants */
6345
6346         /* Correction factor in 1/100000 units */
6347         if (t > 80)
6348                 corr = ((t * 2349) + 135940);
6349         else if (t >= 50)
6350                 corr = ((t * 964) + 29317);
6351         else /* < 50 */
6352                 corr = ((t * 301) + 1004);
6353
6354         corr = corr * ((150142 * state1) / 10000 - 78642);
6355         corr /= 100000;
6356         corr2 = (corr * dev_priv->ips.corr);
6357
6358         state2 = (corr2 * state1) / 10000;
6359         state2 /= 100; /* convert to mW */
6360
6361         __i915_update_gfx_val(dev_priv);
6362
6363         return dev_priv->ips.gfx_power + state2;
6364 }
6365
6366 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6367 {
6368         unsigned long val;
6369
6370         if (INTEL_INFO(dev_priv)->gen != 5)
6371                 return 0;
6372
6373         spin_lock_irq(&mchdev_lock);
6374
6375         val = __i915_gfx_val(dev_priv);
6376
6377         spin_unlock_irq(&mchdev_lock);
6378
6379         return val;
6380 }
6381
6382 /**
6383  * i915_read_mch_val - return value for IPS use
6384  *
6385  * Calculate and return a value for the IPS driver to use when deciding whether
6386  * we have thermal and power headroom to increase CPU or GPU power budget.
6387  */
6388 unsigned long i915_read_mch_val(void)
6389 {
6390         struct drm_i915_private *dev_priv;
6391         unsigned long chipset_val, graphics_val, ret = 0;
6392
6393         spin_lock_irq(&mchdev_lock);
6394         if (!i915_mch_dev)
6395                 goto out_unlock;
6396         dev_priv = i915_mch_dev;
6397
6398         chipset_val = __i915_chipset_val(dev_priv);
6399         graphics_val = __i915_gfx_val(dev_priv);
6400
6401         ret = chipset_val + graphics_val;
6402
6403 out_unlock:
6404         spin_unlock_irq(&mchdev_lock);
6405
6406         return ret;
6407 }
6408 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6409
6410 /**
6411  * i915_gpu_raise - raise GPU frequency limit
6412  *
6413  * Raise the limit; IPS indicates we have thermal headroom.
6414  */
6415 bool i915_gpu_raise(void)
6416 {
6417         struct drm_i915_private *dev_priv;
6418         bool ret = true;
6419
6420         spin_lock_irq(&mchdev_lock);
6421         if (!i915_mch_dev) {
6422                 ret = false;
6423                 goto out_unlock;
6424         }
6425         dev_priv = i915_mch_dev;
6426
6427         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6428                 dev_priv->ips.max_delay--;
6429
6430 out_unlock:
6431         spin_unlock_irq(&mchdev_lock);
6432
6433         return ret;
6434 }
6435 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6436
6437 /**
6438  * i915_gpu_lower - lower GPU frequency limit
6439  *
6440  * IPS indicates we're close to a thermal limit, so throttle back the GPU
6441  * frequency maximum.
6442  */
6443 bool i915_gpu_lower(void)
6444 {
6445         struct drm_i915_private *dev_priv;
6446         bool ret = true;
6447
6448         spin_lock_irq(&mchdev_lock);
6449         if (!i915_mch_dev) {
6450                 ret = false;
6451                 goto out_unlock;
6452         }
6453         dev_priv = i915_mch_dev;
6454
6455         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6456                 dev_priv->ips.max_delay++;
6457
6458 out_unlock:
6459         spin_unlock_irq(&mchdev_lock);
6460
6461         return ret;
6462 }
6463 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6464
6465 /**
6466  * i915_gpu_busy - indicate GPU business to IPS
6467  *
6468  * Tell the IPS driver whether or not the GPU is busy.
6469  */
6470 bool i915_gpu_busy(void)
6471 {
6472         bool ret = false;
6473
6474         spin_lock_irq(&mchdev_lock);
6475         if (i915_mch_dev)
6476                 ret = i915_mch_dev->gt.awake;
6477         spin_unlock_irq(&mchdev_lock);
6478
6479         return ret;
6480 }
6481 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6482
6483 /**
6484  * i915_gpu_turbo_disable - disable graphics turbo
6485  *
6486  * Disable graphics turbo by resetting the max frequency and setting the
6487  * current frequency to the default.
6488  */
6489 bool i915_gpu_turbo_disable(void)
6490 {
6491         struct drm_i915_private *dev_priv;
6492         bool ret = true;
6493
6494         spin_lock_irq(&mchdev_lock);
6495         if (!i915_mch_dev) {
6496                 ret = false;
6497                 goto out_unlock;
6498         }
6499         dev_priv = i915_mch_dev;
6500
6501         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6502
6503         if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6504                 ret = false;
6505
6506 out_unlock:
6507         spin_unlock_irq(&mchdev_lock);
6508
6509         return ret;
6510 }
6511 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6512
6513 /**
6514  * Tells the intel_ips driver that the i915 driver is now loaded, if
6515  * IPS got loaded first.
6516  *
6517  * This awkward dance is so that neither module has to depend on the
6518  * other in order for IPS to do the appropriate communication of
6519  * GPU turbo limits to i915.
6520  */
6521 static void
6522 ips_ping_for_i915_load(void)
6523 {
6524         void (*link)(void);
6525
6526         link = symbol_get(ips_link_to_i915_driver);
6527         if (link) {
6528                 link();
6529                 symbol_put(ips_link_to_i915_driver);
6530         }
6531 }
6532
6533 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6534 {
6535         /* We only register the i915 ips part with intel-ips once everything is
6536          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6537         spin_lock_irq(&mchdev_lock);
6538         i915_mch_dev = dev_priv;
6539         spin_unlock_irq(&mchdev_lock);
6540
6541         ips_ping_for_i915_load();
6542 }
6543
6544 void intel_gpu_ips_teardown(void)
6545 {
6546         spin_lock_irq(&mchdev_lock);
6547         i915_mch_dev = NULL;
6548         spin_unlock_irq(&mchdev_lock);
6549 }
6550
6551 static void intel_init_emon(struct drm_i915_private *dev_priv)
6552 {
6553         u32 lcfuse;
6554         u8 pxw[16];
6555         int i;
6556
6557         /* Disable to program */
6558         I915_WRITE(ECR, 0);
6559         POSTING_READ(ECR);
6560
6561         /* Program energy weights for various events */
6562         I915_WRITE(SDEW, 0x15040d00);
6563         I915_WRITE(CSIEW0, 0x007f0000);
6564         I915_WRITE(CSIEW1, 0x1e220004);
6565         I915_WRITE(CSIEW2, 0x04000004);
6566
6567         for (i = 0; i < 5; i++)
6568                 I915_WRITE(PEW(i), 0);
6569         for (i = 0; i < 3; i++)
6570                 I915_WRITE(DEW(i), 0);
6571
6572         /* Program P-state weights to account for frequency power adjustment */
6573         for (i = 0; i < 16; i++) {
6574                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6575                 unsigned long freq = intel_pxfreq(pxvidfreq);
6576                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6577                         PXVFREQ_PX_SHIFT;
6578                 unsigned long val;
6579
6580                 val = vid * vid;
6581                 val *= (freq / 1000);
6582                 val *= 255;
6583                 val /= (127*127*900);
6584                 if (val > 0xff)
6585                         DRM_ERROR("bad pxval: %ld\n", val);
6586                 pxw[i] = val;
6587         }
6588         /* Render standby states get 0 weight */
6589         pxw[14] = 0;
6590         pxw[15] = 0;
6591
6592         for (i = 0; i < 4; i++) {
6593                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6594                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6595                 I915_WRITE(PXW(i), val);
6596         }
6597
6598         /* Adjust magic regs to magic values (more experimental results) */
6599         I915_WRITE(OGW0, 0);
6600         I915_WRITE(OGW1, 0);
6601         I915_WRITE(EG0, 0x00007f00);
6602         I915_WRITE(EG1, 0x0000000e);
6603         I915_WRITE(EG2, 0x000e0000);
6604         I915_WRITE(EG3, 0x68000300);
6605         I915_WRITE(EG4, 0x42000000);
6606         I915_WRITE(EG5, 0x00140031);
6607         I915_WRITE(EG6, 0);
6608         I915_WRITE(EG7, 0);
6609
6610         for (i = 0; i < 8; i++)
6611                 I915_WRITE(PXWL(i), 0);
6612
6613         /* Enable PMON + select events */
6614         I915_WRITE(ECR, 0x80000019);
6615
6616         lcfuse = I915_READ(LCFUSE02);
6617
6618         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6619 }
6620
6621 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6622 {
6623         /*
6624          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6625          * requirement.
6626          */
6627         if (!i915.enable_rc6) {
6628                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6629                 intel_runtime_pm_get(dev_priv);
6630         }
6631
6632         mutex_lock(&dev_priv->drm.struct_mutex);
6633         mutex_lock(&dev_priv->rps.hw_lock);
6634
6635         /* Initialize RPS limits (for userspace) */
6636         if (IS_CHERRYVIEW(dev_priv))
6637                 cherryview_init_gt_powersave(dev_priv);
6638         else if (IS_VALLEYVIEW(dev_priv))
6639                 valleyview_init_gt_powersave(dev_priv);
6640         else if (INTEL_GEN(dev_priv) >= 6)
6641                 gen6_init_rps_frequencies(dev_priv);
6642
6643         /* Derive initial user preferences/limits from the hardware limits */
6644         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6645         dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6646
6647         dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6648         dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6649
6650         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6651                 dev_priv->rps.min_freq_softlimit =
6652                         max_t(int,
6653                               dev_priv->rps.efficient_freq,
6654                               intel_freq_opcode(dev_priv, 450));
6655
6656         /* After setting max-softlimit, find the overclock max freq */
6657         if (IS_GEN6(dev_priv) ||
6658             IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6659                 u32 params = 0;
6660
6661                 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6662                 if (params & BIT(31)) { /* OC supported */
6663                         DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6664                                          (dev_priv->rps.max_freq & 0xff) * 50,
6665                                          (params & 0xff) * 50);
6666                         dev_priv->rps.max_freq = params & 0xff;
6667                 }
6668         }
6669
6670         /* Finally allow us to boost to max by default */
6671         dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6672
6673         mutex_unlock(&dev_priv->rps.hw_lock);
6674         mutex_unlock(&dev_priv->drm.struct_mutex);
6675
6676         intel_autoenable_gt_powersave(dev_priv);
6677 }
6678
6679 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6680 {
6681         if (IS_VALLEYVIEW(dev_priv))
6682                 valleyview_cleanup_gt_powersave(dev_priv);
6683
6684         if (!i915.enable_rc6)
6685                 intel_runtime_pm_put(dev_priv);
6686 }
6687
6688 /**
6689  * intel_suspend_gt_powersave - suspend PM work and helper threads
6690  * @dev_priv: i915 device
6691  *
6692  * We don't want to disable RC6 or other features here, we just want
6693  * to make sure any work we've queued has finished and won't bother
6694  * us while we're suspended.
6695  */
6696 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6697 {
6698         if (INTEL_GEN(dev_priv) < 6)
6699                 return;
6700
6701         if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6702                 intel_runtime_pm_put(dev_priv);
6703
6704         /* gen6_rps_idle() will be called later to disable interrupts */
6705 }
6706
6707 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6708 {
6709         dev_priv->rps.enabled = true; /* force disabling */
6710         intel_disable_gt_powersave(dev_priv);
6711
6712         gen6_reset_rps_interrupts(dev_priv);
6713 }
6714
6715 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6716 {
6717         if (!READ_ONCE(dev_priv->rps.enabled))
6718                 return;
6719
6720         mutex_lock(&dev_priv->rps.hw_lock);
6721
6722         if (INTEL_GEN(dev_priv) >= 9) {
6723                 gen9_disable_rc6(dev_priv);
6724                 gen9_disable_rps(dev_priv);
6725         } else if (IS_CHERRYVIEW(dev_priv)) {
6726                 cherryview_disable_rps(dev_priv);
6727         } else if (IS_VALLEYVIEW(dev_priv)) {
6728                 valleyview_disable_rps(dev_priv);
6729         } else if (INTEL_GEN(dev_priv) >= 6) {
6730                 gen6_disable_rps(dev_priv);
6731         }  else if (IS_IRONLAKE_M(dev_priv)) {
6732                 ironlake_disable_drps(dev_priv);
6733         }
6734
6735         dev_priv->rps.enabled = false;
6736         mutex_unlock(&dev_priv->rps.hw_lock);
6737 }
6738
6739 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6740 {
6741         /* We shouldn't be disabling as we submit, so this should be less
6742          * racy than it appears!
6743          */
6744         if (READ_ONCE(dev_priv->rps.enabled))
6745                 return;
6746
6747         /* Powersaving is controlled by the host when inside a VM */
6748         if (intel_vgpu_active(dev_priv))
6749                 return;
6750
6751         mutex_lock(&dev_priv->rps.hw_lock);
6752
6753         if (IS_CHERRYVIEW(dev_priv)) {
6754                 cherryview_enable_rps(dev_priv);
6755         } else if (IS_VALLEYVIEW(dev_priv)) {
6756                 valleyview_enable_rps(dev_priv);
6757         } else if (INTEL_GEN(dev_priv) >= 9) {
6758                 gen9_enable_rc6(dev_priv);
6759                 gen9_enable_rps(dev_priv);
6760                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6761                         gen6_update_ring_freq(dev_priv);
6762         } else if (IS_BROADWELL(dev_priv)) {
6763                 gen8_enable_rps(dev_priv);
6764                 gen6_update_ring_freq(dev_priv);
6765         } else if (INTEL_GEN(dev_priv) >= 6) {
6766                 gen6_enable_rps(dev_priv);
6767                 gen6_update_ring_freq(dev_priv);
6768         } else if (IS_IRONLAKE_M(dev_priv)) {
6769                 ironlake_enable_drps(dev_priv);
6770                 intel_init_emon(dev_priv);
6771         }
6772
6773         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6774         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6775
6776         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6777         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6778
6779         dev_priv->rps.enabled = true;
6780         mutex_unlock(&dev_priv->rps.hw_lock);
6781 }
6782
6783 static void __intel_autoenable_gt_powersave(struct work_struct *work)
6784 {
6785         struct drm_i915_private *dev_priv =
6786                 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6787         struct intel_engine_cs *rcs;
6788         struct drm_i915_gem_request *req;
6789
6790         if (READ_ONCE(dev_priv->rps.enabled))
6791                 goto out;
6792
6793         rcs = &dev_priv->engine[RCS];
6794         if (rcs->last_context)
6795                 goto out;
6796
6797         if (!rcs->init_context)
6798                 goto out;
6799
6800         mutex_lock(&dev_priv->drm.struct_mutex);
6801
6802         req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6803         if (IS_ERR(req))
6804                 goto unlock;
6805
6806         if (!i915.enable_execlists && i915_switch_context(req) == 0)
6807                 rcs->init_context(req);
6808
6809         /* Mark the device busy, calling intel_enable_gt_powersave() */
6810         i915_add_request_no_flush(req);
6811
6812 unlock:
6813         mutex_unlock(&dev_priv->drm.struct_mutex);
6814 out:
6815         intel_runtime_pm_put(dev_priv);
6816 }
6817
6818 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6819 {
6820         if (READ_ONCE(dev_priv->rps.enabled))
6821                 return;
6822
6823         if (IS_IRONLAKE_M(dev_priv)) {
6824                 ironlake_enable_drps(dev_priv);
6825                 intel_init_emon(dev_priv);
6826         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6827                 /*
6828                  * PCU communication is slow and this doesn't need to be
6829                  * done at any specific time, so do this out of our fast path
6830                  * to make resume and init faster.
6831                  *
6832                  * We depend on the HW RC6 power context save/restore
6833                  * mechanism when entering D3 through runtime PM suspend. So
6834                  * disable RPM until RPS/RC6 is properly setup. We can only
6835                  * get here via the driver load/system resume/runtime resume
6836                  * paths, so the _noresume version is enough (and in case of
6837                  * runtime resume it's necessary).
6838                  */
6839                 if (queue_delayed_work(dev_priv->wq,
6840                                        &dev_priv->rps.autoenable_work,
6841                                        round_jiffies_up_relative(HZ)))
6842                         intel_runtime_pm_get_noresume(dev_priv);
6843         }
6844 }
6845
6846 static void ibx_init_clock_gating(struct drm_device *dev)
6847 {
6848         struct drm_i915_private *dev_priv = to_i915(dev);
6849
6850         /*
6851          * On Ibex Peak and Cougar Point, we need to disable clock
6852          * gating for the panel power sequencer or it will fail to
6853          * start up when no ports are active.
6854          */
6855         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6856 }
6857
6858 static void g4x_disable_trickle_feed(struct drm_device *dev)
6859 {
6860         struct drm_i915_private *dev_priv = to_i915(dev);
6861         enum pipe pipe;
6862
6863         for_each_pipe(dev_priv, pipe) {
6864                 I915_WRITE(DSPCNTR(pipe),
6865                            I915_READ(DSPCNTR(pipe)) |
6866                            DISPPLANE_TRICKLE_FEED_DISABLE);
6867
6868                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6869                 POSTING_READ(DSPSURF(pipe));
6870         }
6871 }
6872
6873 static void ilk_init_lp_watermarks(struct drm_device *dev)
6874 {
6875         struct drm_i915_private *dev_priv = to_i915(dev);
6876
6877         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6878         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6879         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6880
6881         /*
6882          * Don't touch WM1S_LP_EN here.
6883          * Doing so could cause underruns.
6884          */
6885 }
6886
6887 static void ironlake_init_clock_gating(struct drm_device *dev)
6888 {
6889         struct drm_i915_private *dev_priv = to_i915(dev);
6890         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6891
6892         /*
6893          * Required for FBC
6894          * WaFbcDisableDpfcClockGating:ilk
6895          */
6896         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6897                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6898                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6899
6900         I915_WRITE(PCH_3DCGDIS0,
6901                    MARIUNIT_CLOCK_GATE_DISABLE |
6902                    SVSMUNIT_CLOCK_GATE_DISABLE);
6903         I915_WRITE(PCH_3DCGDIS1,
6904                    VFMUNIT_CLOCK_GATE_DISABLE);
6905
6906         /*
6907          * According to the spec the following bits should be set in
6908          * order to enable memory self-refresh
6909          * The bit 22/21 of 0x42004
6910          * The bit 5 of 0x42020
6911          * The bit 15 of 0x45000
6912          */
6913         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6914                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6915                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6916         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6917         I915_WRITE(DISP_ARB_CTL,
6918                    (I915_READ(DISP_ARB_CTL) |
6919                     DISP_FBC_WM_DIS));
6920
6921         ilk_init_lp_watermarks(dev);
6922
6923         /*
6924          * Based on the document from hardware guys the following bits
6925          * should be set unconditionally in order to enable FBC.
6926          * The bit 22 of 0x42000
6927          * The bit 22 of 0x42004
6928          * The bit 7,8,9 of 0x42020.
6929          */
6930         if (IS_IRONLAKE_M(dev)) {
6931                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6932                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6933                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6934                            ILK_FBCQ_DIS);
6935                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6936                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6937                            ILK_DPARB_GATE);
6938         }
6939
6940         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6941
6942         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6943                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6944                    ILK_ELPIN_409_SELECT);
6945         I915_WRITE(_3D_CHICKEN2,
6946                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6947                    _3D_CHICKEN2_WM_READ_PIPELINED);
6948
6949         /* WaDisableRenderCachePipelinedFlush:ilk */
6950         I915_WRITE(CACHE_MODE_0,
6951                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6952
6953         /* WaDisable_RenderCache_OperationalFlush:ilk */
6954         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6955
6956         g4x_disable_trickle_feed(dev);
6957
6958         ibx_init_clock_gating(dev);
6959 }
6960
6961 static void cpt_init_clock_gating(struct drm_device *dev)
6962 {
6963         struct drm_i915_private *dev_priv = to_i915(dev);
6964         int pipe;
6965         uint32_t val;
6966
6967         /*
6968          * On Ibex Peak and Cougar Point, we need to disable clock
6969          * gating for the panel power sequencer or it will fail to
6970          * start up when no ports are active.
6971          */
6972         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6973                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6974                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6975         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6976                    DPLS_EDP_PPS_FIX_DIS);
6977         /* The below fixes the weird display corruption, a few pixels shifted
6978          * downward, on (only) LVDS of some HP laptops with IVY.
6979          */
6980         for_each_pipe(dev_priv, pipe) {
6981                 val = I915_READ(TRANS_CHICKEN2(pipe));
6982                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6983                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6984                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6985                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6986                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6987                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6988                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6989                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6990         }
6991         /* WADP0ClockGatingDisable */
6992         for_each_pipe(dev_priv, pipe) {
6993                 I915_WRITE(TRANS_CHICKEN1(pipe),
6994                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6995         }
6996 }
6997
6998 static void gen6_check_mch_setup(struct drm_device *dev)
6999 {
7000         struct drm_i915_private *dev_priv = to_i915(dev);
7001         uint32_t tmp;
7002
7003         tmp = I915_READ(MCH_SSKPD);
7004         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7005                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7006                               tmp);
7007 }
7008
7009 static void gen6_init_clock_gating(struct drm_device *dev)
7010 {
7011         struct drm_i915_private *dev_priv = to_i915(dev);
7012         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7013
7014         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
7015
7016         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7017                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7018                    ILK_ELPIN_409_SELECT);
7019
7020         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
7021         I915_WRITE(_3D_CHICKEN,
7022                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7023
7024         /* WaDisable_RenderCache_OperationalFlush:snb */
7025         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7026
7027         /*
7028          * BSpec recoomends 8x4 when MSAA is used,
7029          * however in practice 16x4 seems fastest.
7030          *
7031          * Note that PS/WM thread counts depend on the WIZ hashing
7032          * disable bit, which we don't touch here, but it's good
7033          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7034          */
7035         I915_WRITE(GEN6_GT_MODE,
7036                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7037
7038         ilk_init_lp_watermarks(dev);
7039
7040         I915_WRITE(CACHE_MODE_0,
7041                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
7042
7043         I915_WRITE(GEN6_UCGCTL1,
7044                    I915_READ(GEN6_UCGCTL1) |
7045                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7046                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7047
7048         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7049          * gating disable must be set.  Failure to set it results in
7050          * flickering pixels due to Z write ordering failures after
7051          * some amount of runtime in the Mesa "fire" demo, and Unigine
7052          * Sanctuary and Tropics, and apparently anything else with
7053          * alpha test or pixel discard.
7054          *
7055          * According to the spec, bit 11 (RCCUNIT) must also be set,
7056          * but we didn't debug actual testcases to find it out.
7057          *
7058          * WaDisableRCCUnitClockGating:snb
7059          * WaDisableRCPBUnitClockGating:snb
7060          */
7061         I915_WRITE(GEN6_UCGCTL2,
7062                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7063                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7064
7065         /* WaStripsFansDisableFastClipPerformanceFix:snb */
7066         I915_WRITE(_3D_CHICKEN3,
7067                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
7068
7069         /*
7070          * Bspec says:
7071          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7072          * 3DSTATE_SF number of SF output attributes is more than 16."
7073          */
7074         I915_WRITE(_3D_CHICKEN3,
7075                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7076
7077         /*
7078          * According to the spec the following bits should be
7079          * set in order to enable memory self-refresh and fbc:
7080          * The bit21 and bit22 of 0x42000
7081          * The bit21 and bit22 of 0x42004
7082          * The bit5 and bit7 of 0x42020
7083          * The bit14 of 0x70180
7084          * The bit14 of 0x71180
7085          *
7086          * WaFbcAsynchFlipDisableFbcQueue:snb
7087          */
7088         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7089                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7090                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7091         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7092                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7093                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7094         I915_WRITE(ILK_DSPCLK_GATE_D,
7095                    I915_READ(ILK_DSPCLK_GATE_D) |
7096                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
7097                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7098
7099         g4x_disable_trickle_feed(dev);
7100
7101         cpt_init_clock_gating(dev);
7102
7103         gen6_check_mch_setup(dev);
7104 }
7105
7106 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7107 {
7108         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7109
7110         /*
7111          * WaVSThreadDispatchOverride:ivb,vlv
7112          *
7113          * This actually overrides the dispatch
7114          * mode for all thread types.
7115          */
7116         reg &= ~GEN7_FF_SCHED_MASK;
7117         reg |= GEN7_FF_TS_SCHED_HW;
7118         reg |= GEN7_FF_VS_SCHED_HW;
7119         reg |= GEN7_FF_DS_SCHED_HW;
7120
7121         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7122 }
7123
7124 static void lpt_init_clock_gating(struct drm_device *dev)
7125 {
7126         struct drm_i915_private *dev_priv = to_i915(dev);
7127
7128         /*
7129          * TODO: this bit should only be enabled when really needed, then
7130          * disabled when not needed anymore in order to save power.
7131          */
7132         if (HAS_PCH_LPT_LP(dev))
7133                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7134                            I915_READ(SOUTH_DSPCLK_GATE_D) |
7135                            PCH_LP_PARTITION_LEVEL_DISABLE);
7136
7137         /* WADPOClockGatingDisable:hsw */
7138         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7139                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
7140                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7141 }
7142
7143 static void lpt_suspend_hw(struct drm_device *dev)
7144 {
7145         struct drm_i915_private *dev_priv = to_i915(dev);
7146
7147         if (HAS_PCH_LPT_LP(dev)) {
7148                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7149
7150                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7151                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7152         }
7153 }
7154
7155 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7156                                    int general_prio_credits,
7157                                    int high_prio_credits)
7158 {
7159         u32 misccpctl;
7160
7161         /* WaTempDisableDOPClkGating:bdw */
7162         misccpctl = I915_READ(GEN7_MISCCPCTL);
7163         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7164
7165         I915_WRITE(GEN8_L3SQCREG1,
7166                    L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7167                    L3_HIGH_PRIO_CREDITS(high_prio_credits));
7168
7169         /*
7170          * Wait at least 100 clocks before re-enabling clock gating.
7171          * See the definition of L3SQCREG1 in BSpec.
7172          */
7173         POSTING_READ(GEN8_L3SQCREG1);
7174         udelay(1);
7175         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7176 }
7177
7178 static void kabylake_init_clock_gating(struct drm_device *dev)
7179 {
7180         struct drm_i915_private *dev_priv = dev->dev_private;
7181
7182         gen9_init_clock_gating(dev);
7183
7184         /* WaDisableSDEUnitClockGating:kbl */
7185         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7186                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7187                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7188
7189         /* WaDisableGamClockGating:kbl */
7190         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7191                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7192                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7193
7194         /* WaFbcNukeOnHostModify:kbl */
7195         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7196                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7197 }
7198
7199 static void skylake_init_clock_gating(struct drm_device *dev)
7200 {
7201         struct drm_i915_private *dev_priv = dev->dev_private;
7202
7203         gen9_init_clock_gating(dev);
7204
7205         /* WAC6entrylatency:skl */
7206         I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7207                    FBC_LLC_FULLY_OPEN);
7208
7209         /* WaFbcNukeOnHostModify:skl */
7210         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7211                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7212 }
7213
7214 static void broadwell_init_clock_gating(struct drm_device *dev)
7215 {
7216         struct drm_i915_private *dev_priv = to_i915(dev);
7217         enum pipe pipe;
7218
7219         ilk_init_lp_watermarks(dev);
7220
7221         /* WaSwitchSolVfFArbitrationPriority:bdw */
7222         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7223
7224         /* WaPsrDPAMaskVBlankInSRD:bdw */
7225         I915_WRITE(CHICKEN_PAR1_1,
7226                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7227
7228         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7229         for_each_pipe(dev_priv, pipe) {
7230                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7231                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
7232                            BDW_DPRS_MASK_VBLANK_SRD);
7233         }
7234
7235         /* WaVSRefCountFullforceMissDisable:bdw */
7236         /* WaDSRefCountFullforceMissDisable:bdw */
7237         I915_WRITE(GEN7_FF_THREAD_MODE,
7238                    I915_READ(GEN7_FF_THREAD_MODE) &
7239                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7240
7241         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7242                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7243
7244         /* WaDisableSDEUnitClockGating:bdw */
7245         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7246                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7247
7248         /* WaProgramL3SqcReg1Default:bdw */
7249         gen8_set_l3sqc_credits(dev_priv, 30, 2);
7250
7251         /*
7252          * WaGttCachingOffByDefault:bdw
7253          * GTT cache may not work with big pages, so if those
7254          * are ever enabled GTT cache may need to be disabled.
7255          */
7256         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7257
7258         /* WaKVMNotificationOnConfigChange:bdw */
7259         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7260                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7261
7262         lpt_init_clock_gating(dev);
7263 }
7264
7265 static void haswell_init_clock_gating(struct drm_device *dev)
7266 {
7267         struct drm_i915_private *dev_priv = to_i915(dev);
7268
7269         ilk_init_lp_watermarks(dev);
7270
7271         /* L3 caching of data atomics doesn't work -- disable it. */
7272         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7273         I915_WRITE(HSW_ROW_CHICKEN3,
7274                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7275
7276         /* This is required by WaCatErrorRejectionIssue:hsw */
7277         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7278                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7279                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7280
7281         /* WaVSRefCountFullforceMissDisable:hsw */
7282         I915_WRITE(GEN7_FF_THREAD_MODE,
7283                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7284
7285         /* WaDisable_RenderCache_OperationalFlush:hsw */
7286         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7287
7288         /* enable HiZ Raw Stall Optimization */
7289         I915_WRITE(CACHE_MODE_0_GEN7,
7290                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7291
7292         /* WaDisable4x2SubspanOptimization:hsw */
7293         I915_WRITE(CACHE_MODE_1,
7294                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7295
7296         /*
7297          * BSpec recommends 8x4 when MSAA is used,
7298          * however in practice 16x4 seems fastest.
7299          *
7300          * Note that PS/WM thread counts depend on the WIZ hashing
7301          * disable bit, which we don't touch here, but it's good
7302          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7303          */
7304         I915_WRITE(GEN7_GT_MODE,
7305                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7306
7307         /* WaSampleCChickenBitEnable:hsw */
7308         I915_WRITE(HALF_SLICE_CHICKEN3,
7309                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7310
7311         /* WaSwitchSolVfFArbitrationPriority:hsw */
7312         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7313
7314         /* WaRsPkgCStateDisplayPMReq:hsw */
7315         I915_WRITE(CHICKEN_PAR1_1,
7316                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7317
7318         lpt_init_clock_gating(dev);
7319 }
7320
7321 static void ivybridge_init_clock_gating(struct drm_device *dev)
7322 {
7323         struct drm_i915_private *dev_priv = to_i915(dev);
7324         uint32_t snpcr;
7325
7326         ilk_init_lp_watermarks(dev);
7327
7328         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7329
7330         /* WaDisableEarlyCull:ivb */
7331         I915_WRITE(_3D_CHICKEN3,
7332                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7333
7334         /* WaDisableBackToBackFlipFix:ivb */
7335         I915_WRITE(IVB_CHICKEN3,
7336                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7337                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7338
7339         /* WaDisablePSDDualDispatchEnable:ivb */
7340         if (IS_IVB_GT1(dev))
7341                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7342                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7343
7344         /* WaDisable_RenderCache_OperationalFlush:ivb */
7345         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7346
7347         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7348         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7349                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7350
7351         /* WaApplyL3ControlAndL3ChickenMode:ivb */
7352         I915_WRITE(GEN7_L3CNTLREG1,
7353                         GEN7_WA_FOR_GEN7_L3_CONTROL);
7354         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7355                    GEN7_WA_L3_CHICKEN_MODE);
7356         if (IS_IVB_GT1(dev))
7357                 I915_WRITE(GEN7_ROW_CHICKEN2,
7358                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7359         else {
7360                 /* must write both registers */
7361                 I915_WRITE(GEN7_ROW_CHICKEN2,
7362                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7363                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7364                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7365         }
7366
7367         /* WaForceL3Serialization:ivb */
7368         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7369                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7370
7371         /*
7372          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7373          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7374          */
7375         I915_WRITE(GEN6_UCGCTL2,
7376                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7377
7378         /* This is required by WaCatErrorRejectionIssue:ivb */
7379         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7380                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7381                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7382
7383         g4x_disable_trickle_feed(dev);
7384
7385         gen7_setup_fixed_func_scheduler(dev_priv);
7386
7387         if (0) { /* causes HiZ corruption on ivb:gt1 */
7388                 /* enable HiZ Raw Stall Optimization */
7389                 I915_WRITE(CACHE_MODE_0_GEN7,
7390                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7391         }
7392
7393         /* WaDisable4x2SubspanOptimization:ivb */
7394         I915_WRITE(CACHE_MODE_1,
7395                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7396
7397         /*
7398          * BSpec recommends 8x4 when MSAA is used,
7399          * however in practice 16x4 seems fastest.
7400          *
7401          * Note that PS/WM thread counts depend on the WIZ hashing
7402          * disable bit, which we don't touch here, but it's good
7403          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7404          */
7405         I915_WRITE(GEN7_GT_MODE,
7406                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7407
7408         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7409         snpcr &= ~GEN6_MBC_SNPCR_MASK;
7410         snpcr |= GEN6_MBC_SNPCR_MED;
7411         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7412
7413         if (!HAS_PCH_NOP(dev))
7414                 cpt_init_clock_gating(dev);
7415
7416         gen6_check_mch_setup(dev);
7417 }
7418
7419 static void valleyview_init_clock_gating(struct drm_device *dev)
7420 {
7421         struct drm_i915_private *dev_priv = to_i915(dev);
7422
7423         /* WaDisableEarlyCull:vlv */
7424         I915_WRITE(_3D_CHICKEN3,
7425                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7426
7427         /* WaDisableBackToBackFlipFix:vlv */
7428         I915_WRITE(IVB_CHICKEN3,
7429                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7430                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7431
7432         /* WaPsdDispatchEnable:vlv */
7433         /* WaDisablePSDDualDispatchEnable:vlv */
7434         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7435                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7436                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7437
7438         /* WaDisable_RenderCache_OperationalFlush:vlv */
7439         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7440
7441         /* WaForceL3Serialization:vlv */
7442         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7443                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7444
7445         /* WaDisableDopClockGating:vlv */
7446         I915_WRITE(GEN7_ROW_CHICKEN2,
7447                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7448
7449         /* This is required by WaCatErrorRejectionIssue:vlv */
7450         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7451                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7452                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7453
7454         gen7_setup_fixed_func_scheduler(dev_priv);
7455
7456         /*
7457          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7458          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7459          */
7460         I915_WRITE(GEN6_UCGCTL2,
7461                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7462
7463         /* WaDisableL3Bank2xClockGate:vlv
7464          * Disabling L3 clock gating- MMIO 940c[25] = 1
7465          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7466         I915_WRITE(GEN7_UCGCTL4,
7467                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7468
7469         /*
7470          * BSpec says this must be set, even though
7471          * WaDisable4x2SubspanOptimization isn't listed for VLV.
7472          */
7473         I915_WRITE(CACHE_MODE_1,
7474                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7475
7476         /*
7477          * BSpec recommends 8x4 when MSAA is used,
7478          * however in practice 16x4 seems fastest.
7479          *
7480          * Note that PS/WM thread counts depend on the WIZ hashing
7481          * disable bit, which we don't touch here, but it's good
7482          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7483          */
7484         I915_WRITE(GEN7_GT_MODE,
7485                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7486
7487         /*
7488          * WaIncreaseL3CreditsForVLVB0:vlv
7489          * This is the hardware default actually.
7490          */
7491         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7492
7493         /*
7494          * WaDisableVLVClockGating_VBIIssue:vlv
7495          * Disable clock gating on th GCFG unit to prevent a delay
7496          * in the reporting of vblank events.
7497          */
7498         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7499 }
7500
7501 static void cherryview_init_clock_gating(struct drm_device *dev)
7502 {
7503         struct drm_i915_private *dev_priv = to_i915(dev);
7504
7505         /* WaVSRefCountFullforceMissDisable:chv */
7506         /* WaDSRefCountFullforceMissDisable:chv */
7507         I915_WRITE(GEN7_FF_THREAD_MODE,
7508                    I915_READ(GEN7_FF_THREAD_MODE) &
7509                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7510
7511         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7512         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7513                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7514
7515         /* WaDisableCSUnitClockGating:chv */
7516         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7517                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7518
7519         /* WaDisableSDEUnitClockGating:chv */
7520         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7521                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7522
7523         /*
7524          * WaProgramL3SqcReg1Default:chv
7525          * See gfxspecs/Related Documents/Performance Guide/
7526          * LSQC Setting Recommendations.
7527          */
7528         gen8_set_l3sqc_credits(dev_priv, 38, 2);
7529
7530         /*
7531          * GTT cache may not work with big pages, so if those
7532          * are ever enabled GTT cache may need to be disabled.
7533          */
7534         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7535 }
7536
7537 static void g4x_init_clock_gating(struct drm_device *dev)
7538 {
7539         struct drm_i915_private *dev_priv = to_i915(dev);
7540         uint32_t dspclk_gate;
7541
7542         I915_WRITE(RENCLK_GATE_D1, 0);
7543         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7544                    GS_UNIT_CLOCK_GATE_DISABLE |
7545                    CL_UNIT_CLOCK_GATE_DISABLE);
7546         I915_WRITE(RAMCLK_GATE_D, 0);
7547         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7548                 OVRUNIT_CLOCK_GATE_DISABLE |
7549                 OVCUNIT_CLOCK_GATE_DISABLE;
7550         if (IS_GM45(dev))
7551                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7552         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7553
7554         /* WaDisableRenderCachePipelinedFlush */
7555         I915_WRITE(CACHE_MODE_0,
7556                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7557
7558         /* WaDisable_RenderCache_OperationalFlush:g4x */
7559         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7560
7561         g4x_disable_trickle_feed(dev);
7562 }
7563
7564 static void crestline_init_clock_gating(struct drm_device *dev)
7565 {
7566         struct drm_i915_private *dev_priv = to_i915(dev);
7567
7568         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7569         I915_WRITE(RENCLK_GATE_D2, 0);
7570         I915_WRITE(DSPCLK_GATE_D, 0);
7571         I915_WRITE(RAMCLK_GATE_D, 0);
7572         I915_WRITE16(DEUC, 0);
7573         I915_WRITE(MI_ARB_STATE,
7574                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7575
7576         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7577         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7578 }
7579
7580 static void broadwater_init_clock_gating(struct drm_device *dev)
7581 {
7582         struct drm_i915_private *dev_priv = to_i915(dev);
7583
7584         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7585                    I965_RCC_CLOCK_GATE_DISABLE |
7586                    I965_RCPB_CLOCK_GATE_DISABLE |
7587                    I965_ISC_CLOCK_GATE_DISABLE |
7588                    I965_FBC_CLOCK_GATE_DISABLE);
7589         I915_WRITE(RENCLK_GATE_D2, 0);
7590         I915_WRITE(MI_ARB_STATE,
7591                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7592
7593         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7594         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7595 }
7596
7597 static void gen3_init_clock_gating(struct drm_device *dev)
7598 {
7599         struct drm_i915_private *dev_priv = to_i915(dev);
7600         u32 dstate = I915_READ(D_STATE);
7601
7602         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7603                 DSTATE_DOT_CLOCK_GATING;
7604         I915_WRITE(D_STATE, dstate);
7605
7606         if (IS_PINEVIEW(dev))
7607                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7608
7609         /* IIR "flip pending" means done if this bit is set */
7610         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7611
7612         /* interrupts should cause a wake up from C3 */
7613         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7614
7615         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7616         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7617
7618         I915_WRITE(MI_ARB_STATE,
7619                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7620 }
7621
7622 static void i85x_init_clock_gating(struct drm_device *dev)
7623 {
7624         struct drm_i915_private *dev_priv = to_i915(dev);
7625
7626         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7627
7628         /* interrupts should cause a wake up from C3 */
7629         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7630                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7631
7632         I915_WRITE(MEM_MODE,
7633                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7634 }
7635
7636 static void i830_init_clock_gating(struct drm_device *dev)
7637 {
7638         struct drm_i915_private *dev_priv = to_i915(dev);
7639
7640         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7641
7642         I915_WRITE(MEM_MODE,
7643                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7644                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7645 }
7646
7647 void intel_init_clock_gating(struct drm_device *dev)
7648 {
7649         struct drm_i915_private *dev_priv = to_i915(dev);
7650
7651         dev_priv->display.init_clock_gating(dev);
7652 }
7653
7654 void intel_suspend_hw(struct drm_device *dev)
7655 {
7656         if (HAS_PCH_LPT(dev))
7657                 lpt_suspend_hw(dev);
7658 }
7659
7660 static void nop_init_clock_gating(struct drm_device *dev)
7661 {
7662         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7663 }
7664
7665 /**
7666  * intel_init_clock_gating_hooks - setup the clock gating hooks
7667  * @dev_priv: device private
7668  *
7669  * Setup the hooks that configure which clocks of a given platform can be
7670  * gated and also apply various GT and display specific workarounds for these
7671  * platforms. Note that some GT specific workarounds are applied separately
7672  * when GPU contexts or batchbuffers start their execution.
7673  */
7674 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7675 {
7676         if (IS_SKYLAKE(dev_priv))
7677                 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7678         else if (IS_KABYLAKE(dev_priv))
7679                 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7680         else if (IS_BROXTON(dev_priv))
7681                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7682         else if (IS_BROADWELL(dev_priv))
7683                 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7684         else if (IS_CHERRYVIEW(dev_priv))
7685                 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7686         else if (IS_HASWELL(dev_priv))
7687                 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7688         else if (IS_IVYBRIDGE(dev_priv))
7689                 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7690         else if (IS_VALLEYVIEW(dev_priv))
7691                 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7692         else if (IS_GEN6(dev_priv))
7693                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7694         else if (IS_GEN5(dev_priv))
7695                 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7696         else if (IS_G4X(dev_priv))
7697                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7698         else if (IS_CRESTLINE(dev_priv))
7699                 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7700         else if (IS_BROADWATER(dev_priv))
7701                 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7702         else if (IS_GEN3(dev_priv))
7703                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7704         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7705                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7706         else if (IS_GEN2(dev_priv))
7707                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7708         else {
7709                 MISSING_CASE(INTEL_DEVID(dev_priv));
7710                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7711         }
7712 }
7713
7714 /* Set up chip specific power management-related functions */
7715 void intel_init_pm(struct drm_device *dev)
7716 {
7717         struct drm_i915_private *dev_priv = to_i915(dev);
7718
7719         intel_fbc_init(dev_priv);
7720
7721         /* For cxsr */
7722         if (IS_PINEVIEW(dev))
7723                 i915_pineview_get_mem_freq(dev);
7724         else if (IS_GEN5(dev))
7725                 i915_ironlake_get_mem_freq(dev);
7726
7727         /* For FIFO watermark updates */
7728         if (INTEL_INFO(dev)->gen >= 9) {
7729                 skl_setup_wm_latency(dev);
7730                 dev_priv->display.update_wm = skl_update_wm;
7731                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7732         } else if (HAS_PCH_SPLIT(dev)) {
7733                 ilk_setup_wm_latency(dev);
7734
7735                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7736                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7737                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7738                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7739                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7740                         dev_priv->display.compute_intermediate_wm =
7741                                 ilk_compute_intermediate_wm;
7742                         dev_priv->display.initial_watermarks =
7743                                 ilk_initial_watermarks;
7744                         dev_priv->display.optimize_watermarks =
7745                                 ilk_optimize_watermarks;
7746                 } else {
7747                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7748                                       "Disable CxSR\n");
7749                 }
7750         } else if (IS_CHERRYVIEW(dev)) {
7751                 vlv_setup_wm_latency(dev);
7752                 dev_priv->display.update_wm = vlv_update_wm;
7753         } else if (IS_VALLEYVIEW(dev)) {
7754                 vlv_setup_wm_latency(dev);
7755                 dev_priv->display.update_wm = vlv_update_wm;
7756         } else if (IS_PINEVIEW(dev)) {
7757                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7758                                             dev_priv->is_ddr3,
7759                                             dev_priv->fsb_freq,
7760                                             dev_priv->mem_freq)) {
7761                         DRM_INFO("failed to find known CxSR latency "
7762                                  "(found ddr%s fsb freq %d, mem freq %d), "
7763                                  "disabling CxSR\n",
7764                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7765                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7766                         /* Disable CxSR and never update its watermark again */
7767                         intel_set_memory_cxsr(dev_priv, false);
7768                         dev_priv->display.update_wm = NULL;
7769                 } else
7770                         dev_priv->display.update_wm = pineview_update_wm;
7771         } else if (IS_G4X(dev)) {
7772                 dev_priv->display.update_wm = g4x_update_wm;
7773         } else if (IS_GEN4(dev)) {
7774                 dev_priv->display.update_wm = i965_update_wm;
7775         } else if (IS_GEN3(dev)) {
7776                 dev_priv->display.update_wm = i9xx_update_wm;
7777                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7778         } else if (IS_GEN2(dev)) {
7779                 if (INTEL_INFO(dev)->num_pipes == 1) {
7780                         dev_priv->display.update_wm = i845_update_wm;
7781                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7782                 } else {
7783                         dev_priv->display.update_wm = i9xx_update_wm;
7784                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7785                 }
7786         } else {
7787                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7788         }
7789 }
7790
7791 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7792 {
7793         uint32_t flags =
7794                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7795
7796         switch (flags) {
7797         case GEN6_PCODE_SUCCESS:
7798                 return 0;
7799         case GEN6_PCODE_UNIMPLEMENTED_CMD:
7800         case GEN6_PCODE_ILLEGAL_CMD:
7801                 return -ENXIO;
7802         case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7803         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7804                 return -EOVERFLOW;
7805         case GEN6_PCODE_TIMEOUT:
7806                 return -ETIMEDOUT;
7807         default:
7808                 MISSING_CASE(flags)
7809                 return 0;
7810         }
7811 }
7812
7813 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7814 {
7815         uint32_t flags =
7816                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7817
7818         switch (flags) {
7819         case GEN6_PCODE_SUCCESS:
7820                 return 0;
7821         case GEN6_PCODE_ILLEGAL_CMD:
7822                 return -ENXIO;
7823         case GEN7_PCODE_TIMEOUT:
7824                 return -ETIMEDOUT;
7825         case GEN7_PCODE_ILLEGAL_DATA:
7826                 return -EINVAL;
7827         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7828                 return -EOVERFLOW;
7829         default:
7830                 MISSING_CASE(flags);
7831                 return 0;
7832         }
7833 }
7834
7835 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7836 {
7837         int status;
7838
7839         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7840
7841         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7842          * use te fw I915_READ variants to reduce the amount of work
7843          * required when reading/writing.
7844          */
7845
7846         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7847                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7848                 return -EAGAIN;
7849         }
7850
7851         I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7852         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7853         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7854
7855         if (intel_wait_for_register_fw(dev_priv,
7856                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7857                                        500)) {
7858                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7859                 return -ETIMEDOUT;
7860         }
7861
7862         *val = I915_READ_FW(GEN6_PCODE_DATA);
7863         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7864
7865         if (INTEL_GEN(dev_priv) > 6)
7866                 status = gen7_check_mailbox_status(dev_priv);
7867         else
7868                 status = gen6_check_mailbox_status(dev_priv);
7869
7870         if (status) {
7871                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7872                                  status);
7873                 return status;
7874         }
7875
7876         return 0;
7877 }
7878
7879 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
7880                             u32 mbox, u32 val)
7881 {
7882         int status;
7883
7884         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7885
7886         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7887          * use te fw I915_READ variants to reduce the amount of work
7888          * required when reading/writing.
7889          */
7890
7891         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7892                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7893                 return -EAGAIN;
7894         }
7895
7896         I915_WRITE_FW(GEN6_PCODE_DATA, val);
7897         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7898
7899         if (intel_wait_for_register_fw(dev_priv,
7900                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7901                                        500)) {
7902                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7903                 return -ETIMEDOUT;
7904         }
7905
7906         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7907
7908         if (INTEL_GEN(dev_priv) > 6)
7909                 status = gen7_check_mailbox_status(dev_priv);
7910         else
7911                 status = gen6_check_mailbox_status(dev_priv);
7912
7913         if (status) {
7914                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7915                                  status);
7916                 return status;
7917         }
7918
7919         return 0;
7920 }
7921
7922 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7923 {
7924         /*
7925          * N = val - 0xb7
7926          * Slow = Fast = GPLL ref * N
7927          */
7928         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7929 }
7930
7931 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7932 {
7933         return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7934 }
7935
7936 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7937 {
7938         /*
7939          * N = val / 2
7940          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7941          */
7942         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7943 }
7944
7945 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7946 {
7947         /* CHV needs even values */
7948         return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7949 }
7950
7951 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7952 {
7953         if (IS_GEN9(dev_priv))
7954                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7955                                          GEN9_FREQ_SCALER);
7956         else if (IS_CHERRYVIEW(dev_priv))
7957                 return chv_gpu_freq(dev_priv, val);
7958         else if (IS_VALLEYVIEW(dev_priv))
7959                 return byt_gpu_freq(dev_priv, val);
7960         else
7961                 return val * GT_FREQUENCY_MULTIPLIER;
7962 }
7963
7964 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7965 {
7966         if (IS_GEN9(dev_priv))
7967                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7968                                          GT_FREQUENCY_MULTIPLIER);
7969         else if (IS_CHERRYVIEW(dev_priv))
7970                 return chv_freq_opcode(dev_priv, val);
7971         else if (IS_VALLEYVIEW(dev_priv))
7972                 return byt_freq_opcode(dev_priv, val);
7973         else
7974                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7975 }
7976
7977 struct request_boost {
7978         struct work_struct work;
7979         struct drm_i915_gem_request *req;
7980 };
7981
7982 static void __intel_rps_boost_work(struct work_struct *work)
7983 {
7984         struct request_boost *boost = container_of(work, struct request_boost, work);
7985         struct drm_i915_gem_request *req = boost->req;
7986
7987         if (!i915_gem_request_completed(req))
7988                 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
7989
7990         i915_gem_request_put(req);
7991         kfree(boost);
7992 }
7993
7994 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
7995 {
7996         struct request_boost *boost;
7997
7998         if (req == NULL || INTEL_GEN(req->i915) < 6)
7999                 return;
8000
8001         if (i915_gem_request_completed(req))
8002                 return;
8003
8004         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
8005         if (boost == NULL)
8006                 return;
8007
8008         boost->req = i915_gem_request_get(req);
8009
8010         INIT_WORK(&boost->work, __intel_rps_boost_work);
8011         queue_work(req->i915->wq, &boost->work);
8012 }
8013
8014 void intel_pm_setup(struct drm_device *dev)
8015 {
8016         struct drm_i915_private *dev_priv = to_i915(dev);
8017
8018         mutex_init(&dev_priv->rps.hw_lock);
8019         spin_lock_init(&dev_priv->rps.client_lock);
8020
8021         INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8022                           __intel_autoenable_gt_powersave);
8023         INIT_LIST_HEAD(&dev_priv->rps.clients);
8024
8025         dev_priv->pm.suspended = false;
8026         atomic_set(&dev_priv->pm.wakeref_count, 0);
8027         atomic_set(&dev_priv->pm.atomic_seq, 0);
8028 }